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SPARCbook 1 Technical Reference Manual

Tadpole Technology Inc 12012 Technology Blvd.

Austin, TX 78727 USA

Tel: 512-219-2200 Fax: 512-219-2222

Tadpole Technology pie Cambridge Science Parle

Milton Road Cambridge, CB4 4WQ

ENGLAND

Tel: 0223 250030 Fax: 0223 250036

FCC Class B Notice

This equipment has been tested and found to comply with the limits for a Class B digital device, pursuant to Part 15 of the FCC rules. These limits are designed to provide reasonable protection against harmful interference in a residential installation. This equipment generates, uses and can radiate radio frequency energy and, if not installed and used in accordance with the instructions, may cause harmful interference to radio communications. However, there is no guarantee that interference will not occur in a particular installation. If this equipment does cause harmful interference to radio or television reception, which can be determined by turning the equipment off and on, the user is encouraged to try to correct the interference by one or more of the following measures:

• Reorient or relocate the receiving antenna • Increase the separation between the equipment and receiver • Connect the equipment into an outlet on a circuit different from that to which the

receiver is connected •Consult your supplier, or an experienced radio or television technician for help

Modifications

This equipment contains no user-serviceable parts. You are advised that unauthorized changes or modifications to the equipment could cause it to exceed Class B limits and may void the authority granted by the FCC to operate the equipment

Shielded Cables

Connections between the SP ARCbook and any connected peripherals must be made using shielded cables to maintain compliance with FCC radio frequency emission limits.

FCC Part 68 Modem Information

This equipment complies with Part 68 of the FCC rules. On the underside of this equipment is a label that contains, among other information, the FCC registration number and ringer equivalence number (REN) for this equipment If requested, this information must be provided to the telephone company.

This equipment uses the following USOC jacks: RJl 1 C

The REN is used to determine the quantity of devices which may be connected to the telephone line. Excessive RENs on the telephone line may result in the devices not ringing in response to an incoming call. In most, but not all areas, the sum of the RENs should not exceed five (5.0). To be certain of the number of devices that may be connected to the line, as determined by the total REN s, contact the telephone company to determine the maximum REN for the calling area.

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If this equipment causes harm to the telephone network, the telephone company will notify you in advance that temporary discontinuance of service may be required. If advance notice is not practical, the telephone company will notify the customer as soon as possible. Also, you will be advised of your right to file a complaint with the FCC if you believe it is necessary. The telephone company may make changes in its facilities, equipment, operations or procedures that could affect the operation of the equipment If this happens, the telephone company will provide advance notice in order for you to make the necessary modifications in order to maintain uninterrupted service.

If trouble is experienced with this equipment, please contact Tadpole Technology Inc, 83 lOCapital of Texas Highway North, Austin, Texas 78731 Tel: (512) 338 4221 for repair and/or warranty information. H the trouble is causing harm to the telephone network, the telephone company may request you remove the equipment from the network until the problem is resolved.

The following repairs can be done by the customer: None

This equipment cannot be used on telephone company-provided coin service. Connection to Party Line Service is subject to state tariffs.

Tradanalks

All rights reserved. This product or document jg proccctcd by copyright and diallibuted under licenses res1ricling its use, copying, dislribulionanddecompilalion. Nopartoflhisproductordoaunentmaybereproclucedinanyfonnbyanymcanswilhoutpriorwriaen audiorizalim of Sun and its licenson, if any. This produet or the pmduCIS depicled henin may be proccctcd by _me or moro U.S. or intemalional pat.enla or pending patents. Porliona al. this product may be derived from the UNIX• and Bakeley 4.3 BSD systcma, liccnsedfromUNIXSystcmal..aboraiories,Inc.andthcUnivcnityol.California,reapeclively. Thirdpartyfontsoftwarcinthiaproduct jg protected by copyright and licensed from Sun's Fent Supplicra.

RESTRICTED RIGHrS LEGEND: Use, duplicalion, or diaclosuro by the government jg subject IO reslrictions u set forth in subparagraph (c) (1) (ii) of the Righta in Technical Data and Computer Softwaro clause al DFARS 252.227-7013 md FAR 52.227-19.

Sun, Sun Mic:rosystcma, the Sun Logo, OpenWmdows, SunV"tcw, SunOS, X· 11 NEWS, DeakSet, NFS and NEWS aro tradanalks or regjltcnld tradcmalks of Sun Microsystems, Inc. UNIX and OPEN LOOKaro regiataed tradanub al.UNIX Systcma Laboratories, Inc. All ether product names mallioned herein aro the tradcmub of their m1pectivc ownc:n. All SPARC tradc:mmb, including the SCDCompliantLogo,arotradc:muksorregistcrecltndcmllbol.SPARCintcmalional,Inc:. TheSPARCbooktradcmaJkjgliccnsed cxclusively IO Tadpole Technology, Inc. Products bearing SPARC tndcmalks arc bued upon an architecturo developed by Sun Microsystems, Inc.

ThcOPEN LOOK• and Sun TM Graphical User Interfaces wcro dcvdopocl by Sun Microsystems, Inc. for its U11C1B and lic:ensecs. Sun acknowledges the pioneming cfforta of Xaroa in racardiing md developing the concept al. visual or graphical user inlafaccs for the computer industry. Sun holds a nm-cJ1clusive license from Xcro11 IO the Xaroa Graphical Usar Intarfac:c, which liccnso also covcm Sun's licensees who implement OPEN LOOK GUl's and otherwise comply with Sun's written license agreancnts.

The X Window System is a product of the Massachuscus Institute ofTcchnology.

UNIX and OPEN LOOK arc regiataed tndcmalks of UNIX SySICm Laboratories PostScript jg a tndcmuk of Adobe Systems, Inc Sendfaa jg a rqjatcred tradcmailt c4 Sima Semiconductor Corp SoftPC is a rcgistared tradanailt of Insignia Solulions Lid

Issue A of January 1992 Part Number: 980 011

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©1992 by Tadpole Technology Printed in the UK

CONTENTS

INTRODUCTION TO THE SPARCbook TECHNICAL REFERENCE MANUAL ....................... 9

MANUAL STRUCTURE ........................................................................................................... 10 INDENTED AUDIENCE .......................................................................................................... 10 CONVENTIONS USED IN THIS DOCUMENT ....................................................................... 11

Logic States ........................................................................................................................ 11 Data Length Definitions ............................................................................................... ..... 11

CHAPTER ONE OVERVIEW ...................................................................................................... 13

CENTRAL PROCESSOR .......................................................................................................... 14 MAIN MEMORY ....................................................................................................................... 14 DISPLAY ................................................................................................................................... 15 UNIVERSAL PERIPHERAL CONTROUER ........................................................................... 16 MICROCONTROUER SUBSYSTEM ...................................................................................... 17 ETHERNET INTERFACE ........................................................................................................ 17 MODEM .................................................................................................................................. ~18 REAL TIME CLOCK AND EPROM ......................................................................................... 18 SPARCBOOK TECHNICAL SPECIFICATION ....................................................................... 19 SPARCBOOK DETAILED ADDRESS MAP ............................................................................ 22

DRAM ................................................................................................................................ 22 Display Controller ............................................................................................................. 22 Ethernet Controller ............................................................................................................ 23 Modem Interface ................................................................................................................ 24 Real Time Clock I SRAM ................................. .................................................................. 24 16-Bit 110 Region - Hard Disk Data Interface ................................................................. 24 8-Bit 110 Region - UPC Associated Interfaces ................................................................. 25 MP! ASIC .................................................................................................... ~ ...................... 26

CHAPTER TWO ARCHITECTURE ............................................................................................ 27

BUS STRUCTURE .................................................................................................................... 28 Mbus .................................................................................................................................. 28 Pbus ................................................................................................................................... 28 Mbus - Pbus Interface ........................................................................................................ 29

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CHAPTER THREE THE SPARC CPU MODULE .......................................................................... 31

CY7C601A INTEGER UNIT .. ................................................................................................... 32 Instructions Overview ........................................................................................................ 32 CY7C601A Internal Registers ............................................................................................ 34 Traps and Interrupts .......................................................................................................... 38 Memory Protection ............................................................................................................ 38

FLOATING POINT UNIT ........................................................................................................ 40 Overview ..................... .. ..................................................................................................... 40 Floating Point Registers .................................................................................................... 40 Floating-Point State Register ............................................................................................ 41

CACHE CONTROLLER AND MEMORY MANAGEMENT UNIT ......................................... .43 Memory Management Unit .... .............................................. .............................................. 43 Cache Controller ............................................................................................................... 47

CY7C157A CACHE STORAGE UNIT ...................................................................................... 49

CHAPTER FOUR MAIN' MEMORY ............................................................................................. 51

FUNCTIONAL DESCRIPTION ............................................................................................... 52

CHAPTERS MBUS TO PBUS INTERFACE ...................................................................... 53

INTRODUCTION TO THE MP/ ............................................................................................... 54 PERIPHERAL BUS INTERFACE ............................................................................................ 54

Direct Operation ................................................................................................................ 54 FIFO Operations ............................................. .................................................................. 56 Peripheral Space Address Decoder ................................................................................... 57

COUNTER-TIMERS ................................................................................................................. 59 System Timers .................................................................................................................... 60 Bus Timeout Timer ............................................................................................................. 60

SERIAL 110 PORT .................................................................................................................... 60 Serial Input ........................................................................................................................ 61 Serial Output ................... ................................................................................................... 61

POWER MANAGEMENT FUNCTIONS .................................................................................. 61 Clock Control ..................................................................................................................... 61

INTERRUPT CONTROUER ................................................................................................... 62 INTERNAL REGISTERS .......................................................................................................... 64

FIFO Control Registers ..................................................................................................... 65 Timer Control Registers ............................................... ..................................................... 67

POWER MANAGEMENT CONTROL REGISTERS ................................................................ 69 Interrupt Control Registers ................................................................................................ 70

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Serial Input/Output Registers ............................................................................................ 7I Software Reset Register ..................................................................................................... 72 Error Status Register ......................................................................................................... 73

CHAPTER SIX MICROCONTROLLER SUBSYSTEM ......................................................... 75

KEYBOARD INTERFACE ........................................................................................................ 76 Key Repeat ......................................................................................................................... 76 Special Characters ............................................................................................................. 77 Special Routines ................................................................................................................. 77

MOUSEKEY INTERFACING ................................................................................................... 78 Mousekey Initialization ...................................................................................................... 78 Mousekey Events ................................................................................................................ 79

HARDWARE INTERFACES ..................................................................................................... 80 Host Instruction Protocol .................................................................................................. 80 Host Interrupts ................................................................................................................... 84 EEPROM Data .................................................................................................................. 84

CHAPTER SEVEN UNIVERSAL PERIPHERAL CONTROLLER ............................................ 85

FLOPPY DISK CONTROLLER ................................................................................................ 86 Host Interface .................................................................................................................... 86 Floppy Disk Co1nlnllnds ..................................................................................................... 87 FDC Operating Modes ...................................................................................................... 89

IDE HARD DISK INTERFACE ................................................................................................. 89 IDE Overview .................................................................................................................... 89 IDE Interface Operating Modes ........................................................................................ 90 Task File Registers ............................................................................................................ 90 IDE Command Su1nlnllry ................................................................................................... 92

PARALLEL PORT .................................................................................................................... 96 Printer Interface Registers ................................................................................................ 96

MOUSE PORT .......................................................................................................................... 98 Mouse Port Registers ......................................................................................................... 98

SERIAL PORT .......................................................................................................................... 99 Serial Port Registers .......................................................................................................... 99

UPC CONFIGURATION ......................................................................................................... 102 UPC Configuration Sequence ............................................................................................ 103 Configuration Register Description ............................................................................... ... 104

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CHAPTER EIGHT MODEM ............................................................................................................ 107

MODEM OVERVIEW .............................................................................................................. 108 INTERFACE CONTROL .. ........................................................................................................ 109

MAC Integral UART Registers .......................................................................................... 110 THE AT COMMAND SET ........................................................................................................ 111

Basic Corrunand Set ........................................................................................................... 112 Sendfax Corrunand Set ........................................................... ............................................ 114

S-REGISTERS ........................................................................................................................... 115 FAX RESPONSES ..................................................................................................................... 116

CHAPTER NINE ETHERNET INTERFACE .............................................................................. 119

NETWORKING OVERVIEW .................................................................................................... 120 Ethernet Protocol ................................................................... ............................................ 120 Basic Operations ........................................................................................................... .... 121

THE SPARCBOOK ETHERNET IMPLEMENTATION ........................................................... 122 FUNCTIONAL DESCRIPTION OF THE NICE ...................................................................... 123

NICE Host System Interface .............................................................................................. 124 Bu/fer Manager .................................................................................................................. 126

INTERRUPTS ........................................................................................................................... 128

CHAPTER TEN DISPLAY CONTROLLER .............................................................................. 129

DISPLAY INTERFACE OVERVIEW ........................................................................................ 130 HOST INTERFACE ........................................................................... : ...................................... 130

Host Accesses to the Color Lookup Table ......................................................................... 131 Display Access to Video Memory ...................................... ................................................ 132

INTERNAL RAMDAC OPERATION ........................................................................................ 132 SIMULTANEOUS DISPLAY ENABLING ................................................................................ 133 INTEWGENT POWER MANAGEMENT AND SEQUENCING ............................................ 133

CHAPTER ELEVEN MK48T02 BATTERY BACKED REAL TIME CLOCK AND SRAM ................................................................ 137

BA1TERY BACKED SRAM ................................................................... ................................... 138 REAL TIME CLOCK ................................................................................................................ 138

RTC Operation ................................................................................................................... 139 Real Time Clock Calibration .. ........................................................................................... 140

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CHAPTER TWELVE SI-BASE SCHEMATICS DESCRIPTION .................................................... 141

Sheet 1-DRAM CONTROL .............................................................................................. 141 Sheet 2 -DRAM ................................................................................................................. 142 Sheet 3-PARITYGENERATION ..................................................................................... 142 Sheet 4 -MBUS INTERFACE & MISCELLANEOUS 110 ................................................ 143 Sheet5-PERIPHERALllO .............................................................. ................................ 144 Sheet 6 - GRAPHICS ......................................................................................................... 145 Sheet 7-MODEM AND ETHERNET ............................................................................... 145 Sheet8-CONNECTORS .................................................................................................. 146 Color Syste11'1S only - Sheet 9 ...................................................................................... ....... 146

Sl-110 SCHEMATIC DESCRIPTION .................................................. .................................... 148 SJ-CPU SCHEMATIC DESCRIPTION ............................ ........................................................ 149

Sheet 1 - CY7C601 INTEGER UNIT ................................................................................. 149 Sheet 2-100-WAY MINIATURE CONNECTOR .............................................................. 149

CHAPTER THIRTEEN SYSTEM COMPONENT SPECIFICATIONS .............................................. 151

LCD COLOR DISPLAY ............................................................................................................ 151 Mechanical Characteristics ............................................................................................... 151 Electrical Characteristics .................................................................................................. 152 Optical Characteristics ....................... ............................................................................... 153

MONOCHROME DISPLAY ..................................................................................................... 154 Mechanical Characteristics ............................................................................................... 154 Temperature Range ............................................... ............................................................. 154 Absolute Maximum Ratings ............................................................................................... 155 Electrical Characteristics ............................................................................................... ... 155 Optical Characteristics ...................................................................................................... 156

80MBYTE HARD DISK ............................................................................................................ 157 Mechanical Dimensions ..................................................................................................... 157 Environmental limits ......................................................................................................... . 157 Power Requirements ..................... .. ................................................................................... 158 Timing Specifications ............................ .. ........................................................................... 158

120MBYTE HARD DISK .......................................................................................................... 160 Mechanical Dimensions ................ ..................................................................................... 160 Environmental limits .......................................................................................................... 160 Power Requirements ............................................. .. .......................................................... . 160 Timing Parameters ............................................................................................................ 161

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INTRODUCTION TO THE

SPARCbook TECHNICAL REFERENCE MANUAL

The SPARCbook Technical Reference Manual is published as a supplement to the SPARCbook User's Guide to provide additional technical infonnation. This document describes the hardware operation of the SP ARCbook notebook computer and also provides details about the resident operating system supplied with each unit.

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MANUAL STRUCTURE

The SP ARCbook Technical Reference Manual is structured as follows:

• Technical Overview Chapter 1 discusses the principle features of the SPARCbook and introduces the reader to the main hardware devices that provide control over the SPARCbook's operations.

• Architecture Overview Chapter 2 describes the internal architecture of the SP ARCbook, showing how the major devices are connected together.

• Detailed Device Descriptions Chapters 3 - 11 discuss in some depth the implementation of the major hardware devices in the SPARCbook.

• Schematics Description Chapter 12 provides a description of the schematic diagrams and discusses the theory of operation.

INTENDED AUDIENCE

The SP ARCbook Technical Reference Manual is aimed at the hardware engineer wishing to carry out service or repairs, and at the software engineer wishing to implement hardware drivers.

It is assumed that the reader is familiar with the operation of SPARCbook, as detailed in the SPARCbook User Guide, and has a basic understanding of computer hardware.

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CONVENTIONS USED IN THIS DOCUMENT

The reader is advised to note the following conventions employed in the SPARCbook Technical Reference Manual.

Logic states

The tenns Clear or low indicate that the signal being discussed is at the logic level 'O',

The tenns Set or high indicate that the signal being discussed is at the logic level 'l'.

The tenn Asserted indicates that a signal is in its true or active state regardless of whether that state is high or low.

The tenn Negated indicates that a signal is in its false or inactive state regardless of whether that state is high or low.

Data Length Definitions

A Halfword is taken to contain 16 bits.

A word is taken to contain 32 bits.

A doubleword is taken to contain 64 bits

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CHAPTER ONE OVERVIEW

The SP ARCbook provides in a compact notebook fonnat many of the advanced features and high performance nonnally associated with desktop workstations. Low power consumption and compactness have been achieved by the use of highly integrated components without compromising either the functionality or perfonnance of the SPARCbook.

The SP ARCbook is housed in a magnesium alloy case measuring 11.8" x 8.5'' x 1.9", and weighs 6.81bs, including batteries and peripherals.

The SP ARCbook 's standard features include a 640 x 480 pixel color or monochrome liquid crystal display, an 82-key keyboard, a 3.5" floppy disk drive, an IDE hard disk drive, and Modem, Ethernet, Centronics and serial interfaces. A second hard disk drive is available as an option, when it is fitted in substitution for the floppy disk drive.

All of the major integrated circuit components are carried on a single printed circuit board, using the latest surface mount technology and avoiding the need for space consuming and power hungry expansion cards. The use of components with low power demand and the SPARCbook's advanced power management facilities allow the SP ARCbook to be used continuously for 2.5 hours or more when powered from the battery.

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CENTRAL PROCESSOR

Processing power in the SP ARCbook is provided by the Cypress CY7C600 implementation of the Scalable Processor Architecture (SPARC) RISC microprocessor. The Cypress CY7C600 is a chip set which comprises the following:

• Integer Unit (IU) • Cache Controller and Memory Management Unit (CMU) • Optional Floating Point Unit (FPU) • 64Kbytes zero wait state Cache

The IU is the basic processing engine which executes all of the inslruction set except for floating point inslructions which are performed by the FPU when it is fitted. The CMU provides memory management and address translation facilities between the SPARC virtual bus and the main system bus. Two CY7C157 SRAM devices provide 64Kbytes of fast cache memory resident on the SPARC virtual bus.

The SPARC CPU is a RISC (reduced inslruction set computer) based processor. It uses a simplified range of commands to carry out operations, enabling most inslructions to execute within a single clock cycle.

Conventional processors tend to use large and complex instruction sets, taking several clock cycles to perform each instruction. Many of the instructions available to this type of processor are rarely if ever used, a fact that has led to the development of RISC processor concepts.

The already high performance of the SP ARC CPU is further enhanced by the ability of FPU to execute instructions simultaneously with the IU, and by the provision of cache memory. The Cache memory is specialized area of fast (zero wait state) memory which allows many ins1ructions and operands to be fetched locally by the CPU without it having to access the comparatively slow main memory.

MAIN MEMORY

The SP ARCbook is built using either 4Mbit or 16Mbit DRAM devices to provide 8 or 32Mbytes of DRAM. The main memory provides a 64-bit wide bus interface designed specifically to support burst cycles by the CPU.

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The memory management unit maintains entries in cache memory called cache lines, each one a 256 bits wide copy of a similar sized area of main memory. When the IU requires data that is not present in the cache, the MMU copies the new data from main memory to cache memory using burst cycles of four 64-bit reads (see Chapter Three).

Using burst transfers, the memory interface is capable of a transfer rate of 72Mbyte/s. While using random access a transfer rate of 40Mbyte/s is achieved. Both rates are at a 25MHz processor clock speed.

The main memory also features software selectable parity protection.

DISPLAY

The SP ARCbook is equipped with a 640 x 480 pixel color or monochrome liquid crystal flat panel display. Both types are side-lit by a cold fluorescent lamp, which can be controlled to vary the screen brightness. Reducing the brighbless of the sidelight reduces the power consumption, prolonging battery life.

The display is controlled by a GD6410 VGA compatible display controller made by Cirrus Logic. This provides control for a monochrome LCD display and for an external color CRT display. Both displays may be used simultaneously. Advanced grey scale control by the GD6410 provides quality grey scale rendering of color images for clear display on the LCD.

In the color SPARCbook, a GD6340 color LCD controller provides the additional control required for the color LCD display. The color model is able to display 16 colors simultaneously from a palette of 262144.

The SP ARCbook supports three display modes:

• Mode 1 - Inbuilt LCD only • Mode 2 - Simultaneous LCD and standard VGA 640 x 480 Color monitor • Mode 3 - Extended VGA 800 x 600 external high resolution only

Both color and monochrome models of the SPARCbook are able to display an image in 16 colors on the external monitor. They are both able to display the same image simultaneously on the LCD and external CRT when in mode 2.

Mode 3 allows the SPARCbook to display an image on an external high resolution monitor, but turns the inbuilt LCD screen off. This mode requires the use of a multisync monitor.

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UNIVERSAL PERIPHERAL CONTROLLER

One of the highly integrated devices used in the SPARCbook to achieve its compact size is the 82C710 Universal Peripheral Controller (UPC) manufactured by Chips and Technologies Inc. This single device provides the following:

• Hard Disk Control • Floppy Disk Control • Centronics Interfacing • External Mouse/Keyboard Interfacing • RS232 Serial Interfacing

Floppy Disk Control The UPC provides control for one or two IDE (Integrated Drive Electronics) PC/AT compatible hard disk drives. It provides a complete electronic interface, and control of a 16-bit data buffer.

Floppy Disk Control Single hard disk versions of the SPARCbook contain a 3.5" floppy disk drive. The UPC provides an NEC765 compatible command set for control of the drive, and the SPARCbook's operating system allows 720Kbyte and l.4Mbyte SUN and DOS format disks to be read and written.

Centronics Interface The UPC provides control and data buffering for the parallel interface which appears on the rear panel of the SPARCbook. This interface supports connection to a printer with a Centronics interface.

External Mouse/Keyboard Interface The UPC provides data buffering and control over a serial interface. This interface supports the connection of an external mouse or keyboard and appears via a 6-way mini DIN socket on the rear panel. This interface operates with TIL signal levels and does not allow the connection of RS232 devices.

RS232 Serial Interface In addition to the Tl1.. serial interface, the UPC provides data buffering and control over an RS232 serial interface.

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MICROCONTROLLERSUBSYSTEM

An 87C51 microcontroller provides control over the in-built keyboard, the bit 1/0 interface and the power management functions.

The bit 1/0 interface enables aspects of the SPARCbook's functionality to be controlled in software using keyboard commands. The microcontroller interprets certain special characters from the keyboard as being commands, and carries out system configuration changes accordingly. This includes display screen brightness and contrast.

The bit J/O interface also controls the LEDs next to the display in order to convey machine status information to the user.

The power management function maintains a constant check on the condition of the supply voltages, and provides early warning when the battery requires recharging. Recharging is carried an in-built power supply unit and battery charger when the SP ARCbook is connected to an external electricity supply.

The microcontroller also provides control over the Mousekey.

ETHERNET INTERFACE

The SP ARCbook is equipped with an IEEE802.3 compliant Ethernet interface controlled by a ·86960 Network Interface Controller with Encoder (NICE) from Fujitsu. This provides complete control over the network interface.

The NICE has direct control over a 64Kbyte area of SRAM in which it maintains receive and transmit buffers. The host is able write data into the ll'ansmit buffer and read data of the receive buffer via port in the NICE's address space. The NICE is able to carry out network operations with minimal demand on the CPU, and an integral driver and receiver interfaces directly to the 15-way D-type socket at the rear of the unit.

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MODEM

The SPARCbook's modem interface is implemented with chipset comprising a Sierra SCI I075 Modem Access Controller {MAC) and SCI 1054. The SCI 1075 provides a direct interface between the host system and SCI I054 modem; it incorporates an Intel 8096 equivalent processor core, supporting an AT command set; it contains a built-in I6C450 equivalent UART; and it contains I6Kbytes of on-chip ROM and 320bytes of RAM.

The SC I 1054 is a complete 2400bps (bits per second) modem IC which. when combined with the SCI 1075, provides Sendfax capability up to 9600bps.

The modem interface can be controlled completely using Hayes compatible commands written to the UART section of the MAC. Commands are sent to the interface using character strings, and these are interpreted by the MAC' s in-built processor core and acted on appropriately.

Command characters and data for transmission onto the telephone line are written into the UART's transmit buffer. Data received from the telephone line and status information from the MAC can be read from the UART's receive buffer.

REAL TIME CWCK AND EPROM

Many of the background operations of the SPARCbook, such as system startup and battery condition monitoring, are controlled by the Tadpole resident finnware monitor. This is a body of software (most often referred to as finnware) that is permanently stored in an EPROM and is not erased when the machine is without power.

A 48T02 provides a battery backed real time clock and non-volatile RAM. This provides time of day clock and calendar functions and a 2Kbyte area of RAM which retains data when the board is without power.

A IMbit serially accessed EEPROM is used by the resident firmware to store the SPARCbook's Ethernet address and manufacturing information. The EEPROM is accessible via the microcontroller.

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SPARCbook TECHNICAL SPECIFICATION

• Processor and Memory Processor 25MHz CY601 Integer Unit

Cache Controller/MMU 25MHz CY604 CMU Cache 64Kbyte direct mapped virtual cache

FPU (optional) 25MHz CY602 Floating Point Unit DRAM (standard) 8Mbytes with byte parity

DRAM (-E models) 32Mbytes with byte parity

• Components

EPROM

SERIAL

MISC

128Kbytes - lMbyte One 8-bit 32-pin JEDEC socket

UPC One asynchronous RS232 port TxD, RxD, CT'S, RTS, DCD, DTR,DSR,RING

MK48T02 RTC/2Kbyte DRAM with battery backup NMC93C46 lKbit EEPROM

NETWORK Fujitsu NICE Controller IEEE802.3 interface with local buffer memory

DISK 82C710 UPC Controller Two IDE disks supported Floppy disk controller

• 1/0 Interfaces Ethernet IEEE802.3 compliant

15-pin D-type AUi interface with slidelock Centronics IBM PS/2 compatible interface

36-pin miniature D-type with cable to 25-pin D-type socket

Mouse/Keyboard IBM PS/2 compatible (TIL) 6-pin mini-DIN socket

Modem 2400baud data and 9600baud SendFax FCC Part 68 compliant, 0.3 REN V.29, V.27ter, V.22bis, V.22, V.21 Bell 212A, Bell 103 standards RJl 1 jack socket

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• Peripherals

• Display

• Keyboard

• LEDs

VGA 640x480 25.057MHz dot clock 800x600 36.242MHz dot clock (external monitor) 15-pin PS!2 compatible D-type connector

Serial 110 to 38400baud 9-pin mini-DIN connector

Winchester disk 85Mbyte formatted IDE interface or 125Mbyte formatted IDE interface, depending upon model One or two drives per system Maximum transfer rate 8Mbyte/s buffer to memory Maximum sustained transfer rate 1.8Mbyte/s

Floppy disk 720Kbyte/l.44Mbyte formatted 3.5" floppy disk drive Fitted in single Winchester disk models

Monochrome 640x480 VGA paper-white display side-lit Displays 16 gray scales from 64

Color (-C models) 640x480 VGA color STN display side-lit Displays 16 colors from 256

82-key notebook style with integral Mousekey based upon Force Sensitive Resistor (FSR) technology

External DC supply connected Hard disk active User controlled indicator Battery low/exhausted indicator

• Case and Emissions Magnesium alloy AZ91 castings SPARCbook is certified to FCC Part 15 Class B

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• Power Supply

• Physical

Internal Swirched mode PSU with battery charge and charge detection facilities

External Universal input 110V-240V AC Output 18V 0-3.lA DC

Dimensions 11.8" x 8.5'' x 1.95" Weight (with battery) 6.8lbf7.0lb (monochrome/color)

(without battery) 5.2lb/5.4lb (monochrome/color)

• Environmental Temperature (operational) 5-40 degrees Celsius

(storage) -20- 60 degrees Celsius Vibration (operational) 5-lOOHz 0.25G

(storage) 5- lOOHz 1.2G Shock (operating) 4G

(storage) 500 Humidity (operating) 8-80% relative humidity

• Operating System SunSoft Solaris 1.01 SPARCbook Version A

Comprising SunOS 4.1.2 sun4m architecture Open Windows V3 SPARCbook utilities Meets SPARC Compliance Definition (SCD) 1.1

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SPARCbook DETAILED ADDRESS MAP

This section provides a detailed address map for the SPARCbook. Please note the meanings of the following abbreviations used in the address map. All addresses are shown in hexadecimal.

R/W: R =read, W =Write SIZE: b = byte, h= halfword (16-bits), w= word (32-bits), d = doubleword (64-bits)

DRAM

ADDRESS

000000000 - 0007FFFFF 000000000 - OOlFFFFFF

Display Controller

OOCOOOOOO - OOCCFFFFF OOC0003B4 OOC0003B5 OOC0003CO

OOC0003Cl OOC0003C2

OOC0003C3 OOC0003C4 OOC0003C5 OOC0003C6 OOC0003C7

OOC0003C8 OOC0003C9 OOC0003CA OOC0003CC OOC0003CE OOC0003CF OOC0003D4 OOC0003D5 OOC0003DA

OOC0046E8

DEVICE or REGISTER

DRAM (8Mbyte) DRAM (32Mbyte)

R/W

R/W R/W

CL-GD6410/CL-GD6340t r;_.; c: in1!J~0f ~ '!/:0

CRTCindexMP ti {O b '- 5 R/W CRTC Data MP R/W Attribute Controller Index R/W Data W Attribute Controller Data R Misc Output W Feature R Motherboard Sleep Address R/W Sequencer R/W Sequencer R/W RAMDAC Pixel Mask R/W RAMDAC Address - Read Mode W RAMDAC Status Register R RAMDAC Address - Write Mode W RAMDAC Data R/W Feature Control R Misc Output R Graphics Controller and Extensions Index R/W Graphics Controller and Extensions Data R/W CRTC Index R/W CRTC Data R/W Feature Control W Display Status R AT Adapter Sleep Address R/W

SIZE

b/h/w/d b/h/w/d

b b b b b b b b b b b b b b b b b b b b b b b

Note t CL-006340 only present in color models. It contains RAMDAC registers shadow mapped over similar CL-GD6410 registers.

22


-u lJ u u Ethernet Controller

ADDRESS DEVICE or REGISTER R/W SIZE

u OOC200000 - OOCFFFFF Fujitsu 86960 NICE OOC200000 Transmit Status R/W b OOC200001 Receive Status R/W b

u OOC200002 Transmit Interrupt Mask R/W b OOC200003 Receive Interrupt Mask R/W b OOC200004 Transmit Mode R/W b OOC200005 Receive Mode R/W b

I . OOC200006 Control Register 1 R/W b I I OOC200007 Control Register 2 R/W b LJ OOC200008 Node ID (Register Bank 0) R/W b

Mask Address (Register Bank 1) R/W b

u Buffer Memory Port (Register Bank 2) R/W h OOC2()()()()1) Node ID (Register Bank 0) R/W b

Mask Address (Register Bank 1) R/W b OOC20000A Node ID (Register Bank 0) R/W b u Mask Address (Register Bank 1) R/W b

Transmit packet Control 1 (Register Bank 2) R/W b OOC20000B Node ID (Register Bank 0) R/W b

u Mask Address (Register Bank 1) R/W b Transmit packet Control 2 (Register Bank 2) R/W b

OOC20000C Node ID (Register Bank 0) R/W b Mask Address (Register Bank 1) R/W b

u OMA Enable (Register Bank 2) R/W b OOC20000D Node ID (Register Bank 0) R/W b

Mask Address (Register Bank 1) R/W b OMA Burst Control (Register Bank 2) R/W b

u OOC20000E TDR (LSB) (Register Bank 0) R/W b Mask Address (Register Bank 1) R/W b Receive Buffer Pointer (Register Bank 2) R/W b

u OOC20000F TDR (MSB) (Register Bank 0) R/W b

Mask Address (Register Bank 1) R/W b

Note: Register Bank 0, 1 and 2 are selected using bits 2 and 3 of Control Register 2

u u u LJ 23

u

Modem Interface

ADDRESS DEVICE or REGISTER R/W

OOC400000 - OOC4FFFFF Sierra SCl 1075 - UART Registers OOC400000 Receive Buffer R

Transmit Buffer w Divisor Latch (LSB)t R/W

OOC400001 Interrupt Enable R/W Divisor Latch (MSB) t R/W

OOC400002 Interrupt ID R OOC400003 Line Control R/W OOC400004 Modem Control R/W OOC400005 Line Status R/W OOC400006 Modem Status R/W OOC400007 Scratch Pad R/W

Note: t The divisor latch can be accessed only when bit 7 of the Line Control Register is set

Real Time Clock I SRAM

OOC600000 - OOC7FFFFF OOC600000 OOC6007F8 OOC6007F9 OOC6007FA OOC6007FB OOC6007FC OOC6007FD OOC6007FE OOC6007FF

MK48T02 SRAM Calibration Seconds Minutes Hours Day Date Month Year

16-Bit 110 Region - Hard Disk Data Interface

OOC800000 - OOCBFFFFF OOC8001FO IDE - Hard Disk Data Interface

24

R/W R/W R/W R/W R/W R/W R/W R/W R/W

R/W

SIZE

b b b b b b b b b b b

b/h/w/d b b b b b b b b

h


u u u u

8-Bit 110 Region - UPC Associated Interfaces

ADDRESS DEVICE or REGISTER R/W SIZE

u OOCCOOOOO-OOCEFFFFF 82C710 Universal Perpheral Controller OOCCOOlFl IDE - Error Register R b OOCC001F2 IDE - Sector Count R/W b OOCC001F3 IDE - Sector Number R/W b

u OOCC001F4 IDE - Cylinder Low R/W b OOCC001F5 IDE - Cylinder High R/W b OOCC001F6 IDE - Drive/Head Register R/W b OOCC001F7 IDE - Status Register R b

u IDE - Command Register w b OOCC003F6 IDE - Alternate Status R b

IDE - Fixed Disk Register w b

u OOCC00310 Mouse Port - Data Register R/W b OOCC00311 Mouse Port - Status/Control Register R/W b

u OOCC00330 Parallel Port - Data Register R/W b OOCC00331 Parallel Port - Status Register R b OOCC00332 Parallel Port - Command Register w b

u OOCC00390 UPC Configuration Index w b OOCC00391 UPC Configuration data R/W b

u OOCC003F2 Floppy l/F - Digital O/P Register w b OOCC003F4 Floppy l/F - Main Satus Register R b OOCC003F5 Floppy l/F - Data Register R/W b OOCC003F7 Floppy l/F - Data Rate w b

, I Floppy l/F - Digital Input Register R b

~ OOCC003F8 UART - Receive Buffe R b UART - Transmit Buffer w b

u UART - Baud Rate Divisor (LSB)t R/W b OOCC003F9 UART- Interrupt Enable Register R/W b

UART - Baud Rate Divisor (MSB)t R/W b OOCC003FA UART- Interrupt Flag Register R/W b

u OOCC003FB UART - Byte Format Register R/W b OOCC003FC UART - Modem Control Register R/W b OOCC003FD UART- Line Status Register R/W b

LJ OOCC003FE UART - Modem Status Register R/W b OOCC003FF UART- Scratch Pad R/W b

Note: t The Baud Rate Divisor Registers can only be accessed when bit 7 of the Byte Control Register is set.

u u 25

u

MP/ASIC

ADDRESS DEVICE or REGISTER R/W

00000000 - OODFFFFFF Mbus to Pbus Interface Controller 000000000 Mbus Error Status R 000000010 Set Count CTO R/W OOOOOOOI8 Current Count CTO R 000000020 ControlCTO R/W 000000028 Set Count CTI R/W 000000030 Current Count CTI R 000000038 Control CTI R/W 000000050 Interrupt Pending R 000000058 Interrupt Polarity R/W 000000060 Interrupt Enable R/W 000000068 Interrupt Acknowledge w 000000070 Serial Receive Port R 000000088 Serial Receive Status R 000000090 Serial Transmit Port w 000000098 Serial Transmit Data w OOOOOOOAO Reset R/W OOOOOOOA8 Clock Control R/W OODOOOOB8 Power Down w OODOOOOCO FIFO Start Address R./W OODOOOOC8 FIFO Control R/W OODOOOOF8 FIFO Data R/W

R/W: R =read, W =Write SIZE: b = byte, h = halfword (16-bits), w = word (32-bits), d = doubleword (64-bits)

26

SIZE

b w w b w w b w w w w b b b b b b b w w d


u u u u u u u LJ

u u u u u u 1 1 -u u u

CHAPTER TWO ARCHITECTURE

One of the factors that contributes to the compactness of the SPARCbook is that at its heart is a single board of less than 12 square inches, the Base Board. This one board carries the processor module, provides 8 or 32Mbytes of memory and provides all of the control required for the display, keyboard, disks and interfaces.

This section provides a brief description of the architecture of the SP ARCbook. Figure 2-1 shows how the main components connect together.

:······························, '

El!PllOM

CY7ao4 CV70602 CY7alll MCT FPU RJ

8701 Miaocontroller

EPROM

' ························ __ ..... __ l/32Mbyla

DRAM

Power Supply Unit 111d Bonory C.arac:r

.. ' · ....................................... .. ........................ / OC M- RS23lC Panllel l!diomot Modem ID Port Serial Oontronica

Figure 2-1 SP ARCbook Internal Architecture

27

BUS STRUCTURE

It will be seen from Figure 2-1 that the SPARCbook is based on a dual bus architecture, with the SP ARC CPU and DRAM connected to a fast 64-bit bus, called the Mbus, and the 1/0 devices connected to a 16-bit peripheral bus called the Pbus.

The SP ARC processor is the only Mbus master device and is able to access all locations in DRAM, and locations on the Pbus via the MPI.

As described in the previous chapter, the SPARC CPU comprises the integer unit, floating point unit and the combined memory management unit and cache controller. These communicate via a private address bus which remains local to the SPARC chipset This consists of a 32-bit address bus, an 8-bit address space identifier bus, and a 32-bit data bus. The IU uses logical (or virtual) addresses as labels to identify locations in its address space. The memory management unit translates the virtual addresses used on this bus into physical addresses used on the M-bus.

Mbus

The Mbus is an address and data multiplexed bus, which means that some of the wires are used to carry both address information and data, though at different times. The time when address information is on the bus is the address phase, and the time when data is on the bus is the data phase. In a SPARC based environment, a bus cycle consists of an address phase followed by one data phase for single access cycle, or an address phase and four data phases for a burst cycle.

The memory management unit produces a physical address on Mbus(35:0) and, during the address phase of the Mbus, provides bus control information on Mbus(45:36). The whole bus, Mbus(63:0), is used to transfer data during the data phase.

Pbus

The Pbus is a 16-bit PC-AT style bus which supports the on-board 1/0 devices. It consists of 16 data lines, PD(l5:0), and 19 address lines, PA(l8:0). The CPU addresses and exchanges data with the disk, Ethernet , modem and serial interfaces and the EPROM and RTC using the Pbus.

28


u u u u u u u u u u u I I w

' I u u LJ

LJ

u u

Mbus - Pbus Interface

The gateway between the Mbus and Pbus is provided by the Mbus to Pbus Interface controller (MPI), a Tadpole Technology designed custom ASIC (Applications Specific Integrated Circuit).

The MPI provides an internal 512byte bidirectional FIFO, address decode facilities for the Pbus, interrupt support and two internal counter/timers. It provides a byte packing interface which converts between 8-, 16-, 32- and 64-bit accesses used on the Mbus, and 8- and 16-bit accesses used on the peripheral bus. This allows the two buses to operate at their optimum speed.

The MPI provides two data paths between the Mbus and Pbus .. The first path provides direct access by the CPU to the Pbus devices, and the second path is via the MPI's internal 512byte FIFO. The MPI also provides DMA support for floppy disk operations.

In addition to providing an interface between the Mbus and Pbus, the MPI contains a fifteen level interrupt controller and two 16-bit counter/timers. The interrupt controller section is used to consolidate the large number of interrupt requests from devices within the SPARCbook, and from the FIFO controller and counter/timers within the MPI. Interrupt controller provides the CPU with a code which identifies a pending interrupt, and allows individual interrupts to be masked

29

u u u u u u u u u u 1 1 L-"

LJ

u u u LJ

u u

CHAPTER THREE THE SPARC CPU MODULE

The SPARC CPU module comprises the CY7C601A integer unit {IU), the CY7C602A floating point unit (FPU), and the CY7C604A cache controller and memory management unit (CMU). In the SPARCbook implementation, these are carried on a small module along with two CY7Cl57 A cache storage units (CSU).

The devices on the SP ARCbook CPU module are connected together via a 32-bit virtual address bus and a 32-bit data bus. The CMU provides an interface between this bus and the Mbus. The Mbus is a SPARC architecture standard 64-bit multiplexed address and data bus that provides the SPARCbook with a high bandwidth data path between the CMU and main memory. The CMU performs address translations between these buses and provides memory management and cache control functions. The two CY7Cl57 A SRAMs provide 64Kbytes of zero wait-state cache memory.

CY7C601 Integer Unit

A(31:0) :: 0(31:0)

CY7C602 Floating Poim

Unit

A(31:0) 0(31:0)

.· .. ·•·.· .. -........................ ·.·.·.•.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.· .. ·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.·.· .. ·.::·

CY7C604A Cache ConD'Oller/

Memory management Unit

A(IS:2)

Figure 3-1 The SPARC CPU Module

0(31:0)

2xCY7ClS7A 64Kbyte

Cache

31

CY7C601A INTEGER UNIT

The IU is the main processing engine that executes all of the instruction set except for floating point operations.

Instructi.ons Overview

The CY7C600 architecture supports 62 integer instructions which fall into the following basic categories:

Load and Store Instructions Arithmetic, Logical and Shift Instructions Control Transfer Instructions Read/Write Control Registers Instructions

The load and store instructions are the only instructions which cause the movement of data on the Mbus. They use two registers, or a register and a constant, to calculate the memory address involved. Halfword accesses must be aligned on 2-byte boundaries, word accesses on 4-byte boundaries, and doubleword accesses on 8-byte boundaries. These alignment restrictions greatly speed up memory access.

The arithmetic, logical and shift instructions compute a result that is a function of one or two source operands and then place the result non-destructively in a register. They perform arithmetic, logical, or shift operations.

The control transfer instruction category includes jumps, calls, traps, and branches. Control transfers are usually delayed until after execution of the next instructions so that the pipeline is not emptied every time a control transfer occurs, allowing compilers to be optimized for delayed branching.

The read/write control register instructions include instructions to read and write the contents of various control registers. Generally the source or destination is implied by the instructions.

In addition to the instruction types within the categories listed above, there are Floating Point instructions executed by the FPU.

Table 3-1 provides a summary of the IU instruction set

32


u u u u INPUTS OPERATION

Load and Store Instructions LDSB(LDSBA*) Load Signed Byte (from Alternate Space)

u LDSH(LDSHA*) Load Signed Halfword (from Alternate Space) LDUB(LDUBA*) Load Unsigned Byte (from Alternate Space) LDUH(LDUHA*) Load Unsigned Halfword (from Alternate Space) LD(LDA*) Load Word (from Alternate Space)

u LDD(LDDA*) Load Doubleword (from Alternate Space) LDF Load Floating Point LDDF Load Double Floating Point LDDFSR Load Floating Point Status Register

u LDC Load Coprocessor LDDC Load Double Coprocessor LDDCSR Load Coprocessor Status Register STB(STBA*) Store Byte (In Alternate Space)

LJ STH(STHA*) Store Halfword (In Alternate Space) ST(STA*) Store Word (In Alternate Space) STD(STDA*) Store Ooubleword (In Alternate Space) STF Store Floating Point

u STDF Store Double Floating Point STFSR Store Floating Point Status Register STDFQ* Store Double Floating Point Queue STC Store Coprocessor

u STDC Store Double Coprocessor STCSR Store Coprocessor Status Register STDCQ* Store Double Coprocessor Queue

u LDSTUB(LDSTUBA *) Atomic Load/Store Unsigned Byte (In Alternate Space) SWAP(SWAPA*) Swap r Register With Memory (In Alternate Space)

' Arithmetic, Logical and Shift

u ADD(ADDcc) Add (Modify ice) ADDX(ADDXcc) Add With Carry (Modify ice) T ADD(T ADDccTV) Tagged Add and Modify ice (and Trap on Overflow) MULScc Multiply Step and Modify ice

u AND(ANDcc) AND (Modify ice) ANDN(ANDNcc) AND NOT (Modify ice) OR(ORce) OR (Modify ice) ORN(ORNce) OR NOT (Modify ice)

u XOR(XORce) Exclusive OR (Modify ice) XNOR(XNORcc) Exclusive NOR (Modify ice) SLL Shift Left Logical SRL Shift Right Logical

u SRA Shift Right Arithmetic SETHI Set High 22 Bits of r Register SAVE Save Caller's Window RESTORE Restore Caller's Window

LJ

u 33

u

INPUTS OPERATION

Control Transfer Bice Branch on Integer Condition Codes FBicc Branch on Aoating Point Condition Codes CBccc Branch on Coprocessor Condidition Codes CALL Call JMPL Jwnp and Link RETT Return from Trap Tice Trap on Integer Condition Codes

Read/Write Control Registers ROY Read Y Register RDPSR Read Processor State Register RDWIM Read Window Invalid Mask RDTBR Read Trap Base Register WRY Write Y Register WRPSR* Write Processor State Register WRWIM* Write Window Invalid Mask WRTBR* Write Trap Base Register UNIMP Unimplemented Instruction !FLUSH Instruction Cache Hush

FP and Coptoceuor Ops FPop Aoating Point Operations CPop Coprocessor Operations

* Privileged instuctions

Table 3-1 Instruction Set Summary

CY7C601A Internal Registers

The IU contains two types of registers, working registers (or r registers) and control registers. The r registers are used for storage by processes and the control registers are used to track and control the state of the IU. The r registers are contained within a large register file containing one hundred and thirty-six 32-bit registers. Eight of these are global registers and are always accessible to a program, and the remaining registers are accessed via register windows.

Figure 3-2 shows the register window organization

34


u u u u u u u u u u LJ

u u u u LJ

u u

The register file contains eight register windows, and each window contains twenty-four working registers. Each register window is divided into three sections called ins, outs, and locals. There are eight registers in each of these sections. A window shares its ins and outs with adjacent windows. The outs of the previous window are the ins of the current window, and the outs of the current window are the ins of the next window. The windows are joined together in a circular stack where the outs of the last window are the ins of the first window.

A current window pointer (CWP) in the processor state register keeps track of which window is currently active. The CWP is decremented when the program calls a subroutine that causes the processor to access to the next window, and is incremented when the processor returns to the previous window.

Register windows may be marked as invalid in the WIM register, and interrupts may be enabled to signal when movement into an invalid window is caused by an instruction.

Previous Window r31

INS r24 r23

LOCALS r16 rl5

OUTS r8

Current Window

!IJ'll.l,_!1111~11.=m!::llilllllilllllllll,

Figure 3-2 Window Register Organization

35

Next Window

INS

r23

LOCALS r16 r15

OUTS r8

n n n

Control Registers These include the Processor State Register, the Window Invalid Mask Register, the Trap Base Regis- n ter, the Y Register, illustrated in Figure 3-3, and the Program Counter.

Processor Status Register

31 28 27

imp

31

24 23

vcr

20 19 14 13 1211 8 7 6 s 4 0

ICC lfJlf~~"§faiffaiJECjEFI PIL CWP

8 7 0

w~e=d Mask :::::tltlMilttllltMfllllltH~¥.R~lMtlMWtHftfiHtt::::::nutmm::~:

Trap Bue Register

31

Trap Base Address

Window7

Window 6 ----'

Windows

Window4

Window3

Window2

Window 1

WindowO

1211 4 3 2 1 0

TrapTypc I I I I I

n n n n n

Figure 3-3 IU Control Registers n The Processor Status Register (PSR) contains a number of fields that control the processor and hold status information. The PSR is modified by SA VE, RESTORE, Tice and RETT instructions, and also n by all instructions that modify the condition codes. The privileged instructions RDPSR and WRPSR read and write the PSR directly.

Bits 31:28 impl- identifies the implementation of the IU

Bits 27:24 ver - identifies the version number of the IU

Bits 23:20 ice-contains the IU 's condition code and are set by the conditions occurring during integer logic and arithmetic operations: Bit 23 = Negative flag Bit 22 = Zero flag Bit 21 = Overflow flag Bit 20 = Carry

Bits 19:14 Reserved

Bit 13 EC - Enable Coprocessor. This feature should remain disabled

36

n n n n n n n

u u u u u u u u u LJ

u u

u u LJ

u u

Bit 12

Bits 11:8

Bit 7

Bit 6

Bit5

Bits 4:0

EF - Enable Floating Point Unit. This bit enables the FPU. An FP instruction will trap if the EF = 0, or if an FPU is not fitted.

PIL - identifies the interrupt levels in operation. The IU will only accept intenupts whose level is greater than the contents of this field.

S-Supervisor. This bit determines whether the processor is insupervisororusermode. S = 1 selects supervisor mode.

PS - Previous Supervisor. This bit indicates the value of the S bit at the time of the most recent trap.

ET - Enable Traps. This bit determines whether traps are enabled. A trap automatically resets ET. When ET = 0, an interrupt request is ignored and an execution trap causes the IU to halt execution, typically resulting in a reset trap.

CWP - Current Window Pointer. This field identifies the current window into the r registers. Hardware decrements the pointer when traps are encountered and on SA VE instructions. The pointer is incremented on RESTORE and RE'IT instructions

Window Invalid Mask Register The Window Invalid Mask Register {WIM) allows windows to be marked as invalid in the WIM register. Movement into an invalid window caused by a SA VE, RES'IORE or RE'IT instruction will cause a window overflow or underflow interrupt to be generated.

Trap Base Register The Trap Base Register contains three fields that generate the address of the trap handler when a trap occurs.

Bits 31: 12 Trap Base Address. This contains the most significant 20 bits of the trap table address.

Bits 11:4

Bits 3:0

Y Register

Trap Type. This field is written by hardware at the time of a trap. It provides an offset into the trap table.

Reserved - Should always be written as zeros.

The Y Register is used to store the partial product during multi-step instructions.

Program Counter The Program Counter (PC) contains the address of the instruction being executed. The next Program Counter contains the address of the next instruction to be executed.

37

Traps and Interrupts

The CY7C600 design supports a full set of traps and interrupts. They are handled by a table that supports 128 hardware and 128 software traps. Even though floating-point instructions can execute concurrently with integer instructions, floating-point traps are precise because the FPU supplies (from the table) the address of the instruction that failed.

The IU supports both asynchronous traps (interrupts) and synchronous traps (error conditions and trap instructions). Traps transfer control to an offset within the trap table. The base address of the table is specified by the Trap Base Register and the off set is a function of the trap type. Traps are taken before the current instruction causes any changes visible to the programmer and can therefore be considered to occur between instructions.

Table 3-2 shows priority levels of the exceptions and traps.

Interrupts from the peripheral devices within the SP ARCbook are controlled and prioritized by the Mbus to Pbus interface (MPI) ASIC (see Chapter 5).

Memory Protecti.on

The CY7C600 design provides memory protection, which is essential for smooth multitasking operation. Memory protection makes it impossible for user programs to corrupt the system, other user programs, or themselves.

The IU supports a multitasking operation system by providing user and supervisor modes. Some• instructions are privileged and can only be executed while the processor is in supervisor mode. Changing from user to supervisor mode requires taking a hardware interrupt or executing a trap instruction. This instruction execution protection ensures that user programs cannot accidentally alter the state of the machine with respect to its peripherals.

38


u u u u TRAP PRIORITY OFFSET

Reset 1 ?? Instruction access exception 2 OxOl

u Illegal Instruction 3 Ox02 Privileged Instruction 4 Ox03 FP Disabled 5 Ox04 CPDisabled 5 Ox24

u Window Overflow 6 Ox05 Window Underflow 7 Ox06 Unaligned Memory Address 8 Ox07

u FP Exception 9 Ox OS CP Exception 9 Ox28 Data Access Exception 10 Ox09 Tag Overflow 11 OxOA

u Trap Instruction 12 Ox SO OxFF

Intenupt Level 15 - Microcontroller/Floppy Disk 13 OxlF

u Intenupt Level 14 - Battery Power Low 14 OxlE Intenupt Level 13 - MPI (Cowtter/timer 0) 15 OxlD Intenupt Level 12 - MPI (Cowtter/timer 1) 16 OxlC

u Intenupt Level 11 - MPI (Keyboard buffer) 17 OxlB Intenupt Level 10 - Mouse 18 OxlA Intenupt Level 9 - Serial Port 19 Oxl9 Intenupt Level 8 - Modem 20 Oxl8

u Intenupt Level 7 - Ethernet Interface 21 Oxl7 Intenupt Level 6 - VGA Controller 22 Oxl6 Intenupt Level 5 - Hard Disk Interface 23 Oxl5 Intenupt Level 4 - MPI (FIFO Full/Empty) 24 Oxl4

u Intenupt Level 3 - MPI (FIFO Op Complete) 25 Ox13 Intenupt Level 2 - Microcontroller/Floppy Disk 26 Oxl2 Intenupt Level 1 - Centronics Interface 27 Oxll

: I lJ

Implementation Dependent Exceptions Dependent Ox60- 7F

Table 3-2 Trap Table

u u u LJ 39

u

FLOATING POINT UNIT

The FPU provides high-perfonnance, IEEE STD-754 compatible single- and double-precision floating-point calculations for CY7C(i()() systems and is designed to operate concurrently with the IU. All address and control signals for memory accesses by the FPU are supplied by the IU.

Overview

The IU and FPU are able to execute instructions simultaneously. The FPU perfonns all floating-point calculations with its own set of registers and arithmetic and logic unit

Floating-point instructions are addressed by the IU, and are simultaneously latched from the data bus by both it and the FPU. Floating-point instructions are concurrently decoded by the IU and the FPU, but do not begin executing in the FPU until after the instruction is enabled by a signal from the IU. Pending and currently executing FP instructions are placed in an on-chip queue while the IU continues to execute non-floating-point instructions.

Floating Point Registers

The FPU contains thirty-two 32-bit floating-point F registers. These fonn a 32 x 32-bit register file. The contents of these registers are transferred to and from external memory under control of the IU using floating-point load/store instructions. Addresses and control signals for data accesses during a floating-point load or store are supplied by the IU, while the FPU supplies or receives the data.

31 0 £31

£30 . . . . . . fl

m

Figure 3-4 F Registers

40


I I

LJ

u u

u LJ

u I

iU iu u u u u u u u

Although the FPU operates concurrently with the IU, a program containing floating-point computations generates results as if the instructions were being executed sequentially.

Figure 3-4 illustrates the F registers.

A single F register is able to one single-precision operand, two are required to hold a double precision operand, and four are required to hold and extended precision operand.

Floating-Point State Register

The floating-point status register (FSR) contains mode and status infonnation about the FPU. It is read and written using the STFSR and LDFSR. Figure 3-5 illustrates the FSR.

FPU State Register

31 30 29 28 27

Figure 3-5 FSR

23 2221 17 16 14 13 12 11 10 9

7 AU

5 4

aexc CCXC

Bits 31 :30 RD - Rounding Direction. These select the rounding direction for floating-point results: 00= Nearest 01 =Zero lO=+oo

11 =--Bits 29:28 RP - Extended Rounding Precision

00 = Extended 01 =Single 10= Double 11 =Unused

Bits 27:23 TEM - Trap Enable Mask. These are enable bits for each of the five floating-point exceptions: Bit 27 = Invalid Operation Trap Mask Bit 26 = Overflow Trap Mask Bit 25 = Underflow Trap Mask Bit 24 = Divide by Zero Trap Mask Bit 23 = Inexact Trap Mask

0

Bit 22 AU -Abrupt Underflow. When set, this bit causes denormalized FP operands or results to be rounded to zero.

Bits 21:17 Reserved

41

Bits 16: 14 ftt - Floating-Point Trap Type. These indicate the type of exception: O=None 1 = IEE E Exception 2 = Unfinished FP operation 3 = Unimplemented FP operation 4 = Sequence Error 5-F = reserved

Bit 13 qne - Queue Not Empty. When set, this bit indicates that the FP queue is not empty following an FP exception or STDFQ instruction was executed.

Bit 12 Reserved

Bits 11: 10 fee - FPU Condition Codes. These bits are updated by FP compare instructions: 00 = fsrl = fsr2 01 = fsrl < fsr2 10 = fsrl > fsr2 11 = fsrl ? fsr2 (unordered)

Bits 9:5 aexc - Accrued Exception Bits.

Bits 4:0

Bit 9 = Accrued Invalid Operation Bit 8 =Accrued Overflow Bit 7 = Accrued Underflow Bit 6 = Accrued Divide by Zero Bit 5 = Accrued Inexact

cexc - Current Exception Bits Bit 4 =Current Invalid Operation Bit 3 = Current Overflow Bit 2 = Current Underflow Bit 1 = Current Divide by Zero Bit 0 = Current Inexact

42


u u I I w

u u u I I

LJ

u LJ

u u

. I I I w

LJ

u u u

CACHE CONTROLLER AND MEMORY MANAGEMENT UNIT

The interface between the bus, on which the IU, FPU and cache memory reside, and the Mbus, on which the main memory and peripheral interfaces reside, is provided by a CY7C604 Cache Controller and Memory Management Unit (CMU). This device provides translation between the 32-bit virtual addresses used on the CPU module and 36-bit physical addresses used on the Mbus. It provides hardware support for a demand-paged virtual memory environment for the IU. The Page size is fixed at 4Kbytes. The CMU also manages a 64Kbyte cache memory.

Memory Management Unit

The memory management unit (MMU) conforms to the standard SPARC architecture definition for memory management

The MMU provides virtual to physical address translation using a translation lookaside buffer (TI..B}. This is an area of specialized on-chip memory containing sixty-four Page Table Entries (PTE) as shown in Figure 3-6.

Virtual Section Physical Section

/r~~~J/'...~~~~- -~~~~~~~-/'...~~~~~~~--' / ' VA(31:12) CXN(ll:O) I PPN(35:12) IC !Ml ACC(2:0) ST(l:O) v

i i i l i i i i

I 64n1~.,J,

VA(31:12) CXN(ll:O) I PPN(35:12) c M ACC(2:0) ST(l:O) v

Figure 3-6 Translation Lookaside Buffer

Each entry within the TLB contains a virtual section and a physical section. The virtual section comprises a virtual address field, for comparison with V A(31: 12), and 12-bit context field, for comparison with the contents of the context register.

43

The physical section contains the physical address field, PPN(35: 12), a cache control bit, a modified bit, a 3-bit access protection field, a translation control field, and a valid bit

Bits (31:12) of the virtual address are translated and expanded to physical address bits (35:12). During an access by the IU, the virtual address supplied by the IU and the contents of the context register are compared with the virtual section of all sixty-four entries simultaneously. When a match is found (or a "hit" occurs), the physical address field PPN(35: 12) supplies the address of a 4Kbyte page in memory. Virtual address bits A(l 1:00) from the IU are passed through unchanged to supply a byte offset. This is illustrated in Figure 3-7. Each hit TLB entry is checked for memory protection attributes automatically and violations are reported to the IU as memory exceptions.

31 24 23 18 17 12 11 0

Virlual Address Index I lndex2 Index 3 Page Offset

TLBEnuy

Hit Dcteaion Logic

ASl(S:O)------------------RD-------------------.-i

Context register

ACC(2:0) ST(! :0) V

Access Violation IDST0--------------------1-i..._ _______ _J

Figure 3-7 Address Translation

If the virtual address from the IU does not match an entry in the TLB, the CMU automatically performs a search (or table walk) through a translation table in main memory to obtain an address translation.

The translation table forms a tree structure in main memory as illustrated in Figure 3-8. The Context Pointer register provides a pointer to the context table, and the context register provides an index to the Root Pointer, which in turn points to a level 1 page table. Index 1 from the virtual address selects an entry within Level 1 pointing to a level 2 page table, where Index 2 selects a pointer to a level 3 table. Index 3 then selects one of the entries in the level 3 table which should point to a 4Kbyte memory page.

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When a page table pointer (P'IP) is encountered within the tables, the search continues to the next lower level. If a page table entry (PTE) is found, the search is tenninated and the entry is stored in the 1LB. If no PTE is found at all, a synchronous fault exception is signalled to the IU.

The PTE provides a pointer to a physical page while the lower 12 bits of the virtual address provides an offset.

The level at which a table walk tenninates (i.e. a PTE is found) is related to the size of addressing region associated with the entry. A table walk which finds a PTE in the context table corresponds to a region of 4Gbytes. A PTE in level 1 corresponds to a 16Mbyte region, or 256Kbyte in level 2, or 4Kbyte in level 3. The virtual address bits not used to index table entries are used to supply the page offset.

31 24 23 1817 1211 0

Vil'lllal Address I Inda 1 Index. 2 Index. 3 I Offset

L ---------l---------·· ~------- - --------- - -- ----------------------------------I Contellt Pointer I ' ' Contellt Table

' -Resister I ' ' ' Level I Page

' ' ... Table !Cont.en Resiater 1 Root Poinler

' ' Level 2Page ' ' Table ' -' ...... PTP ' ' Leve13 Page ' ... Table - PTP

- PTE -' ' ' ' ~----------------------------------------------------------------------------

35 , 12 11 ! 0

Physical Address I Physical Page Number I Byte Ofrsc:t

Figure 3-8 A Three Level Table Walle in Memory

45

Figure 3-8 shows a table walk which uses three page table levels. In this example A(31:12) from the virtual address are used to index the page tables, and A(l 1 :0) supply an offset address into the selected memory page

Figure 3-9 shows a table walk which terminates at level 2. In this case A(31: 18) are used as index bits, and A(l 7:0) provide an offset address into the selected page.

31 24 23 1817 0

Virtual Address I lndeJ< 1 lnda2 Offset I L

-------_J_ _ ---- ----- --- ---_1_ - - - - - - - - -- -, --------------------' I Context Pointer I Context Table ' - ' ' Register I ' ' Level 1 Pase ' '

!Context Register - Table ' Root Pointer ' - ' ' Levcl2 Pase ' ' - Table ' ' - PI'P - ' ' ' ' ' ...... PT!! .... ' ' ' ' ' ' ' . ' . ' . ' . ' . ' . ' . ' ' . ' . ' . ' . ' .

~--------------------------------------------------------

___ ,

3S ., 18 17 ! 0

Physical Address I Physical Pase Number I Byte Offset I

Figure 3-9 A TwoLevel Table Walk in Memory

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Cache Controller

The cache controller provides access control for the 64Kbyte cache memory implemented on the CPU module.

The cache is organized with 2048 cache lines of 32bytes each, as illustrated in Figure 3-10. The CMU provides on-chip storage for 2048 cache address tags, one for each line. The tag entries can be directly written or read by the processor.

8 x 32-bit Words __ __,A..._ __ _

/ ' VA(lS:S)

64Kbyte Cache' 2048Lines

Figure 3-10 Cache Memory Organization

During an IU read operation, virtual address bits V A(15:5) select one of the 2048 lines and, at the same time, one of the cache tags maintained by the CMU. If the virtual address within a cache tag matches with V A(15:5), and the context field matches with context register, a hit occurs. The cache line represented by the valid tag is selected by the CMU and one or more of the 32bytes in the cache line are selected by V A(4:0) from the IU. If a miss occurs the CMU reads in a new cache line from main memory. Burst accesses are used by the CMU to fill cache lines. Burst accesses are always 64-bits wide and always consist of an address phase followed by four data transfer phases (32bytes in total). The IU is held until the CMU has loaded the new cache line, but this is completely transparent to the programmer.

47

Figure 3-11 illusttates cache tag comparison by the CMU.

Virtual Address I Cache Line Select I Byte Select

31 16 15 s 4 0

I VAP116) aN(ll~ ITl'I '------~~::r=rr1rY~m@=:1r=::rnr:'tt:m:~n~u1r,:¥?MM=1

.------+-i------1 ! 11 I I VA(31:16) CXN(ll:O) lvlMI sl

Context Regisrer I

'. '. ~

' / '" /

I ~

& : CacbeHit

Figure 3-11 Cache Tag Comparison

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CY7C157A CACHE STORAGE UNIT

The CY7C157A cache storage unit is a 16Kbyte x 16 SRAM CSU designed to interface easily to a CY7C600 processor and provide maximum performance. The CSU is a specialized device which has registered address inputs, and latched data inputs and outputs as well as a self-timed write pulse.

The device has a single clock that controls loading of the address registers, data input latches, data output latches, pipeline control latch, and chip enable register. The chip enable is clocked into a register and pipeline through a control register to condition the output enable. This pipeline design allows a cache that works as an extension of the internal instruction pipeline of the IU.

Figure 3-12 shows the internal architecture of a CY7C157 A CSU chip.

Figure 3-12 CSU Internal Architecture

49

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CHAPTER FOUR MAIN MEMORY

The SP ARCbook may be manufactured with either 8Mbytes or 32Mbytes of main memory which provides a 64-bit wide storage for the SPARC CPU. The SPARCbook's Base board is always fully populated with DRAM chips. It is fitted with an array of sixteen lMbit x 4 DRAMs, if equipped with 8Mbytes of memory, or the same number of 4Mbit x 4 DRAMs if equipped with 32Mbytes. Field upgrades are not possible. Two additional DRAMs, of the same size as those used in the main memory array, provide storage for parity bits generated for each byte location.

Figure 4-1 shows the an:hitecture of the main memory.

Figure 4-1 SP ARCbook Main Memory

51

MACH210 l'IJ)

Unc:cm:ctablc Enor

CPU Module

FUNCTIONAL DESCRIPTION

Memory Acces.ws All main memory accesses in the SPARCbook are initiated by the SPARC CPU. It supports single cycle reads and writes of 8, 16, 32 and 64bits, and also burst cycles.

Access Control and memory refresh for the main memory array is provided by a powerful programmable logic device (PLO) containing the equivalent of 1800 logic gates. This, in conjunction with a custom 32-bit buffer chip, provides full addressing suppon for all of the SPARC CPU's memory access cycles.

Parity Checking During writes to DRAM, parity bits are generated for each byte location written to. When the data is read out again, the parity bits and the stored data are checked. Errors in any byte lane are signalled to the PLC which in turn signals an uncorrectable error to the SPARC CPU. Parity checking is enabled via the microcontroller (see Chapter 6), and parity error interrupts are enabled via the MPI (see Chapter 5).

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CHAPTERS MBUS TO PBUS INTERFACE

The SP ARCbook baseboard is based on a dual bus architecture (see Chapter 2). The SP ARC CPU and main memory are located on the SPARC architecture standard 64-bit Mbus, and the peripheral controllers are located on the 16-bit PC-AT style Pbus.

In the SPARCbook, transactions between these two buses are controlled by the Mbus to Pbus Interface conttoller (MPI). This is an application specific integrated circuit (ASIC) designed by Tadpole Technology.

Mbus MAD(63:00)

Mbus ._ _ _.,.-t

aoct Controller and

Power Management Unit

Bus Timer

F.nor ::.c=========~ Counterffimer 0

Cl'U Interrupt Bus IRL(3:0)

Figure 5-1 MPI Architecture

External Interrupts IRQ(9:0)

53

Peripheral Spac:e Address Decoder

.....-.-•"' Peripheral i---,,, Address Bus

PA(l8:00)

INTRODUCTION TO THE MP/

The Mbus and Pbus have very diverse characteristics so that interactions between them are complex. The Mbus is a 64-bit multiplexed data and address bus which operates at 25MHz and is capable of sustaining a data transfer rate of 40Mbyte/s in and out of main memory. The SPARC CPU also uses part of the Mbus to supply control signals during the address phase of a transfer operation.

The Pbus uses separate address and data buses, and separate control lines to control transfers. It is also very much slower than the Mbus.

The MPI contains data packing registers which allow direct 64-bit accesses by the SP ARC CPU to the 8- and 16-bit peripheral controllers on the Pbus by converting 8-, 16-, 32- and 64-bit accesses on the Mbus into the appropriate number of single cycle accesses on the Pbus. It also contains a 512byte FIFO buffer which extends this access conversion to support Mbus burst cycles.

The MPI provides complete address decode facilities for the Pbus (the peripheral address space) and converts the control information from the Mbus into the Pbus control signals necessary to support accesses to the AT style peripheral controllers employed in the SPARCbook. In addition, the MPI provides the SPARCbook with a 15 level interrupt controller and two 16-bit counter/timers

PERIPHERAL BUS INTERFACE

The MPI is the only Pbus master device in the SPARCbook, no other device is able to initiate a data transfer cycle on the Pbus. Data may be transferred to and from the Pbus using 8- or 16-bit accesses by one of two independent paths. The first is a direct access path into the peripheral address space, and the second is via the internal FIFO.

Direct Operation

The direct access path into the peripheral address space takes a single transfer of 8, 16, 32 or 64bits from the host bus and performs the corresponding number of transfers required on the Peripheral bus. The Mbus transfers and corresponding Pbus transfers supported are shown in Table 5-1.

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On a write cycle, the MPI allows write-posting from the Mbus. It latches the data presented into internal buffers and completes the Mbus transaction immediately, allowing the SPARC CPU to use the Mbus for main memory accesses. In the mean time, the MPI performs the appropriate number of write cycles to the addressed peripheral. The only possible errors on write-posted cycles are accesses by the CPU to non-responding or illegal locations, which are immediately decoded by the MPI and signalled as an uncorrectable Mbus error.

When the SP ARC CPU executes a read operation to the peripheral address space, the MPI holds the Mbus until the requested data has been read from the Pbus into the internal buffers and then completes the Mbus cycle. Up to eight Pbus read operations (for a single 64-bit Mbus operation) are carried out for each Mbus read operation.

MBUS TRANSFER PORT SIZE PBUS TRANSFER

Byte on byte boundary Byte I Byte transfer Byte on byte boundary Halfword I Byte transfer (lower or upper) Halfword on halfword boundary Byte 2 Byte transfers Halfword on halfword boundary Halfword I Halfword transfer Word on word boundary Byte 4 Byte transfers Word on word boundary Halfword 2 Halfword transfers Doubleword on doubleword boundary Byte 8 Byte transfers Doubleword on doubleword boundary Halfword 4 Halfword transfers

Note: Halfword= 16bits, Word= 32bits, Doubleword = 64bits

Table 5-1 Conversion of Mbus Transfers to Pbus Transfers

55

FIFO Operati.ons

The second means of data transfer to and from the host bus is by using the MPl's internal FIFO. Mbus transfers to and from the FIFO port are only permitted using 64-bit transfers.

FIFO operations are initiated by the SPARC CPU. To execute a FIFO operation, the SPARC CPU must set up control registers in the MPI to specify the following parameters:

• The Peripheral addr~ space start address The number of bytes to be transferred The direction of transfer (read or write) Incrementing or static Pbus addressing Pbus DMA (floppy disk operations only) or polled operation

A FIFO operation is started by setting the FSTART bit in the FIFO control register.

Read Transactions After the FIFO control registers have been used to initiate a read operation, the MPI executes a series of read operations on the Pbus, transferring the data into the FIFO. The operation is complete when either the FIFO becomes full or the byte count in the FCOUNT register reaches zero, signifying that the specified number of bytes have been transferred. The FIFO full and FCOUNT equals zero conditions are signalled to the SPARC CPU with interrupts.

In polled mode operations, the data transfers proceeds at the fastest rate pennitted by the peripherals. In OMA mode, the DRQJDACK lines are used to control the peripheral bus transfers. This latter mode is intended for floppy disk transfers. •

Once in the FIFO, the data may be read out by the SPARC CPU using 64-bit single cycle or burst transfers. While data may be read from the FIFO as soon as it is available, the SPARC CPU should not read more data than has been read from the Pbus (this can be checked by using the FCOUNT status register). Reading more data than is available in the FIFO will result in a FIFO Empty interrupt (if it is enabled), and undefined data being returned.

Once the required number of bytes have been read by the CPU, Pbus transfers are stopped and the host is interrupted (under software control).

Write Transactions For a write operation the host may write up to 512bytes into the FIFO data register using 64-bit single or burst transfers. Bursts of up to 32bytes (four Mbus data transfer cycles) are supported without wait states.

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The FIFO Control register contains full and empty flags which may be programmed to generate interrupts. The MPI may be programmed to interrupt the CPU when the FIFO Full flag or FIFO Empty flag in the FIFO Control register become set.

The FIFO Start bit in the FIFO Control register must be set in order to allow a FIFO operation to proceed. Then, once the CPU writes data into the FIFO the corresponding Pbus transactions commence, beginning at the address specified in the FIFO Start Address register.

A special operating mode allows data in the FIFO to be written directly to the peripheral bus (a write operation with no data supplied by the SP ARC CPU).

NOTES:

1 FIFO transfers may not be carried out over a IKbyte peripheral address boundary.

2 At any time the FIFO may be reset by asserting a bit in the System Reset Register. This causes the FIFO pointers and counters to be reset and creates an empty FIFO.

3 Mbus transfers other than those in Table 5-1 (eg misaligned transfers) are not supported.

Peripheral Space Address Decoder

All addresses for the Pbus are decoded by the MPI. The MPI divides the Pbus address space into six 2Mbyte regions, resulting in the address map shown in Figure 5-2.

In four regions the MPI asserts the chip select for one device, while the remaining two are assigned to provide one 8-bit region and one 16-bit Pbus l/O region. Accesses to non-responding locations will return undefined data on reads and write to undefined locations on writes.

The MPI does not provide a chip select signal for the 82C710 UPC, which is used to provide control of the disk and external mouse interface. This device is accessible at various locations within the 8-and 16-bit access regions (see Chapter 7).

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OxOOCCFFFFF

OxOOCCOOOOO

OxOOC800000

Ox00C600000

OxOOC400000

OxOOC200000

OxOOCOOOOOO

Figure 5-2 Pbus Memory Map

8-bit Pbus Operations

16-bit Pbus Operations

Real Time Clock

Modem Interface Controller

Ethernet Controller

VGA Controller

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COUNTER-TIMERS

The MPI incorporates two general purpose 32-bit counter/timers, CTO and CTI for software use, and a bus timeout timer which prevents the SPARCbook from stalling due to an access to a non-responding location. These are illustrated in Figure 5-3.

lMHz

CTOCount=O

CTO U Counter/Counter Current Value

CTO Set Collllt Register

CTl Set Count Register

CTl U Counter/Counter Current Value

CTl Count=O

Figure 5-3 MPI Counter Timers

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System Timers

The two general purpose counter/timers each consist of a 32-bit up counter, a 32-bit time constant register and a counter control register. These are clocked from a IMHz clock, internally generated by the MPI, giving a timing resolution of lµs. The timers count up and may be used to generate an interrupt after a programmable delay.

The timers can be chained to create a single 64-bit counter/timer. In this mode of operation, Timer 0 supplies the timing for Timer 1.

The timers may be programmed to operate in either one-shot mode or continuous mode. In one-shot mode the timer counts up from a preloaded value and completes the count when it reaches one after passing zero.

In continuous mode, the timer is reloaded with the preset count value each time it reaches zero and continues counting, generating a periodic interrupt each time zero is reached.

Further information is provided in the register descriptions in this chapter.

Bus Timeout Timer

The MPI also contains a bus timeout timer (see Interrupts below). This timer monitors all Mbus transactions. Any Mbus transaction that is not completed after detection of four CLK32K clocks causes termination of the cycle and an Mbus Error. This corresponds to a timeout of approximately 125µs. The bus timeout timer has a fixed timeout period and signals an Mbus error if this period expires.

This facility is used for all Mbus cycles and is not limited to accesses to the MPI control registers or to the peripheral address space.

SERIAL 110 PORT

The MPI contains a single channel serial interface which operates in conjunction with the microcontroller to provide an interface to the keyboard.

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Serial Input

A single serial input line receives asynchronous data at 976.6 baud (1.024ms period) from the keyboard microcontroller. Data is formatted as 8 data bits with one start bit (0) and one stop bit (1), with the least significant bit transferred first. No other data formats are permitted. Up to three characters are buffered by the MPI. An interrupt may be generated if there are any received characters in the buffer.

Serial Output

A single serial output line transmits asynchronous data at 976.6 baud to the keyboard microcontroller. Data is formatted as 8 data bits with one start bit (0) and one stop bit (1). No other data formats are permitted. A status register contains a busy bit If the busy bit is not asserted the host may write a single byte to the transmit register. The busy bit will be asserted until the transmitter buffer becomes available again.

POWER MANAGEMENT FUNCTIONS

The MPI incorporates a power management unit (PMU) which controls the SP ARCbook internal clocks and power supply to the peripheral controller devices.

PMl is used to switch off the main power to the system.

Clock Control

The MPI controls the main Mbus clock, MCLKO, to which all Mbus transactions are synchronized . The MPI performs the following functions using the input reference 25MHz.

Normal Operation MCLKO & MCLKl are generated from CLK25M and operate at 25MHz. A lMHz timing reference for the counter/timers is derived from CLK25M.

Slow Operation MCLKO & MCLKl are generated from CLK25M but are reduced to 12.SMHz. The timing reference for the counter/timers remains unchanged.

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Stop Operation MCLKO is stopped in the high state at the end of the cycle after the deassertion of /MRDY. MCLKI is output at 12.5MHz. The timing reference for the counter/timers is unchanged.

Pause Operation MCLKI is not affected (remains at 12.5 or 25MHz). MCLKO can be stopped temporarily in one of two software selectable (via the relevant CLK_CTL register bits) modes. The first is the INTPAUSE mode. In this mode the MCLKO signal is held high (stopped) from the clock after the MAS strobe until the clock before the MRDY or MERR cycle termination for accesses which are to the MPI.

In the second, EX'IPAUSE mode, the MCLKO is held high (stopped) for a programmable number of clocks from 0 (default) to 7 after the MAS cycle when the MPI is not being addressed. This is used to conserve power during initial memory accesses. Note that in the INTPAUSE mode the Mbus timeout will still operate to terminate the cycle if required.

INTERRUPT CONTROLLER

The MPI incorporates an interrupt controller. This consists of a priority encoder and Interrupt Mask registers. The interrupt controller is illustrated in Figure 5-4.

I I .

I a T I

• . I I . r . I . r . ' r . r r r p • . r I p . p I p I .. I . p p . B k . I . . • . d I I w I ' b I a I I .

I . I , - d

I I .

Figure 5-4 SPARCbook Interrupt Architecture

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Table 5-2 shows the interrupt sources from the SPARCbook's devices and from within the MPI itself.

The MPI performs a simple priority encoding of the sixteen interrupt sources to four interrupt request lines to the SPARC CPU, IRL(3:0). The MPI external interrupts are all level sensitive, and may be individually programmed to be active high or active low. Each interrupt may be individually enabled or masked. At power up all interrupts are masked.

After an Mbus clock stop operation (under CPU control), the activation of any non-maskable interrupts will automatically restart the MCLK clock in the same mode (25MHz or 12.5MHz) as when it was halted.

IRQ9 is a special case. It is latched internally within the MPI when it has been asserted for one clock period. The latched signal is fed into the interrupt priority circuit The latch (and the interrupt) is cleared by writing to the appropriate Interrupt Acknowledge bit.

LABEL SOURCE IRL(3:0) DEVICE

IRQ9 External 1111 CMU IRQ8 External 1110 Power Low/Floppy Disk CTO Internal 1101 Counter Timer 0 CTI Internal 1100 Counter Timer 1 KBD Internal 1011 Keyboard Buffer IRQ7 External 1010 External Mouse IRQ6 External 1001 Serial IRQ5 External 1000 Modem IRQ4 External 0111 Ethernet IRQ3 External 0110 Display IRQ2 External 0101 Hard Disk FFE Internal 0100 FIFO Full/Empty FOP Internal 0011 FIFO Operation complete (FCOUNT=O) IRQl External 0010 Power Low/Floppy Disk IRQO External 0001 Centronics

0000 No Interrupt

Table 5-2 SPARCbook Interrupt Sources

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INTERNAL REGISTERS

The MPI contains twenty control registers which affect the activity of the elements that the MPI contains. In addition to the control registers, the MPI provides a twenty first location which is used to move data into (for writes), and out of (for reads), the FIFO.

Table 5-3 summarizes the internal address map of the MPI. It provides the address, label, name and size of each register. The size refers to the data width that must be used when accessing the register.

ADDRESS LABEL NAME ACCESS SIZE

OxOODOOOOOO MERR_ST A rus Mbus Error Status RO 8-bit OxOODOOOOlO CTO_TIME Set Count CTO R/W 32-bit OxOOD000018 CTO_VALUE Current Count CTO RO 32-bit OxOOD000020 CTO_CONTROL ControlCTO R/W 8-bit Ox00D000028 CTl_TIME Set Count CTI R/W 32-bit OxOOD000030 CTI_ VALUE Current Count CTI RO 32-bit Ox00D000038 CTI_CONTROL Control CTI R/W 8-bit OxOOD000050 INT_PEND Interrupt Pending RO 32-bit Ox00D000058 INT_pOLARITY Interrupt Polarity R/W 32-bit OxOOD000060 INT_ENABLE Interrupt Enable R/W 32-bit OxOOD000068 INT_ACK Interrupt Acknowledge WO 32-bit OxOOD000070 KBDDATA Serial Receive Port RO 8-bit Ox00D000088 KBDSTATIJS Serial Receive Status RO 8-bit Ox00D000090 TXDATA Serial Transmit Port WO 8-bit OxOOD000098 TXSTATIJS Serial Transmit Status RO 8-bit OxOODOOOOAO RESET Reset R/W 8-bit Ox00DOOOOA8 CLK_CTI. Clock Control R/W 8-bit OxOODOOOOB8 PM_PORT Power Down WO 8-bit OxOODOOOOCO FIFO_START FIFO Start Address R/W 32-bit OxOODOOOOC8 FIFO_CONTROL FIFO Control R/W 32-bit OxOODOOOOF8 FIFO_DATA FIFO Data R/W 64-bit only

Table 5-3 MPI Internal Registers

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FIFO Control Registers

FIFO control registers are used to program the FIFO.

FIFO Start Addr~ Register This register is used to specify the Peripheral Space start address for a FIFO transaction. The first Pbus transaction accesses this address. Subsequent transactions will either automatically increment the Pbus address by the size of the port (by 1 for byte, by 2 for halfword), or retain the same address if the FNOINC bit is set in the FIFO_CONTROL register.

Note that although only 24 bits are valid the full address may be written into this register, the upper bits are ignored. On a read, address bit A(20) is set (signifying FIFO address). A(19) is hardwired to 0.

Bits 31:24 Reserved Bits 23:0 Address Bits 23:0

31 30 29 28 27 26 2S 24 23 0 ~~ ~-------FIF0--0-jXrSU-.on-S_Wt_Addn:ss-----------.

Bits 31 :24 Reserved

Figure 5-5 FIFO Start Address Register

FIFO Control Register This register is used to to control and initiate FIFO operations. It also contains status bits to reflect the state of the FIFO.

31 20 19 18 17 16 IS 14 13 12 11 10 9 0

OxOODOOOOCB <- - - RX>UNf BilS 9:0 -- -->

Bits 31 :20 Reserved FULL FSTART

EMPTY---- ----FRNW FNHD -------' -------FINT F.NFULL---------- ---------FDMA ENFEMPTI------------- "'------------FNOINC

Figure 5-6 FIFO Control Register

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Bits 31:20 Reserved

Bit 19 FULL

Bit 18

Bit 17

Bit 16

Bit 15

Bit 14

Bit 13

Bit 12

1 = FIFO is full

EMPTY 1 = FIFO is empty

FNHD 0= 1=

ENFULL 0 = Disable FIFO FUU interrupts 1 = Enable FIFO FULL interrupts

ENFEMPTY 0 = Disable FIFO EMPTY interrupts 1 = Enable FIFO EMPTY interrupts

FSTART 0 = Disable FIFO operations 1 = Enable FIFO operations

FRNW 0 = CPU write to Pbus 1 = CPU read from Pbus

FINT 0 =Disable FCOUNT equals interrupts 1 = Enable FCOUNT equals i.ero interrupt

Bit 11 FDMA 0 = Polled FIFO operations 1 = DMA FIFO operations (floppy disk only)

Bit 10 FNOINC

Bit9:0

0 =Use incrementing Pbus address 1 = Use same Pbus address

FCOUNT Bits 9:0 - Number of bytes to be transferred.

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A FIFO Full/Empty interrupt will cause the FEMPTY and FFULL bits to be frozen until the register is read by the CPU. These bits are set on a transition to the EMPTY or FULL state. They will not cause a new interrupt if the associated state is still true after being acknowledged, or if enabled when the FIFO is already in the Full/Empty state.

An operation is initiated by programming the FIFO Start Address register, programming the FIFO Control register parameters and setting the FST ART bit The FST ART bit may be set in the same CPU as the programming of the rest of the FIFO Control register.

Initially, FCOUNT must be a multiple of 8. FCOUNT is decremented by 1 (for byte operations) or 2 (for halfword operations) for each peripheral bus read or write. The FINT bit detennines whether a transition on FCOUNT to zero causes a FOP interrupt

FIFO Data Register The FIFO _DAT A register is used for host FIFO data transfer operations. Only doubleword (64-bit) or 32byte burst operations are allowed to this register. FIFO data will be transferred into or out of the FIFO. Data is aligned to SPARC conventions. Full byte swapping and packing/unpacking between the Peripheral bus and the Mbus is perfonned within the MPI. Note that byte swapping cannot deal with addresses or pointers passed between the Mbus and Pbus.

Timer Control Registers

Set Count CTO (CTI) These are read-write registers used to set the count value for the associated counter. The value is specified in microseconds.

Counter Current Value These registers provide the current Counter Value for the associated counter. They are read only registers, a write has no effect.

Counter 0 Control This register provides control for Counter 0. The COSTART bit may be set in the same operation as the setting of the rest of the control register.

7 6

Figure 5-7 Counter 0 Control Register

2 I 0

COCONr amm!N----o OISl"AllT ___ _,

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Bits 7:3

Bit2

Bit l

BitO

Reserved

COCO NT 0 =Counter continues on zero to l (one shot) l =Counter reloads from CTO_TIME and continues running

COINTEN 0 = Disable interrupt on zero l = Enable interrupt on zero

COST ART 0 = Stop counter l = Start counter

Counter 1 Control This register provides control for Counter 1. The C lST ART bit may be set in the same operation as the setting of the rest of the control register.

0..00D000038

Cl CONT

CILINK ------Figure 5-8 Counter 1 Control Register

Bits 7:3

Bit3

Bit2

Bit 1

BitO

Reserved

Cl CONT 0 =Counter continues on zero to 1 (one shot) 1 =Counter reloads from CTO_TIME and continues running

ClINTEN 0 = Disable interrupt on zero 1 = Enable interrupt on zero

Cl START 0 = Stop counter 1 = Start counter

Cl LINK 0 = Count from lMHz Clock 1 = Count from CTO

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POWER MANAGEMENT CONTROL REGISTERS

Power Management Port This register is used to control the state of the power management line provided by the MPI. It is an 8-bit read/write register containing one valid bit in DO. If this bit is set the PMl line is asserted (high) and the system is powered down.

Clock Control Register This register performs the MCLK management for the main CPU clock. Note that the only way of restarting MCLKO after MCLKSTOP has been asserted is by the receipt of a non-masked interrupt. The programmer should therefore be careful to ensure that this will happen or the system will hang.

When an interrupt is received MCLKO is automatically restarted and the MCLKSTOP bit is cleared. Note that when the clock restarts both MCLK0-1 will be restarted at 25MHz if MCLK12 is reset, and at 12.5MHz if MCLK12 is set

6

O&OODOOOOA8

4

PAUSF.CNI'

EXTPAUSB

INTPAUSB

MCLXSl'OP----

0

Figure 5-9 Clock Control Register MCUtl2-----

Bit7

Bits 6:4

Bit3

TEST Must be set to 0

PAUSECNf 001 -111 = NumberofMCLKOclock cycles to stop during EXTPAUSE. 0 = do not pause clock

EXTPAUSE 1 =Enable EXTPAUSE clock stopping during other Mbus accesses

Bit 02 INTPAUSE 1 =Enable INTPAUSE clock stopping during MPI wait states

BitDl MCLKSTOP 1 = MCLKO stopped (MCLKl operates at 12.5MHz)

Bit DO MCLK12 0 = MCLKO and MCLKl are 25MHz 1 = MCLKO and MCLKl are 12.5MHz

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Interrupt Control Registers

Interrupts Pending This register may be read to determine which of the interrupts are pending at any given time.

Interrupt Polarity This register is used to specify the polarity level for the external interrupts. Bits corresponding to the internally generated interrupts are ignored and read as zero. A bit cleared to zero specifies an active low interrupt, a bit set to one specifies an active high interrupt. The register JX>wers up as zero.

Interrupt Enable This register is used to specify the interrupts which may interrupt the host. Clearing a bit to zero masks the corresponding interrupt level. A bit set to a one enables the corresponding level. All bits power up as zero.

Interrupt Acknowledge This register is used to acknowledge the internally generated interrupt sources. It has no effect on the external interrupt sources except for IRQ9. It is write-only and a bit is set to acknowledge the corresponding interrupt. For the counter timers the interrupt will not occur again until the count ttansitions to zero. For the FIFOs the empty, full or FCOUNT=O interrupt will not occur again until the ttansition to that condition happens again.

The interrupt control registers are organized as shown in Figure 5-10. Each of the interrupt request sources is assigned to the same bit in each of the control registers.

lS 14 13 12 11 10 9 8 7 6 S 4 3 2 0

0 I ~~1 ~:~-'---!~---L..~...&-----JL----L~-'-~'----1-~--L-~L---1-~-'-~~~~--!

Intemipt Polarity OxOODOOOOS8

Intemipt Acknowledge Ox00D000068

: i

IRQ9 IRQ8 CTO CTI KBD IRQ7 IRQ6 IRQS IRQ4 IRQ3 IRQ2

Figure 5-10 Interrupt Control Registers FIFO FulVEmpty FIFO Operation Complet

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0

0

I 0

IRQl IRQO NULL


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IRQ9-CMU IRQ8 - Low Power W aming CTO - Counter Timer 0 CTl - Counter Timer 1 KBD - Keyboard Character Buffer IRQ7-Mouse IRQ6 - External Serial Interface IRQ5 - Modern IRQ4 - Ethernet IRQ3 - Display Controller IRQ2 - Hard Disk Interface FIFO FULL/EMPTY

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 BitlO Bit9 Bit 8 Bit7 Bit6 Bit5 Bit4 Bit 3 Bit 2 Bit 1 BitO

FIFO Operation Complete (FCOUNT = 0) IRQl -Aoppy Disk Interface IRQO - Centronics Interface NULL - No Interrupt, hardwired to 0

Serial Input/Output Registers

Keyboard Byte This register is read-only, it contains data from the serial input port which is used to communicate with the microcontroller (see Chapter 6). Up to three bytes are buffered in the MPI and the programmer is responsible for ensuring there is no overflow. A write to this register has no effect.

Note that Mousekey infonnation passes via the Keyboard byte.

Keyboard Status This register provides a single bit (Bit DO) that is asserted when there is valid data in the data register. It is cleared on a data read operation to the K.BDST A TUS register. If there is further data to be read it is reasserted when that data is in the K.BDDATA register.

Transmit Byte This register is a write only 8-bit register; a read will return undefined data. Data may be written to this register when the TXBUSY status bit is not asserted.

Transmit Status This register provides a single bit (Bit DO) that is asserted when the transmitter is busy.

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Software Reset Register

Bit4 RESET Reinitialii.es the MPI, clears FIFO and sets all l/O bits to default levels - same effect as Power On Reset

Bit 3 IORESET

Bit 2

Bit I

BitO

Asserts PRST line for 2µs

FIFOSTOP Terminates any FIFO activity, resets FCOUNT and FSTART

TSTl Test vectors - must be left at 0

TST2 Test vectors - must be left at 0

ltllSEI'

TSTt-----' TSTO------Figure 5-11 Software Reset Register

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Error Status Register

This register provides the cause of an Mbus error generated by an access to the MPI ASIC. A read to this register clears the register bit latches.

Bit5 Bit4 Bit3 Bit2 Bit 1 BitO

BTO TYPE SIZE FNHD PFERR MFERR

MBus timeout Invalid MBus Type Field Invalid MBus Size Field FIFO No Host Data Error Pbus FIFO Setup Error Mbus FIFO Setup Error

6

Bi117:6 -BTO TYPE SIZB---_.

2 I 0

l'NllD ------_____ ___,

MFllRR--------' Figure 5-12 Error Status Register

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CHAPTER SIX MICROCONTROLLER SUBSYSTEM

Software monitoring of battery condition, keyboard input, and conlrol of screen brightness and contrast are concrolled by a dedicated microcontroller. This offloads these tasks from the main CPU, allowing its processing power to be concentrated on running applications.

MPI

Status

75

Sy.111111 Temperature MODitoring

The microcontroller performs the following functions:

Keyboard interfacing Mousekey interfacing

• Power supply monitoring • Controlling the Status LEDs • System temperature monitoring • Screen brightn~ and contrast control • System EEPROM interfacing • Hardware reset control

The microconttoller interfaces with the CPU (or host) via the serial interface of the MPI (see Chapter 5). During normal operation, the microcontroller performs keyboard and Mousekey scanning and monitors the power supply. On receipt of a command from the host or user command from the keyboard it perfonns a nwnber of additional functions.

Note: the host and microcontroller exchanae characters which represent hexadecimal numbers. In this manual, hexadecimal numbers are shown with the prefix Ox. The characters Ox do not form part of the command code or the data returned.

KEYBOARD INTERFACE

The microcontroller interfaces to the keyboard via a Honeywell 380105 keyboard scanner. This periodically scans the keyboard to detect key press events, and passes the serialized character codes for any depressed keys to the microcontroller. The microcontroller in tum interprets characters received and acts upon any that represent microcontroller commands, and conveys all others to the host via the serial port of the MPI (see Chapter 5).

Key Repeat

n n n n n n n n n n n n

The microcontroller provides a software programmable key repeat function which produces multiple n characters while a key remains depressed. Key depression and release are registered. A key press causes an a character code to be returned to the host, and key release causes the same code character to be returned but with the top bit (bit 8) set Thus, if the code Ox33 is returned when a key is pressed, n OxB3 is returned when it is released.

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The key repeat rate is specified by two parameters: the time until repeat and the time between repeats. These are programmable via a host command and are both measured in units of !Oms. The time until repeat is the time from when a key is pressed until it starts to repeat. Once repeat has started, the key code of the last key pressed will be presented to the host every time-between-repeats x !Oms.

Special Characters

Certain character combinations are intercepted by the microcon1roller and used to activate keyboard enetered user commands. These are as follow:

Display Brightness Control ALT and UP or DOWN together

Display Contrast Control ALT and LEFT or RIGHT together

• Reset Control ALT and ESC and R together

Only the ALT depression and release codes are sent to the host during these sequences. The operations performed by these sequences are repeated at a rate determined by the current key repeat parameters.

Special Routi.nes

Brightness Control The brightness of the in-built LCD display is controlled with a digital potentiometer. This is a device which contains a software conlrollable variable resistance, providing 99 (dee) steps.

The UP cursor key pressed simultaneously with the ALT key increases the brightness (decreases the Brighbless digital potentiometer value). If the key continues to be depressed the brighbless continues to be changed until the end of track is reached.

The DOWN cursor key decreases the brighbless (increases the pot value)

Contrast Control A similar digital potentiometer controls the brightness of the in-built LCD display. This facility functions in a similar manner to the Brighbless Control.

77

Reset Control If a reset command from the keyboard is detected, the Power Supply Status bit is set to a 1 (indicating a user initiated reset) and the System Reset Line is asserted Low for lOOms. This causes a system reset.

MOUSEKEY INTERFACING

The Mousekey contains four force sensitive resistors (FSR); two are used to control vertical cursor movement, and two are to used to control horizontal movement. The Mousekey is isolated from the rest of the keyoard and is scanned separately via four channels of an LTC1093 combined data aquisition and analogue to digital converter (ADC) chip. Each of the four channels is assigned one FSR. The pressures exerted on a each resistor is measured in terms of a voltage and converted to a binary value by the ADC.

When the Mousekey left hand edge is pressed, for example, pressure is increased on the left FSR and reduced on the right FSR. The microconttoller calculates the difference between the voltages measured across the two FSRs and uses the result to determine magnitude and direction of any cursor movement.

Mousekey Initializati.on

At system initialization, the Mousekey is calibrated by reading FSR voltages and storing them in variables within the microconttoller memory. When the Mousekey is subsequently scanned, any voltages that differ from these calibration values are deemed to be an indication of Mousekey pressure. The algorithm for converting left, right, up and down voltages into mouse movements is shown below.

Read voltage on left FSR

Read voltage on right FSR

Calculate the difference (Vright - Vleft)

If result is 0 - no horizontal motion requested

If result is positive a net right motion has been requested.

Return this as a positive X motion.

If result is negative a net left motion has been requested

Return this as a negative X motion.

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Vertical movements are calculated in a similar way and returned as positive or negative Y motions respectively. The algorithm evaluates relative voltages to counteract drift in the steady state FSR values due to thermal effects.

Mousekey Events

The microcontroller passes mouse events to the host as a sequence of four bytes, Ox.FD OxSS OxXX OxYY. The first byte, OxFD, indicates to the host that three mouse event bytes are to follow. The next, OxSS, provides the following status information:

Bit 7

Bit 6

Bit5

Bit4

Bit 3 Bit2

Bit 1

BitO

Y data overflow (always 0) 1 =overflow X data overflow (always 0) 1 =overflow Y data sign 1 = negative Y motion X data sign 1 = negative X motion Event Flag Middle button status 1 = depressed Right button status 1 = depressed Left button status 1 = depressed

The OxXX and Ox YY bytes represent the magnitude of the X and Y motions recorded in a particular mouse event The force on the Mousekey is represented by 3 bits, so the values ofOxXX and OxYY ranges from OxOO to Ox07. These values cannot overflow, so the X and Y data overflow bits will always beO.

Mouse Buttons The buttons found on a conventional three button mouse are simulated using special key combinations on the keyboard. Mouse button events are detected by the keyboard scanning routine, which is always executed immediately before the Mousekey scanning routine. During system initialii.ation, the Event Flag is cleared to 0. If the keyboard scanning routine detects a mouse button event, it sets the associated button bits, and sets the Event Flag to indicate that the status has changed and a mouse event packet should be sent to the host.

79

Cursor Movement Requests After the keyboard scanning routine is complete, the mouse scan routine is called. It detennines if a net motion has been detected and if so, fills in the sign bits, X and Y data fields and sets the Event Flag (it may already have been set by the keyboard scanning routine) to indicate a changed status.

At the end of the Mousekey scanning routine, the Event Flag is checked to see if it has been set. If it has, a mouse event packet is sent to the host and the reserved bit is cleared.

Mouse Event Parameters Mouse operation is controlled by two parameters: the force on the Mousekey, and the time between successive calls to the mouse scan routine. Key pressure is quantized into eight levels, so that a light key pressure moves the cursor in steps of one unit every time the mouse scan routine is called, and the heaviest measureable key pressure causes the cursor to move in steps of 8 units every time the mouse scan routine is called. The result of this is that increasing the pressure on the Mousekey accelerates cursor motion.

Mouse scan rate is variable in units of !Oms and determines how fast the mouse moves when a constant pressure is applied to the Mousekey. This rate is software programmable and is stored in EEPROM to maintain its value during system power down.

HARDWARE INTERFACES

The microcontroller communcates with the host via serial pon of the MPI. It provides control, data aquisition and staws aquisition via four ports, each with eight 1-bit I/O ports. These are assigned as shown in Table 6-1

Host Instruction Protocol

The microcontroller incorporates a mask programmable read-only memory which contains the complete microcontroller firmware. The host may make various requests to the microcontroller via the serial pon of the MPI. The microcontroller receives and interprets these requests and takes the appropriate action. It returns values (if required) to the host as characters.

The microcontroller issues the code OxFE to acknowledge all host instructions, followed by one or more bytes as required to fulfill the request before resuming normal keyboard and Mousekey scanning.

Table 6-2 outlines the request codes available to the host and the responses from the microcontroller.

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BIT-PORT DIRECTION

PortO(O) Output PortO(l) Output Port0(2) Input Port0(3) Input Port0(4) Input Port0(5) Input Port0(6) Input Port0(7) Input

Portl(O) Output Portl(l) Output Port1(2) -Portl(3) -Port1(4) -Port1(5) -Port1(6) Input Port1(7) Input

Port2(0) Output Port2(1) Output Port2(2) Output Port2(3) Output Port2(4) Output Port2(5) Output Port2(6) Output Port2(7) Output

Port3(0) Input Port3(1) Output Port3(2) Output Port3(3) Output Port3(4) Output Port3(5) Output Port3(6) Output Port3(7) Output

Table 6-1 Bit-Port Assignment

FUNCTION

Keyboard Scanner Reset Keyboard Scanner Clock Keyboard Data DC Level OK Battery Level 1 Battery Level 2 Battery On Battery Full

Parity Detect Enable Parity Error Inject Reserved Not Used Not Used Not Used Floppy Disk Density Status Floppy Disk Ready Status

Bit 1/0 Device Control 1 Bit 1/0 Device Control 2 Brightness Chip Select Contrast Chip Select ADC Chip Select EEPROM Chip Select Temperature Sense Read Data EEPROM Read Data

Serial Data From MPI Serial Data to MPI System Reset Sound Beeper Battery low LED User LED External LED Interrupt CPU on Level 14

81

n n

REQUEST MEANING VALUE RETURNED (after Ox.FE) n System Information

OxlO Read Ethernet Address 3bytes with Net Address. n For example, for address Ox0044F A the bytes returned would be OxOO, Ox44, Ox.FA

Oxll Read Hardware Revision 2bytes with Hardware Revision Major and Minor. For example Rev 1.3 is returned as OxOl, Ox03

n Oxl2 Read Controller Firmware Rev Format as for Hardware Revision

This data is hardwired into the microcontroller n firmware

Oxl3 Read System MAXTEMP Value in degrees centigrade hexadecimal Eg 25 degrees is returned as Ox 19. n

Ox14 Read System MINTEMP As for MAXTEMP

Ox15 Read Temperature Sensor ADC As for MINTEMP n Ox16 Read POWERCOUNT 2bytes, most significant fust, giving the number of

times the SPARCbook has been powered. n Ox17 Read POWERONSECONDS 4bytes seconds SPARCbook has been powered

Ox18 Return Microcontroller Status Returned byte n Bit 7 Bad Checksum Bit 6 Diagnostics Fail Bit 5 Watchdog Reset (l=Watchdog Reset) Bit4 User Reset bit (O=POR) n Bit3 Battery Full bit Bit2 Battery On bit Bit 1 Battery Level 2 BitO Battery Level 1 n

Ox19 OxNN Read ADC channel OxNN 2 bytes containing 10-bit value. First byte contains most significant 8 bits, second byte contains least significant 2 bits i.e. bbbbbbbb OOOOOObb

n CH OxNN FUNCTION

0 OxOO Force sensitive resistor 0 n

1 OxOl Force sensitive resistor 1 2 Ox04 Force sensitive resistor 2 3 Ox OS Force sensitive resistor 3 4 Ox02 Battery Voltage sensor

n 5 Ox03 Temperature sensor

n 82 n

n

u I I ~

u REQUEST MEANING VALUE RETURNED

u Commands

Ox20 Tum USER LED off None

u Ox21 Tum USER LED on None

Ox220x.NN Sotmd Beeper for OxNN increments of lOms None

u Ox230x.NN Increment Brightness OxNN times (0 - 63 hex) None

Ox240xNN Decrement Brightness OxNN times (0 - 63 hex) None

u Ox25 Ox.NN Increment Contrast OxNN times (0 - 63 hex) None

Ox260xNN Decrement Contrast OxNN times (0 - 63 hex) None I I u Ox270xNN Read EEPROM register OxNN 16-bit register Value

LJ Ox28 OxNN OxXX Ox YY Write EEPROM register OxNN with data OxXXYY None

Ox29 OxMM OxNN Rollover parameters None MM is initial delay in lOms increments, OxNN is

LJ the interval between characters in 1 Oms increments. Default is 400ms and 10 chars/sec.

Ox2AOxNN Mouse scan period in units oflOms None

LJ Ox2B OxNN Write byte OxNN to microcontroller port 1 . None

Ox2COx.NN Read pin values from microcontroller port 1 1-byte port value

u Miscellaneous

u Ox30 Acknowledge Interrupt None

Ox40 Enable Watchdog None

u (if watchdog commands are not received at least 1 per second the system will be reset)

Ox41 Disable Watchdog (default) None

u Ox42 Watchdog command None

u Table 6-2 Host Instructions and Replies

u 83

LJ

Host Interrupts

If either of the battery low signals is detected low, or the external power supply is plugged in or removed, the host is interrupted on Level 14 by setting the Interrupt Host port bit. The port bit remains set until an interrupt acknowledge is received from the host. It is returned to its default zero condition. The host is able to read the Microcontroller Status Byte to determine the cause of the interrupt and then take the appropriate action.

EEPROMData

The following data is defined in the EEPROM. This is a 1024bit device treated as 128 byte locations:

Note that bytes 0-31 may be not written, they are reserved for manufacturing information.

BYTE FUNCTION COMMENT

0 Ethernet Address (serial no) low byte 1 Ethernet Address (serial no) middle byte 2 Ethernet Address (serial no) high byte 3 HW Revision - Minor Level 4 HW Revision - Major Level 5-14 RESERVED for hardware use 15 Byte Checksum for bytes 0-14 16 MAXTEMP in degrees C 17 MINTEMP in degrees C 18 POWERCOUNT byte 0 No of power up cycles 19 POWERCOUNT byte 1 20 POWERONSECONDS byte 0 No of power on secs 21 POWERONSECONDS byte 1 22 POWERONSECONDS byte 2 23 POWERONSECONDS byte 3 24 Keyboard time until repeat lOms units 25 Keyboard time between repeats lOms units 26 Time between Mouse scans lOms units 27-31 RESERVED for system use Access code protected 31-63 RESERVED for system use No Access code needed 64-127 RESERVED for application use No Access code needed

Table 6-3 EEPROM Address Map

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CHAPTER SEVEN UNIVERSAL PERIPHERAL CONTROLLER

One of the devices implemented in the SP ARCbook design to achieve its high level of integration is the 82C710 Universal Peripheral Controller (UPC) from Chips and Technologies Inc. This single chip provides the SPARCbook with the following facilities:

•

l'loppy Diot Dri.., (DOI fillDd in dual bud dilk modcll)

Floppy disk controller IDE Hard disk interface Parallel Centronics interface Serial Port Mouse Interface

Universal Peri heral Controller

HardDilk Ccillllvller

Figure 7-1 UPC Peripheral Control Architecture

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MPI

FLOPPY DISK CONTROLLER

The UPC contains a floppy disk controller (FDC) fully compatible with the NEC µPD72065B. An integral 48mA floppy interface buffer allows the disk drive to connect directly to the UPC. The SPARCbook is equipped with one 3.5" floppy disk drive in single hard disk models, but does not contain a floppy disk drive in dual hard disk models.

Host Interface

The activities of the FDC are controlled via a set of four register locations, shown in Table 7-1.

Digital Output Register This is a write-only register which provides drive select (bits 1 :0 = OObin), motor enable (bit 4 = 1 ), DMA enable (bit 3 = 1) and reset control (bit 2 = 1 ).

Main Status Register This is an 8-bit register which contains information about current activity by the FDC.

Data Register The data register is used by the host to issue instructions to the FDC, and by the FDC to return status information to the host. The FDC automatically directs information to or from the appropriate internal location.

Data Rate Register The lower two bits in this register are used to select the data rate for the FDC. OObin selects a 500Kbyte/s data rate.

Digital Input Register Only bit 7 in this register is used for FDC operations. It provides the complement of the Disk Change input pin.

ADDRESS REGISTER ACCESS

OxOOC:C003FO Unused OxOOC:C003Fl Unused OxOOC:C003F2 Digital Output Register w OxOOC:C003F3 Unused OxOOC:C003F4 Main Status Register R OxOOC:C003F5 Data Register R/W OxOOC:C003F6 Unused OxOOC:C003F7 Data Rate Select Register w

Digital Input Register R

Table 7-1 FDC Register Map

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Floppy Disk Commands

The host controls the FDC with commands written via the Data Register at OxOOCC003F5. There are seventeen commands available which are initiated by a multi-byte write to the data register. The first byte contains an operation code, and this is followed by a number of bytes containing parameter information (the number of parameter bytes depends upon the instruction). Most commands to the FDC entail a three part sequence consisting of the Command Phase, the Execution Phase and the Result Phase.

Command Phase During the command phase, the host writes an instruction byte together with the parameters required to carry out the instruction via the Data Register. The FDC automatically determines number of parameters required with the command byte and the order in which they should be supplied by the host

Execution Phase During the execution phase, the FDC acts upon the command supplied during the command phase.

Result Phase After execution of an instruction, the FDC automatically presents status information for the host to read from the Data Register. The status information supplied varies according to the action carried OUL

Figure 7-2 summarizes the command set of the FDC. The bytes written during the command phase are shown within shaded areas, next to the bytes read by the host during the associated result phase.

Key to abbreviations used in Figure 7-2:

c Cylinder HD Selected head NCN New cylinder number D Data pattern HLT Head load time R Record DTL Data length HUT Head Wlload time R/W Read/Write EOT End of track MF FMJMFMmode SC Sectors per cylinder GPL Gap 3 length MT Multi-track SK Skip H HeadNumber N Bytes per sector SRT Step rate time STP Scan step STO, 1, 2, 3 Stabls registers 0, l, 2, 3 USO, l Selected drive number

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STI sn c H R N

c H R N

x x

Figure 7-1 FDC Instruction Summary

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STO STI ST2 c H R N

Result Phase

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FDC Operating Modes

The FDC in the SPARCbook application only ever conttols a single 3.5" floppy disk drive. The FDC reads and write SunOS format disks, which can be either high density 1.4Mbyte disks or low density 720Kbyte disks.

Table 7-2 summarizes the disk types supported by the SPARCbook and the parameters required to configure the FDC to correctly carry out commands.

PARAMEIBR HIGH DENSITY LOW DENSITY UNIT

Step Rate 3 3 ms Head Unload Time 64 64 ms Head Load Time 12 12 ms Gap 3 Lengtht Ox24 Ox2A bytes Gap 3 Lengthtt Ox6D Ox50 bytes Filler (format pattern) OxE5 OxE5 -Number of Cylinders 80 80 Sectors/track 18 9 -Sector Size 512 512 bytes Surfaces 2 2 Data Encoding Mode MFM MFM

t Gap 3 for read and write commands tt Gap3 for format command

Table 7-2 Floppy Disk Parameters

IDE HARD DISK INTERFACE

The UPC provides an interface conttoller capable of supporting two hard disk drives with Integrated Drive Electronics (IDE) interfaces. The UPC also provides conttol of external 16-bit data buffers.

IDE Overview

IDE hard disk drives incorporate an integral controller which interprets conttol signals and commands from the host, and reads data from and writes data to the disk surfaces.

IDE drives are able to support applications in PC/XT and PC/ AT environments. The SP ARCbook only supports drives configured for PC/ AT compatibility. One or two drives may be present, but in a two drive system, the drives must be electrically configured as primary and secondary drives. Reference should be made to the technical literature supplied with the disk drive for information about drive configuration.

89

IDE Interface Operating Modes

The UPC provides two IDE interface modes: the AT mode, used in the SP ARCbook and the XT mode. The mode is configured via bit 6 of the UPC Configuration Register at OxOC. When this bit is at '1 ', the AT mode is selected.

The UPC IDE interface control registers are accessible in the 8-bit J/O region of the SPARCbook memory map, and the data register is accessible within the 16-bit I/() region of the MPI's Pbus address map. This results in the address loactions of the IDE Task File Registers shown in Table 7-3. Transfers between hard disk sectors and the SPARCbook main memory take place via the MPI (see Chapter 5). The hard disk interface uses polled operations only, OMA operations are not supported.

Task File Registers

The activities of an IDE hard disk drive are controlled via a set of register locations within the integral drive controller called Task File Registers. The UPC decodes host accesses to these registers. Table 7-3 lists the task file registers

ADDRESS

OxOOC8001FO OxOOCCOOlFl OxOOCC001F2 OxOOCCOOIF3 OxOOCC001F4 OxOOCCOOlF5 OxOOCCOO IF6 OxOOCCOOIF7

OxOOCC003F6

OxOOCC003F7

Table 7-3 Task File Registers

Data Register

REGISTER

Data Register Error Register Sector Count Sector Number Cylinder Low Cylinder High Drive/Head Status Register Command Register Alt Status Register Fixed Disk Register Digital Input Register

ACCESS

R/W R

R/W R/W R/W R/W R/W

R w R w R

The data register is the register through which all data is passed on read and write commands. All data transfers are 16-bits with the exception of the ECC bytes transferred during Read or Write Long commands. Data is stored on the disk least significant byte first, then most significant byte.

Error Register This read-only register contains the status of the last executed command.

Sector Count Register This register contains the number of sectors to be read or written during a Verify, Read, Write or Format command. Note that a value of 0 means a 256 sector transfer.

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Sector Number Register This register contains the starting sector number for Read, Write and Verify commands.

Cylinder Number Registers These registers contain the LSB and MSB of the first cylinder number where the disk is to be accessed for Read, Write, Seek and Verify commands.

Drive/Head Register This register contains the drive and head select bits:

Bit4

Bit 3:0

Drive select 0= Primary 1 = Secondary Head number

Status Register This register contains status infromation for the drive and controller. The contents of this register are updated at the completion of each command. Pending interrupts are cleared whenever this register is read by the host.

Bit 7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit 1 BitO

Busy Ready for command Fault Seek command completed Ready to transfer data Data correction sucessful Index mark detected Error from last command

Command Register This register is used to pass commands to the hard disk. The commands consist of an 8-bit command code. Execution begins immediately after this register is written. Table 7-4 shows a summary of the executable commands and the parameters used.

Alternate Status Register This register contains the same information as the Status Register. The difference is that reading the alternate status register will not clear pending interrupts.

Fixed Disk Register This register contains interrupt enable and reset control bits. Bit 3 when set holds the drive in a reset state. If two drives are present, the second drive will be reset as well. Bit 2 when clear enables interrupts from the hard disk drives.

Digital Input Register This register loops back the drive select and head select of the currently selected drive. Bit 7 of this register is used by the FDC and has no relevence to the IDE interface.

91

COMMAND NAME CODE PARAMETERS USED (hex) SC SN CY SDH

Recalibrate lx n n n D Read Sector (retry) 20 y y y y Read Sector (no retry) 21 y y y y Read Sector Long (retry) 22 y y y y Read Sector Long (no retry) 23 y y y y Write Sector (retry) 30 y y y y Write Sector (no retry) 31 y y y y Write Sector Long (retry) 32 y y y y Write Sector Long (no retry) 33 y y y y Read Verify Sector (retry) 40 y y y y Read Verify Sector (no retry) 41 y y y y Format Track 50 n n y y Seek 7x n n y y Drive Diagnostics 90 n n n n Initialize Drive Parameters 91 y n n y Read Sector Buffer E4 n n n d Write Sector Buffer ES n n n d Identify Drive EC n n n d Power Management F8-FD

Key: SC = Sector Co\Dlt Register; SN = sector number Register; CY = Cylinder Register; SDH = Drive Head Register; y = Parameter is used; n = Parameter not used; D = drive parameter only; x = Dont care

Table 7-4 AT Command Summary

IDE Command Summary

Recalibrate This command moves the heads to cylinder 0. On receipt of this command, the drive sets BSY and moves the heads to cylinder 0. The drive waits for the seek to complete before updating its status, resetting BSY, and generating an interrupt. If the drive cannot reach cylinder 0, it sets both the "ERR" bit in the Status register and the ''TKO" bit in the Error register. An aborted command response will be given if the drive is not ready. When the command completes successfully, the Task File registers will be affected as follows:

Cylinder High Cylinder Low Error SDH Sector Count Sector Number

00 00 00 Unchanged Unchanged Unchanged

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Read Sector This command reads from I to 256 sectors, as specified in the Task File, beginning at the specified sector. A sector count of 0 requests 256 sectors. As soon as the Command register is written, the drive sets BSY and begins execution of the command. An ID not found error is returned if incorrect task file parameters are passed. If the drive is not already on the desired track, a seek is initiated. When the sector ID is located, the DRQ bit is set, and an interrupt is generated.

The DRQ bit is always set, regardless of the presence or absence of an error condition at the end of a sector. When the command completes successfully, the Task File register contains the cyclinder, head, and sector number of the last sector read. The sector count is zero after successful execution of the command.

Multiple sector reads set DRQ and generate an interrupt at the completion of each sector. DRQ is reset and BSY is set immediately when the Host completes reading the sector. If an error occurs during a multiple sector read, it will terminate after the sector in error is transferred to the host. The Task File indicates the location of the sector where the error occurred. The Host may then read the Task File to determine what error has occured, and on which sector. If no error is detected, the cylinder, head, and sector registers are updated to point to the next sequential sector.

Read Long The Read Long command performs similarly to the Read Sectors command, except that it returns the data and the ECC bytes contained in the data field of the desired sector. During a Read Long command, the drive does not check the ECC bytes to determine if there has been a data error. Only single sector Read Long operations are supported. Data transfers are 16bits wide and ECC byte transfers are 8bits wide.

Write Sector This command writes up to 256 sectors, as specified in the Task File, beginning at the specified sector. As soon as the Command register is written, the drive waits for the Host to fill the sector buffer with the data. There is no interrupt generated to start the first buffer fill operation. Once the buffer is full, the drive sets BSY and begins command execution.

An ID not found error is returned if incorrect task file parameters are passed. If the drive is not already on the desired track, an implied seek is performed. Once at the desired track, the drive locates the appropriate ID field and writes data from the buffer, plus 7 bytes of ECC. Upon command completion, the Task File registers contain the cylinder, head, and sector number of the last sector written. The sector count is zero after successful execution of the command.

Multiple sector writes set DRQ and generate an interrupt each time the buffer requires filling. DRQ is cleared and BSY set immediately when the Host fills the sector buffer. If an error occurs during a multiple sector write, it will terminate at the sector where the error occurs. The Task File indicates the location of the sector where the error occurred. The Host may then read the Task File to determine which error occured, and on which sector. If an error is not detected, the cylinder, head, and sector registers are updated to point to the next sequential sector.

93

Write Long This command is identical to the Write Sectors command, except that it writes the data and ECC bytes directly from the sector buffer. The drive does not generate ECC for this command. Only single sector operations are supported.

Read Verify This command functions identically to the Read Sectors command, except that no data is transferred to the Host. Up to 256 sectors will be read into the sector buffer and the ECC bytes are verified.

When each sector has been verified, the Task File is updated, but no DRQ or interrupt is set until all sectors have been verified. A value of 0 in the sector count register indicates that 256 sectors are to be verified.

Format Track This command fonnats the track specified in the Task File. Once command registers have been written, the drive waits for the host to fill the buffer with 512 bytes of fonnat data. After the data is written to the data register, the drive analyzes the infonnation for each sector and perfonns the requested action for each sector. Upon command completion, the drive places status infonnation in the Task File and signal an IRQ to the host.

The 512 bytes of data in the sector buffer must consist of 2 bytes for each sector to be fonnatted. The most significant byte of each word designates the sector to be fonnatted. The least significant byte contains a descriptor indicating which action should be carried out with that sector as follows:

OxOO Fonnat Sector Good Ox80 Fonnat Sector Bad Ox40 Assign Sector to Alternate Ox20 Unassign Alternate Location for this Sector

Seek This command initiates a seek to the track and selects the head specified in the Task File. The drive need not be fonnatted for a seek to execute properly. When the command is issued, the drive sets BSY, initiates the seek, clears BSY, and generates an interrupt. Only the Cylinder register is valid for this command. The drive does not wait for the seek to complete before returning the interrupt. Seek complete (DSC) will be set upon completion of the command. If a new command is issued while a seek is in progress, the drive will wait, with BSY active, until the seek is complete before starting the new command. No checks are made on the validity of the sector number. The ERR bit in the Status register and the IDNF bit in the Error register will be set if an illegal cylinder number is specified.

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Initialize Drive Parameters This command enables the host to set the head switch and cylinder increment points for multiple sector operations. In translate mode, the logical head, sector, and cylinder numbers in the Task File will be translated to their native physical values in the Task File. They are not checked for validity by this command, therefore if they are invalid, no error will be reported until an illegal access is made by some other command. Upon receipt of the command, the drive sets BSY, saves the parameters, resets BSY, and generates an interrupt

Read Buffer This command allows the host to read the current contents of the drive's sector buffer. When this command is issued, the drive sets BSY, sets up the sector buffer for a read operation, sets DRQ, clears BSY, and generates an interrupt The host then reads up to 512bytes of data from the buffer.

Write Buffer This command allows the host to overwrite the contents of the drive's sector buffer with any data pattern desired. Only the command register is valid for this command. When this command is issued, the drive will set BSY, set up the sector buffer for a write operation, set DRQ, reset BSY, and generate on interrupt. The host may then write up to 512 bytes of data to the buffer.

Identify Drive The Identify Drive command allows the host to obtain parameter information from the drive. When the command is issued, the drive sets BSY, stores the required parameter information in the Sector buffer, sets the DRQ bit, and generates an interrupt. The parameter words in the buffer are in hexadecimal format right justified as shown Table 7-5.

WORD DESCRIPTION

()() A constant - OASA 01 Number of fixed cylinders 02 Number of removable cylinders 03 Number of heads 04 Number of unformatted bytes/track 05 Number of unformatted bytes/sector 06 Number of physical sectors/track 07 Number of bytes in the inter-sector gaps 08 Number of bytes in the sync fields 09 Vendor Unique 10-19 Serial number 20 Buffer type 21 Buffer size (x 512 bytes) 22 Number of ECC bytes passed during read or write long commands 23-26 Controller firmware revision 27-46 Model Number 47 Number of sectors/interrupts 48 Double word transfer flag 49-255 Reserved

Table 7-5 Drive Parameters

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Power Save Commands In order to conserve power, these commands allow the drive to operate in modes other than fully operational. These are: Idle Mode, in which the driveis up to speed is and ready to accept a command; Sleep Mode in which the drive is spun down with only the interface chip powered up; and Standby Mode in which the drive is spun down with all normal electronics on.

The Power Save Commands are as follows:

OxEO Enter Standby Mode immediately.

OxEl Enter Idle Mode immediately.

OxE2 Enter Standby Mode immediately.

OxE3 Enter Idle Mode immediately.

OxE5 This command allows the host to check the drive power status. If it is in Active or Power Save mode, the Sector Count register will be set to OxFF. If the drive is in, going to, or recovering from STANDBY MODE, the Sector Count register will be set to 00.

OxE6 Enter Sleep Mode

PARALLEL PORT

The Parallel Port is compatible to the IBM XT-AT Parallel Port, with a PS/2 like extended mode for bi-directional transfers. When the parallel port is disabled via the configuration register, all outputs are disabled, and register contents are preserved. Upon power up, the control signals are inactive. The status registers reflects the status signals.

Printer Interface Registers

Table 7-6 shows the registers associated with the parallel printer port These are compatible with the IBM PC parallel port. All addresses for the parallel port are offset from the base address specified during the UPC configuration process. The table shows the value contained in the parallel port registers after a hardware reset.

The parallel port registers are accessible in the SPARCbook's 8-bit 1/0 region at OxOOCCOOOOO. The address offset of the parallel port registers is programmable via one of the UPC configuration registers. Table 7-6 shows the addresses assigned by the resident firmware.

Data Register Data written to this register is transmitted to the printer. Data read from this port is identical to that which was last written by the host.

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OxOOCC00330 Data Register R/W OxOOCC00331 Status Register R OxOOCC00332 Control Register w

Table 7-6 Parallel Port Registers

Printer Status Registers This register contains the following status information:

Bit7 BUSY 0 = Printer busy 1 = Printer ready to accept data

Bit 6 ACK. 0 =Printer has received a character and is ready for another. 1 = Printer not ready

Bit5

Bit4

Bit3

Bits 2:0

PE-Paper Empty 0= Paper OK 1 =Paper end

SLCf 0 = Printer not selected 1 = Printer is online

ERROR 0 = Printer Error 1 = No errors.

Reserved

Printer Control Register The bit definitions for this register are:

Bit 7:6 Reserved

Bit5 DIR - Parallel Control Direction

RESET

DontCare Ox80 OxOO

In printer mode, the direction is always out, regardless of the state of this bit. In the extended mode: 0 =output 1 =input

Blt4 IRQEN. 0 = IRQ disabled 1 = Enable IRQ when ACK changes from active to inactive

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Bit 3

Bit 2

Bit 1:

BitO:

SLCTIN 0 = Printer not selected 1 = Printer selected

INIT 0 = Start the printer (50µ.s pulse minimum)

AUTOFD 0 = No autofeed. 1 = Printer to generate a line feed after each line

STROBE 0= No strobe 1 = Assert STROBE

MOUSE PORT

The SP ARCbook features an inbuilt Mousekey on the keyboard which is controlled by the microcontroller (see Chapter 6), and not the UPC.

In addition, the UPC provides a port which appears via a 6-pin mini-DIN connector located on the connector panel, to which an external pointing device (such as a mouse or graphics tablet) or keyboard may be connected.

Pointing devices provide the computer to which they are connected with position and button press information, and external keyboards provides character information. The UPC provides a serial data input channel and shift register to allow the host to read this information from an 8-bit data port. The UPC also provides a clock output used by the external device to synchronize its communications.

Devices connected to the mouse port must use TIL level signals and not RS232.

Connecting RS232 devices to the mouse port may cause damage to the SPARCbook

Mouse Port Registers

The UPC contains two registers associated with mouse controller operations. These are accessible in the 8-bit 1/0 region at OxOOCCOOOOO. The offset address for the mouse registers is programmable via one of the UPC configuration registers. The address used by the resident firmware is Ox310. Table 7-7 shows the mouse port registers.


OxOOCC00310 Mouse Port Data R Ox00CC00310 Mouse Port Status/Control R/W

Table 7-7 Mouse Port Registers

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Mouse Data Port This location is read by the host to obtain data input by an external mouse.

Mouse Status and Control Register This register contains a number of status bits and a number of control bits:

Control Bits Bit 7 Mouse Clock Enable

0 = Clock disabled 1 = Clock enabled

Bit 4 Pointing Device Interrupt 0 = Disable interrupt 1 = Enable interrupt

Bit 3 Pointing Device Reset 0 = Normal operation 1 = Reset device

Status Bits Bit 6 Pointing Device Clear

Bit5 Pointing Device Error

Bit 2 Pointing Device Transmit Idle

Bit 1 Pointing Device Character Received

BitO Pointing Device Idle

SERIAL PORT

The UPC incorporates a universal asynchronous receiver and transmitter (UAR'!) which provides a serial interface. This appears on the connector panel via an 8-pin mini DIN connector. Buffers external to the UPC convert the serial channel signals to RS232C levels. The UART allows data rates from 50 to 38400 Baud; a character size of 5 to 8 bits, with one start bit and l, 1.5 or 2 stop bits; and the use of even, odd or no parity .

Serial Port Registers

The UPC contains eleven registers associated with UART operations. These are accessible in the Pbus 8-bit 1/0 region at OxOOCCOOOOO. The offset address for the UART registers is programmable via one of the UPC configuration registers. The address used by the resident firmware is Ox3F8. Table 7-8 shows the UART port registers.

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Access to the Transmit and Receive buffers, to the Interrupt Enable register and Divisor register is controlled by bit 7 of the Byte Format register.

ADDRESS REGISTER

Byte Format Register Bit 7 = 0 OxOOCC003F8 Receive Buffer/fransmit Buffer OxOOCC003F9 Interrupt Enable Register

Byte Format Register Bit 7 = 1

Ox00CC003F8 Baud Rate Divisor LSB OxOOCC003F9 Baud Rate Divisor MSB

Byte Format Register Bit 7 = x

OxOOCC003FA Interrupt Flag Register OxOOCC003FB Byte Format Register OxOOCC003FC Modem Control Register OxOOCC003FD Line Status Register OxOOCC003FE Modem Status Register OxOOCC003FF Scratch Pad Register

Table 7-8 UPC Serial Port Registers

Transmit and Receive Butlers A read from this location returns data received from the serial port. A write is used to load a byte for transmission.

Interrupt Enable Register This register controls the enabling of four UART interrupt sources.

Bits 7:4

Bit 3

Bit 2

Bit 1

Bit 0

Reserved

Modern Status Interrupts 0 = Interrupts disabled 1 = Interrupt when Modem Register bits change state

Error Status Interrupts 0 = Interrupts disabled 1 = Interrupt on error

Transmit Buffer Interrupt 0 = Interrupt disabled 1 = Interrupt on Transmit Buffer empty

Receive Buffer Interrupt 0 = Interrupt disabled 1 = Interrupt when Receive Buffer contains valid data

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Interrupt Flag Register This register identifies the highest pending interrupt. It can be read to detennine the source of a UART intemipt.

Bits 7:0

Bits 2:1

BitO

Reserved

Interrupt Source 11 = Error Interrupt - highest priority 10 =Receive Buffer Full 01 = Transmit Buffer Empty 00 = Modem Status

Interrupt Aag 0 = Valid interrupt pending 1 = No interrupts pending

Byte Format Register This register is used to select the character length, number of stop bits, parity control and break control. It also contains a bit which controls host access to the Divisor registers.

Bit 7 Divisor register address bit

Bit6

Bit5

Bit4

Bit3

Bit 2

Bits 1:0

0 = No host access to divisor registers 1 = host access to divisor registers

Break control l = Force TxD pin to logic 0 (break condition) 0 = TxD pin normal operation

Force Parity 0 = Force Parity Disabled 1 = Force Parity Enabled

Parity Sense 0 = Odd Parity 1 = Even Parity

Parity Enable 0 = no parity generation or checking 1 = Parity generation and checking enabled

Stop Bits 0 = 1 Stop bit 1 = 1.5 if character length is 5 bits 2 bits if word length is 6, 7, or 8 bits

Character Length 00= 5 bits 01=6 bits 10= 7 bits 11=8 bits

101

Modem Control This register conttols the handshake lines.

Bit 7:2

Bit 1

BitO

Reserved in SP ARCbook Should be O's

RTS Control 0 = Assert RTS

DTRcontrol 0 = Assert DTR

Line Status Register This register contains information about error conditions. The following conditions are signified when the corresponding bit is at 1.

Bit 7 Always 0 Bit 6 Transmitter Empty Bit 5 Transmit Buffer Empty Bit 4 Break Interrupt Bit 3 Framing Error Bit 2 Parity Error Bit 1 Overrun Error Bit 0 Receive Buffer Full

Modem Status Register This register contains the information about modem lines.

Bit 7 Bit 6 Bit 5 Bit4 Bit3 Bit 2 Bit 1 Bit 0

Current DCD state Current Ring Indicator state Current DSR state Current CTS state DCD changed since this register was last read Ring Indicator changed since this register was last read OCR changed since this register was last read CTS changed since this register was last read

UPC CONFIGURATION

n n n n n n n n n n n n n

A significant portion of the 82C710 circuitry is used for configuration, all of which can be performed n under software control. This permits user friendly (menu-driven) UPC configuration. DIP switches and jumpers are eliminated meaning that it is not necessary to open the chassis to change the configu- n ration of a peripheral interface.

Since the UPC is software configured, a setup program must be run whenever the configuration is changed. This process entails placing the UPC in configuration mode and programming the on-chip n configuration registers.

n 102

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It should be noted that although the SP ARCbook provides a PC-AT style hardware environment for the UPC, it does not use a standard BIOS implementation. The SPARCbook operating system manages all device configurations and it is therefore not normally necessary for the user to access the UPC's internal registers.

UPC Configuration Sequence

In order to setup or change the configuration of the UPC, two consecutive addresses are used to select and access the internal configuration registers. These are occupied by the Configuration Register Index (CRD which is located at an even address and is used to point to the configuration register; and the Configuration Access Port (CAP) which is located at the next address, and is used to write data to the selected register.

Before these two locations can be used, however, the UPC must be placed in Configuration Mode, and in the process an address for the CRI supplied.

The UPC is located within the 8-bit 1/0 region of the SPARCbook's address map. Any address chosen for the CRI will have to lie within this region.

The configuration sequence comprises three steps:

1 Entering the configuration mode 2 Configuring the 82C710 3 Escaping the configuration mode

Entering Configuration Mode Assuming an address of OxOOCC00390 is selected for CRI, the following sequence would be used to enter the configuration mode:

Write Ox55 to OxOOCC002FA Write OxAA to OxOOCC003FA Write Ox36H to OxOOCC003FA Write OxE4 to OxOOCC003FA (Where OxE4 is Ox390 divided by 4) Write OxlB to Ox00CC002FA (Where OxlB is the complement ofOxE4)

LJ Following this sequence, the UPC is in configuration mode. If there is any departure from this sequence, the UPC will revert to its idle state, and the sequence will need to be started again.

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Configuring the UPC To access and write data to any of the configuration registers, two writes are needed.

First a pointer is written to the CRI; bit 3:0 provide the pointer to the configuration register, and bits 7:4 should be set to 0.

Following this, the data may be written to the selected register via the CAP.

Escaping Conraguration Mode To escape configuration mode, write any value into the configuration register F, as follows:

Write OxOF to Ox00CC00390 Write Ox?? to OxOOCC00391 (??=any value)

Configuration Register Description

There are sixteen configuration registers in the UPC. Settings are retained as long as standby power is maintained.

These registers are not affected by the RESET signal and are set to their default state only upon power up. Table 7-9 shows the configuration registers in the UPC with the default values upon power up, and values loaded by the SPARCbook resident firmware required for normal operation.

OFFSET FUNCTION POWER UP SPARCbook DEFAULT DEFAULT

OxOO Configuration 0 OxOC OxOC OxOl Configuration 1 OxOO Ox40 Ox02 Configuration 2 Ox Ox Ox Ox Ox03 Reserved - -Ox04 UART Port Address - Unused OxFE Ox FE Ox05 Reserved - -Ox06 Parallel Port Address Ox9E Ox CC Ox07 Reserved - -Ox08 Reserved - -Ox09 General Port Chip Select - Unused Ox BO OxBO OxOA Configuration A OxOO OxOO Ox OB Configuration B OxOO OxFO OxOC Configuration C OxAO OxAO Ox OD Mouse Port Address OxOO OxC4 Ox OE Configuration E OxOO OxOO Ox OF Configuration Index - -

Table 7-9 UPC Configuration Registers

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The only registers changed by the firmware are:

Configuration Register 1 Parallel Port Address Configuration Register B Mouse Port Address

Configuration Register 1

Only bit 6 in this register is changed in order to configure the parallel port for printer operation. All other bits retain their default settings.

Bit 7 Reset Conttol This bit determines the mamter in which the Reset pin affects the serial porL The default is 0, normal Reset.

Bit 6

Bit5

Bit4

Parallel Port Mode 0 =Output, printer only 1 =Bi-directional

UART CTS Control - Not used

UART DSR Control - Not used

Bit 3 UART DCD Conttol - Not used

Bits 2:0 Reserved

Parallel base address This register holds the base address of the parallel port. The contents of this register are multiplied by 4 to give the base address of the parallel port. A setting of OxCC identifies an address of Ox330.

Configuration B This register is used to set the polarity of the interrupts issued by the UPC. All interrupts in the SPARCbook are prioritized by the MPI (see Chapter 5) which requires requests to be configured as active low.

Bit 7

Bit6

Bit5

Mouse Interrupt Polarity 0 = Active High 1 = Active Lowt

Floppy Interrupt Polarity 0 = Active High 1 = Active Lowt

UART Interrupt Polarity Not used, should be 0

105

Bit4

Bit 3:0

Parallel Port Interrupt Polarity 0 = Active High 1 = Active Lowt

Not Used

t- Required by SPARCbook

Mouse Port Address This register holds the base address of the mouse port. The contents of this register are multiplied by 4 to give the base address of the parallel port. A setting of OxC4 identifies an address of Ox310.

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CHAPTER EIGHT MODEM

The SP ARCbook is equipped with a modem interface which allows its connection via a public telephone system (in the US only) for data communications or facsimile transmission.

The modem ·interface is implemented on the base board with a two-chip set comprising the SCl 1075 modem access controller (MAC) and the SCl 1054 modem, both from Sierra Semiconductor Corporation. These provide an extremely compact and low power interface with power management facilities to reduce power consumption when the modem is not in use.

Figure 8-1 shows the implementation of the modem interface in the SP ARCbook.

SC1107S Modem

Advanced Con1roller

RJNG INDICATOR

SC11S4 Modem

OFF HOOK

107

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MODEM OVERVIEW

The SCl 1075 provides a direct interface between the host system and SCl 1054 modem; it incorporates an Intel 8096 equivalent processor core, supporting an AT command set; contains a built-in 16C450 equivalent UART; and contains 16Kbyte of on-chip ROM and 320bytes of RAM.

The SCl 1054 is a complete 2400bps (bits per second) modem IC which, when combined with the SCl 1075, provides Sendfax capability of up to 9600bps.

The modem interface can be controlled using Hayes compatible commands written to the UART section of the MAC. Commands are sent to the interface using character strings, and these are interpreted by the MAC's processor core and acted on appropriately.

Command characters and data for transmission onto the telephone line are written into the UART's transmit buffer. Data received from the telephone line and status information from the MAC can be read from the UARTs receive buffer.

The modem interface operates in two modes: Command Mode or On-Line Mode. In Command Mode, characters written to the transmit buffer are regarded as being command characters. In the On-line mode, data written to this location (apart from the escape sequence+++) are transmitted onto the telephone line.

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INTERFACE CONTROL

The host may access the UART registers within the MAC; the MAC contains a number additional registers but these are accessible only by the internal microcontroller. The UART registers are accessible at base address Ox00C400000 and are shown in Table 8-1.

Bit 7 in the Line Control register is used as a pointer to either the transmit and receive buffers and the IRQ Enable register, or to the Divisor Latch registers. Bit 7 must contain 'O' to gain access to the ttansmit and receive Buffers.

The host is responsible for managing the transmit and receive buffers. During transmit operations, the host must supply data at a sufficient rate to ensure that there is always a new character for the modem to transmit; the modem is unable to wait and will regard an empty buffer as an error condition and disconnect the telephone line. During receive operations, the host must read the data in the buffer in time for the next incoming character from the telephone line.

The Modem generates interrupts on IRQ5 when the receive buffer contains a character, when the transmit buffer is empty, and also to signal error conditions. All interrupt requests within the SPARCbook are maskable and are prioritized by the MPI, encoding IRQ5 from the modem on the CPU level 8 interrupt request (see Chapter 5).


OOC400000 Receive Buffer R Transmit Buffer w Divisor Latch (LSB)t R/W

OOC400001 Interrupt Enable R/W Divisor Latch (MSB) t R/W

OOC400002 Interrupt ID R OOC400003 Line Control R/W OOC400004 Modem Control R/W OOC400005 Line Status R/W OOC400006 Modem Status R/W OOC400007 Scratch Pad R/W

Table 8-1 UART Registers

Note: t The divisor latch can be accessed only when bit 7 of the Line Control Register is set.

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MAC Integral UART Registers

This section describes the more significant registers in the UART, from the point of view of managing the flow of commands and data between main memory and the UART.

Interrupt Enable Register This register contains interrupt control bits. Setting one of the interrupt enable bits has the effect of enabling the associated interrupt request

Bits 7:4 Bit 3 Bit 2 Bit 1 Bit 0

Reserved Enable Modem Status Interrupt Enable Receiver Line Status Interrupt Enable Transmitter Holding Register Empty Interrupt Enable Received Data Available Interrupt

Interrupt Identification Register This register provides the identity of the highest priority pending interrupt condition, and a flag which indicates whether or not there is an interrupt pending. The UART prioritizes the internal interrupt requests as shown below.

Bit 7:3 Bit 2:1

BitO

Reserved Interrupt ID 11 = Receiver Line Status - highest priority 10 =Receiver Data Available 01 =Transmit Buffer Empty 00 =Modem Status - lowest priority Interrupt Pending Flag 1 = No Interrupt Pending 0 = Interrupt Pending

Line Status Register The Line Status register contains infromation which allows the condition of the transmit and receive buffers to be monitored.

Bit 7 Bit 6

Bit 5

Bit4

Reserved Transmitter Empty This bit when set indicates that both the transmit buffer and the transmit shift register are empty Transmitter Buffer Empty This bit when set indicates that the transmit holding register is empty. It is cleared automatically when the host writes data into the transmit holding register Break Interrupt Flag

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Bit 3 Framing Error Flag Bit 2 Parity Error Bit 1 Overrun Error Bit 0 Receiver Data Ready

THE AT COMMAND SET

This section describes the basic AT command set supported by the SCI 1075/1154 chipset, and the Sendfax extended command set. Table 8-2 provides a summary of the commands supported by the SPARCbook.

CODE DESCRIPTION

Basic AT Commands

A Go Off-hook in Answer Mode N Re-execute Previous Command AT Attention Characters B BelVCCfIT Protocol D Dial Telephone Number E Command Echo Hn Switch Hook Control In Identification L Speaker Volume M Speaker Control 0 Return to Online Qn Quiet Command Reset Code Sn= Writing to S-Register Sn? Reading From S-Register v Enable Short-form Result Code x Enable Extended Result Code Set &F Fetch Factory Configuration +++ Switch to Command Mode, but retain line connection

Sendfax Commands

#Bn Speed Control #En Received Frame Display Format Selection #Fn Mode Control #Pn Number of Pages to be Transmitted #Rn Resolution Control

Table 8-2 Hayes AT Command Set Summary

111

The modem enters the Command Mode when it is reset, when it loses contact with a remote modem, or when it is in Data Mode and receives the escape sequence+++.

When the modem is in Command Mode, it will accept instructions in the form of command lines, and in many instances will return responses. The Command Mode allows the modem to be instructed to perform functions such as originating or answering a call. When the modem makes a connection with a remote modem, it sends a connect response to the CPU.

Commands lines are written to the UART location at OxOOC400000 and responses are read from the same location.

All commands lines begin with the characters AT (with the exception of A/), may contain one or more commands and are terminated by a RETURN. Command lines may contain up to 40 characters, not including spaces. All characters before AT are ignored.

Basic Command Set

A Answer Incoming Call This forces the modem to go off-hook in answer mode.

Al Re-execute Previous Command The Ncommand repeats the last command. It is not preceded by the AT characters or terminated by pressing RETURN.

AT A Tention Characters

Bn Bell/CCITT Protocol

D Dial Telephone Number

These characters must appear at the beginning of all command lines.

This command selects the communication standard: n = 0 CCITT V.21 n = 1 V.22N.22bis n=2 V.23

This command causes the modem to dial up a remote modem. The following modifiers may be added: P Pulse Dial T Touch-tone Dial R Originate Call in Answer Mode W Wait for Dial Tone

Delay a Dial Sequence

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@ Wait for Quiet Go On-hook Return to Command Mode

S=n Dial a Stored Number

En Echo Command Characters This controls whether the modem echoes command characters back to the host:

Hn Switch Hook Control

n = 0 Characters Echoed n = I Characters Echoed

n = 0 Modem goes on-hook (hangs up) n = I Modem goes off-hook to access the telephone line

In Identification This command causes the modem to respond to the host by providing identification codes: n = 0 Request Product Code n = I ROM Checksum n = 2 Return OK Response n = 3 Manufacturers ID n = 4 Configuration Mode n = 33 Sierra ID

0 Return to Online This command is used to return to the MAC to the Data Mode following an escape sequence used to enter Command Mode.

Qn Command Response Control This command controls whether the modem provides responses to commands:

Sr=n Change Register Value

Sn? Read S Register

n = 0 Return Response to host n = I Do Not Send Response

This command selects an S register and changes its contents: r= 0- 27 n = 0-255

This command returns the contents of an S register: n=0-27

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Vn Response Format

Xn Select Extended Response Set

This command is used to select the fonnat of response made by the modem to the host: n = 0 Single Digit Response n = 1 Extended Response

&F Fetch Factory Configuration This command recalls the factory settings of the modem chipset.

Send/ax Command Set

#Bn Speed Control This command selects the initial fax transmission speed: n =4 2400bps n = 5 4800bps n = 6 7200 bps n = 7 9600bps

#En Received Frame Display Format This command selects the display fonnat for

#Fn Mode Control

HDLC frames: n = O Disable Display of HDLC Frames n = I Display Frame in Binary Fonnat n = 2 Display Frame in 2 Digit ASCII Hex Fonnat

This Command selects the modem operating mode n = 0 Return to Nonna! Mode n = 1 Enter Fax Mode

#Pn Number or Pages to be Transmitted n = 0 to 255

#Rn Resolution Control This command selects the resolution used for document transmission: n = 0 Send Document with Nonnal Resolution n = 1 Send Document with Fine Resolution

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S-REGISTERS

The MAC maintains a set of registers which can be written to and read using the S-register commands described previously. There are twenty-eight S-Registers summarized in Table 8-3.

REGISTER

so SI S2 S3 S4 SS S6 S7 S8 S9

SIO Sil Sl2 Sl3 Sl4 SIS Sl6 Sl7 Sl8 Sl9 S20 S21 S22 S23 S24 S2S S26 S27

FUNCTION

Rings Until Auto-answer Calls Count Number of Incoming Rings Escape Character Carriage Return Character Line Feed Character Backspace Character Dial Tone Wait Time Wait Time for Remote Carrier Comma Pause Time Carrier Detect Response Time Delay Time Between Loss of remote Carrier and Hang-up DTMF Dialing Speed Escape Guard Time Reserved E, Q, V Commands; Accept or Ignore Commands; TPDA Commands Reserved Modem Loopback Tests Reserved Modem test Timer Reserved Reserved J, &R, &D, &C, &S, Y Commands L, M, X, &P, &T4, &TS Commands, DTE Speed, Parity &T4 and &TS Commands, DTE Speed, Parity Reserved DTR Delay for Synchronous Operation RTS/CTS Delay &M, &L, &X and B Commands

Table 8-3 S-Register Summary

llS

Reading an S-Register The current value of an S-Register can be read using the Read S-Register command. For example, the command line:

ATSO?

will cause the modem to respond by returning the contents of the S-Register 0 in three-digit form followed by OK.

Changing an S-Register The contents of an S-Register can be changed using the Change S-Register Command. For example, the command line:

ATS0=2

will cause the modem to change the contents of S-Register 0 to 2. The modem responds by returning OK.

FAX RESPONSES

When a command is executed by the MAC, the hardware may report the result to the host Status information is returned to the host in the form of responses. The MAC may return short response codes consisting of a single character (or digit), or verbose responses consisting of a string of characters. The responses produced as a result of a fax session are summarized in Table 8-4.

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CED CFR CONNECT2400/FAX CONNECT4800/FAX CONNECT7200/FAX CONNECT9600/FAX CRCERROR CPR CSI DCN DIS FTT INVALID FRAME MCF RTN R1P

Table 8-4 Response Summary

DIGIT MEANING

a Answertone Detected g Remote Machine confirmation to receive w Connection Speed 2400bps x Connection Speed 4800bps y Connection Speed 7200bps z Connection Speed 9600bps e Error in received frame c Repeal Request - Remote Machine Identification d Disconnect b Remote Machine Capabilities Frame f Failure to Train i Received Frame Invalid m Message Received OK h Message Not Received OK j Retrain Positive

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CHAPTER NINE ETHERNET INTERFACE

The SP ARCbook is equipped with an Ethernet interface which allows its connection to a network for fast communications with other workstations, ftleservers, printservers, and so on.

This section of the SP ARCbook Technical Reference describes how the Ethernet interface in the SP ARCbook is implemented. An in-depth discussion about networking is beyond the scope of this manual, but a brief overview is provided.

Figure 9-1 SP ARCbook Network Connection

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NETWORKING OVERVIEW

Ethernet is a send and receive half duplex serial communications system capable of data transfers at up to 10 million bits per second.

A networking standard has been formalized by the Institute of Electrical and Electronic Engineers in the IEEE802.3 standard. This defmes the type of cables and connections used to form the network, the topology of the network and the protocols which control access to the network.

Coupling the SPARCbook to a network cable requires an external network transceiver and transceiver cable (sometimes called a 'drop cable'). The network transceiver is attached to the network cable, and the transceiver cable is connected between the 15-way locking D-type connector on the rear of the SPARCbook and the network transceiver, as illustrated in Figure 9-1.

The transceiver transmits and receives the data carrier signal on the network cable. In addition, it provides isolation between the SP ARCbook and network so that its addition to or removal from the network does not affect the network. The transceiver is also responsible for detecting 'collisions', which occur when two or more nodes attempt to transmit simultaneously.

Ethernet Protocol

The IEEE802.3 standard specifies a Carrier Sense Multiple Access with Collision Detection protocol (CSMNCD) as a simple and efficient means of determining how a node may gain access to and transmit information over the network.

Carrier Sense A node wishing to transmit data over the network must first listen to the cable to detect whether another station is already using the cable. Transmission is deferred until the cable is clear.

Multiple Acee~ Any station wishing to transmit may do so if the cable is clear. There is no central controller to allocate use of the network.

Collision Detection This provides a mechanism for resolving the situation which may occur when more than one station starts to transmit at precisely the same moment Each transmitting station listens to the signal on the cable. If more than one station is transmitting, then the signal on the cable will no longer be the same the signal being transmitted, but will be garbled; i.e. a collision will have occurred. In this situation

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the competing stations continue to transmit for a time in order to 'jam' the network, which signals the collision to other stations on the network. All competing stations then suspend tarnsmission for a random delay before attempting again.

Basic Operations

At any given time, stations attached to the network function as either a transmitter or receiver. Data is passed between stations in bursts (or packets) at up to 10 million bits per second.

An Ethernet packet contains the destination address of the intended recipient, the source address identifying the sender, the data length and then the data itself. The format of an Ethernet packet is shown in Figure 9-2.

6Bytes 6Bytes 2Bytes 46 - 1500Bytes 4Bytes

I O..tination Address I Source Address 11-3 Data ? PAD I CRC

Figure 9-2 Ethernet Packet

Transmission Packets are placed into an area of buffer memory by the CPU ready for transmission by the Ethernet conttoller. The Ethernet controller automatically performs a cyclic redundancy check (CRC) during transmission and appends a 4byte result to the end of the packet as a frame check. The overall length of the packet must be between 64 to 1518bytes, including the checksum; padding may be added by the conttoller to achieve the minimum required length if required. The controller also adds a preamble and synchronization pattern to the start of the packet to enable detection and synchronization by the receiver. A Manchester encoder produces a differential signal which carries the data and an embedded clock signal onto the network cable.

Reception When the receiver node detects a carrier on the network, it passes the incoming packet to the Manchester decoder within the controller. A phase locked loop synchronizes with the preamble to allow recovery of the clock signal and data. The controller examines the destination address in the header and stores packets containing a valid address in a buffer memory where it can be read by the CPU. During reception, the receiver performs a CRC and checks the result against the frame check. Discrepancies are reported as CRC errors.

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Errors The Ethernet controller reports any errors, such as CRC errors or missed packets, to the host using interrupts and error bits in its status registers.

Addressing There are three addressing modes. The first mode is physical addressing which uses the 48-bit (6byte) destination address in the packet header to uniquely identify one receiver. The physical address requires comparison by a receiver with its own unique 'Node ID'. The issuing of Ethernet addresses is overseen by the IEEE, ensuring globally that no two stations share the same physical address. Each SPARCbook has its own unique Ethernet address programmed into it during manufacture.

The second mode is Multicast (or Logical) Addressing which may be used to send packets to several receivers at once. The third mode is Broadcast Addressing, where packets are sent to every node attached to the network.

THE SPARCBOOK ETHERNET IMPLEMENTATION

The Ethernet interface in the SP ARCbook is implemented with a Fujitsu 86960 Network Interface Controller with Encoder/Decoder (NICE). NICE is a highly integrated device which incorporates a Manchester encoder and decoder, a data link controller, and a buffer memory management unit in a single chip.

Figure 9-3 illustrates the architecture of the Ethernet interface in the SPARCbook.

/-------·----------···········--··------ - - - -----------------~ . . . . : SPARCbook : • fDlaDoJ • . . • CPU ' . . . . . . . . : .

64-bitMbua MPf

ASIC

Figure 9-3 Ethernet Interface Architecture

16-bit

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The NICE is provided with a dedicated 64Kbyte buffer memory accessible to the SPARC CPU (or host) via a 16-bit buffer port. The NICE allows multiple data frames to be transmitted directly from the buff er to the network with a single transmit command.

The interface between the NICE and the SPARC CPU is provided by the MPI (see Chapter 5). The MPI transfers data between the buffer memory and the Mbus via internal FIF'Os and provides data packing between the Mbus and Pbus, allowing the CPU to access the buffer memory using 64-bit single cycle or burst accesses.

Fabricated in low power CMOS technology, the NICE features a stand-by mode which can be used to reduce its power consumption when the network interface is not in use. The SPARCbook's power management facility takes full advantage of this feature in order to maximize battery life.

FUNCTIONAL DESCRIPTION OF THE NICE

The MB86960 incorporates four major functional elements, as shown in Figure 9-4, these are:

• • • •

Host System Interface Buffer Management Unit Data Link Controller Manchester Encoder and Decoder

Buffer Mmlqer

Figure 9-4 NICE Simplified Block Diagram

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NICE Host System Interface

The host system interface provides the connection between the NICE' s internal registers and buffers and the Pbus and hence the SPARC CPU. The NICE contains three register sets. These are the Data Link Controller Register set, the Multicast Address Register set, and the Buffer Port Memory Register set. These are shown in Figure 9-5.

Data Link Controller Register Set The Data Link Controller register set contains sixteen registers which are used by the host to initialire and control the activity of the NICE, and to provide the host with error status infonnation. The lower eight registers of this group occupy the lower eight address locations within the NICE's address space, and are always accessible. The upper eight registers in this group share the NICE's remaining address space with the two other register groups.

Bits 2 and 3 in Control Register 2 are used to select between the register groups sharing the upper half of the NICE' s address space, as illustrated in Figure 9-5.

Register Address

Ox00C20000

Ox00C20001

Ox00C20002

Ox00C20003

Ox00C20004

Ox00C2000S

Ox00C20006

Ox00C20007

Ox00C20008

Ox00C20009

Ox00C2000A

OxOOC2000B

OxOOC2000C

Ox00C2000D

Ox00C2000E

Ox00C2000F

Da1a Link Controller Set

Tnmmitlnll tMtlk

Node ID

Node ID

Node ID

Node ID

Node ID

Node ID

TDR(LSB)

TDR(MSB)

Figure 9-5 NICE Internal Registers

Con1rol Regista" 2 Bits3:2

Mask Address Set

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Buffer Pert Memory Set

':::::11:·:~ii';i:,.t'.=~;:~;·~~;:1:::'.·: I Bulfer~ Part I ~~~~tt;~t~~~;~~~tt~~~i~~~i~~~~~~r~~~~~~~~r~~~~~~~~~~~!tt~~!:

Tnmmit l'lclmt ClllllrOl 2

DMAl!mble

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After initialization, it is normally only necessary to access the lower eight registers in the Data Link Controller registers, to obtain status information, and the Buffer Memory Port to read and write data packets and to issue transmit commands.

The NICE supports 8- or 16-bit accesses, little or big-endian byte ordering and can provide OMA support. In the SPARCbook implementation the NICE should be set up with a 16-bit interface and little endian addressing. The NICE's own OMA facilities should be disabled; these are not used because host accesses to the NICE are controlled by the MPI.

When the NICE receives a data packet from the network, it checks the header information for a valid destination address.

Physical addresses, those with a 'O' in the least significant bit, are compared with the contents of the Node ID registers in the Data Link Controller Register set These combine to form a single 48-bit node ID. When an address match occurs, the receiver ttansfers the incoming packet into the receive buffer memory.

Mask Address Register Set All eight registers in this set combine to provide a 64-bit logical address filter (or hash filter). A multicast (or logical) address is identified by a '1' in the least significant bit of the destination address contained in the packet header.

When the NICE detects a 'l' in the first bit of an incoming address, it passes the address through its internal CRC logic. This produces a 32-bit result The least significant 6bits of this result are used to provide an address for one of the 64bits contained in the eight multicast address registers. If the bit selected is a '1'' then the packet is accepted into the receive buffer.

This mechanism provides the NICE with the ability to recognize up to 64 destination addresses from the network as being possibly valid for the SPARCbook; the software has to examine the validity of the address, but has to do so far less often than if every address had to be checked in software.

Multicast address filtering is illustrated in Figure 9-6

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~ 0

Destination Addrcll1

Multicast Address (Bit 0 = 1)

CRC Logic

Enable

Multicast Address Registers (combined IO form a 64-bit hash filter)

Figure 9-6 Multicast Address Filterering

Buffer Port Memory Register Set

32 s 0 CRCR..Wtant

6-bit Address selects one bit from Multicast Address Filter

The Buffer Port Register set provides the host with access to the transmit and receive buffer memory and also contains packet control and DMA control registers.

The Buffer Memory Port allows the host to write data into the transmit buffer using 16-bit transfers. The NICE maintains internal pointers so that repeated writes to this location are automatically directed to the next 16-bit location. Similarly, the internal pointers allow successive reads of the Buffer Memory Port to access successive 16-bit locations in the receive buffer memory.

Bit 7 in Packet Control Register 1 is used by the host to command a start of transmission, and bits 6:0 are used to inform the buffer manager of the number of packets to be transmitted, allowing back to back transmission of up to 128 packets.

The DMA control registers should be configured to disable DMA operations by the NICE.

Buffer Manager

Two SRAM devices provide the NICE with a 64Kbyte buffer memory. The Buffer Manager within the NICE automatically prioritizes and services requests for access to the buffer from the host and Data Link Controller. It updates all buffer pointers and allocates memory space for incoming packets, and provides status information via the status registers.

In the SPARCbook, the CPU is able to write to the Buffer Memory Port using 64-bit single cycle accesses or burst accesses via the MPI (see Chapter 5). The MPI automatically converts a 64-bit access into a sequence of four 16-bit cycles on the Pbus.

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8Kbytea1----------1

Transmit Buffer 2

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Figure 9-7 Transmit and Receive Buffer Memory Organization

The buffer contains two areas: one for transmit data and one for receive data. These are shown in Figure 9-7.

Transmit Buffer The transmit buffer may be configured in software, via Control Register 1, as a single banked 16Kbyte buffer or a dual banked 4, 8 or 16Kbyte buffer. With a dual banked configuration, the host is able to write to one bank while the Data Link Controller transmits from or receives packets into the other bank. The internal pointer controls bank and location selection within the buffer transparently to the programmer. The NICE switches banks each time a Start Transmission command is issued.

When all packets to be transmitted have been loaded into the buffer, transmission is initiated by programming the number of packets in Packet Control Register 1 bits and asserting the transmit start bit in the same register. ·

Receive Buffer The receive buffer occupies the remaining space in the buffer memory after the allocation of the transmit buffer size.

Each received packet is preceded by a 4byte header. The first byte provides status information, the second contains irrelevant data, and the remaining two contain the packet length. Reading more than the indicated number of bytes will advance the internal pointers beyond one packet and into the beginning of the next or may cause a bus read error. Reading fewer bytes will leave garbage at the start of the next packet

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INTERRUPTS

All interrupts in the SPARCbook are handled via the MPI (see Chapter 5). The NICE produces an active low interrupt on IRQ level 7.

Interrupts are generated when a packet is transmitted or received, or if a transmit or receive error occurs and the corresponding mask is set.

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CHAPTER TEN DISPLAY CONTROLLER

The SPARCbook uses a CL-GD6410 to provide control of the LCD flat panel display built in to the SPARCbook and an external CRT monitor. It provides a VGA subsystem for SPARCbook allowing the user to operate an externally connected analogue CRT VGA monitor without disabling the LCD display, and without using a VGA add-on card. The CL-GD6410 supports the generic VGA monitor concept advanced by the Video Electronics Standards Association (VESA) for 350, 400 and 480 scan line monitors.

Models fitted with a color LCD display also contain a CL-006340 Color LCD Controller. This provides additional interfacing between the display controller and color LCD display. To software, the display controller and color LCD controller appear to be one device. Each one decodes addresses for accesses to its internal registers and color palette.

Figure 10-1

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DISPLAY INTERFACE OVERVIEW

The CL-GD6410 interfaces directly to the CPU via the 16-bit Pbus and MPI, to 256 Kbytes of video memory and to the display devices.

The SP ARCbook is equipped with a 640 x 480 pixel monochrome or color LCD panels. The color version is able to display up to 16 colors simultaneously from a palette of 262144, while the monochrome version provides color to grayscale rendering to display 16 gray levels. Color to grayscale rendering allows color images to be displayed to good effect on the monochrome LCD display.

The Cl..6410 provides a host interfacewhich allows access to.its internal control register, color palette and display memory. The CL.6410 also incorporates a digital to analogue converter which transforms color information from the color palette into the RGB signals required to directly drive a color CRT display.

HOST INTERFACE

In the SPARCbook, the MPI provides the SPARC CPU with direct access to the CL-GD6410. Memory reads and writes use 16-bit bus cycles, while 1/0 commands use 8-bit bus cycles.

Some of the internal registers within the CL-G 06410 and CL-GD6340 can be accessed directly by the host, but many others are accessed via index registers. To access an extension register, a pointer to the required register is written to the index registers and then, in a second access cycle, the data is written to or read from the selected register. During register accesses by the host, memory accesses by the CL6410 and screen refresh activities continue to occur uninterrupted.

Host accesses to video memory are channelled via the CL-GD6410. The SPARCbook resident firmware establishes the proper address/data/timing parameters in the CL-GD6410 registers in order to transfer to and from video memory. The CL-GD6410 also contains an intelligent address sequencer that allocates video memory cycles to the host, to the VRAM refresh and the display CRT controllers.

Although the SPARCbook provides a PC-AT style hardware environment for the display controllers, it does not provide a standard BIOS. Configuration of the display interface is normally carried out via the operating system, as described in the SPARCbook User's Guide.

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ADDRESS VGA PORT

Ox00C0003B4 CRTC Index MP (r/w) OxOOC0003B5 CRTC Data MP (r/w) OxOOC0003CO Attribute Controller Index (r/w) Data (w) OxOOCOOffiCl Attribute Controller Data (r) in VGA

Attribute Controller Data (r/w) in EGA OxOOC0003C2 Misc Output (w), Feature (r) Ox00C0003C3 Motherboard Sleep Address (r/w)

In address space only if switched enable. OxOOC0003C4 Sequencer (r/w) OxOOC0003C5 Sequencer (r/w) Ox00C0003C6 RAMDAC Pixel Mask (CPRd and CPWr) OxOOC0003C7 RAMDAC Address Reg. Read Mode(w)

(affects CPWr on writes) RAMDAC Status Register

OxOOC0003C8 RAMDAC Address Register Write Mode (CPRd and CPWr) OxOOC0003C9 RAMDAC Data (CPRd and CPWr) Ox00C0003CA Feature Control (r) Ox00C0003CC Misc Output (r) OxOOC0003CE Graphics Controller and Extensions Index (r/w) Ox00C0003CF Graphics Controller and Extensions Data (r/w) OxOOC0003D4 CRTC Index (r/w) OxOOC0003D5 CRTC Data (r/w) OxOOC0003DA Feature Control (w), Display Status (r) Ox00C0046E8 AT Adapter Sleep Address (r/w) (if switch enabled)

Table 10-1 Display Controller Memory Map Summary

Host Accesses to the Color Lookup Table

To write a color definition to the lookup table, a value specifying the address location in the lookup table is first written to the RAMDAC Write Mode address register. Following this, the color values for the red, green and blue intensities are written in succession to the RAMDAC Pixel Data register. After the blue data is latched, the new color data is transferred into the lookup table at the defined address, and the address register is incremented automatically to point to the next palette location.

Read operations are similar but use the RAMDAC Read Mode Address register to point to locations in the color palette.

If the address register is loaded with a new starting address while an unfinished sequence is in progress, the system resets and starts the new sequence.

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Display Access to Video Memory

The GD6410 contains video shift registers which interface with the display. It performs the operations necessary to fetch scan line data from the font bitmaps, while seperately controlling the video memory address buses.

The display interface in the SPARCbook is operated in a bit-mapped graphics mode, with 4bits/pixel. The pixel data is used to address entries in the color palette, selecting red, green and blue color value for that pixel to be output to the DAC. The GD6410 monitors the active and inactive areas of the screen and cursor position, and supplies the HSYNC, VSYNC, BLANK and Display Enable screen control signals.

The GD6410 is connected directly to a monochrome dual-scan LCD display. An additional 64K x 4 DRAM is provided to act as a frame accelerator for split-panel data formating. Data from the frame accelerator and the video memory is supplied in parallel to the 4-bit upper and lower panel data buses of the LCD flat panel. This technique maintains normal display contrast but reduces the power consumption of the video circuitry becuase the rate at which data is fetched from video memory is effectively half the panel frame rate.

In the color version, the CL-006340 takes the pixel information for the LCD and provides color mapping for the color LCD display.

INTERNAL RAMDAC OPERATION

The GD6410 and GD6340 both include an internal RAMDAC. A RAMDAC consists of an area.of RAM containing a color lookup table (or color palette) and a digital to analogue converter.

The color palettes contain 256 x 18 color lookup table which is addressed by pixel information from the VRAM to provide three 6-bit color values for each pixel. The digital to analogue converter converts the three 6-bit values from the palette into the analogue red, green and blue video signals required to drive a CRT. The RAMDAC also provides a pixel mask register and a border color register.

The two color palettes occupy the same address in the SPARCbook's address map so that the color mappings contained by the two display controllers are always identical. Since the external CRT is controlled by the GD6410 in both the monochrome and color models of the SP ARCbook, identical color palettes in the two devices ensures color consistency between the color LCD and CRT displays

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SIMULTANEOUS DISPLAY ENABLING

Simultaneous display operations are controlled by the CL-GD6410 using the Display Mode Register, the Write Control Register, and the CRTC Test Register

The CL-GD6410 includes all registers and data paths required for VGA compatibilty. VGA enhancements include sixteen simultaneously loadable text fonts , Write Mode 3 and readable registers. The CL-GD6410 supports extended-resolution display modes with CRT displays.

Extended graphics resolution of 800 x 600 mode with a 4:3 aspect ratio can be displayed using multifrequency analog CRT monitors.

High-resolution text modes of between 100 columns by 30 rows and 132 columns by 60 rows can be supported on analog CRT monitors by the CL-GD6410. Text modes of up to 100 columns by 30 rows are supported for 640 x 480 LCD flat panel displays.

Grayscaling and color rendering for the LCD displays is accomplished by modulating the ON-to-OFF time of individual pixels in the panel.and allowing the eye to integrate the superimposed pixels to 16 perceptible grays levels on a monochrome display or 256 colors on a color display. Flicker is eliminated by proprietary Cirrus Logic techniques involving distribution of time between ON and OFF pixels during frame modulation.

INTELLIGENT POWER MANAGEMENT AND SEQUENCING

Notebook and laptop PCs have stringent power limitations due to battery operation and heat dissipation. To meet these needs, the CL-GD6410 is manufactured using low-power CMOS technology. In addition, the CL-GD6410 has programmable output pins as well as other intelligent power management features

Normal Mode Conditions

•

Power to LCD panel and full screen refresh CPU access to video memory Refresh to video memory CPU access to the VO registers and the RAMDAC

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Standby Mode Conditions

No power to LCD panel; no screen refresh Panel power Sequencing is observed CPU access to video memory, 110 registers and the RAMDAC Refresh to video memory Frequency Synthesizer remains powered-up

The primary power savings in this mode comes from shutting down power to the LCD panel only. Since there is no screen refresh, normal clock rates are not required and may be replaced by slower clock rates to further reduce power consumption. Any RAMDAC 1/0 can be executed.

The system will recover from standby mode after detecting either video memory read or write accesses or the presence of the SSCLK signal. If power sequencing is in progress, then the CL-GD6410 will allow the sequencing to complete before exiting from standby mode.

Power-save timers that allows it to be programmable in increments of 1 minute up to 63 minutes. If the power-save timer is enabled, the programmed time-out time from the last stimuli is used to automatically switch to standby mode. The timer can be activated by either the SSCLK signal or by reads or writes to CPU memory access.

Suspend Mode

No power to LCD panel; no screen refresh Panel power sequencing is observed Refresh to video memory continues

• No CPU access to RAMDAC, video memory, or registers Frequency Synthesizer is powered-down

The power savings in this mode occurs because host access to video memory is denied, and a slower clock is in use. This slow clock refreshes video memory by keeping CAS low and pulsing on RAS throughout the Suspend Mode. If slow-refresh DRAM is used, a clock running as slow as 32 kHz can be used, clocking both edges. Other than this refresh logic, the rest of the CL-GD6410 has no clocks, reducing power consumption even further.

Suspend Mode can be activated or deactivated, under program control.

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Shut Down

Prior to initiating a system-wide shutdown, the system can save the state of the video subsystem so it can be restored later. The CL-GD6410 allows the system to save or restore the staws of all controller registers.

A pixel word mask is incorporated to allow the incoming pixel address to be altered or masked, permitting changes to the color lookup table contents to be made immediately. This feawre allows special display operations such as flashing objects and overlays to be created.

The color lookup table contents are accessed via its 8-bit-wide host interface. An internal synchronizing circuit allows the color value accesses to be completely asynchronous to the pixel video operation.

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CHAPTER ELEVEN MK48T02 BATTERY BACKED

REAL TIME CLOCK AND SRAM

The MK48T02 is a 2Kbyte zero power timekeeper and RAM which combines a CMOS SRAM, a bytewide accessible real-time clock, a crystal oscillator and a long life lithium-carbon-monofluoride battery in a single package. The device appears as an ordinary 2K x 8 RAM array with the added advantages that data is retained during power-down periods and that the uppermost 8bytes provide an accurately updated real-time clock.

The RTC/RAM appears in the SPARCbook address map at address OxOOC600000. Within the 2Kbyte space that the device occupies, the RTC is contained in the uppermost 8bytes, and the RAM the remaining 2040bytes.

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BATTERYBACKEDSRAM

The battery-backed RAM of the MK48T02 is used in the conventional manner. The power-up and power-down ttansitions to and from the battery-backed mode are handled automatically by the hardware and do not require any special intervention from the user.

REAL TIME CWCK

The Real Time clock area of the MK48T02 consists of 8 registers which contain the clock data and control information. The register organisation of the MK48T02 is shown in Figure 11-1.

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RTC Operanon

Within the RTC are a number of Binary Coded Decimal (BCD) counters configured to operate as a seconds, minutes, hour, day/date, month and year counter chain. A set of read-write registers are used to communicate with the counter chain. The counter chain is timed by a quartz crystal oscillator and programmable calibrator which generate accurate master signals to clock the entire RTC. Finally, a set of control and status bits are used to control of the oscillator, calibrator and read and write registers .

The control bits which govern the read and write operations to the RTC are bits 6 and 7 of the control register. These are positive polarity enable bits which control the transfer of data between the RTC counter registers and the external bus.

When the Read bit is set, the data at the RTC counter output is latched into the RTC read registers. In this mode the unchanging RTC data can be read accurately . Although the RTC data is stationary when the Read Bit is asserted, the RTC counter stages continue to be updated in the normal manner. When the RTC data has been read, the Read bit should be cleared. Conventional read operations of the RTC counter registers are possible when the Read Bit is 'O', but in this mode the changing data cannot be guaranteed to be read correctly.

When the write bit is set, values may be written into the RTC. In this mode a complete set of time and date infonnation may be assembled at leisure within the relevant RTC inputs. When the Write Bit is subsequently cleared the assembled time infonnation is transferred in one operation into the RTC counters. The RTC then recommences operation from this point with the new information.

When the RTC is not required for very long periods of time (many months), it can be placed in a lowpower mode to extend the battery life. In this case the oscillator is halted and normal RTC operation ceases. The low power mode is initiated by setting the ST bit, the most significant bit (bit 7) of the Seconds register. The typical lifetime of the RTC/SRAM is expected to be in excess of 7 years for most operating conditions.

139

In order to start the oscillator again, not only must the Stop bit be reset back to a 'O', but also the Start bit must be taken slowly through a 0, 1, O cycle. In this case the complete start-up sequence is follows:

1. Set the Write bit to a 1 - to enable write operations to the RTC 2. Reset the Start bit to a 0 - to enable oscillations 3. Set the Start bit to a 1 - to set up the Start Oscillator command 4. Reset the Write bit to a 0 - to issue the Start Oscillator command 5. Wait 2 seconds- to allow the Oscillator to settle 6. Set the Write bit to a 1 - to enable write operations to the RTC 7. Reset the Start bit to a 0 - to turn off kick-start mode 8. Set the correct time and date 9. Reset the Write bit to a 0 - to transfer new data into the RTC

Real Time Clock Calibration

Although the RTC has good time-accuracy, the final operational accuracy will depend on the temperature and temperature-stability of the operating environment

Recalibration is performed by writing a calibration value into the control register. This figure is used to periodically add or subtract pulses from the RTC chain. The value that is required for compensation can be calculated most easily from a knowledge of the parts-per-million (ppm) error of the RTC. This can be derived from the quantity of error which accumulates over a known time period.

The calibration value that is written into the controlregister is the ppm error divided by -2.034; that is, the RTC can be calibrated in increments of 2 ppm (approximately). The calibration data occupies the lowest 6 bits of the control register. Of this data, the lowest 5 bits constitute a calibration value and the most significant bit is a sign bit. When the sign bit is a zero, the calibration figure is negative and controls how much slower the clock will run; when the sign bit is a one, the calibration value is positive and controls how much faster the clock will run.

140


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CHAPTER TWELVE Sl-BASE SCHEMATICS DESCRIPTION

Sheetl DRAM CONTROL

The MACH210 device (U39) is a progammable device similar to a PAL but considerably larger. Full details of the mode of operation of this device are available in Chapter 5. It is used as the DRAM State Machine, controlling the operation of the DRAM array.

The TS32A (U43) is used as the DRAM address multiplexer, providing the Row and Column addresses for the DRAM array on the BMA lines. The multiplexing is controlled by the signals I ROWEN and /COLEN generated by U39. The address is latched from the MAD lines into the 'B' side of the TS32A by the signal MCLK qualified by the signal /MAS, which is the synchronized cycle start signal. /MAS is generated by Ul on Sheet 1 of the S 1-CPU board schematics. Three of the multiplexed address lines (BMAO, 1 and 10) are driven by the TS32A during the Row Address phase and by U39 during the Column Address phase.

U43 also latches MAD(3:0, 41:40) onto the permanently enabled DLA lines and MAD(36) onto the permanently enabled READ line. These are used as control signals by U39.

U19 and U51 are the Parity Storage DRAMs, holding one parity bit per byte for the entire memory array. Write-Per-Bit DRAMs are used, which allow any combination of the x4 active bits at each address to be altered in a single cycle (masking off the remaining bits). The masking is carried out by writing a code to the device on the data lines during the Row Address phase of the Write cycle. U12 is used to buffer the code supplied by U39 onto the parity data bus, PARD(7:0), and is enabled during the Row Address phase by the signal /ROWEN from U39.

141

SHEET2 DRAM

The DRAM is organized into a 64-bit wide array, using sixteen x4 devices, either 4Mbit or 16Mbit fast page mode chips. The array is subdivided into two 32-bit wide blocks, the Upper and Lower blocks, which are identified by the use of the /RASU and /RASL signals. These, combined with the CAS(3:0) signals, allow valid combinations of byte, halfword, word and doubleword to be made active. Note that accesses that are unaligned across the upper and lower block boundaries are not catered for - the Parity Storage system will not cater for these types of (illegal) access. The DRAMs take the row and column addresses from the BMA(l 1 :0) lines and data is on the MD(63:0) bus.

Sheet3 PARITY GENERATION

On the right-hand side of the sheet are eight ACT11286 devices (U7, Ul 1, U14, U21, U40, U41, U49

n n n n n n n

and U50). The ACT11286 is a 9-bit Parity Generator/Checker chip. For Writes to the DRAM array, n the /PARXMIT signal is driven low, causing the Parity Error lines to be driven high (ie inactive) and the PARO lines are driven to the correct parity levels as generated by the 11286 devices. When the I P ARXMIT signal is high, the P ARD lines are used as inputs into the 11286 devices and the stored parity is checked against the data on the MD bus. Errors are flagged by one or more of the PERR n lines being driven low. The individual PERR lines are then combined by U47 to produce a common parity error signal P ARERR. If an even number of the data lines to a single device are High, the associated P ARD line should be high; if an odd number of data lines are high, then the P ARD line n should be low.

The ACT16245 devices also shown on Sheet 3 are the DRAM data buffers. They connect the n memory data bus to the multiplexed MAD bus. The direction of data flow is controlled by the I DBUFDlR signal and the devices are enabled by the /DBUFEN signal. Both of these signals are generated by U39 on Sheet 1. When /DBUFDIR is Low, the data flow is from the MAD bus to the n MD bus. When /DBUFDIR is High, the data flow is from the MD bus to the MAD bus.

142

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Sheet4 MBUS INTERFACE & MISCELLANEOUS 110

U38 is the MPI ASIC (Mbus to Peripheral Interface Application-Specific Integrated Circuit) that fonns the interface between the Mbus (MAD0:63) and the on-board PC-AT style buses PA(l8:0) and PD(l5:0). Several other functional units are integrated into U38, including a programmable interrupt encoder (encoding the indiviual interrupt lines /IRQ(9:0) onto the four IRL(3:0) lines that are connected to the 7C600 Integer Unit), an address decoder (decoding the Mbus address map and providing several Chip Select signals- see Chapter 5) and two connections to U28, the 87C51 programmable microcontroller. The MPI ASIC is discussed fully in Chapter 5.

The MPI ASIC operates by changing Mbus cycles into PC-AT bus cycles. The device includes a OMA controller for floppy disk data transfers, and an internal 512byte FIFO to improve efficiency. The Mbus cycles can be 8, 16, 32 or 64bit transfers. The MPI perfonns byte packing and unpacking as required on the 16-bit Pbus, running the necessary number of data cycles on the Pbus until the required amount of data has been transferred. The MPI also handles write-posting to the Pbus from theMbus.

U28 features four 8bit 1/0 ports and is used to control the following facilities:

Keyboard scanning Mouse key interface with host conversion Intercepting specific keyboard commands (eg brightn~ contrast

adjustment) Monitoring power supply status Interfacing to power supply and user system LED indicators System temperature measurement ' Reading/writing the system EEPROM Adjusting brightness and contrast Hardware reset

U35, the LTC1093 from Linear Technology, is a six-channel lObit serial analogue to digital converter. A serial command word can be clocked into the device and the AID conversion result, from the channel selected by the command, clocked out and into U28. This provides the mechanism by which the system temperature and mouse key are monitored. Four channels are dedicated to the forcesensitive resistors that make up the mouse key, enabling the 87C51 to return a mouse motion value to the IU (the 87C51 calculates the mouse motion using the values returned from the force-sensitive resistors and an algorithm programmed into its internal memory).

143

U58 and U59 are digitally controlled potentiometers, with a minimum resistance of 40'2, an increment size of 5050 and a maximum resistance of 50ldl. U58 controls the display brightness and U59 the contrast. The X9C103 from Xicor contains a small area of nonvolatile memory (EEPROM) so that settings are not lost when the system is powered off. In response to user commands, the 87C51 can increment or decrement the setting of the potentiometer, thereby adjusting the LCD brigh111ess and contrast.

U31, the 380105 device, is a keyboard scanner. At the start of a sequence, U28 asserts then releases the Reset line to U31. The 87C51 then issues a string of CLK pulses to the keyboard scanner, continuing until the cycle is finished when Reset is driven again. U31 responds by driving DR(l) on the first clock after Reset, DR(2) on the second, and so on. U31 also monitors the Sense line, SL(x) that corresponds to the currently active Drive line, DR(x). If U31 detects a returned signal, it asserts the KEYOUT line. The program within U28 keeps track of which Drive lines produce a Sense signal within each cycle. If a keyboard character is detected, an interrupt is issued to the JU, causing the JU to read the character from a register within U28.

U32 is a battery-backed 2Kbyte nonvolatile RAM chip, with an integral real time clock. The RTC control and time registers overlay the top eight bytes of the memory. U33 is the system EPROM, containing the operating firmware for the board. The 8bit data from the EPROM is assembled into 32-bit instructions and fixed data for the CPU by the MPI ASIC.

Sheets PERIPHERAL 110

U3 is the 82C710 Universal Peripheral Controller, which features a 16450-compatible USART (Universal Serial Asynchronous Receiver/Transmitter), an IDE interface for connection to one or two hard disk drives, a µPD72065B-compatible Floppy Disk Controller, a mouse port and a 16-bit PC-AT compatible bidirectional parallel port. The 82C710 contains a large number of registers and many features are software-selectable. To change any of the configuration register values, a complicated sequence of write operations has to be undertaken before the changes can be made. This configuration sequence is intentionally kept complicated to minimize the chance of changes being made as a result of a programming bug.

The USART section of U3 is connected to U45 which converts TTL-level signals to and from RS232 levels for the serial interface.

144

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Sheet6 GRAPHICS

U46 is the VGA display controller for the monochrome flat panel display, with a supplementary CRT display capability. The two 256K x4 DRAMs, U16 and U17, form the video memory block, with U16 containing memory planes 0 and 1, Ul 7 planes 2 and 3. The 64K x4 DRAM, US, is the Frame Accelerator memory, used to buffer the top and bottom half of the display alternately. This procedure is used to reduce the display flicker without drastically increasing the current consumption of the display conbOller chip. Note that this device is not required in a color system.

U23 is a Western Digital WD90C61 frequency synthesizer chip. The internal voltage-controlled oscillators and phase-locked loop circuits derive the clock signals OSC and SQCLK from the 14.312MHz oscillator (XL4) signal. The frequency of OSC is conbOlled by the three CLKSEL lines. SQCLK is fixed at 37.585MHz by the settings of the MCLK pins.

The LT1017 (U34) is a dual comparator/op amp device and is used to pass the LCD contrast and drive signals to the LCD. The signals out of U34 can be turned off by the signal PPCTL, which is derived from the /DISPOFF signal using TR2 (also on Sheet 6). This circuitry provides a software-controlled mechanism for turning off the LCD. The signal BLOFF from TR 1 turns the LCD backlight off.

Sheet 7 MODEM AND ETHERNET

U15 is the Fujitsu 86960 NICE Ethernet Controller, a 16-bit Ethernet controller which uses a 64Kbyte block of buffer memory (U53, U56) for storing receive/transmit data. The CPU accesses the buffer memory via the Buffer Memory Port registers within the 86960. Reads from this register retrieve data from the receive buffer, writes are directed to the transmit buffer. Read and write pointers are maintained by the 86960 itself, simplifying the operation of loading and retrieving network packets. The buffer memory is addressed using the BA(14:0) bus, and data is transferred over the SD(15:0) bus.

U22 and U57, together with associated components, make up the Modem interface. U22, the Modem Advanced Controller (MAC), communicates with U57 over the 8bit AD bus and the /SIN, /SOUT lines (Serial In, Serial Out). The serial lines are for transmit and receive data. The parallel bus is a multiplexed address and data bus and is used for setting up, and passing commands to, U57. U22 communicates with the IU over the lower 8 bits of the PD bus, with 3 address bits selecting the register within the MAC to be accessed by the IU. U22 contains an area of ROM which is programmed to interact with U57 and provide a 2400bps full duplex intelligent modem. The two device chip-set performs all the modem functions as well as automatic control features compatible with the Hayes "AT" command set.

145

Sheets CONNECTORS

Sheet 8 shows all the connectors present on the S 1 Base card.

PHI is the 100-way miniature interboard connector that carries the signal between the base board and the CPU module.

SKI carries the signals between the base board and the internal floppy disk drive unit. SK2 connects to the LEDs.

SK3, 4 and 5 make connections with the SI-1/0 board, carrying signals for several of the external interfaces.

SK6 passes the control, timing and data sugnals to the LCD.

SK7, a 5-pin flexible circuit connector, is used to carry signals to the flat panel display backlighting system.

SK8 connects to the force sensitive resistors that make up the mouse key and the On/Off switch.

SK9, an 8-way connector marked 'KEYBD l' on the schematics, is used in conjunction with SKlO, an 11-way connector marked 'KEYBD 2' on the schematics, to make connection with the built-in keyboard. SK9 carries the Sense lines, SKlO the Drive lines.

PLl is used to make the connection to the internal hard disk unit or units.

{Note the presence of two Chip Select signals, /HDCSO and 1, to allow up to two IDE devices to be connected to the cable from PLl.)

PL2 is used to carry signals and power to and from the power supply unit, with TR3 being used to hold the supply ON when the Power On switch is activated.

Color Systems only - Sheet 9

On the color version of the SP ARCbook, the S 1-BASE-C schematics vary slightly from the monochrome version. The changes are confined to some minor changes on Sheets 6 and 8 and the addition ofa Sheet 9.

Sheet 8 has extra connectors to carry the signals to the color display.

146


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Sheet 9 shows the CL-GD6340 color LCD interface controller (U60) which works in conjunction with U46 on Sheet 6, plus the color LCD power supply generator circuitry (U63 and associated components).

147

SJ -110 SCHEMATIC DESCRIPTION

The S I-1/0 board is used to mount the connectors that interface to the external devices via the backpanel of the SPARCbook. Numerous filtering and screening components are present to reduce electromagnetic radiation, allowing the SPARCbook to meet FCC standards.

The circuitry in the lower half of the sheet is used to connect the SCI 1054 modem device (U57, Sheet 7 of the SI-Base schematics) to the telecommunications network. The signal OH is generated by the SCI 1075 Modem Advanced Controller or MAC (U22, Sheet 7 of the SI-Base schematics) and is the "off-hook" signal. /MRI is the Ring signal from the same device and when active indicates that the modem is receiving a ringing signal. RXT A is the analogue receive/transmit line which is referenced toMVREF.

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SJ-CPU SCHEMATIC DESCRIPTION

Sheet 1 CY7C601 INTEGER UNIT

Sheet I shows the CY7C601 Integer Unit (or IU, the Central Processor Unit, U2), the CY7C602 Floating Point Unit (U3), the CY7C604 Cache Controller and Memory Management Unit (Ul, the MCT), and two 16Kbyte Cache Storage Units (U4 and U5) - a specialized fonn of SRAM. All these devices are linked by the IU address and data buses, A(3 l :0) and 0(31 :0) respectively. Ul provides the interface between these buses and the 64-bit multiplexed Mbus, MAD(63:0). It also keeps track of the information stored within the cache memory and controls the cache memory (U4 and U5). For example, if the Integer Unit carries out a read operation from a main memory location marked as cacheable, Ul will cause the data to be written into the cache memory at the same time as it is read by U2. If U2 later attempts to carry out another operation to that same address, Ul will divert the cycle to the cache instead. If U2 addresses a location that is not held in cache, Ul will translate the processor bus cycle into an Mbus cycle. U 1 will also handle any logical to physical address translation that may be required.

The IU is the SP ARC processor itself. The two SIZE lines define the size of transfer currently being executed. 8, 16, 32 and 64-bit operations are identified, with 64-bit operations {Load/Store Double) being a special category of data transfer using two 32-bit bus cycles. The ASI lines are the "address space identifier" lines, used by multitasking operating systems. MHOLDA is an active LOW signal, used to freeze the clock to both the IU and the FPU in the event of a cache miss or an access to slow memory via the MCT. DOE is also an active LOW signal and is deasserted to tristate the bus drivers on the IU and FPU, allowing the MCT to control the address and data buses.

The optional FPU (U3) operates concurrently with the IU. The IU identifies floating point instructions by means of the FINS lines and allows the FPU, when fitted, to pick up instructions and data or to supply data. A floating point instructions is concurrently decoded by both the IU and FPU, but does not begin executing in the FPU until after the instruction is enabled by a signal from the IU. Several signal lines pass between the FPU and IU to provide the control and handshaking required for these operations.

Sheet2 100-WAY MINIATURE CONNECTOR

Sheet 2 shows the 100-way miniature connector that carries the signals between the CPU board and the base board.

149

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CHAPTER THIRTEEN LJ SYSTEM COMPONENT SPECIFICATIONS

u u LCD COWR DISPLAY

LJ Mechanical Characteristics

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Structure

Dot size

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Effective area

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Operating temperature

Storage temperature

Ambient temperature (Ta)

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224(w) x174(h) xl0.5 max

640 x R.G.B x 480 (h)

0.07 (w) x 0.25(h)

0.09 (w) x 0.27 (h)

178 (w) x 134 (h)

10 40

-10 50

Ta:S 40°C

Ta>40°C

151

mm

dot

mm

mm

mm

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85% Relative Hwnidity max

Below maximum absolute hwnidity

of 40"C 85% RH

Absolute Maximum Ratings

Power supply for logic 0

Power supply for LC

Driving 0

Input voltage

Electrical Characteristics

Ta= 25°C, V00 = 5.0V ±5%, Vfill.-V ss = +38V ±IV

~ Condition

Input high voltage v111 Input low voltage vn. Clock frequency fQ.2

Current conswnption 1no fQ.2 = 5.61MHz

~ UD,-UD, =low

LD,-LD, =low

152

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MONOCHROME DISPLAY

Mechanical Characteristics

Speclflcatton

Dimensions 255(w) x172(h) x9.0 max

Structure 640 x 480 (h)

Dot size 0.27 (w) x 0.27(h)

Dot pitch 0.30 (w) x 0.30 (h)

Temperature Range

Min

Operating temperature 10 40

Storage temperature -20 60

Ambient temperature (Ta) Ta~40'C

(no dew) Ta>40'C

154

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Below maximwn absolute humidity

of 40'C 85% RH

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Clock frequency fCFL (70) (85) KHz

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1m v e:.-V SS= -22.0V (11.0) mA

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Condition

Operating voltage Ta= 10·c

Ta=25°C

Ta=40°C

Optical Characteristics

Copd!tion

Viewing angle Ta=25°C

Contrast ratio Ta=25°C

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80MBYTE HARD DISK

Mechanical Dimensions

Height (max)

Width

Depth

Weight

Environmental limits

Ambient temperature

Ambient Relative Humidity

Specification

19.0mm

70.0mm

101.6mm

176g

Operating

-40'C to 70'C 5·c to 55·c

20'C/hr gradient lO'C/hr gradient

5 to 95% non-condensing 8 to 85% non~oondensing

157

Power Requirements (at nominal environmental condiaons)

Soec!Ocation

Voltage +5V±5%

Ripple and Noise 50mV

Current:

Sleep/Standby 0.04A

Parked 0.16A

Idle 0.34A

Active (R/W) 0.40A

Active (Seeking) 0.44A

Start up (Peak) 1.lOA

Timing Specifications

Maximum under nominal conditions

Single-Track Seek 5

Average Seek 19

Full Stroke Seek 30

Average Rotational Latency 8.3

Sequential Head Switch 4

Command Overhead 1

Power on to Drive Ready <4.0

Sleep/Standby to Drive Ready <2.5

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Power On to Drive Ready is the time elapsed between the supply voltage reaching the operating range and the drive being ready to accept all commands.

An ambient temperature of25'C, nominal supply voltages and no applied shock or vibration constitute nominal conditions.

Vibration and Shock

Nongperatlp& Ope ratio&

Vibration:

5 to 300Hz sine wave (peak to peak) 20 lG

1 oct/min sine sweep

Shock:

1/2 sine wave of lOms duration 1000 100

(10 hits max; >2 seconds between hits)

159

120MBYTE HARD DISK

Mechanical Dimensions

Specification

Height (max) 19.1 mm

Width(max) 70.1 mm

Depth(max) 101.9 mm

Weight (max) 185 g

Environmental limits

Operating

Ambient temperature -40°C to 70°C s·c to ss·c 30°C/hr gradient 30°C/hr gradient

Ambient Relative Humidity 8 to 90% non-condensing 8 to 80% non-condensing

Power Requirements (at nominal environmental conditions)

Voltage +5V±5%

Current:

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Active (R/W) 0.42A

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Start up (Peak) 1.00A

Timing Parameters

Maximum under nom!pal conditions

Single-Track Seek 8 ms

Average Seek 19 ms

Full Sttoke Seek 30 ms

Average Rotational Latency 8.7 ms

Vibration and Shock

Nogsuzeratlp& Qpemtio&

Vibration:

22 to 500Hz sine wave (peak to peak) 4G 0.5G

1 oct/min sine sweep

Shock:

in. sine wave of 1 Oms duration 1000 100

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