test technology trends in nanometer age - elsevier · ee141 4 vlsi test principles and...

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1VLSI Test Principles and Architectures Ch. 12 - Test Technology Trends In Nanometer Age - P. 1

Chapter 12Chapter 12

Test Technology Trends Test Technology Trends

in Nanometer Agein Nanometer Age

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What is this Chapter About?What is this Chapter About?

� Introduce the test technology roadmap

� Focus on a number of difficult challenges and test solutions:

� Delay testing, Physical failures and Soft errors, FPGA testing, MEMS testing, High-speed I/O testing, and RF testing

� Concluding remarks

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Section 12.1Section 12.1

Test Technology RoadmapTest Technology Roadmap

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Moore’s Law and Test ChallengesMoore’s Law and Test Challenges

� Moore’s law: the number of transistors integrated per square inch will double approximately every 18 months.

� To keep track of Moore’s law: die size , feature size , gate delay , interconnect delay

� To reduce interconnect delay, interconnects are made taller and taller, and this causes crosstalk noises between adjacent lines due to capacitive and inductive coupling (called signal integrity problem). This is very difficult to test.

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Moore’s Law and Test ChallengesMoore’s Law and Test Challenges

� Power integrity: clock frequency , supply voltage , power supply voltage can drop by L(di/dt). This is very difficult to test.

� Process variation: precise control of silicon process is becoming more and more difficult. For example, it is hard to control effective channel length of a transistor. This makes power and delay exhibit large variability. This is hard to detect.

� Low-power design faults: low-power design circuits might result in fault models that are difficult to test. For example,drowsy cache design by reducing power supply will cause drowsy faults.

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Fabrication Capital versus Test CapitalFabrication Capital versus Test Capital

1982 1985 1988 1991 1994 1997 2000 2003 2006 2009 2012

Based on 1997 SIA Roadmap Data

and 1999 ITRS Roadmap 1999 Roadmap

1

0.1

0.01

0.001

0.0001

0.00001

0.000001

0.0000001

Test capital/transistor (Moore’s law for test)

Fab capital/transistor (Moore’s law)

Cost (cents/transistor)

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International Technology Roadmap International Technology Roadmap

for Semiconductors (ITRS)for Semiconductors (ITRS)

� ITRS identifies technological challenges and needs facing the semiconductor industry over the next 15 years

� ITRS test and test equipment near-term challenges [SIA 2004]:

� High-speed device interfaces

� Highly integrated designs

� Reliability screens

� Manufacturing test costs

� Modeling and simulation

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� ITRS test and test equipment long-term challenges [SIA 2004]:

� DUT (device under test) and ATE (automatic test equipment) interfaces

� Test methodologies

� Defect analysis

� Failure analysis

� Disruptive device technologies

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� ITRS design test near-term challenges [SIA 2004]:

� Effective speed test with increasing core frequencies and widespread proliferation of multi-GHz serial I/O protocols

� Capacity gap between DFT/test generation/fault grading tools/design complexity

� Quality and yield impact due to test process diagnostic limitations

� Signal integrity testability and new fault models

� SOC and SIP test

� ITRS design test long-term challenges [SIA 2004]:

� Integrated self-testing for heterogeneous SOCs and SIPs

� Diagnosis, reliability screens and yield improvement

� Fault tolerance and on-line testing

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Sections 12.2Sections 12.2

Delay TestingDelay Testing

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Why Delay Testing?Why Delay Testing?

� Three sources of yield loss� Random defects – causing both logical and timing failures

� Systematic failures – causing both logical and timing failures

� Parametric variations – more likely causing timing failures

Yrandom

Ysystematic Yparamtric

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Fault Models: Fault Models:

PathPath--Delay & GateDelay & Gate--Delay FaultsDelay Faults

Path-delay fault:

� Propagation delay of path exceeds clock interval

� # of paths grows exponentially with number of gates

�Only consider long paths or a subset of paths

� Tests can detect small distributed failures

� Tests for longest paths also useful for speed-sorting

Gate-delay fault:

� A logic model for a defect that delays a rising or a falling transition

� Small distributed timing failures could be missed

� # of modeled faults is much smaller and manageable

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Transition Faults & Small GateTransition Faults & Small Gate--Delay FaultsDelay Faults

Transition fault (Gross gate-delay fault):

� The extra delay caused by the fault is assumed to be large enough to prevent the transition from reaching any PO at the time of observation

� Can be tested along any path from fault site to any PO

� The test is a vector pair that creates a transition at the fault site and the second vector is a test for the stuck-at fault at the fault site

Small gate-delay fault:

� Is tested along the longest propagation delay path

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Path Delay Faults Path Delay Faults -- Type of TestsType of TestsSingle-path-sensitization test:

• Guarantee that DUT will fail if and only if the path under test has excessive delay

• Fully characterize the timing of the path and is ideal for delay fault diagnosis

• All side inputs of gates along the given path must be stable

S1

S1

S1S1

S1S0

S0

Single-path-sensitization test conditions (for AND gate):

V1 V2

Target path

Off-path inputs V1 V2Off-path inputs

Target path

Must be stable “1” Must be stable “1”

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Could be either 1 or 0

V1 V2

Target path

Off-path inputs V1 V2 Off-path inputs

Target path


Path Delay Faults Path Delay Faults -- Type of Tests (ContType of Tests (Cont’’d)d)

Non-robust test :

• Test may be invalidated in presence of other path delay faults

S1 / S1 /

S1 / S1 /

S1 /

S0 /S0 /

Non-robust test conditions (for AND gate):

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Path Delay Faults Path Delay Faults -- Type of Tests (ContType of Tests (Cont’’d)d)

Robust test :

• Guarantees DUT will fail if the path under test has excessive delay

S0S0

S1 / S1 /

S1 /

S1 /

S1 /


V1 V2

Target path

Off-path inputs V1 V2Off-path inputs

Target path

Must be stable “1”

Robust test conditions (for AND gate):

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Application of Delay TestsApplication of Delay Tests

� Require application of a vector pair to the combinational logic portion and the circuit being clocked at speed

Combinational

Circuit

InputInput

clockclockoutputoutput

clockclock

input

latchesoutput

latches

�An arbitrary vector pair may not be applied to a sequential circuit under full-scan, partial-scan or non-scan methodology

Input

clock

Output

clock V1 applied V2 appliedOutput latched

Rated clock

period

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AtAt--Speed TestSpeed Test

� At-speed test means application of test vectors at the rated-clock speed.

� Methods of at-speed test:

� External, functional test

�Functional vectors applied by high-speed testers

� At-speed scan test

� Built-in self-test (BIST)

� Software-based self-testAt-speed test does not necessarily guarantee high-quality delay testing unless tests are designed to detect delay faults!

At-speed test does not necessarily guarantee high-quality delay testing unless tests are designed to detect delay faults!

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Applying AtApplying At--Speed Scan TestsSpeed Scan TestsV2 states generated, (A) by one-bit scan shift of V1, or

(B) by V1 applied in functional mode.Combinational

Logic

PrimaryInputs

PrimaryOutputs

FF

FF

ModeSwithch

Scan in

FF

Scan out

0

1

D-FF

Q

Q

MUX Scan Cell

DATA

SCAN_IN

MODE_SW

CLKScan chain length: L

MODE_SW

CLK

L+1 cycles 1 cycle

� � ��

Test Mode Functional mode

V1 applied

V2 applied

Response captured

MODE_SW

CLK

L cycles 2 cycles

� � ��

Test mode Functional mode

V1 applied

V2 applied

Response captured

Test application scheme (A): Test application scheme (B):

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Classifications of PathsClassifications of Paths

There are untestable paths even if full-scan is used to deliver tests!But do we really need to test them, if defects/variations on them do

NOT degrade circuit performance in functional mode?

There are untestable paths even if full-scan is used to deliver tests!But do we really need to test them, if defects/variations on them do

NOT degrade circuit performance in functional mode?

S-P-S testable

robust testable

non-robust testable

total path population

Based on test conditions:

functional testable

scan testable

total path population

Based on test application schemes:

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A CostA Cost--Effective Test StrategyEffective Test Strategy

� Use functional vectors

� Functional vectors can be applied at-speed and should catch some delay defects.

� Functional vectors should be evaluated for transition fault coverage.

� Derive and apply tests for undetected transition faults

� Derive and apply tests for long path-delay faults

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Delay Test/Speed Binning Delay Test/Speed Binning Challenges for Nanometer DevicesChallenges for Nanometer Devices

� Delay variability increases due to process, circuit,

temperature, power, and noise factors.

� No. of critical paths increases due to speed and

power saving techniques.

� Clock is increasingly susceptible to

faults/variations creating test inaccuracy and

escapes.

� Conventional transition and path delay models and

test methodologies are severely challenged!

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Variability of Path DelayVariability of Path Delay

� Noise-induced variability� Coupling cap -- pattern (excitation/propagation)/timing specific

� Power grid fluctuation -- pattern specific

� Circuit induced -- leakage, charge sharing (pattern specific)

� Process-induced variability� Spatial & temporal parametric variability: lot to lot, wafer to

wafer, die to die

� Limitations in lithography

� CMP induced variability

� Thermal-induced variability

� Power-induced variabilitySource: TM Mak, Intel

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More Critical Paths: Slowing Down More Critical Paths: Slowing Down

NonNon--Critical PathsCritical Paths

� Severe power constraint drove

power optimization everywhere.

� Slowed-down paths + sped-up

paths all crowded around

required period.

� More critical paths make it easier

for crosstalk-slowdown to

propagate.

�� Bus coupling effect over local wires Bus coupling effect over local wires

may be more likely & frequent.may be more likely & frequent.

# o

f p

ath

s

delay

required time

critical paths to be fixed

# o

f p

ath

s

delay

required time

non critical pathsto be slowed down

critical paths to be fixed

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Potential Solution: Go Statistical!Potential Solution: Go Statistical!

� Circuit delays can be modeled as correlated random variables to take various local & global factors into account:� Noise, process variations, pattern dependency, temp. variations, etc.

� Global effects can be modeled by correlations factors between delay random variables.

Mean/variance of pin-to-pin

delay or interconnect delay

Mean/variance of pin-to-pin

delay or interconnect delaya15/1

13/2 10/1

9/314/2

12/3

b

c

d

e

f

g

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Notion of Critical PathNotion of Critical Path

15/1

13/2 10/1

9/314/2

12/3

a

b

c

d

e

f

g

Most critical?

Most critical?

The most critical path can be different basedupon which delay model you have in mind!

The most critical path can be different basedupon which delay model you have in mind!

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Critical Path Varies from Chip Critical Path Varies from Chip

Instance to InstanceInstance to Instance

P1: a, e, gP2: b, e, gP3: c, f, gP4: d, f, g

13.7%23.6%19.1%43.6%

P4P3P2P1

Suppose 10000 chip instances are produced:

15/1

13/2 10/1

9/314/2

12/3

b

c

d

e

f

g

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Statistical Delay Test & Diagnosis FrameworkStatistical Delay Test & Diagnosis Framework

Need to consist of five major components:

� Statistical timing analysis

� Statistical critical path selection

� Selecting statistical long and true paths whose tests maximize the detection of DSM delay defects

� Path coverage metric

� Estimating the quality of a path set

� Generation of high quality tests for target paths

� Identifying tests that activate longest delay along the target path

�Path delay is highly pattern dependent

� Delay fault diagnosis based on statistical timing model

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Statistical Timing AnalyzerStatistical Timing Analyzer� Gate/Cell level

� Correlated delay vs.

� Cell delay library

� Interconnect model

� Monte Carlo Based

� Automatically determine convergence condition

� Static and dynamic

� Vector-less or vector-dependentArrival times

(Correlated) cell/interconnect delays

(V1V2….)

Estimate signal arrival time as random variable

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Statistical Critical PathsStatistical Critical Paths

� A critical path can be defined as the one with greater than P probability of exceeding a cut-off period T

� Adjusting P and T to limit the size of critical path set

Not criticalNot criticalCriticalCritical

II

OO

Arrival time of OArrival time of O

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Considering Path Correlation for Path Considering Path Correlation for Path

SelectionSelection

overlapAA

BB

CC

25/325/3

24/324/3

22/222/2

After selecting path A, should path B or C be selected?

Output arrival times:Output arrival times:

Return ofReturn of

testing path Atesting path A

clkclk

Change of distributions Change of distributions

after testing A:after testing A:

Return ofReturn of

testing path Btesting path B

Return ofReturn of

testing path Ctesting path C

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Considering Path Independence for Considering Path Independence for

Path SelectionPath Selection

� Defects on selected paths can be captured.

� However, a (small) defect falls beyond the selected paths may not be captured.

� Even with transition fault tests, path independence can still be an important factor for path selection.

Captured

Not capturedPaths selected for Paths selected for test generationtest generation

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Statistical Critical Path SelectionStatistical Critical Path Selection

� A new method achieving four objectives:� Select statistical long paths

� Consider path correlation

� Achieve path independence

� Eliminate statistical false paths

� Results indicating that selecting statistical long paths considering correlation and independence simultaneously:� Achieves higher test quality with the same number of selected

paths

� Selects fewer paths to achieve same level of test quality

*J.-J. Liou, et al., "Experience in Critical Path Selection For Deep Sub-Micron Delay Test and Timing Validation," ASPDAC 2003.

*J.-J. Liou, et al., "False-Path Aware Statistical Timing Analysis and Efficient Path Selection for Delay Testing & Timing Validation," DAC 2002.

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Section 12.3.1Section 12.3.1

Signal Integrity Signal Integrity

and and

Power Supply NoisePower Supply Noise

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Coping with Coping with

Signal Integrity Signal Integrity

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Signal IntegritySignal Integrity

� Motivation

� Modeling

� Test Methodologies

� Enhanced BIST

� Enhanced Scan

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MotivationMotivation

New

DFTs

Cost: Cents/Transistor

ITRS

� Test cost will be dominant in this decade [ITRS’01]

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Result of Technology ScalingResult of Technology Scaling

1.231.211.181.171.17Self L [nH]

0.970.930.880.840.80Mutual L [nH]

6.427.309.6510.0612.89Ground C [pF]

70.5464.1756.9349.7341.59Coupling C [pF]

0.100.130.180.250.35Technology [nm]

TechnologyFactors

Source:

[ITRS’01 Roadmap]

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Testing for Signal IntegrityTesting for Signal Integrity

Process Variations

“There are only two kinds of designers: the ones who

have signal integrity problems, and the ones who will.”[www.chipcenter.com]

Smaller DesignRules

Increase ofFrequency

Wave-OrientedPhenomena

Shrink ofTechnology

Physical Defects

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Fatal Problems on First SpinFatal Problems on First Spin

0

5

10

15

20

25

30

35

40

45

Functional

Error

Signal

Integrity

Reliability High

Power

Firmware

Error

[www.deepchip.com]

� Overall 61% of new ICs require at least one re-spin

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Core iCore j

Interconnect

� Signal integrity loss occurs due to process variations, manufacturing defects, the parasitic and coupling C/L. Integrity loss leads to failure.

� Signal integrity problem is both design & test issue. A systematic approach for testing is needed.

The Bottom LineThe Bottom Line

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Interconnect ModelInterconnect Model

� Signal integrity problems originate from interconnects.

� Distributed RLC model is too complicated.

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VHthr

Vdd

VHmin

VLmax

Vss

VLthr

Excessive delay

ringing

overshoot

T_SI_R T_SI_F

� Excessive delay degrades performance and causes functional error.

� Ringing causes functional error.

� Overshoot contributes to noise, delay, hot carrier, time-dependent dielectric breakdown, and electromigration.

Integrity Loss ModelIntegrity Loss Model

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Prior WorksPrior Works� Fault model and test pattern generation

� W. Chen, S. Gupta and M. Breuer [ITC98]� M. Cuviello, S. Dey, X. Bai and Y. Zhao [ICCAD99]� A.Attarha, M.Nourani [VTS02]

� Self-test methods for testing interconnects� X. Bai, S. Dey and J. Rajski [DAC00]� M. Nourani and A. Attarha [DAC01] [JETTA02]� I. Rayane, J. Medina and M. Nicolaidis [VTS99]

� Modified boundary scan� J. Shin, H. Kim and S. Kang [DATE99]� K. Lofstorm [ITC96]� C. Chiang and S. Gupta [VTS97]� S. Yang, C. Papachristou and M. Tabib-Azar [DAC01]� M. Tehranipoor, N. Ahmed, M. Nourani [TCAD04]

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Method 1: Enhanced BISTMethod 1: Enhanced BIST� The adverse effects of integrity loss will appear only at

the working frequency.

� The effects of integrity loss are usually transient and intermittent.

� At-speed testing requires high-performance ATEs.

� External test of signal integrity is limited due to speed, access and probing difficulties.

Test

Pattern

Generator

Interconnect Under Test

(IUT)Output

Response

Analyzer

Test Controller

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OnOn--Chip Noise DetectionChip Noise Detection� The internal Noise Detector (ND) and Skew Detector (SD)

cells sample signals and record skew and delay violations.

� Our BIST-based methodology can be integrated within conventional BIST environments with 20% to 50% more overhead.

T

P

G

R

Interconnect Under Test

(IUT)

ND Cell

SD Cell

M

I

S

R

BIST Controller

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T1 T2

T3 T4

T5

T6

T7

Core i Core j

x

y c

Test_mode

To read-out

circuit

signal

Signal + noise

IUT

Noise Detector (ND) CellNoise Detector (ND) Cell� The ND cell detects voltage violations, e.g. overshoot and ringing.

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Behavior of the ND CellBehavior of the ND Cell� The noise detector (ND) cell shows a hysteresis

property and can detect two threshold voltages.

Input:

Output:

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Skew Detector (SD) CellSkew Detector (SD) Cell

Interconnect signal

(Signal + Delay)

TCK

Inverter 1

Inverter 2

a

b b

PDN

c

To flip-flop

Sensor XNOR

Level restorer

TCK

bADR

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ViolationADR

Behavior of the SD CellBehavior of the SD Cell

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Readout ArchitectureReadout Architecture

ND Cell

Vb Vc

ND Cell

Vb Vc

SI

SO

SI

SO

SD Cell

Vb Vc

SD Cell

Vb Vc

ND Cell

Vb Vc

ND Cell

Vb Vc

SI

SO

SI

SO

SI

SO

SI

SO Test ControllerTest Controller

SD Cell

Vb Vc

SD Cell

Vb VcSI

SO

SI

SO

00

11

0

11

1

SD Cell

Vb Vc

SD Cell

Vb VcSI

SO

SI

SO

1

SI

SO

SI

SO

SI

SO

SI

SO

SI

SO

SI

SO Test ControllerTest Controller

00

11

0

11

SI

SO

SI

SO

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Method 2: Enhanced JTAGMethod 2: Enhanced JTAG� Boundary scan provides easy access to the

interconnects

� The boundary scan cells and TAP controller need modification to:

� generate and apply the test patterns (PGBSC)

� capture and read out the integrity violations (OBSC)

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Maximum Aggressor (MA) ModelMaximum Aggressor (MA) Model

Pg0 Pg1 Ng1 Ng0 Rs Fs

AI

AI

AI

AI

VI 01 1

0

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Pattern Analysis in MA ModelPattern Analysis in MA Model

00000

11011

00100

11111

Pg0

Fs

Pg1

Initial value 1

00000

11111

00100

11011

00000

Ng1

Rs

Ng0

Initial value 211111

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Pattern Generation BSC (PGBSC)Pattern Generation BSC (PGBSC)TDO/next cell

Input pin/Core output Output pin/

Core input

SI UpdateDR

TDI/previous cell

ClockDR

ShiftDR

0

10

1

1 0

0

1D1 Q1 D2 Q2

FF1 FF2 Q2

Q1

FF3

Q3

T

Mode

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Operational Modes of PGBSCOperational Modes of PGBSC

0XNormal

10Aggressor

11Victim

SIQ1PGBSC Mode

Victim mode Aggressor mode

UpdateDR

CLK-FF2

Q2

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Encoded Data for Victim LineEncoded Data for Victim Line

201000

300100

500001

400010

110000

Victim LineVictim-Select

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Observation BSC (OBSC)Observation BSC (OBSC)TDO/next cell

SI

ClockDRShiftDR

0

1

0

1D1 Q1

FF1

UpdateDR

D2 Q2

FF2 Q2

ND FF

SD FF

TDI/previous cell

1

1

0

0

Modesel

Output pin/Core input

Input pin/Core output

ND/SD

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Operational Modes of OBSCOperational Modes of OBSC

0XNormal

10SDFF

11NDFF

SIND/SDModes

1X0

111

001

selShiftDRSI

� Values of signal sel:

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Operation of OBSCOperation of OBSC

Capture-DR Shift-DR

TCK

ControllerState

ClockDR

ShiftDR

SI=‘1’

sel=SI+ShiftDR

Select

ND/SD

cell (form the

scan chain)

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Test ArchitectureTest Architecture

1

2

n

IUT

TDI

TCKTMS

TRST

TDO

Core i Core j

OBSCPGBSCBSC

m

1

k

2 2

1

Standard

IEEE1149.1

Interface

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New Test InstructionsNew Test Instructions� Two new instructions are added to the IEEE1149.1

instruction set

� G-SITEST Instruction

� Facilitates test pattern generation based on the MA fault model

� PGBSCs are enabled with signal SI=1

� ND/SD cells become active (CE=1) to capture the signal integrity information

� O-SITEST Instruction

� Is used to capture and scan out the ND/SD FFs data

� Is loaded after the G-SITEST instruction

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Concluding Remarks Concluding Remarks -- SISI� Signal integrity failures are intermittent; therefore, new

test pattern generation, detection and readout strategies are required.

� Enhanced BIST Methodology:

� Is capable of at-speed testing.

� Is relatively expensive unless limited to long buses.

� Provides data for test/reliability analysis and diagnosis.

� Enhanced JTAG Architecture:

� Requires noise/skew detector cells on interconnects.

� Needs modified boundary scan cells.

� Provides a cost effective solution to test interconnects for integrity loss.

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Coping with Coping with

Power Supply NoisePower Supply Noise

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Power Supply Noise (PSN)Power Supply Noise (PSN)

� Noise in high speed design� Sharp rise and fall times (small dt)� Changes in current drawn from Vdd (large di)

� VPSN = L · di(t)/dt + R · i(t)

� Large voltage fluctuation� Intermittent malfunctions� Functional failure� Reliability problem

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MotivationMotivation

� Power supply noise analysis captures noise more globally in high speed circuits.

� PSN analysis can be useful for � Pre synthesis noise/performance estimation� Sensitivity analysis� Power supply network design

� Accurate estimation of PSN in a core based SoC without exhaustive simulation.

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Prior WorkPrior Work

� Genetic algorithms

� Y. Jiang, K. Cheng and A. Krstic [CICC’97]

� G. Bai, S. Bobba and I. Haji [ICECS’01]

� S. Zhao, K. Roy and C. Koh [ICCD’00]

� Estimation based on modeling

� Y. Chang, S. Gupta and M. Breuer [VTS’97]

� L. Zheng, B. Li, and H. Tenhunen [ISCAS’00]

� M. Nourani, M. Tehranipoor, N. Ahmed [VTS’05]

� Application – power distribution and floor planning

� N. Pham, M. Cases, D. Araujo and E. Matoglu [VTS’04]

� S. Zhao, K. Roy and C. Koh [ASP-DAC’02]

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PowerPower Distribution Wire and Pin ModelDistribution Wire and Pin Model

� Vnoise(t) = (Vdd,pin - Vdd,block(t)) – (Vss,pin - Vss,block(t))

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PSN Analysis MetricsPSN Analysis Metrics� Level – A level of a node (distance from primary

input) implies how difficult or restrictive it is to switch that node.

� Fan-Out – Switching time (tP) is inversely proportional to fan-out. Switching low fan-out gates will reduce dt � increase di/dt.

� Fan-In – Large fan-in gates are resized (more wide) to allow proper pull-up and pull-down. Large width allows drawing more current.

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Effect of LevelEffect of Level

Lower level � More switching

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Effect of FanEffect of Fan--OutOut

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Effect of FanEffect of Fan--InIn

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Different MethodsDifferent Methods

LIOLOIOILOLIIOLILOOrder ofMetrics

M6M5M4M3M2M1Method

� Ordering of metrics gives priority to switching one gate over the other.

� Level is given the highest priority due to ease of control.

� M5 (LOI) and M6 (LIO) methods are used.

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Test Pattern GenerationTest Pattern Generation� Exhaustive

� 2n·(2n-1) ≈ 22n possible transitions

� Random

� Cannot guarantee peak power in short time.

� Instead of exhaustive or random search, heuristic-based approach should be used.

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Basic ApproachBasic Approach

� Use conventional s-a-f pattern generation method and tools to stimulate 0�1 or 1�0 transition.

� Determine test pattern pairs by estimating maximum PSN according to three PSN metrics.

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Concluding Remarks (PSN)Concluding Remarks (PSN)

� Power supply noise captures the effect of noise globally.

� One goal is often to generate a pattern pair to stimulate maximum PSN in non-embedded cores.

� Combining individual PSN curves strategically provides a way to estimate PSN of SoCwithout full simulation.

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Parametric Defects, Process Parametric Defects, Process

Variation, and YieldVariation, and Yield

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Defects and Physical DefectsDefects and Physical Defects

� Physical defects occur during manufacturing, and can cause static or timing physical failures

� Defects can be random or systematic, and can be functional or parametric

� Traditional work is more on functional random spots

� Other three types of defects need to be researched

� Defects can also be caused by process variations and random imperfections

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DefectDefect--Based TestBased Test

� Defect-based test can be done by enumerating likely defect sites from layout

� At-speed tests (path-delay tests and transition tests) must be used

RTL

Synthesis Modeling ATPG

Schematics

Gate-level Netlist

Defect-Based Fault Simulator

Fault List

Defect-Based ATPG

Structural Tests

Functional Tests

RC Extraction

Timing Analysis

Path Extractor

Critical Path

List

Logical Fault List

Structural Tests

Physical Faults

Layout

Defect-Based

Fault Enumeration

Fault Mapping

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Supplements of Conventional StuckSupplements of Conventional Stuck--at Testsat Tests

� Bridging tests: enumerate likely bridging fault sites (interconnects) by layout simulation

� N-defect stuck-at tests: detect every stuck-at fault N times by targeting different sensitive paths

� TARO (transition fault propagation to all reachable outputs): generate transition tests one for each reachable output, for each given transition fault.

� IDDQ tests: test by measuring current flow

� Functional Testing: must be added to supplement structural tests

� Key issue: how to generate these defect-based tests in a timely manner to meet test goals.

EE141


Sections 12.3.3 Sections 12.3.3 --12.3.412.3.4

Soft Errors and Fault ToleranceSoft Errors and Fault Tolerance

EE141


Cosmic Ray/Radiation Mechanics

+ -+

+

++

+++

++

+

--

--

---

--

- --

--+

+

+ + +-

-+ -

high energy neutrons

lighter Particles

some particles also may pass through all material without colliding with any atoms

EE141


cosmic rays protons, heavy ions

neutrons

Mechanism of Neutron SERMechanism of Neutron SER

EE141


Neutron EnvironmentNeutron Environment

60,000 feet20,000 m

1,000,000 feet330 km

Ground ~ 1/500 of Peak Flux

150,000 feet50,000 m

γ PrimaryCosmic Rays

η Neutrons

π,µ SecondaryCosmic Rays

Shuttle

Top ofAtmosphere

PeakNeutron

Flux

Aircraft

γ

η π,µ

N,O~ 35,000 feet

10,000 m

Normand et al.γ γ γ γ γ γγ γ γ γ γ γγ γ γ η η η η γ γ γ η η η ηγ γ γ γ γ γ η η η η η η η ηγ γ γ γ γ γγ γ γ γ γ γ η η η η η η η η γ γ γ γ η η η η η η η ηπ µ π υγ π γ η η η η γ µ γ η η η η

η η η η η η η ηγ π µ η η η η γ π µ η η η η η η η η η η η η

π µ η η η η π µ η η η ηπ µ γ π υ γ η η η η η η η η η ηπ µ π µ π µ γ γ η η

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Neutron Energy Spectrum for

Atmospheric Cosmic Rays

1.E-121.E-111.E-101.E-091.E-081.E-071.E-061.E-051.E-041.E-031.E-02

1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05

Neutron Energy (MeV)

Flu

x in

n/(

MeV

*cm

2*s

)

Flux n/(MeV*cm2*s)

n0-Si interaction can result in a short

range, intense burst of charge

varies with altitude and geography

electronsgammas

EE141


Mechanism of Alpha Particle SERMechanism of Alpha Particle SER

� Impurities disintegrate in alpha decay

� Observed alpha flux 0.01/h/cm2

Host material

(package, Si,

oxide, etc.)

Impurity in ppb

amounts

(238U, 232Th, etc.)

electron is stripped from atom

-

-

-

-

The neutral atom gains a + charge= an ion

+

+

Alpha Particle

EE141


� alpha decay from radioactive isotope Pb 210� travel short distance, a few

centimeters

� but they are located at the surface of the dies with C4 mounting

� Traditional solutions, e.g., epoxy die coat, are not effective

Sources of alphaSources of alpha

EE141


0

1

2

3

4

500 350 250 180 130 90

Technology node (nm)

Vc

c

0.001

0.01

0.1

1

Cn

od

e/Q

no

de

(n

orm

ali

ze

d)

desktop Vcc

mobile Vcc

Cnode

Qnode

Shrinking Process Decrease Charge per NodeShrinking Process Decrease Charge per Node

How low will it go?

Soft error is a function of stored charge

at sensitive nodes

Q=CV

i.e., Cnode and Vcc

EE141


RAM cell sensitive areaRAM cell sensitive area

Word line

Bit line

Vss

Bit Line

Vcc

Word line

SER sensitivejunctions

SER sensitiveduring read time

SER Critical area is drain/source junction rather than metal interconnect

Not all diffusion

area are sensitive

Different junction

have different

sensitivity

characteristics

1

µµµµm

EE141


Pentium Pentium

Pro

Pentium II Celeron -A Pentium III Pentium 4 Pentium4+ Core2Duo

%

0

5000

10000

15000

20000

25000

30000

Kbytes

Size of primary embedded cache (desktop)

Size of primary embedded cache (server)0.92-1.180.8

SER / bitVccCGATEADIFF

Tech.

Neutron Scaling Trends

1.08-1.450.70.750.540.7x λ

1111λ

Scaling Factor

α

ccgatediff )V(CAbit

SER −∝

This may lead to

false security

Itanium

Itanium2

Doubling of devices every generation will double soft error rate as well !!

Caches on CPU chip

EE141


Logic Circuit Logic Circuit

SubjectedSubjected to SEUto SEU

Clk

D Q

sensitive junctions

typical D-latch

Feedback loop exists

Disturbance change logic state permanently

� Logic is not immune to SER

� All feedback nodes are susceptible

� Typical hardening techniques will pose performance penalty

� Latch is susceptible when in the holding phase (50% of cycle)

� F/F Master/Slave

� Each is sensitive during its inactive phase

Focuses on meta-stable window results in low probability event

EE141


SER Cannot be Screened During SER Cannot be Screened During

ManufacturingManufacturing

� SER is recoverable error (if recomputed)

� Most memory elements (with feedback) are susceptible to SER (maybe to different degree)

� Errors in compute elements may become SDC (silent data corruption) or at best system crash (equally undesirable)

� Low end system may be OK with a reboot; not acceptable for a server

� SDC is the most vulnerable; won’t know unless computation is repeated at another time

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Redundancy Redundancy -- SpatialSpatial

� Spatial

� Duplication & compare

� Triplicate & vote

� Checkpointing and rollback is a common recovery technique

Identical Compute elements

checkerMiscompare !

Initiate rollback

Continue if correct;

Checkpointing regularly

EE141


Redundancy Redundancy -- TemporalTemporal

� Temporal

� Assume error is not persistent

� Recomputeeverything (twice)

� First result compare to second

� Checkpointing and rollback is common recovery technique

Compute

twice

checker

Compute element

Temporary storage

1st result

stored

temporarily

2nd result

forward for

comparison

Continue if correct;

Checkpointing regularly

Miscompare !

Initiate rollback

EE141


Redundancy Redundancy -- InformationInformation

� Error detection by extra information

� E.g. parity

� Parity is preserved through computation

� Error correction by extra information

� E.g. Hamming code

data

parity

operation

result

Parity

should

match

data

ECC

check

bits

ECC logic

data

Defective bit, correct by ECC

One bit in a row

defective

EE141


Hierarchy of ProtectionHierarchy of Protection

� Start with most unreliable (and highest quantity) elements� DRAM (highest number of bits)

– Parity, ECC

� Hard disk (mechanical)– RAID (Redundant Arrays of Identical Disks)

� IO Channels– CRC, ECC

� Cache – Parity, ECC

� Register files– Parity

� Execution units– DMR

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Defect and Error ToleranceDefect and Error Tolerance

EE141


Defect ToleranceDefect Tolerance� Assumptions:

� Defect rate is low

� Most defects cause single cell/row/column failures

� Repair defect elements using redundant resources

EE141


Redundancy Repair Redundancy Repair –– An ExampleAn Example

� Design in spare rows or columns or blocks

� Test to identify where bad cell or row/column is

� Algorithm to figure out how best to use spare elements to repair all defects

� Fuse change decoders to address spare elements instead of faulty elements

spares

EE141


Error ToleranceError Tolerance� Increasing new computing

applications are with multimedia data

� Compression is generally used for these data types:� E.g. MP3, JPEG, MPEG

� Lossy in nature

� Human senses are not keen enough to spot the difference

� Errors may be tolerated for these kinds of applications

� Accepting more faulty chips will increase effective yield while lowering cost

re: Error Tolerance, Mel Breuer, 2005

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FPGA TestingFPGA Testing

EE141


Field Programmable Gate ArraysField Programmable Gate Arrays� 2-dimensional array

� Programmable logic blocks (PLBs)

� Programmable routing network

� Programmable I/O cells

� Recent FPGAs incorporate specialized cores

� Memory cores: RAMs, FIFOs, etc.

� Digital signal processors (DSPs)

� Embedded processors

=PLB

=I/O buffers

=specialized core

=interconnect

EE141


Basic PLB ArchitectureBasic PLB Architecture

� Look-up Table (LUT)

� implements combinational logic truth table

� Memory elements

� Flip-flop/latch

� Some LUTs also implement small RAMs

� Carry and control logic

carry in

LUT/RAM Carry &

ControlLogic

Flip-flop/Latch

4

carry out

3

Control

Output

Q outputInput[1:4]

clock, enable, set/reset

EE141


Programmable Interconnect NetworkProgrammable Interconnect Network� Wire segments of varying length

� xN = N PLBs in length

N = 1, 2, 4, 6, 8 are most common

� xH = half the array in length

� xL = length of full array

� Programmable Interconnect Points (PIPs)

� Transmission gate connects 2 wire segments

– Controlled by configuration memory bit

� Four basic types of PIPs

configbit

Wire A

Wire B

EE141


Programmable Interconnect PointsProgrammable Interconnect Points� Break-point PIP

� Connect or isolate 2 wire segments

� Cross-point PIP

� 2 nets straight through

� 1 net turns corner and/or fans out

� Compound cross-point PIP

� Collection of 6 break-point PIPs– Can route 2 isolated signal nets

� Multiplexer PIP

� Directional and buffered

� Main routing resource in recent FPGAs

� Select 1-of-N inputs for output

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Ranges of Programmable ResourcesRanges of Programmable Resources

50,000,00032,000Configuration memory bits

1,20062Input/output cellsOther

5000DSP cores

50016Memory cores per FPGA

18,432128Bits per memory coreSpecialized

Cores

1,00080PIPs per PLB

40050Wire segments per PLBRouting

41LUTs and flip-flops per PLB

22,000100PLBs per FPGALogic

LargeFPGA

SmallFPGA

FPGA Resource

Large FPGAs easily exceed 500 million transistors

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FPGA Testing ProblemFPGA Testing Problem� Must test all modes of operation

� Many test configurations must be downloaded

� Long test time

� Large and complex devices

� Large FPGAs exceed 500 million transistors

� Many different types of functions to test

– PLBs

– Routing resources

– Specialized cores (RAMs, FIFOs, DSPs, etc.)

� Frequently changing architectures

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FPGA Testing ApproachesFPGA Testing Approaches� With respect to system application:

� Application independent testing– Test all resources in FPGA regardless of system

function to be implemented

� Application dependent testing– Test only those resources that will be used by a

given system function

� Testing techniques� External testing

– Test patterns applied and output responses monitored through I/O pins with external equipment

� Built-In Self-Test (BIST)

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BIST for BIST for FPGAsFPGAs

� Basic idea: reprogram FPGA to test itself� No area overhead or performance penalties for

system applications

� Applicable to all levels of testing� From device-level through system-level testing

� Cost:� Memory to store BIST configurations

– Goal: minimize number of configurations

� Download time to execute BIST configurations– Goal: minimize downloads and/or download time

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BIST for BIST for PLBsPLBs� Program PLBs as

� Test Pattern Generators (TPGs)– Multiple TPGs prevent faulty PLBs

under test from escaping detection when there is a fault in a TPG PLB

� Identically configured logic blocks under test (BUTs)

� Output Response Analyzers (ORAs)– Comparison-based

� Row or column orientation

� Two test sessions required� TPGs/ORAs and BUTs reverse rolls

=TPG =BUT =ORA

ORA

BUTi output

BUTj output

Pass/

Fail

Test session 1

Test session 2

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BIST for Routing ResourcesBIST for Routing Resources� Program groups of wire segments

and PIPs as wires under test

� Program some PLBs as TPGsand ORAs

� Similar to BIST for PLBs

� Two BIST approaches

� Comparison-based

– Similar to BIST for PLBs

� Parity-based

– TPG produces test patterns with parity

– ORA performs parity check

comparison-based BIST

Pass

Fail

ORA

wires under test

T

P

G

N

N

parity-based BIST

Pass

Fail

ORA

wires under testCnt0

CntN

Parity

T

P

G

......

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Concluding RemarksConcluding Remarks� FPGAs are more SoC-like with

specialized cores � RAMs, DSPs, etc. can be tested with

approach similar to BIST for PLBs

� SoCs are incorporating FPGA cores� These cores can be tested with BIST for

FPGA techniques

� Complex Programmable Logic Devices (CPLDs) are similar to FPGAs� Can be tested with approaches similar to

those used for FPGAs

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MEMS TestingMEMS Testing

EE141


Introduction to MEMSIntroduction to MEMS

� What is MEMS?� MEMS: Micro Electro Mechanical System

� Extremely small (in range of um) devices utilizing both electrical and mechanical properties.

MEMS gear chain and a mite for size comparision(Sandia MEMS)

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Video Clips from Sandia MEMSVideo Clips from Sandia MEMS

� A micro-resonator is used as an actuator to drive MEMS gears with mites crawling on top.

EE141


Commercially Available MEMS DevicesCommercially Available MEMS Devices

Digital Micromirror Device (DMD)(Texas Instruments, Inc.)

MEMS ink jet print head (nozzle)(HP, Inc.)

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Commercially Available MEMS DevicesCommercially Available MEMS Devices

ADXL50 accelerometer(Analog Devices, Inc.)

“LambdaRouter” optical switch(Lucent, Inc.)

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Why MEMS?Why MEMS?

� Why MEMS?� Lower cost due to batch fabrication� Light weight� Smaller size� Lower energy consumption� Higher performance

� MEMS applications� Automobile industry� Health care� Aerospace� Consumer Products� RF telecommunications� Other areas

EE141


World MEMS Market PredictionWorld MEMS Market Prediction

� Worldwide MEMS market is increasing rapidly.� Worldwide MEMS sales > $5 billion in 2004,

> $8 billion in 2007.

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Basic Concepts for Capacitive MEMS DevicesBasic Concepts for Capacitive MEMS Devices

� In static mode: where

� : dielectric constant of air

� S: overlap area between M and F1/F2

� d0: static capacitance gap between M and F1/ F2

0

021

d

SCC

ε==

0ε

EE141



� Assume Vertical stimulus force causes movable mass M to move upward with displacement x, where x << d0

)1()( 00

0

0

02

d

x

d

S

xd

SC −≈

+=

εε

)1()( 0

0

0

0

01

x

d

S

d

S

dxC +≈

−=

εε)1(

)( 00

0

0

02

d

x

d

S

xd

SC −≈

+=

εε

EE141



� To sense displacement x, modulation voltages Vmp and Vmnare applied to F1 and F2 respectively

)1()( 00

0

0

02

d

x

d

S

xd

SC −≈

+=

εε

)(01 tsqrVVV mpF ω==

)(02 tsqrVVV mnF ω−==

Where V0 is modulation voltage amplitude, w is freq of modulation, t is time for operation, sqr is square waveform

EE141



� According to charge conservation law,

)1()( 00

0

0

02

d

x

d

S

xd

SC −≈

+=

εε

)()( 2211 FMMF VVCVVC −=−

� Solve the equation:

� By sensing Vm, we find displacement x.

)()/( 00 tsqrVdxVM ω=

where VM is voltage sensed by movable plate M

EE141


MEMS BIST ResearchMEMS BIST Research

� Statement of problem: MEMS testing is becoming an urgent need.

� MEMS is finding applications in safety-critical areas, such as automobile, aerospace, medical instruments, etc.

� MEMS will be integrated into SoC, so it needs to be thoroughly tested to ensure reliability.

� The commercialization of MEMS technology needs a thorough and efficient testing solution in order to ensure reliability and reduce the test cost.

EE141


MEMS Testing: A Challenging TopicMEMS Testing: A Challenging Topic

� MEMS testing is chanllenging:� multi-field coupling

� diversity in device structure & working principle

� analog signals involved

� vulnerable to various defect souces (stiction, etch variances, particle contamination, etc.)

� Just like VLSI testing, built-in self-test (BIST) isbelieved to be a promising solution for MEMS testing.

� Research goals: develop a robust and efficient BIST solution for capacitive MEMS devices.

EE141


MEMS Sensitivity BIST SchemeMEMS Sensitivity BIST Scheme

� How to generate test stimulus for MEMS?

� Apply voltage Vd to F1 and nominal voltage Vnom to M

� Electrostatic force Fd will be experienced where

2

0

202

d

dSV

dF

ε=

EE141


MEMS Sensitivity BIST SchemeMEMS Sensitivity BIST Scheme

� The force will result in a displacement x.

� The sensitivity BIST scheme requires another similar structure to sense the displacement x.

� Sensed VM is compared with a known value for comparison.

EE141


Symmetry BIST for Capacitive MEMSSymmetry BIST for Capacitive MEMS

mnmp VtsqrVV −== )(0 ω

)()( 21 mnMMmp VVCVVC −=−

)/()( 2121 CCCCVV mpM +−=

EE141


Symmetry BIST for Capacitive MEMS (cont.)Symmetry BIST for Capacitive MEMS (cont.)

� For a fault-free Device:

� C1=C2, then VM=0

� If C1 ≠C2(faulty): VM≠0

� Fixed capacitance plates are partitioned into two equal portions(S1, S2 in top and S3, S4 in the bottom).

� During symmetric BIST, always check VM=0?

� Local Defect causing left-right asymmetry is detected.

* Partitioning by movable plate: see N. Deb and R. D. (Shawn) Blanton,

“Built-in Self Test of CMOS-MEMS Accelerometers,” ITC02, p.1075.

EE141


Capacitance Partition for DualCapacitance Partition for Dual--mode BISTmode BIST

� In Fig (b)

� S1, S2: top sensing plates,

� S3, S4: bottom sensing plates,

� D1,D2: driving plates

� In Fig (b) cont.

� M: movable plate

� C1, C2: top sensing cap.

� C3, C4: bottom sensing cap.

EE141


Capacitance Partition for DualCapacitance Partition for Dual--mode BISTmode BIST

� Fixed plate at each side of the movable plate isdivided into three portions: 1 for electrostatic driving, other 2 equal portions for capacitance sensing.

� The movable capacitance plate is not partitioned.

� Sensitivity and symmetry BIST can be implemented.

EE141


Voltage Biasing Scheme of DualVoltage Biasing Scheme of Dual--Mode BISTMode BIST

� D1 & D2 also participate the normal operation.

� Analog switches are used for mode-switching.

� Any defect causing sensitivity change or left-right asymmetry will be detected.

EE141


MEMS Comb AccelerometerMEMS Comb Accelerometer� Device prototype ADXL50 by Analog Devices Inc.� The serrated comb finger groups are extremely

vulnerable to defects, thus BISR is highly desirable.

Comb accelerometer without BISR

EE141


Working Principles of AccelerometerWorking Principles of Accelerometer

� Uses differential capacitance sensing technique

)()( 2211 FMmF VVCVVC −=−

� Vmp (Vmn): Complimentary

modulation voltages

)1()(

)(

)(

00

0

0

01

d

x

d

hLv

xd

hLvC

ff−

∆−≈

+

∆−=

εε

)1()(

)(

)(

00

0

0

02

d

x

d

hLv

xd

hLvC

ff−

∆−≈

+

∆−=

εε

)()/( 00 tsqrVdxV M ω−=

EE141


Working Principles of Accelerometer Working Principles of Accelerometer

(cont.)(cont.)

� VM is proportional to displacement x, which is in turn directly proportional to acceleration a.

� By sensing VM, the value of a can be measured.

EE141


BIST for Comb AccelerometerBIST for Comb Accelerometer

S3,S7S2,S4,S6,S8S2,S4,S6,S8

D2,D4,D6,D8

Vmn

S1,S5S1,S3,S5,S7S1,S3,S5,S7

D1,D3,D5,D7

Vmp

D2,D4,D6,D8

M1,M4,M5,M8

S2,S4,S6,S8

D2,D4,D6,D8

M1,M4,M5,M8-

Vnom

D1,D3,D5,D7D1,D3,D5,D7-Vd

Symmetry

BIST

SensitivityBIST

Normal

Operation

Voltage Biasing

� Device prototype:

ADXL50

� Since fixed plates are

separated comb

fingers, the partition

can be easily realized.

� M1-M8: movable plates

� D1-D8: fixed driving

plates

� S1-S8: fixed sensing

plates

Ms

D1

D2

M2D4

D3

M5

S1

S2

M2

S5

S6

M3

D5

D6

M4

S4

S3

M6

S8

S7

M7

D8

D7

M8

Driving Fingers

Sensing Fingers

Driving Fingers

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ANSYS Fault Simulation* of Comb AccelerometerANSYS Fault Simulation* of Comb AccelerometerStictionStiction defect simulation resultdefect simulation result

Finger height mismatch simulationFinger height mismatch simulation

1.656.439.2320%

1.239.246.8030%

2.182.232.7510%

2.5107.828.800%

0967.611.85Defect-free

Symmetry

BIST(mV)

SensitivityBIST(mV)

Frequency

(kHz)

Defect

location

128.2921.811.850.3

181.3904.411.850.4

83.9937.111.850.2

42.9951.811.850.1

0967.611.85Defect-free

Symmetry

BIST(mV)

SensitivityBIST(mV)

Frequency

(kHz)

Height mismatch

∆H (um)

* * For definitions of simulated defects, see paper at For definitions of simulated defects, see paper at ITC02, p.1075.ITC02, p.1075.

� Stiction (on right central movable finger): sensitivity BIST is more efficient.

� Finger height is matched (only in right portion): symmetry BIST is more efficient.

EE141


Conclusions of DualConclusions of Dual--Mode BISTMode BIST

� By partitioning fixed instead of movable capacitance plate, the BIST technique can be extended to bulk-micromachining and other MEMS technologies.

� Each sensitivity and symmetry BIST has its own fault coverage. A combination of both ensures better coverage.

� Sensitivity BIST is necessary during in-field usage even after calibration.� Some unstable defects may change status.

� New defects may be developed in in-field usage.

� Stiction is also possible during in-field usage.

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HighHigh--Speed I/O TestingSpeed I/O Testing

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I/O Test Requirements and ArchitecturesI/O Test Requirements and Architectures

� I/O test requirements are largely driven by the interoperability, system performance, and functional performance goals.

� I/O test requirements are closely related to the link architectures.

� For data rates < 1 Gbps, global common clock (CC) and source-synchronized (SS) are popular.

� Above 1 Gbps, serial architectures are dominant

� Timing, voltage, and bit error rate (BER) are common testing parameters.

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I/O Architecture (I) Common Clock (CC)I/O Architecture (I) Common Clock (CC)

� Synchronized global (common) clock

� Common clocks for Tx data driving and Rx data sampling

� Clock skew on board limits its use to < a few 100 Mbps data rate

� Needs to test:

�Data to clock delay at Tx

�Setup/hold time at Rx

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I/O Architecture (I) Common Clock (CC)I/O Architecture (I) Common Clock (CC)

� Synchronized global (common) clock

� Common clocks for Tx data driving and Rx data sampling

� Clock skew on board limits its use to < a few 100 Mbps data rate

� Needs to test:

� Data to clock delay at Tx

� Setup/hold time at Rx

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I/O Architecture (II) I/O Architecture (II) Source Synchronous (SS)Source Synchronous (SS)

� Tx sends data along with strobe (another clock)

� Rx uses sent strobe to sample the data

� No clock or strobe skew issue

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I/O Architecture (II) I/O Architecture (II) Source Synchronous (ContSource Synchronous (Cont’’d)d)

� Some designs use strobe/strobe# to improve timing accuracy.� Needs to test

� Data valid before and after strobe at Tx end� Setup and hold times at Rx end

Data

Strobe

Strobe#

All drivenby

same busclock

& matchedsignalpaths

Tvb Tva TvaTvb

Tsetup Thold

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I/O Architecture (II) I/O Architecture (II) Source Synchronous (ContSource Synchronous (Cont’’d)d)

� Limited by data to data skew due to uneven channels � Board layout� E-M issues: e.g.,

coupling, noises� Variation in drive

among channels

� Achieve up to ~1000 Mbps data rates for wide bus� Can improve data

rate with splitting into many narrower bus

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AC IO loopback selfAC IO loopback self--test test

driver

latch

Dx

Strobe

Bus Clock

board trace delay

wire delay

wire delay

board trace delay

system clock

clock domain 1 clock domain 2data

strobes

receiver

latch

Similar circuit as the receiving end!Testing hardware already exists!

-- test for both drive/receive-- low overhead

Loop time = Tco (or Tvb) + Tsetup OR Tva+Thold

EE141


Strobedelay

stress to fail by

pushing

strobes to the data

edge

(driver or receiver)

buffer group

should have tight

distribution

bus group

faulty buffer

good buffers distribution

wider distribution => local

defective buffers

DefectDefect--based based

IO testIO test

� A wider spread of data valid time indicate faults

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I/O Architecture (III) I/O Architecture (III) Serialier/Deserializer (SERDES)Serialier/Deserializer (SERDES)

� Bit clock is embedded in the serial data and gets recovered at Rx via clock recovery circuit.

� Link layer is composed of encoder and decoder.

� Physical layer (PHY) is composed of Tx, channel, and Rx.

parallel

to serial

encoder

clock

multiplier

system clock bit rate clock

parallel data

Tx serial dataincoming signals

(with embedded clock)

Clock

Recovery

recovered clock

recovered data

serial to

parallel

decoder

Rx

Channel

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I/O Architecture (III) A I/O Architecture (III) A SERDES PHY ImplementationSERDES PHY Implementation

� Bit clock is recovered via a phase interpolator (PI) clock recovery.

� PI clock recovery tracks low frequency jitter from reference clock, Tx, and channel.

� “Differential” PLLs reduce the jitter from reference clock.

� Used widely in PCI Express (2.5 Gen I, 5.0 Gbps Gen II) and FB DIMM (3.2, 4.0, and 4.8 Gbps Gen I).

� Jitter is the major limiting factor/performance metric.

C

- Channel

Rx Ref Clock

(100 MHz) Tx

PLL

25X

PLL

25X

D Q

D

C PI

+

Data

out

Rx eye

Closure

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Jitter Components and TerminologyJitter Components and Terminology

Multi-Gaussian

(MGJ)

Gaussian(GJ)

BUJPeriodic Jitter (PJ)

Inter-symbolInterference

(ISI)

Duty CycleDistortion

(DCD)

Data DependentJitter (DDJ)

Random Jitter (RJ)DeterministicJitter (DJ)

Jitter

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EyeEye--Diagram, Jitter, and Noise TestingDiagram, Jitter, and Noise Testing

Noise PDFs

Jitter PDFs

� For output testing, jitter and noise probability density functions (PDFs), and eye-opening should be upper bounded.

� For input tolerance testing, jitter and noise PDFs, and eye-opening should be lower bounded.

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SummarySummary� Link architecture determines the relevant test

parameters and methods.

� For synchronized CC and SS architectures, critical test parameters include: � Data valid to clock/strobe

� Setup/hold time

� For a SERDES architecture, critical test parameters include:� Jitter, includes deterministic jitter (DJ), random jitter

(RJ), and total jitter (TJ) or timing eye-opening

� Noise, and voltage eye-opening

� Bit error rate (BER)

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Chapter 12.7Chapter 12.7

RF Testing

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Outline of the SectionOutline of the Section

� Introduce the basic concepts related to RF

� Discuss the various challenges associated with RF test

� Describe different core RF building blocks

� Elaborate various test specifications for RF devices

� System-level testing and associated specifications

� Conclude with present and future trends

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Introduction to RFIntroduction to RF

� RF stands for ‘Radio Frequency’

� Usually very high frequencies where signals can be transmitted wirelessly

� Range of frequencies � 300MHz ~ 3GHz

� RF is used synonymously with ‘wireless’

� Significant growth during the last decade in the consumer segment

� Increased consumer applications

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Applications of RFApplications of RF

� Earlier, consumer applications of wireless technology were limited

� Military, space communications, air traffic control

� Currently, consumer applications are on the rise

� Cell phone, laptop, PDA, satellite radio

� Radiofrequency identification (RFID)

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Challenges with RF testingChallenges with RF testing

� Tests are performed in two steps� Characterization test

� Production test

� Various challenges make production test hard and expensive

� RF devices need extra attention during testing (challenge #1)

� Impedance matching @ input and output ports to ensure optimal power transfer

� Shielding from external wireless signals during testing

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Characterization testCharacterization test

� Characterization validates the first set of silicon

� Uses highly accurate instruments to

� Verify the functionality of the design

� Ascertain that the specifications are met

� Ensure high repeatability of the measurement system

� Production test needs to perform all of the above with� Cheaper instrumentation � a least-cost commercial tester

(challenge #2)

� In much smaller duration of the time used for characterization (challenge #3)

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Repeatability and accuracy issuesRepeatability and accuracy issues

� Test procedure should classify:� ‘Good’ devices as ‘good’ and

� ‘Bad’ devices as ‘bad’

� This is constrained by measurement noise� Reduces the accuracy of measurement during production

testing (challenge #4)

� Introduces large variability in the same measurement repeated many times (challenge #5)

� These can be mitigated by using � Accurate test application procedure

� High resolution measurements

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Summary of challengesSummary of challenges

� Challenge #1 is very specific to RF devices � needs careful measurement setup

� Challenge #2 and 3 are also specific to RF

� RF testers are very expensive (> $1M) compared to the analog and digital counterparts

� RF tests are usually longer compared to analog tests

� Challenge #4 and 5 are general for all electronic devices

� However, these are more prominent in RF due to the large amount of noise involved

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Typical RF systemTypical RF system

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RF specificationsRF specifications

� Linearity specifications

� Gain, conversion gain, output power

� Non-linearity specifications

� Third-order intercept (TOI), adjacent channel power ratio (ACPR)

� Noise specifications

� Noise figure (NF), signal-to-noise ratio (SNR), sensitivity, dynamic range

� System specifications

� Error-vector magnitude (EVM), bit error rate (BER)

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A note on decibelA note on decibel

� Decibel is a very commonly used unit in wireless domain

� Notation for decibel � dB

� Any number N can be converted to decibel by

NdB = 20 log10(N)

� A similar unit is mili-decibel (notation � dBm)

� Used to denote power with reference to 1 mW

� P watts of power is converted to dBm by

PdBm = 10 log10(P/1 mW)

� Thus 1W = 1000mW = 30 dBm; 10µW = 0.01mW = -20 dBm

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Gain Gain

� Measures the small-signal gain of the device/system

� Input is a single-tone stimulus within the operating frequency

� Amplitude is within linear range of operation

� Gain = (Output amplitude / Input amplitude), usually expressed in dB

A1

A2

Gain = A2/A1

= 20 log10(A2/A1), in dB

f1f1

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Conversion Gain Conversion Gain � Measures the small-signal gain of mixers

� Mixers translate the input frequency at a different output frequency

� Input is a single-tone stimulus within the input operating frequency, amplitude within linear range of operation

� Gain = (Output amplitude @ f2 / Input amplitude @f1), usually expressed in dB

A1

A2

Gain = A2/A1

= 20 log10(A2/A1), in dB

f1f2

Different frequencies

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TOITOI� Measure of nonlinearity for a device/system

� Two-tone input, within operating range

� Frequencies are closely spaced, difference is usually <1% of the device bandwidth

� Amplitude is larger than linear range of operation

� TOI = Pout + |(Pout – PIMD)/2|

DUT

f1 f2 f1 f2

2f1 - f2 2f2 - f1

PIMD

Fundamental tones

Intermodulation tonesPout

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A note on TOIA note on TOI

� Usually, RF devices exhibit third-order nonlinearity

y(t) = A0 + A1x(t) + A3x(t)3

� TOI is denoted in dBm

� It indicates the output power level where the fundamental tones and intermodulation tones attain same power

Third-order nonlinear term

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Basics of SNRBasics of SNR

� SNR is an important factor for any signal

� SNR for a known signal can be easily computed

� SNR denotes the level of purity

� For this sinusoid, SNR = 50 dB

(-23) – (-73) = 50 dB

� This notion can be extended to any known signal

-23 dBm

-73 dBm

Am

pli

tud

e

Frequency

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Noise figureNoise figure

� Noise figure measures the degradation of SNR of a signal when it passes through the DUT

� Noise figure = SNRin/SNRout

� This indicates the amount of noise added by the DUT

� NF is usually measured in dB (it’s a ratio !!)

� NF is measured using NF meter

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SystemSystem--level test : ACPRlevel test : ACPR

� ACPR test provides an idea of the overall nonlinearity of a system

� Why is ACPR important ?

� In communication systems, information is transmitted in channels (a fixed span of frequencies)

� Many devices communicate simultaneously in different channels

� If power leaks from one channel to other, both channels may result in erroneous transmission

Power leakage to adjacent

channels due to nonlinearity

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ACPR Test ACPR Test

� Pseudo-random bitstream is transmitted from the DSP to test for ACPR� This ensures all frequencies within the channel are equally

likely

� ACPR is the ratio of total power within the desired channel and the adjacent channel� Usually denoted in dB

Test setup

for ACPR

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EVM testEVM test

� RF systems employ modulation during transmission� Helps in protecting information from transmission channel

noise

� Inaccuracies in channel can cause

� Amplitude error

� Phase error

� AM-PM or PM-AM modulation

� EVM is an aggregate measure of all the above effects

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EVM testEVM test

� As done in ACPR, PR sequences are transmitted and received back during EVM test

� Use the demodulated data symbols to compute EVM

� EVM is the RMS of the received symbols compared to the actual symbols

� Need to use a large number of symbols to obtain a statistically correct value

� The amplitudes are normalized for systems employing phase-amplitude based modulation (e.g. 16-QAM, 64-QAM)

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EVM measurementEVM measurement

� The symbols for phase modulated systems should lie on a circle

� Deviations from the circle indicate presence of magnitude error + noise of the system

� Rotation of the symbols indicate phase error

� Non-uniform rotation indicates improper group delay present in the system (usually from passives)

Actual

symbol

received

Ideal

symbol

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EVM (contd.)EVM (contd.)

� EVM is calculated using the following formula

� EVM is a very good indicator of the overall system health

� Typically, EVM is within 3-15 %

� This figure shows EVM for a QPSK system

−= ∑∑

==

N

i

iideal

N

i

imeasurediidealRMS VN

VVN

EVM1

2

,

1

2

,,

11

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Concluding remarksConcluding remarks

� RF test cost is on the rise� It is estimated that test cost can be up to 40%

unless new techniques are developed

� RF test is constantly gaining attention from industry and academia

� RF testers are extremely expensive with limited functionalities compared to analog or digital testers

� In this light, innovative solutions are needed to overcome RF test challenges

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Future trendsFuture trends

� Defect-based test of RF devices can provide a quick estimate in a production test environment� However, it does not provide any info about specifications

� Use of low-cost instrumentations/ATE to perform complex tests� Example, using a multi-tone signal to measure EVM (no

transmitter needed)

� Use alternate measurements/BIST to facilitate test procedure� Can significantly reduce cost of testing + time required to

test

� Minimizes the requirements of the tester

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Concluding RemarksConcluding Remarks

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ConclusionsConclusions

� ITRS challenges for test, test equipment, and design test have been reviewed.

� Promising techniques for delay testing; coping with physical failures, soft errors, and reliability issues; FPGA testing; MEMS testing; high-speed I/O testing; and RF testing have been briefly reviewed.

� BIST/BISR must be pushed to deal with most circuits from digital circuits to analog and mixed-signal circuits.

� Other important test techniques, such as software-based self-test, design for manufacturability (DFM), design for yield enhancement (DFY), and design for debug and diagnosis (DFD) must be researched.

test technology trends in nanometer age - elsevier · ee141 4 vlsi test principles and...

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