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Applications Note
Transceiver Test Program
DevelopmentVersion 1.6
16 December 2008
PCI Configuration Read
1. All PCI signals are in their unasserted state (3.3V level) except IDSEL, which is 0. 2. The host (tester) simultaneously changes CBE[3:0] to 1010, drives AD[31:0] to all 0s, drives FRAME to 0, and drives IDSEL to 1.3. The host waits for the next rising edge of the PCI clock.4. After the rising edge, the host then changes IRDY to 0, FRAME to 1, CBE to 0000, stops driving AD[31:0], and drives IDSEL to 0.5. The ST part should now drive DEVSEL low.6. Within a few clock cycles the ST part should drive TRDY low, and drive AD[31:0] to 0x0981104A
Attached is a logic analyzer capture from an actual ST10/100 part. This assumes that the clock is running, reset is unasserted, and the device is out of reset.
Table X shows the necessary state of the CBE[3:0]:
Read Write CRn 1010 1011 CSRn 0110 0111
PCI Configuration Write to CR5 w/ Base Address as it is the bottom line to accessing CSR's:
Figure 1: CSR0 Write
Figure 2. DUT Reading the Transmit Descriptor
Here is a capture of the ST part reading a transmit descriptor. The ST parts initiates a cycle to host memory. The address is set in CSR4 and in this case is 0x0198F040. The ST part does a burst read which means it reads more than one dword. This is indicated by the four consecutive DATA cycles in that attached capture. A burst is indicated by the master holding FRAME# and IRDY# low after the initial address phase. The attached capture shows all four dwords in the transmit descriptor being read.
Table 1. System Level DUT Logic Analyzer Capture
Sample# Comment CYCLE Add[32] Data[32] AD[31-0] C/BE[3-0] FRAME# IRDY# DEVSEL# TRDY# STOP# Time_Rel-3 IDLE 0183C754 0110 1 1 1 1 1 0. ns-2 IDLE 0183C754 0110 1 1 1 1 1 30. ns-1 write 0x00000001 to CSR0 MEM WR FF1FFC00 FF1FFC00 0111 0 1 1 1 1 3.57797 s0 DATA 00000001 00000001 0000 1 0 0 0 1 60. ns1 IDLE 00000001 0000 1 1 1 1 1 30. ns2 write 0x8000 to XR0 MEM WR FF1FFCB4 FF1FFCB4 0111 0 1 1 1 1 24.45 us3 DATA ----8000 819F8000 1100 1 0 0 0 1 60. ns4 IDLE 819F8000 1100 1 1 1 1 1 30. ns5 write rcv desc address to CSR3 MEM WR FF1FFC18 FF1FFC18 0111 0 1 1 1 1 21.78 us6 DATA 0162A8E8 0162A8E8 0000 1 0 0 0 1 60. ns7 IDLE 0162A8E8 0000 1 1 1 1 1 30. ns8 write xmt desc address to CSR4 MEM WR FF1FFC20 FF1FFC20 0111 0 1 1 1 1 20.82 us9 DATA 016931A8 016931A8 0000 1 0 0 0 1 60. ns10 IDLE 016931A8 0000 1 1 1 1 1 30. ns11 write 0x3000 to XR0 MEM WR FF1FFCB4 FF1FFCB4 0111 0 1 1 1 1 20.16 us12 DATA ----3000 819F3000 1100 1 0 0 0 1 60. ns13 IDLE 819F3000 1100 1 1 1 1 1 30. ns14 read XR1, verify bit 2 is set MEM RD FF1FFCB8 FF1FFCB8 0110 0 1 1 1 1 72.54 us15 DATA ----7809 00007809 1100 1 0 0 0 1 60. ns16 IDLE 00007809 1100 1 1 1 1 1 30. ns85 write 0x0020244A to CSR6 MEM WR FF1FFC30 FF1FFC30 0111 0 1 1 1 1 116.885 ms86 DATA 0020244A 0020244A 0000 1 0 0 0 1 60. ns87 IDLE 0020244A 0000 1 1 1 1 1 30. ns88 ST reads xmit descriptor MEM RD 016931A8 016931A8 0110 0 1 1 1 1 210. ns89 DATA 80000000 80000000 0000 0 0 0 0 1 870. ns90 DATA 62000040 62000040 0000 0 0 0 0 1 30. ns91 DATA 017B99A8 017B99A8 0000 0 0 0 0 1 30. ns92 DATA 00000000 00000000 0000 1 0 0 0 1 30. ns93 IDLE 00000000 0000 1 1 1 1 1 30. ns98 ST reads rcv descriptor MEM RD 0162A8E8 0162A8E8 0110 0 1 1 1 1 210. ns99 DATA 80000000 80000000 0000 0 0 0 0 1 60. ns100 DATA 02000080 02000080 0000 0 0 0 0 1 30. ns101 DATA 01694380 01694380 0000 0 0 0 0 1 30. ns102 DATA 00000000 00000000 0000 1 0 0 0 1 30. ns103 IDLE 00000000 0000 1 1 1 1 1 30. ns104 ST reads xmt buffer MEM RD 017B99A8 017B99A8 0110 0 1 1 1 1 210. ns107 DATA 00000000 00000000 0000 0 0 0 0 1 420. ns108 DATA 55555555 55555555 0000 0 0 0 0 1 30. ns109 DATA AAAAAAAA AAAAAAAA 0000 0 0 0 0 1 30. ns110 DATA FFFFFFFF FFFFFFFF 0000 0 0 0 0 1 30. ns111 DATA 0F0F0F0F 0F0F0F0F 0000 0 0 0 0 1 30. ns112 DIS+DATA 5A5A5A5A 5A5A5A5A 0000 0 0 0 0 0 30. ns113 IDLE 00000000 0000 1 1 1 1 1 60. ns114 MEM RD 017B99C0 017B99C0 0110 0 1 1 1 1 90. ns115 DATA 00FF00FF 00FF00FF 0000 0 0 0 0 1 600. ns116 DATA AA55AA55 AA55AA55 0000 0 0 0 0 1 30. ns117 DATA 00000000 00000000 0000 0 0 0 0 1 30. ns118 DATA 55555555 55555555 0000 0 0 0 0 1 30. ns119 DATA AAAAAAAA AAAAAAAA 0000 0 0 0 0 1 30. ns120 DATA FFFFFFFF FFFFFFFF 0000 0 0 0 0 1 30. ns121 DATA 0F0F0F0F 0F0F0F0F 0000 0 0 0 0 1 30. ns122 DATA 5A5A5A5A 5A5A5A5A 0000 0 0 0 0 1 30. ns123 DATA 00FF00FF 00FF00FF 0000 0 0 0 0 1 30. ns124 DATA AA55AA55 AA55AA55 0000 1 0 0 0 1 30. ns125 IDLE AA55AA55 0000 1 1 1 1 1 30. ns128 ST reads xmit desc MEM RD 016931A8 016931A8 0110 0 1 1 1 1 90. ns129 DATA 80000000 80000000 0000 0 0 0 0 1 540. ns130 DATA 62000040 62000040 0000 0 0 0 0 1 30. ns131 DATA 017B99A8 017B99A8 0000 0 0 0 0 1 30. ns132 DATA 00000000 00000000 0000 1 0 0 0 1 30. ns133 IDLE 00000000 0000 1 1 1 1 1 30. ns134 ST reads xmit buffer MEM RD 017B99A8 017B99A8 0110 0 1 1 1 1 120. ns141 DATA 00000000 00000000 0000 0 0 0 0 1 60. ns142 DATA 55555555 55555555 0000 0 0 0 0 1 30. ns143 DATA AAAAAAAA AAAAAAAA 0000 0 0 0 0 1 30. ns144 DATA FFFFFFFF FFFFFFFF 0000 0 0 0 0 1 30. ns145 DATA 0F0F0F0F 0F0F0F0F 0000 0 0 0 0 1 30. ns146 DIS+DATA 5A5A5A5A 5A5A5A5A 0000 0 0 0 0 0 30. ns147 IDLE 00000000 0000 1 1 1 1 1 60. ns148 MEM RD 017B99C0 017B99C0 0110 0 1 1 1 1 210. ns149 DATA 00FF00FF 00FF00FF 0000 0 0 0 0 1 510. ns150 DATA AA55AA55 AA55AA55 0000 0 0 0 0 1 30. ns
Register Level Test Plan:
This assumes writes to configuration registers (CRn) have been completed.
Write 0x00000001 to CSR0 (offset PBAR1 + 0x00) <----------p 17/66 via the PCI Access Register, Reset all internal HW excluding the transceivers and config registers
Write 0x8000 to XR0 (offset PBAR1 + 0xB4) --------p 31/66 via the Transceiver Control Register, Reset the transceiver
Write 0xF0000000 to CSR3 (PBAR1 + 0x18) --------p 17/66 Rec’v Descriptor Base Address
Write 0xFF000000 to CSR4 (PBAR1 + 0x20) --------p 17/66 Transmit Descriptor Base Address
Write 0x3000 to XR0 (PBAR1 + 0xB4) <---------------- p 31/66 Autonegotiation enabled and 100Mbs selected
Wait 6 seconds --------This is for the PHY to autonegotiate a link to itself.
Write 0x0100 to XR0 (PBAR1 + 0xB4) <---------------- p 31/66 Disable Autonegotiation by driving Bit [12]=0 so that Full Duplex can be selected by driving Bit[8]=1
//Write 0x0020204A to CSR6 (PBAR1 + 0x30) <---------------Currently writing 0x002820C2 which means we're disabling SQE, enabling multicast, and not passing bad packet. Change it to pass bad packet. Write 0x000820CA/0x000824CA to CSR6 (PBAR1 + 0x30) -------- p19/66 in the Network Access Register set the Stop Transfer Bit [13]= 1 to start
TRANSMIT DESCRIPTOR READ- the ST will now read the following 4 DWORDS from 0xFF000000. The tester must respond with this data:
0x80000000 <-----------------------TX DES0
0x62000040 <-----------------------TX DES1 first packet and end of ring. Buffer 2 byte count= 2**6= 64 bytes- 4 bytes per D-Word or 16 D-Word burst
0x20000000 ------------ TX Buffer Start Address
0x00000000 <----------------------TX DES3 s/b don't care, but zero it out.
RECEIVE DESCRIPTOR READThe ST will now read the following 4 DWORDs from 0xF0000000. The tester must respond with this data:
0x80000000 <-----------------RXDES0 set Own Bit [31]
0x02000080 <------------------
0x10000000 <----------RX Buffer Start Address
0x00000000 <----------------------RX DES3 s/b don't care, but zero it out.
TX BUFFER READThe ST will now read the following 16 words from the tester
0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55
0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55
2ND TRANSMIT DESCRIPTOR READThe ST will now read the following 4 DWORDS from 0xFF000000. The tester must respond with this data:
0x80000000
0x62000040
0x20000000
0x00000000
RX BUFFER WRITEThe ST will now write the following 18 words to the tester: <--------------------------- It should be able to burst as long as REQ and GNT are asserted.
0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55
0x00000000
0x55555555
0xAAAAAAAA
0xFFFFFFFF
0x0F0F0F0F
0x5A5A5A5A
0x00FF00FF
0xAA55AA55
0x1B43BCF0
0x00440028
Table 2: Test Vector Micro-Instructions, UUT Syncronization. Here is the test vector code to do a TX Descriptor Read
1 Wait for STE to issue a PCI request as the Initiator (STE asserts REQn Output Low on vector label Wait_TX_Desc_REQ:).2 The tester which is now the Target, then gives the STE its GNTn.3 Wait up to 16 PCI Clocks on vector labled Wait_Memory_Access_1 to Match the actual DUT response with its expected response, which is, that the STE issues the transmit descriptor base address 0x40000000 on the PCI AD bus, and the Memory Read command (0x6) on the command bus, and asserts FRAME#4 Insert dummy turn-around per the Read Transaction waveform5 Then the Target gives the STE Bus Master its DEVSELn and TRDYn by driving them to logic 0, the STE will then begin reading the TX Descriptor first of 4 D-Words TDES0 (pointed to by the transmit descriptor address) on the next PCI Klunk. Note reading means the tester has to drive the TXDES0 own bit MSB 31 Hi.TRDYn is used to hold off the master until the target is ready. On the next the PCI Clock, the tester provides TXDES1 = 0x62000040 (page 40 of 66)which sets the buffer size. 40= 0100 0000 sets the 2 byte count to 2**6= 64 bytes. 64 bytes/4 bytes perD-word= Burst Length of 16. On the next PCI Clock TXDES2, which is the TX Buffer Address 0xA0000000, is written into (read by) the STE
Figure 3: PCI Ethernet Controller with Integrated PHY
Picture # Trace Description
Trace
1 Shows CBEB0 indicative of a 16 word write, followed by a read of CSR5 and then STE writes two more FCS words to RX buffer.
Trace 1: FRAME#Trace 2: TRDY#Trace 3: PCI CLKTrace 4: C/BEB0#
2 This view shows the two word write of the latter part of the scope picture above. The STE reads the TX Buffer again and then does a write to TX DES0.
Trace 1: FRAME#Trace 2: TRDY#Trace 3: PCI CLKTrace 4: C/BEB#
Figure 4: PCI Read Transaction Tutorial
PCICLK RSTn FRAMEn IRDYn GNTn AD[31:0] CBEB[3:0] TRDYn IDSEL DEVSELn REQn STOPn PERRn SERRn PAR INTAn PMEn BRA[16:0] BRD[4:0] BrCSn BrOEn BrWEn LEDLK LEDC1 LEDSpd Vccdct Vauxdct BD6 BD7 EECS;// D LLLVV // P F CCCC E EEECA // C R I //// T I V S P S I B BB B BBB DDDCU // I R A R G A A A A BBBB R D S R T E E N P R RR R RRR MMMDX E// C S M D N D D D D EEEE D S E E O R R P T M A AA D COW 111ED BBE // L T E Y T 3 2 1 0 nnnn Y E L Q P R R A A E 1 00 0 SEE LFSTE DDC // K n n n n 1 3 5 7 3210 n L n n n n n R n n 6 87 4 nnn KDPET 67S // - - - - - -------- -------- -------- -------- ---- - - - - - - - - - - ----------------- ----- --- ----- ---
;ldlc.100//Wait 100 clocks for a PCI REQ# from UUT after TX turned onWait_TX_Desc_REQ:
K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 L X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_TX_Desc_REQ
K 1 X X 1 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_TX_Desc_REQ//GNT# REQ#
K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...// ;ldlc.17//Wait 16 clocks for an access after bus granted to UUT PCI System Architecture p. 61Wait_Memory_Access_1:
K 1 L H 0 LHLLLLLL LLLLLLLL LLLLLLLL LLLLLLLL LHHL 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;Match.Wait_Memory_Access_1//Delays driving bus one clock--klunk vs. PCI timing
K 1 X X 0 XXXXXXXX XXXXXXXX XXXXXXXX XXXXXXXX XXXX 1 0 1 X X X X X X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ... ;JmpFail.No_TX_Desc_Access//Read TXDES0--own bit set for STE10
K 1 L L 0 10000000 00000000 00000000 00000000 XXXX 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. .... ... ..... ...//Read TXDES1, 2, 3//was 32 byte size = 6 bytes x 2 addr + 2 bytes length + 18 data bytes; CSR18 default is 64bytes K 1 L L 0 01100010 00000000 00000000 01000000 LLLL 0 0 0 X X X X 1 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...//Buffer Address K 1 L L 0 10100000 00000000 00000000 00000000 LLLL 0 0 0 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................ ..... ... ..... ... K 1 H L 0 00000000 00000000 00000000 00000000 LLLL 0 0 0 X X X X 0 X X XXXXXXXXXXXXXXXXX XXXXX XXX XXX10 XXX@@ . . u u . ........ ........ ........ ........ .... u . u u u u u . u u ................. ..... ... ..... ...
//--------------------------------------------------------------
# 1
# 3
# 3
# 3
# 2
# 4
# 5# 5# 5
Set Up Transmit and Receive DescriptorsTo set up receive descriptor and transmit descriptors, write a memory location into CSR3 (RDB) and CSR4 (TDB) using PCI memory write accesses.1
During normal operation, the STE10/100A uses the PCI bus to read data from host memory as defined by the transmit-descriptor and move it to the transmit FIFO. The STE10/100A does a PCI write from the receive FIFO to host memory as defined by the receive-descriptor.
Since there is no host memory in the test environment, the LMO500 tester emulates host memory. When the UUT does a read, the tester checks the address and drives data onto the AD lines. When the UUT does a write, the tester checks the address and then checks the data written.
When the pointers to the descriptors are written to CSR3 and CSR4, there is no setup in host memory of the descriptor table, because there is no host memory. The tester emulates the descriptor table by driving the data lines when the UUT reads the locations in the table.
UUT use of the descriptor table in Table 4 occurs after the TX machine starts. When the UUT accesses either of the descriptors, the tester does the following:
1. Set the RDES1 or TDES1 control bits for one packet for transmission or receipt.2. Check the Own bit in DES0 for ‘1.’ The tester drives a ‘1’ to this bit when the UUT does a PCI
memory read to the DES0 location in memory.3. Read Control field and Buffer 1 size of DES1. The tester drives the control bits: TDES1 [31:22]
= “1100000100” or RDES1 [31:22] =”0000001000” and Buffer 1 size (for RX) or byte count (for TX).
4. Read the Buffer 1 address of DES2. The tester drives the Buffer 1 address.5. Read all of the data in Buffer 1 (which is pointed to by DES2) for a transmission or write the
data received to Buffer 1 for a reception.6. When the operation is complete, write status to DES0 and set the own bit to ‘0.’
Table 3 RX Descriptor Table Emulated by Tester31 0
RDES0 Own RX StatusRDES1 ------------- Ctl -- RX Buffer 2 size RX Buffer 1 size = 60hRDES2 RX Buffer 1 addressRDES3 RX Buffer 2 address
Table 4 TX Descriptor Table Emulated by Tester31 0
TDES0 Own TX StatusTDES1 Ctl TX Buffer 2 size TX Buffer 1 size = 20hTDES2 TX Buffer 1 addressTDES3 TX Buffer 2 address
Table 5 and Table 6 show the emulated buffers for Ethernet TX and RX data. On writes to the RX buffer, the LMO500 is a PCI slave device. It checks for correct PCI write data from the UUT when the
1 STE10/100A datasheet page 17.
UUT fills the RX buffer. The tester is the PCI slave device and drives the data in Table 5 when the UUT does PCI reads for data to send over the PHY.
Table 5 Tester-Emulated TX Buffer DescriptionAddress (+offset hex)
Description
TX Buffer 1 Dest address bytes 6, 5, 4, 3 = FF, FF, FF, FF Note 1+4 Destination address bytes, 2, 1 = FF, FF; Src address bytes 6, 5 = 00, 00+8 Source address bytes, 4, 3, 2, 1 = BB, AA (PAR0); DD, CC (PAR1)+c Length =00, 2e; 00, 01+10 02, 03, 04, 05+14 06, 07, 08, 09+18 0A, 0B, 0C, 0D+1c 0E, 0F, 10, 11 Note 2
NOTES:1. Use Broadcast address.2. Padding is turned on in TDES1 [23]—the buffer need not contain 46 data bytes.2
Table 6 Tester-Emulated RX Buffer DescriptionAddress (+offset hex)
Description
RX Buffer 1 MAC Header Bytes 12, 11, 10, 9 = FF, FF, FF, FF+4 MAC Header Bytes 8, 7, 6. 5 =FF, FF; (PAR1);+8 MAC Header Bytes 4, 3, 2, 1 = (PAR0 4 bytes)+c Length bytes 2, 1; Data Byte 1, Data Byte 2 = 00, 2e; 00, 01+10 Data Byte 3, Data Byte 4, Data Byte 5, Data Byte 6 = 02, 03, 04, 05… Data Byte x, Data Byte x+1, Data Byte x+2, Data Byte x+3+38 Data Byte 43, Data Byte 44, Data Byte 45, Data Byte 46 = 00, 00, 00, 00+3c FCS4, FCS3, FCS2, FCS1
2 STE10/100A datasheet page 40.
How PCI Works
1. Address Phase
1a) Initiator identifies the target via the ADX and the type of transaction via the command bus1b) Initiator also asserts FRAME# to indicate the presence of valid ADX and command
2. Data Phase
2a) When the Target determines it is the selected target, it must claim the transaction by asserting DEVSEL# . If the Initiator doesn’t sample DEVSEL# asserted, it aborts the transaction2b) The Initiator indicates the last data transfer of a burst in progress by deasserting FRAME# and asserting IRDY# . When the last data transfer has been completed , the Initiator returns the PCI Bus to idle by deasserting it’s ready line IRDY#, so that another master can detect that the bus is idle by detecting FRAME# and IRDY# both deasserted on the same rising edge of the PCI Clock2c) When the Target samples IRDY# asserted and FRAME# deasserted in a data phase, it realizes this is the final data phase. However the data phase will not complete until the target has also deasserted TRDY#
3. Config Page 121 of PCI System Architecture Fourth Edition by Tom Shanly and Don Anderson
3a) To access Configuartion Registers, a config command must be initiated, and the device must sense it’s IDSEL input asserted during the Address Phase3b) AD[10:8] selects the function; AD[7:2] during the ADX Phase select one of the Target function’s 64 D-Words of Config Space