testability lecture 6: logic simulationlecture 6: logic...

TestabilityLecture 6: Logic SimulationLecture 6: Logic Simulation

Shaahin Hessabi

Department of Computer EngineeringDepartment of Computer Engineering

Sharif University of TechnologyAdapted from the presentation prepared by book authors

Slide 1 of 27

OutlineOutline

Wh i i l i ?• What is simulation?

• Circuit modeling

• True-value simulation algorithmsCompiled-code simulationpEvent-driven simulation

• Summary• Summary

Slide 2 of 27

Simulation• Definition: Simulation refers to modeling of a design, its

function and performance.• A software simulator is a computer program; an emulator is

a hardware simulator.• Applications of simulation:• Applications of simulation:

VerificationDebuggingStudying design alternative (cost/speed)Computing expected behavior for testing purposes

Sim lation for design erification:• Simulation for design verification:Validate assumptionsVerify logic; e.g.,y g ; g ,

independent of power-up statefree of critical races & oscillation

Verify performance (timing)

Slide 3 of 27

Verify performance (timing)

SimulationSimulation

• Problems of simulation-based design verificationTests are hand crafted

A heuristic process that relies heavily on the designer’s intuition & design knowledgeNot a precise procedure

Very hard to prove that a test is completeVery hard to prove that a test is complete.• Types of simulation:

Logic or switch levelTimingCircuitFault

Slide 4 of 27

Evaluating a Logic Simulatorg g

• Attributes are accuracy, efficiency and generality• Accuracy: close correspondence between the

predicted signal values & times, as calculated by the p g , ylogic simulator and those occurring in the real circuit

• Efficiency: Simulators must be cost-effectiveEfficiency: Simulators must be cost effective

• Generality: Should be able to handle a broad class of circuitscircuits

Synchronous, AsynchronousC bi ti l S ti lCombinational, SequentialRace/Hazard detection capabilities

Slide 5 of 27

Simulation for VerificationSimulation for Verification

Specification

S th i

DesignResponse

Synthesis

Design Design(netlist)

Responseanalysis

Designchanges

True-valueComputed True valuesimulation Input stimuli

Computedresponses

Slide 6 of 27Sharif University of Technology Testability: Lecture 6

Modeling for Simulationg

• Modules, blocks or components described byInput/output (I/O) functionDelays associated with I/O signalsExamples: binary adder, Boolean gates, FET, resistors and capacitors

• Interconnects representideal signal carriers, orideal electrical conductors

• Netlist: a format (or language) that describes a design ( g g ) gas an interconnection of modules. Netlist may use hierarchy.

Slide 7 of 27

y

Example: A Full-Adderp

HA; cinputs: a, b;outputs: c, f;AND: A1, (a, b), (c);

a c

d

e

f AND: A2, (d, e), (f);OR: O1, (a, b), (d);NOT: N1, (c), (e);

bd f

HA

FA;inputs: A, B, C;

t t C SHA1A D Carry

outputs: Carry, Sum;HA: HA1, (A, B), (D, E);HA: HA2, (E, C), (F, Sum);OR: O2 (D F) (Carry);

HA1HA2

B C

E F Sum

y

OR: O2, (D, F), (Carry);


Signal States• Two-states (0, 1) can be used for purely combinational logic

with zero-delay, and for synchronous circuits with a known initial stateinitial state.

• Three-states (0, 1, X) are essential for timing hazards and for sequential logic initialization.

X (unknown state) represents:Initial state of FFs and RAMsInterpreted as either 0 or 1

• Four-states (0, 1, X, Z) are essential for MOS devices.

Z

00

(hold previous value)

0• Analog signals are used for exact timing of digital logic and

for analog circuits.

Slide 9 of 27

Information Loss of 3-Valued Logicg

3-value simulation symbolic simulation

• The three-state logic is pessimistic.• Symbolic simulation can be effective if performed locally in aSymbolic simulation can be effective if performed locally in a

circuit.impractical for large circuits.


Modeling Levelsg

Circuit Signal TimingModeling Applicationdescription

Programminglanguage-like HDL

values

0, 1 Clockboundary

level

Function,behavior, RTL

Architecturaland functionalverification

Connectivity ofBoolean gates,flip-flops and

0, 1, Xand Z

Zero-delay,unit-delay,multiple-

,

Logic

verification

Logicverificationand testp p

transistors

Transistor sizeand connectivity,

0, 1, Xand Z

delay

Zero-delaySwitch Logicverification

node capacitances

Transistor technologydata, connectivity,

and Z

Analogvoltage

Fine-graintiming

Timing Timingverification

node capacitances

Tech. Data, active/passive component

vo ge

Analogvoltage,

timing

Continuoustime

Circuit Digital timingand analogcircuit


p pconnectivity

voltage,current

circuitverification

True-Value Simulation Algorithms• True-Value refers to no fault in circuit• Compiled-code simulationCompiled code simulation

The compiled code is generated from an RTL or gate-level description of the circuitSimulation is simply execution of the compiled codeApplicable to zero-delay combinational logic

Timing cannot be properly modeled no hazard or signal propagationTiming cannot be properly modeled no hazard or signal propagation is predicted

Also used for cycle-accurate synchronous sequential circuits for logic ifi tiverification

Efficient for highly active circuits, but inefficient for low-activity circuitsBecause time required to simulate a vector = t *N; whereq ;

– t = time required to simulate an element– N = number of elements

High-level (e g C language) models can be used

Slide 12 of 27

High-level (e.g., C language) models can be used

True-Value Simulation Algorithms (cont’d)g ( )

• Event-driven simulation• Event driven simulationOnly gates or modules with input events are evaluated (event means a signal change)(event means a signal change)Delays can be accurately simulated for timing verificationEfficient for low-activity circuitsEfficient for low activity circuits

The ratio of lines which change values to the total number of lines in the circuit is called activityTypically activity = 2 - 10 %

Can be extended for fault simulation

Slide 13 of 27

Compiled-Code Algorithmp g

• Step 1: Levelize combinational logic and encode in a il bl i lcompilable programming language

Assign all PI lines level 0Th l l f i L 1 ( L L L )The level of a gate g is: Lg = 1 + max ( Li1 , Li2 , …Lin)

Li1 , Li2 , …Lin are levels of inputs of gate g.

• Step 2: Initialize internal state variables (flip flops)• Step 2: Initialize internal state variables (flip-flops)• Step 3: For each input vector

S t i i t i blSet primary input variablesRepeat (until steady-state or max. iterations)

Execute compiled codeExecute compiled code– Elements are simulated in ascending order of logic level

Report or save computed variables

Slide 14 of 27

Compiled Simulation (Example)• Given circuit C:

2 Generate code2. Generate codewhile(1) {Read_in ( a, b, c, d ) ;e = NAND ( a, b ) ;f = INV ( c ) ;g = NOR ( b f ) ;

1. Levelize circuitg = NOR ( b, f ) ;i = AND ( e, i ) ;j = NAND ( i, d );

Level 0: a, b, c, dLevel 1: e, fLevel 2: g

Print ( e, i, j ) ;}

Level 2: gLevel 3: iLevel 4: j


Event-Driven Algorithmg

Slide 16 of 27

Event-Driven Algorithm(E h d li )(Event scheduling)

Scheduledt

Activityli

2a =1c =1 0

e =1 t = 0

events

c = 0

list

d, e

22

d = 0

g =1 1

2 d = 1, e = 0 f, g

4b =1

d = 0

f =03

4 g = 0 sta

ck

g

5

6

g

f 1

Tim

e

Time, t0 4 8

g 6

7

f = 1 g


8 g = 1

Gate Evaluation - Input Scanningp g

• Assume only dealing with AND , OR , NAND, NOR primiti e gatesprimitive gates

• These gates can be characterized by controlling value c & inversion ic & inversion i

I t O t tc i Inputs Output

c x x c ⊕ i

c iAND 0 0OR 1 0

x c x c ⊕ i

x x c c ⊕ i

NAND 0 1NOR 1 1

x x c c ⊕ i

c’ c’ c’ c’ ⊕ i


Delay Types• Transport (propagation) delay: time interval

between the generation of a signal transition at a g ggate output (source) and its arrival at the input of a fanout gate

transition independenttransition dependent : rise/fall delays specified separately

• Inertial (switching) delay: time interval between an input change and the output change of a gate.

Slide 19 of 27

Logic Model of MOS CircuitLogic Model of MOS Circuit

VDVDD

pMOS FETs

DcDa c

a

Ca C

ac

cb Db

Cc Cb

b

nMOS

Da and Db are interconnect or

ti d lFETs propagation delays

D is inertial orCa , Cb and Cc are

parasitic capacitances

Dc is inertial or switching delayof gate


Switching Delay Models• Zero delay: Output changes instantly in response to

an inputpuseful for logic simulation of combinational circuits

• Unit delay: All gates have one unit delay, no delay y g y, yfor interconnects

circuits with feedback can also be simulated• Multiple delay: delays are modeled as multiples of

some time unitEach gate is assigned a rise delay (dr) and a fall delay (df)

• Ambiguous delay or Minmax delay

Slide 21 of 27

Options for Inertial DelayOptions for Inertial Delay(simulation of a NAND gate)

Transient

b

a

Inpu

ts region

c (CMOS)

c (zero delay)

( it d l )atio

n

c (unit delay)

c (multiple delay)ic s

imul

a

rise=5, fall=3

Ti it

c (minmax delay)Log

i

min =2, max =5Unknown (X)


Time units0 5

Event-Driven Simulation with Delay

Need a “time-flow” mechanism


Time Flow Mechanism & Event Scheduling

• When an element i is simulated and it is determined h i i l j h h d ithat its output signal j has changed state; i.e.,

Vnew(j) ≠ Vold(j), then signal j must be scheduled to h V (j) i t Δichange to Vnew(j) at time t+ Δi

where t : the current simulation timeΔi : the delay of element iΔi : the delay of element i

The event ( j, Vnew ( j), t+ Δi ) is scheduled to occur in th f t rin the future.

• Need an event queue for each time of simulation

Slide 24 of 27

Time Wheel (Circular Stack)Time Wheel (Circular Stack)

t=0

maxCurrenttime

1

2

pointer Event link-list

3

44

5

6

7


Efficiency of Event-driven Simulatory

• Simulates events (value changes) only

• Speed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change

Large logicblock without

activity

Steady 0

0 to 1 event

Steady 0(no event) activity0 to 1 event

Slide 26 of 27

Summary

• Logic or true-value simulators are essential tools for design verification.

• Verification vectors and expected responses are generated (often manually) from specifications.

• A logic simulator can be implemented using either g p gcompiled-code or event-driven method.

• Per vector complexity of a logic simulator is• Per vector complexity of a logic simulator is approximately linear in circuit size.

• Modeling level determines the evaluation• Modeling level determines the evaluation procedures used in the simulator.

Slide 27 of 27

testability lecture 6: logic simulationlecture 6: logic...

Documents