testbenches digital electronics design
DESCRIPTION
Testbenches Digital Electronics Design. my_file= file handle. file name and type and mode. write buffer. write to file. Test benches , Text IO. Text IO routines are part of VHDL. TextIO is suitable to use in testbenches to read stimuli from a file and write results on a file. - PowerPoint PPT PresentationTRANSCRIPT
joal 2006 HT:1 Em3
Digital Electronics Design 1
Testbenches
Digital Electronics Design
joal 2006 HT:1 Em3
Digital Electronics Design 2
Testbenches, Text IO
• Text IO routines are part of VHDL. TextIO is suitable to use in testbenches to read stimuli from a file and write results on a file.
• Write procedures:write(….) -- write to buffer writeline(…) -- write to file
• Read procedures:read(…) -- read from bufferreadline(…) -- file to buffer
process variable text_line: line; variable out_data: integer:=0; file my_file: text open write_mode is ”textfile.txt”;begin for i in 0 to 10 loop write(text_line,”counter=”); out_data:=out_data+1; write(text_line, out_data); writeline(my_file, text_line); end loop; wait; -- stop processend process;
declare buffer
my_file=file handle
write to file
write buffer
file name and type and mode
joal 2006 HT:1 Em3
Digital Electronics Design 3
Testbenches, Text IO
• Text IO routines are part of VHDL. TextIO is suitable to use in testbenches to read stimuli from a file and write results on a file.
• Write procedures:write(….) -- write to buffer writeline(…) -- write to file
• Read procedures:read(…) -- read from bufferreadline(…) -- file to buffer
process variable text_line: line; variable in_data: character; file my_file: TEXT open read_mode is ”crc.txt”;begin while not endfile(my_file) loop readline(my_file, text_line); read(text_line, in_data); if in_data=’1’ then -- ascii insig<=’1’; elsif in_data=’0’ then insig<=’0’; else assert false ….. end if; end loop;end process;
read mode
file to buffer
from buffer to variable
loop until end of file
joal 2006 HT:1 Em3
Digital Electronics Design 4
process subtype byte is std_logic_vector(7 downto 0); type storage_array is array (0 to 255) of byte; variable storage: storage_array; variable index: natural; -- natural ={0 to highest int} type load_type is file of byte; file load_file: load_type open read_mode is ”bytefile”;begin index:=0; while not endfile(load_file) loop read(load_file, storage(index)); index:=index+1; end loop; wait;end process;
Test benches, File IO, GeneralFile IO can be used to write and read data elements. One element is written or read for each write or read command. The file pointer is incremented for each write/read command. The type of file and the mode must be declared in the file- declaration.
joal 2006 HT:1 Em3
Digital Electronics Design 5
Composite Data TypesSubtypessubtype short is integer range 0 to 255;subtype byte is std_logic_vector(7 downto 0);
Arraystype ROM_type is array (0 to 31) of byte;variable ROM: ROM_type;
Recordstype time_stamp is record seconds: integer range 0 to 59; minutes: integer range 0 to 59; hours: integer range 0 to 23;end record time_stamp;variable sample_time, current_time: time_stamp;
Examples: sample_time:=current_time; sample_hour:=sample_time.hours;
joal 2006 HT:1 Em3
Digital Electronics Design 6
Verifying the design
How can a component (VHDL) be verified?
• Use script language (Simulator Control Language)– Platform dependent (-)– Risk for same errors in the test bench as in the design ( if the
designer makes the test bench) (-)
• Use VHDL test bench– Platform independent (+)– Same risk for errors as SCL (-)– Can be done by system design engineer (executable spec) (+)
• System level simulations– Good in finding interface errors (+)– Models used are (shall have been) verified (+)
joal 2006 HT:1 Em3
Digital Electronics Design 7
Verifying the design
Conclusion
• Use VHDL Test bench both on behavioral and RT levels as a first step
– Powerful language (compared to SCL)– Portable– Common language
• Simulate on System level as a second step– If VHDL test bench can be used or not depends
on availability of simulation models (for ASICs)
joal 2006 HT:1 Em3
Digital Electronics Design 8
System level simulations
VHDL-RTL
P
EPROM
74HCx RAM
System level simulation represents
the environment(Example)
joal 2006 HT:1 Em3
Digital Electronics Design 9
Verifying the design
Test bench
Computer VHDL ”prototype”
VHDL comp ”signal gener.”
A
VHDL comp ”logic analyzer”
B
Verification with a test bench (A and B) in the computer
joal 2006 HT:1 Em3
Digital Electronics Design 10
Example: UART Testbench
UART(UUT)
Processor (BFM)
FM
Data(7 downto 0)
Controls
Interrupts
Reset/clock
Transmit Data
Receive Data
UUT=Unit Under TestFM=Functional Model
BFM=Bus Functional Model
joal 2006 HT:1 Em3
Digital Electronics Design 11
Verifying the design. Design flow
Design specification
VHDL behavioral model
Graphical VHDL tool
Simulation
VHDL (RTL)
Simulation
A
Behavioral level
Graphical VHDL tool
Specification level
RT level
joal 2006 HT:1 Em3
Digital Electronics Design 12
Verifying the design. Design flow
Synthesis
Test vector generation
Simulation
Place & route (layout)
Simulation
A
Netlist level (before layout)
Implement in hardware
Netlist level (after layout)
joal 2006 HT:1 Em3
Digital Electronics Design 13
Testbenches in VHDL. VerificationThere are three verification steps during
development:• The behavioral model verification• The RTL VHDL model verification• Gate level verification both before and after
layoutTestbenches can be used in all three steps.
VHDL modelVHDL RTL
modelGate level e.g. VITAL
VHDL test- bench
VITAL is a library with VHDL primitives to describe a circuit after layout. Both gate and wire delays are included
Static timing analysis can replace simulation in this step
joal 2006 HT:1 Em3
Digital Electronics Design 14
Testbenches in VHDL. Different parts
Part A: Input stimuli test bench
Part B: Output analysis testbench
Computer VHDL ”prototype”
VHDL comp ”signal gener.”
VHDL comp ”logic analyser”
A B
joal 2006 HT:1 Em3
Digital Electronics Design 15
Testbenches in VHDL. Input stimuli 1• Generation of input signals:
stim1<= ’1’ after 5 ns, ’0’ after 100 ns, ’1’ after 200 ns, ’0’ after 300 ns;
reset<=’1’, ’0’ after 50 ns;• Generation of clock signal:
signal clk: std_logic:=’0’; -- must be set to start value.constant period: time:=100 ns;
……….clk <= not clk after period/2; -- 10 MHz clock
• Synchronized inputs:processbegin wait until clk=’1’; in_signal1<=’1’; in_signal2<=’0’; wait until clk=’1’; in_signal1<=’0’; in_signal2<=’1’;end process;
joal 2006 HT:1 Em3
Digital Electronics Design 16
Testbenches in VHDLInput stimuli 2
Waveform generators:An alternative is to use a waveform generator to create input stimuli.
ROMclock step
stimuli
subtype rom_word is std_logic_vector(3 downto 0);type rom_table is array (0 to 7) of rom_word;constant rom: rom_table:=( ”0100”, ”1100”,signal wave: rom_word;…. wave<=rom(conv_integer(step)); stim1<=wave(0); stim2<=wave(1);
joal 2006 HT:1 Em3
Digital Electronics Design 17
Testbenches in VHDL Output check
Check of output signals:
• Use assert to send messages and stop simulations at errors.• Use wait until clk=’1’ to synchronize to clock.
processbegin if a=’1’ and b=’1’ then assert false report ”a and b violation” severity error; end if; wait until clk=’1’;end process;
joal 2006 HT:1 Em3
Digital Electronics Design 18
Testbenches in VHDL. Different levelsClass 1: Direct signal assignment. Text IO or waveform generator
generates inputs.
Class 2: Outputs are functionally checked with e.g. wait for 50 ns or wait until clk=’1’. Report result with assert command or special check signal.
Class 3: Timing violation is tested. Can only be done on gate level simulation.
Example:wait for 50 ns;if not q’stable(15 ns) then
assert falsereport ”Setup timing violation on q”severity Warning;
end if;
joal 2006 HT:1 Em3
Digital Electronics Design 19
Testbenches in VHDL. Testvectors
• Testvectors are a set of input and output data that is used both for functional verification during development and for chip test during fabrication (only for ASIC).
• Testvectors are handled by the testbench.
• Testvectors are used both for behavioral and gate level verifications.
joal 2006 HT:1 Em3
Digital Electronics Design 20
Testbenches in VHDL. Pull Up/DownA pull up/pull down can be represented by ’H’ and ’L’ respective. If a component has an inout pin the testbench can handle the pull up.
entity test_bench isend;architecture tb of test_bench is component etu is port(enax: in std_logic; iox: inout std_logic); -- resolved!!! end; signal ena, io: std_logic;begin u1: etu port map(ena=>enax, io=>iox); io<=’H’; -- pull up ena<=’0’, ’1’ after 100 ns, ’0’ after 150 ns; io<=’0’, ’Z’ after 100 ns, ’0’ after 150 ns;end tb;
entity etu is port(ena: in std_logic; io: inout std_logic);end;architecture rtl of etu is signal ena, io,a: std_logic;begin io<=a when ena=’1’ else ’Z’;end rtl;
joal 2006 HT:1 Em3
Digital Electronics Design 21
Testbenches in VHDL Behavioural description!
When writing testbenches you are not restricted to use the subset of VHDL that can be
synthesised!
joal 2006 HT:1 Em3
Digital Electronics Design 22
Signals or variables?
• In testbenches ( and in VHDL-models that shall not be synthesized it’s better to use variables:– Much faster simulations– Less memory is required
joal 2006 HT:1 Em3
Digital Electronics Design 23
DesignSynchronizing of FSMs and external events
Timer FSM
clk
bitclk
outp<='0'outp<='0'
S3
S2
S1reset='1'
outp<='0'outp<='0'
outp<='1'outp<='1'
bitclk='1'
bitclk='1'
bitclk='1'
Tbitclk
Tclk
joal 2006 HT:1 Em3
Digital Electronics Design 24
Synchronization of processes
• Strobe method– Compare to synchronization with timer on previous
slide– Generate a strobe as a “one clock pulse”– Processes must be synchronous (have the same clock
and little “skew”)
• Hand shaking– To be used if the clocks are not synchronous
joal 2006 HT:1 Em3
Digital Electronics Design 25
Synchronization. Strobe
Stb<=‘1’
Stb=‘0’
Stb<=‘0’
Stb=‘1’
synch
joal 2006 HT:1 Em3
Digital Electronics Design 26
Design Synchronizing of FSMs and external events 1
entity timer is port(clk,reset: in std_logic; bitclk: out std_logic);end;
architecture rtl of timer is signal cntr: integer range 0 to 9;begin process(reset,clk) begin if reset=’1’ then cntr<=0; bitclk<=’0’; elsif clk’event and clk=’1’ then if cntr=0 then bitclk<=’1’; else bitclk<=’0’; end if; if cntr=9 then cntr<=0; else cntr<=cntr+1; end if; end if; end process;end rtl;
joal 2006 HT:1 Em3
Digital Electronics Design 27
Synchronization. Hand shaking
Process A Process B
Req=‘1’
Ack=‘1’
Req=‘0’
Ack=‘0’
Ack<=‘0’
Req=‘0’
Ack<=‘1’
Req=‘1’Req=‘1’
Ack<=‘0’
Req=‘0’
joal 2006 HT:1 Em3
Digital Electronics Design 28
Design. Meta stability 1Meta stability may occur when data is changing on the clock edge. The output decision of the latch or register is arbitrary.This problem will be found when data and clock are not synchronized e.g. inputs that shall be read by state machines.
When a latch/register is meta stable the subsequent circuitry can interpret the output of the latch as two different values (setup and hold time violations).
clk
data
output
0
1data
output
clk
joal 2006 HT:1 Em3
Digital Electronics Design 29
Design. Meta stability 2
Some FPGAs are very sensitive to Meta stability. Use synchronizing mechanism to avoid problems.
D Q
C
R
D Q
C
R
D Q
C
R /Q
input
clk
reset
&rising edge pulse
joal 2006 HT:1 Em3
Digital Electronics Design 30
Design.Synchronizing of FSMs and external events 2.
Synchronizer FSM
clk
i_synch
input
Tclkinput
joal 2006 HT:1 Em3
Digital Electronics Design 31
Design Synchronizing of FSMs and external events 2.
entity synchronizer is port(clk,reset,input: in std_logic; i_synch: out std_logic);end;architecture rtl of synchronizer isbegin process(reset,clk) begin if reset=’1’ then i_data<=’1’; elsif clk’event and clk=’1’ then q1<=input; q2<=q1; q3<=q2; end if; end process; i_synch<=q2 and not q3; end rtl;
joal 2006 HT:1 Em3
Digital Electronics Design 32
Xilinx Spartan FPGA 1
CLB (Configurable Logical Block) in Spartan series
clk
G-LUT
F-LUT
H-LUT
FF
FF
joal 2006 HT:1 Em3
Digital Electronics Design 33
PLD structures
PALMacrocell
LUT
Addr I1 I2 O1
0 0 0 0
1 1 0 1
2 0 1 1
3 1 1 0
O1= (I1 and not I2) or (not I1 and I2)
LUT1(16*1 bit mem) LUT = LookUpTable
16 product terms /LUT
O1FF1
LUT1
IO
IO
IO
IOLUT2
I1I2
Programmable LUTs and programmable routing
joal 2006 HT:1 Em3
Digital Electronics Design 34
CLB (Configurable Logical Block) in Spartan series
Xilinx Spartan FPGA 2
clk
16*1 RAM
16*1 RAM
H-LUT
FF
FF
Distributed RAM
joal 2006 HT:1 Em3
Digital Electronics Design 35
CLB (Configurable Logical Block) in Spartan series
Xilinx Spartan FPGA 3
clk
16*1 RAM
16*1 RAM
H-LUT
FF
FF
Distributed RAM
Spartan XCS10 has 196 CLBs => max 32*196 bits = 6272 if all CLBs are used for memory.
ROM is the same as RAM but the content is stored when the FPGA is programmed.
joal 2006 HT:1 Em3
Digital Electronics Design 36
CLB (Configurable Logical Block) in Spartan series
Xilinx Spartan FPGA 4
clk
16*1 RAM
16*1 RAM
H-LUT
FF
FF
Distributed RAM
The HDL synthesis tool can infer (”dra slutsatsen”) that this shall be a distributed memory.
The code must then be written a defined way.
joal 2006 HT:1 Em3
Digital Electronics Design 37
Two methods to include ROM and RAM in a design:
• Instancing a technology specific ROM or RAM.• Write VHDL code that is inferred (tolkad) to be a ROM or RAM.• A RAM can also be implemented as registers (not efficient)
Xilinx Spartan FPGA 5
joal 2006 HT:1 Em3
Digital Electronics Design 38
architecture rtl of rom is constant rom_w: integer:=8; constant rom_l: integer:=4; subtype rom_word is std_logic_vector (rom_w-1 downto 0); type rom_table is array (0 to rom_l-1) of rom_word; signal rom: rom_type;begin q<=rom(conv_integer(addr));end rtl;
Xilinx Spartan FPGA 6
Inferred distributed ROM
joal 2006 HT:1 Em3
Digital Electronics Design 39
architecture rtl of ram_test is type mem_type is array (7 downto 0) of std_logic_vector (3 downto 0)); signal mem: mem_type;begin q<=mem(conv_integer(addr)); process(clk, we,addr) if (rising_edge(clk) then if we=‘1’ then mem(conv_integer(addr))<=d; end if; end process;end rtl;
Xilinx Spartan FPGA 7
Inferred distributed RAM
Required
joal 2006 HT:1 Em3
Digital Electronics Design 40
Xilinx Spartan FPGA 7
Inferred distributed RAM
joal 2006 HT:1 Em3
Digital Electronics Design 41
Lab assignment 4• Design a CRC generator• Design a testbench to test the CRC generator• Use input data from a test and the testbench to verify the design.
CRC generatorclk
ser_in
reset_n
crc_ok
joal 2006 HT:1 Em3
Digital Electronics Design 42
Lab assignment 4
D QCR
D QCR
D QCR
D QCR
D QCR
D QCR
D QCR
D QCR
D QCR
=1
=1
0 1 4 5 11
12 13 14 15
Q11
=1
Q11
Q15
Q15
Q4
Q4
X1
X1
X1
ser_in
clkreset
q15
crc_ok&
q0
joal 2006 HT:1 Em3
Digital Electronics Design 43
Lab assignment 4. CRC
entity crc is port(clk,reset,ser_in: in std_logic; crc_ok: out std_logic);end;
architecture rtl of crc is signal crc_reg: std_logic_vector(15 downto 0);begin p1:process(clk,reset) -- synchronous process for shift register end process; p2:process(crc_reg) -- combinational process for crc_ok end process;end rtl;
joal 2006 HT:1 Em3
Digital Electronics Design 44
Lab assignment 4. CRC testbench
use std.textio.all;entity crc_tb isend;
architecture behav of crc_tb is-- declare component crc-- declare signalsconstant period: time:= 100 ns;begin -- instantiate component crc as U1 -- clock and reset generation process file crc_file: text open read_mode is ”G:\VHDL\crc.txt”; variable text_line: line; variable inchar: character; begin -- read file and control input to crc end process; -- continues on next page
joal 2006 HT:1 Em3
Digital Electronics Design 45
Lab assignment 4. CRC Testbench
-- continues from previous page process begin -- count 48 pulses to crc -- assert to display crc_ok end process;end behav;
joal 2006 HT:1 Em3
Digital Electronics Design 46
Lab assignment 4. Testbench
constant period: time:=100 ns;
begin reset<=’1’, ’0’ after period/4; clk<=not clk after period/2;…………end behav;
wait until clk=’1’;readline(..);read(..);
clk
reset
joal 2006 HT:1 Em3
Digital Electronics Design 47
Syntax:
assert <condition>
report <message>
severity <error_level>
if crc_ok=’1’ then assert false report ”crc ok” severity failure;else assert false report ”crc not ok” severity failure;end if;
An assert message is sent
if the condition is not met
Lab assignment 4. Testbench
stop simulator
joal 2006 HT:1 Em3
Digital Electronics Design 48
- tb_exempel-- joal 2003-10-07-- Abstract: To demonstrate how multiple drivers can be-- generated in a test bench and-- how to avoid problems with that
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;
-- ***********************************************LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;
ENTITY tb_exempel ISEND tb_exempel ;
ARCHITECTURE behav OF tb_exempel IS component tt_buffer is port(rd: in std_logic; out_buffer: inout std_logic_vector(7 downto 0)); end component; signal rd: std_logic; signal out_buffer: std_logic_vector(7 downto 0);BEGIN u1: tt_buffer port map (rd,out_buffer); process begin
rd<='1'; wait for 500 ns; rd<='0'; wait;
end process; process begin
wait for 1 us; out_buffer<="10101010"; wait;
end process;END behav;
VHDL Test bench problem
joal 2006 HT:1 Em3
Digital Electronics Design 49
- tb_exempel-- joal 2003-10-07-- Abstract: To demonstrate how multiple drivers can be-- generated in a test bench and-- how to avoid problems with that
LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;
-- ***********************************************LIBRARY ieee;USE ieee.std_logic_1164.ALL;USE ieee.std_logic_arith.ALL;
ENTITY tb_exempel ISEND tb_exempel ;
ARCHITECTURE behav OF tb_exempel IS component tt_buffer is port(rd: in std_logic; out_buffer: inout std_logic_vector(7 downto 0)); end component; signal rd: std_logic; signal out_buffer: std_logic_vector(7 downto 0);BEGIN u1: tt_buffer port map (rd,out_buffer); process begin
rd<='1'; wait for 500 ns; rd<='0'; wait;
end process; process begin-- out_buffer driver in this process must have a start value – otherwise ’U’ is used and can't be resolved!!!! out_buffer<="ZZZZZZZZ";
wait for 1 us; out_buffer<="10101010"; wait;
end process;END behav;
VHDL Test bench problem
joal 2006 HT:1 Em3
Digital Electronics Design 50
VHDL Test bench problem
Before code corrected
rd
out_buffer UUUUUUUU 10101010
After code corrected
rd
out_buffer 01010101 10101010
1 s