testing and verification of symq board for detection of symmetric quenches andrzej skoczen agh-ust,...

A. Skoczen AGH-UST, CERN

Testing and Verification of SymQ Board for Detection of Symmetric

QuenchesAndrzej SkoczenAGH-UST, FP&ACS, DPI&DT, Cracow

CERN-TE-MPE-EPin strict collaboration with Jens Steckert

Abstract:The main part of SymQ board is a VHDL code to configure FPGA device ProASIC3E from MicroSemi. The quality and architecture of this code are critical for proper functionality of symmetric quench detection system with special attention for radiation environment influence. Therefore a number of simulation and new test procedures were developed. Simultaneously several important modifications were introduced. Presentation focuses on several aspects of this work carried out during last months.

Activities during last months: Finding bugs (VHDL)

Corrections to enhance simulation and/or synthesis

Building new modules (VHDL)

Development of scripts managing synthesis or simulation processes (PowerShell, TCL, Unix shell)

Building simulation test-benches for whole system and its parts (VHDL, Verilog, TCL)

Development of applications for hardware test-bench (LabView, USB-6353, USB-8451)

Performing and designing hardware tests and analysing results


SimulationINCISIVE, ModelSim

Board Level

Verification

LabView

Design Flow

SynthesisSynplify

Place & Route

Libero Designer

FPGA

Gate Level Netlist + TimingVHDL, SDF

ASIC

Configuration

BitstreamFlash Pro

Gate Level Netlist + TimingVHDL, SDF

RTL Description

VHDL, Verilog

BUG !

VERIFY !

BU

G

!


FPGA ProASIC3E A3PE1500System Gates 1 500 000VersaTiles (D-flip-flops) 38 400RAM Kbits (1,024 bits) 2704,608-Bit Blocks 60FlashROM Kbits 1Secure (AES) ISP YesCCCs with Integrated PLLs2 6I/O Banks 8Maximum User I/Os 444

Architecture consists of five distinct and programmable elements:

FPGA VersaTiles Dedicated FlashROM (not used in SymQ) Dedicated SRAM/FIFO memory Extensive CCCs and PLLs (not used in SymQ) Pro I/O structure


SPI master

to 4 ADC’s

Signal processing pipelineSignal processing

pipelineSignal processing pipelineSignal processing chainM

APPE

R Quench detection

logic

Heater & Interlock outputs

Command Decoder

Configuration RegistersI2C

slave

Circular buffers


SCK 6410

sps

SCL

SDA

SymQ architecture

System clock 40MHzSynchronic reset

SCK

SCK

SCK

SymQ processing chain


Median Filter Avarage

Filter Corrector

INV

Preset

LP filter used as a notch filter at 50Hz with length 128, depth 7 and frequency 6410Hz

Confi

gura

tion

Regi

ster

s

Confi

gura

tion

Regi

ster

s

Confi

gura

tion

Regi

ster

s

Confi

gura

tion

Regi

ster

s

Confi

gura

tion

Regi

ster

s

Data inversion because of inverting property of analogue input stage

Digital correction of offset and gain caused by analogue part: voltage divider, instrumentation and operational amplifiers

Confi

gura

tion

Regi

ster

s

Confi

gura

tion

Regi

ster

s

Confi

gura

tion

Regi

ster

s

Nonlinear digital filtering for noise reduction as a pre-processing step


Simulation and re-designing: Sequential multiplication Synchronisation of reset

Hardware testing: Delay time from abrupt change of magnet voltage to interlock opening Range of gain adjustment

UUTSymQ

design

RTL VHDL

I2C master

Behavioural Verilog

I2C masteropencores.org

RTL Verilog

Cmd file

Data file

ADC

Behavioural Verilog

max1162Signal file

Analog signal generator(optional) Verilog-AMS

ADC

Behavioural Verilog

max1162Signal file


ADC

Behavioural Verilog

max1162Signal file

Analog signal generator(optional)

ADC

Behavioural Verilog

max1162Signal file


Clock Reset Behavioural VHDL

script TCL

ncsi

m

simulation

Addi

tiona

l in

foRe

port

.out

Adr

Simulation testbench for whole of SymQ design

Cadence INCISIVE 12.1

interchangeably with Gate Level VHDL + SDF coming from Synplify Premier (G-2010.09) or Libero Designer (11.0)


Verilog-AMS

txt

txt

txt

txt

txt

txt

txt

txt

SPI

SPI

SPI

SPI

I2C

VHDL testbenchControl script

Wav

efor

m

grap

hica

l da

taba

se


SymQ design statistics Instance name TMR Nr of

instancesNr of

library cellsNr of sequential

library cellsNr of combinational

library cellsi2c_slave yes 1 397 171 226discriminator_disc_a_1* yes 5 90 36 54clkdiv24_counter_0* yes 2 172 75 97multS_multS_2* yes 4 397 111 286i2com yes 1 5992 2430 3562logic_quad yes 1 541 201 340sunglass yes 1 426 90 336logic_dip yes 1 3428 1182 2246aspirine_medicine* yes 2 234 72 162autozero no 1 648 151 497triggerbox yes 1 23 0 23buffer_trigger_unit yes 1 617 204 413fastbuffer_4 no 1 489 103 386fastbuffer_16_fb0* no 4 689 153 536corrector_correction0* yes 4 789 402 387median_filter_median0* yes 4 2146 894 1252meanram_fsm_mean0* yes 4 951 369 582max1162_interface_flex_quad yes 1 1020 456 564mapper yes 1 309 0 309top yes 1 2447 1332 1115

TOTAL 41 37495 14516 22979

Smaller then total available VersaTiles 38400

Target part A3PE1500_PQFP208_-2Clock frequency 40 MHzRequired time 25 nsPropagation time 16.746 nsSlack (critical) 8.254 nsNumber of logic level(s) 17Core Cells 887 of 38400 (2%)

sequential 0

entity multS is generic (W1, W2: natural; omode: std_logic); port(clk :in std_logic; multiplier :in std_logic_vector(W1-1 downto 0); multiplicand :in std_logic_vector(W2-1 downto 0); product :out std_logic_vector(W1+W2-2 downto 0)); end mults;

architecture behavioral of multS is signal tmp: std_logic_vector(W1+W2-1 downto 0); begin tmp <= std_logic_vector(signed(multiplicand)*signed(multiplier));

product <= tmp(W1+W2-2 downto 0); end behavioral;

Signed multiplication - combinational

W1 = 16 bitsW2 = 14 bitsomode = ‘0’


Signed multiplication - sequential

Target part A3PE1500_PQFP208_-2

Clock frequency 40 MHz

Required time 24.272 ns

Propagation time 10.476 ns

Slack (critical) 13.796 ns

Number of logic level(s) 11

Core Cells 282 of 38400 (1%)

sequential 37

16 periods of system clockFor W1=16, W2=14

multipliermultiplicandproduct

startready


entity flipflop is port (clk, rst, en, d : in std_logic; q : out std_logic); end flipflop; architecture rtl of flipflop is

begin ff: process(clk) begin if rising_edge(clk) then if rst = '1' then q <= '0'; else if en = '1' then q <= d; end if; end if; end if; end process; end rtl;

Synchronous reset ensures that reset can only occur at an active clock edge.

The clock works as a filter for small reset glitches.

When a synchronous reset is being used, then both the leading and trailing edges of the reset must be away from the active edge of the clock.


Synchronizing reset


begin ff: process(clk, rst) begin if rst = '1' then q <= '0'; elsif rising_edge(clk) then

if en = '1' then q <= d; end if; end if; end process; end rtl;

Designs that are pushing the limit for data path timing, cannot afford to have added gates and additional net delays in the data path due to logic inserted to handle synchronous resets.

Using an asynchronous reset, the designer is guaranteed not to have the reset added to the data path.

Attention must be paid to the release of the reset so as to prevent the chip from going into a metastable unknown state when reset is released.


Synchronizing reset



begin ff: process(clk) begin if rising_edge(clk) then if rst = '1' then q <= '0'; else if en = '1' then q <= d; end if; end if; end if; end process; end rtl;

Synchronizing resetentity flipflop is port (clk, rst, en, d : in std_logic;

q : out std_logic); end flipflop; architecture rtl of flipflop is

begin ff: process(clk, rst) begin if rst = '1' then q <= '0'; elsif rising_edge(clk) then if en = '1' then q <= d; end if; end if; end process; end rtl;

Asynchronus Synchronus

There are about 100 sequential process blocks in the design.The transformation was done automatically by means of using a small Java program prepared by Oliver Bitterling

Hardware test-bench


PCWindowsLabView

CRATEMOTHER BOARD

DQLPU_S

USB 8451

SymQ

X SeriesUSB 6535

AO0AO1

USB

USB

USB FlashPro

JTAG

AO2

D1D2D3

AO3

D4

INTERLOCK OUTINTERLOCK IN

GNDP1.6


Delay measurementMethod: Time Edge Separation with internal hardware counter ctr0 in USB-6535 device It consists of : Generation of analogue pulse with changing

amplitude with time-width 50ms as a “magnet voltage”

Generation of simultaneous digital pulse

Acquisition of opening interlock as a digital pulse

Counting clock pulses between two rising edges of digital pulses

~50ms

ampl

0

0

1

1

Δt


inADC

thfilter

Vf

Vlt

1

Delay measurementFilter length:lfilter = 2depth = 27 = 128

Threshold voltage:Vth = 125,74 mV

Input voltage divider was modified to fit dynamical range of analogue stage to +10V ÷ -10V range available at analogue output of USB-6535.

Sampling rate of ADC:fADC = 6410 Hz


Corrector adjustment

Extreme values in the range of gain adjustment with Corrector module:

Gain G

Red + 3 458,11 1/V

Green × 3 249,28 1/V

Range of gain adjustment: ~6%

Gain of analog-digital signal chain:

G = Avd ∙ AAmp ∙ CADC ∙ SCorr

Avd Attenuation of input voltage divider 1/62,1 V/V

AAmp Amplification of input amplifier (INA and OpAmps) 10 V/V

CADC Analogue-digital conversion factor 76,3 µV/bit

SCorr Slope correction


Autozero effectivnessDeviation from 0 digital value at 0V input voltage:

Red + -2,67

Green × -1,82


ConclusionNegative: VHDL code is still wasteful. It wastes too many resources giving a trouble at each

modification. It produces still too many disturbing warnings “a simulation mismatch is possible”

during synthesis.

Positive:We have made significant progress: New components in the design (sunglass, median filter – Jens). Re-designing of many components (multiplication, circular buffer (?) - Andrzej). Correction of bugs. New test measurements.


Thank you for attention,

testing and verification of symq board for detection of symmetric quenches andrzej skoczen agh-ust,...

Documents

skoczen aghust

number of simulation

simulation andor synthesis

verification of symq

vhdl code

new test procedures

hardware testbench labview

fpga device proasic3e