testing solutions for very deep sub-micron cmos technologiestsiatouhas/data/activities.pdf ·...

11VDSM TestingVDSM Testing19991999--20032003

Testing Solutions for Very Deep Sub-Micron CMOS TechnologiesTesting Solutions for Very Deep

Sub-Micron CMOS Technologies

University of University of IoanninaIoanninaDept. of Computer ScienceDept. of Computer Science

IoanninaIoannina -- Greece

University of AthensUniversity of AthensDept. of Informatics & TelecommunicationsDept. of Informatics & Telecommunications

Athens Athens -- GreeceGreece Greece

Southern Illinois UniversitySouthern Illinois UniversityDept. of Electrical & Computer EngineeringDept. of Electrical & Computer Engineering

Carbondale Carbondale -- USAUSA

University of University of PatrasPatrasDept. of Computer Engineering & InformaticsDept. of Computer Engineering & Informatics

Rio Rio -- PatrasPatras -- GreeceGreece


Delay Testing“On-Line and Off-Line DFT Techniques”

Delay Testing“On-Line and Off-Line DFT Techniques”

• A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing – DFT 1999

•• A A Zero Aliasing BuiltZero Aliasing Built--In Self TesIn Self Test Tet Technique for Delay Fault chnique for Delay Fault TestingTesting – DFT 1999

• A Versatile Built-In Self Test Scheme for Delay Fault Testing –DATE 2000

• A Versatile Built-In Self Test Scheme for Delay Fault Testing –DATE 2000


DFT for Delay Fault TestingDFT for Delay Fault TestingDFT for Delay Fault Testing

CLEAR

Error Indication Output

Dflip-flop

ENB

CLCK

D

VDD

TPG

PIPO Register

CUT

Primary Outputs

Primary Inputs

R-CLK

N/T

G-CLK

n

nn

m

m

m

MUX

Transition DetectionCircuitry

EDFT-99


Off-Line Delay TestingOffOff--Line Delay TestingLine Delay Testing

Start of CurrentTest Phase

Application of Vi

End of ValidData Output

Responses

Capture of ViResponse

Start of ValidData Output

Responses

End of CurrentTest Phase

Application of Vi+1

Τ1 Τ2 Τ3 Τ4Valid ResponseErroneousResponse

ErroneousResponse

R-CLK

G-CLK

Test Phase

ENB

dmax

DFT-99


On-Line Delay TestingOnOn--Line Delay TestingLine Delay Testing

Τ1 Τ2 Τ3 Τ4

Valid Responses

Erroneous Response

R-CLK

NormalSystemClock

Test Phase

ENB dmax

PrimaryOutputs

Stable States

DFT-99


A Current Mode Technique for Delay TestingA Current Mode Technique for Delay TestingA Current Mode Technique for Delay Testing

. . .

CUTCUT

BICSBICS

TDUTDU

Primary Outputs

ENB

ERR

m

m

Dummy Buffers Virtual Ground

DATE - 00

TPGTPGTPG

CUTCUT

Primary Outputs

Primary Inputs

ENB

N/T

G-CLK

n

n n

m

MUXMUX

ERR TDUTDUTDU


Off-Line Delay TestingOffOff--Line Delay TestingLine Delay Testing

Test Phase

Valid Response

Erroneous Response

Τ1 Τ2

G-CLK

ENB

Start of Current Test PhaseApplication of Vj

Enable TDU

End of Valid Data Output

Enable TDU Start of Valid Data Output Responses

Disable TDU

Erroneous Response

Τ3 Τ4

Responses

End of Current Test PhaseStart of Next Test Phase

Application of Vj+1

dmax

DATE - 00


On-Line Delay TestingOnOn--Line Delay TestingLine Delay Testing

Τ1 Τ2 Τ3 Τ4Valid

ResponseErroneous Response

Erroneous Response

Detection Phase j+1

CLKENB

Start of Detection PhaseInput Ij

Enable TDU

End of Valid Data Output Responses

Start of Detection PhaseInput Ij+1

Enable TDU Start of Valid Data Output Responses

Disable TDU

Start of Valid DataOutput Responses

Disable TDU

Detection Phase j-1

DATE - 00

Detection Phase j


Concurrent Testing“Soft and Timing Error Detection

Circuits and Techniques”

Concurrent Testing“Soft and Timing Error Detection

Circuits and Techniques”

• A Hierarchical Architecture for Concurrent Soft Error Detection

Based on Current Sensing – IOLTW 2002

• A Hierarchical Architecture for Concurrent Soft Error Detection

Based on Current Sensing – IOLTW 2002

• A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs – IOLTS 2003 (subm.)

• A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs – IOLTS 2003 (subm.)


The Time Redundancy TechniqueThe Time Redundancy TechniqueThe Time Redundancy Technique

Output FFCombinational

LogicERR

OUT

CLK

FFO

Functional Circuit

IN

Monitoring Circuit

Output FFCombinational

LogicERR

OUT

CLK

FFO

Functional Circuit

IN

Monitoring Circuit


Current Mode ComparatorCurrent Mode ComparatorCurrent Mode ComparatorCurrent Mode Comparator

ERR

ENB

VDD

OUT FFO

Activation Circuit (AC)

BICSBICSSN

DTCT

ENBPreset

ErrorFF DTCT

δ

OUT

CLK

ENB

FFO

ERR

Preset ActionSensing Mode

Transient Pulse

IOLTW - 02


The Hierarchical Error Detection ArchitectureThe Hierarchical Error Detection ArchitectureThe Hierarchical Error Detection Architecture

AC11 AC1m ACnm

BICS

. . .

SN

EIFERRMultiple Lines

Current Sensing Comparator(ML-CSC)

OUT & FFOPair

ACn1

. . . . . .m m

Functional Circuit

nCM1 CMn

1st LevelActivation

2nd LevelPre-Sense

3rd LevelFinal Sense

CL1 CLn

N1 Nn

CSC_out

Cluster ofPairs

OUT11 OUTnmFFO11 FFOnmOUT1m FFO1m OUTn1 FFOn1

IOLTW - 02


Multiple Lines Current Sensing ComparatorMultiple Lines Current Sensing ComparatorMultiple Lines Current Sensing Comparator

ERR

ENB

VDD

N

ENB

EIFSN BICSBICS

Current Mirror (CM)

From the rest ACs of the cluster

From the rest CMs

IOLTW - 02

Multiple Lines Current Sensing Comparator

ML-CSC

OUT FFO

Preset

CSC_out

Activation Circuit (AC)


Sense Amplifier Based DetectorSense Amplifier Based DetectorSense Amplifier Based Detector

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .EN

EN

INLINR

EN

EN

SenseAmplifier

(SA)

ERR

FFOk

OUTk

FFOk

OUTk

MFL

MFR

MCL

MCR

SBL

SBR

RESET

SCLK

EIFFSAO

EN

VDD

VDD

Gnd

Gnd

PSB

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .

FFO1

OUT1

FFO1

OUT1

FFOk

OUTk

. . .EN

EN

INLINR

EN

EN

SenseAmplifier

(SA)

ERR

FFOk

OUTk

FFOk

OUTk

MFL

MFR

MCL

MCR

SBL

SBR

RESET

SCLK

EIFFSAO

EN

VDD

VDD

Gnd

Gnd

PSB

IOLTS - 03


Timing WaveformsTiming WaveformsTiming Waveforms

OUT

FFO

CLK

EN

ERR

Unknown Data Valid Data Erroneous Data

Set-Up

Hold

MonitoringPhase

Set-Up

Hold

MonitoringPhase

Error Free Error Present

FFO = OUT FFO ≠ OUT

δmax

dmax

Normal Phase Normal PhaseNormal Phase

OUT

FFO

CLK

EN

ERR

Unknown Data Valid Data Erroneous Data

Set-Up

Hold

MonitoringPhase

Set-Up

Hold

MonitoringPhase

Error Free Error Present

FFO = OUT FFO ≠ OUT

δmax

dmax

Normal Phase Normal PhaseNormal Phase

IOLTS - 03


Detection Time vs Monitored PairsDetection Time Detection Time vs vs Monitored PairsMonitored Pairs

100

150

200

250

300

350

400

450

500

0 100 200 300 400 500 600

Monitore d Pa irs

Det

ectio

n Ti

me

IOLTS - 03


IDDQ Testing“The Challenge of VDSM Technologies”

IDDQ Testing“The Challenge of VDSM Technologies”

• Extending the Viability of IDDQ Testing in the Deep SubmicronEra – ISQED 2002

•• Extending the Viability of IExtending the Viability of IDDQDDQ Testing in the DeepTesting in the Deep SubmicronSubmicronEra Era – ISQED 2002

• An Embedded IDDQ Testing Architecture and Technique – ISQED 2003

• An Embedded IDDQ Testing Architecture and Technique – ISQED 2003


Background Current CompensationBackground Current CompensationBackground Current Compensation

T_EN

Vdd

Fault IndicationOutput

Gnd

EN

Gnd

Vdd

LeakageCompensator

IB IDEF

BCCBCCBICSBICS

CUTCUT ITH

Higher Current ResolutionITH as low as BICS and/or BCC permit

Higher Current ResolutionITH as low as BICS and/or BCC permit

ISQED - 02


The BCC Based IDDQ Testing TechniqueThe BCC Based IThe BCC Based IDDQDDQ Testing TechniqueTesting Technique

Vdd

Fault IndicationOutput R

BICSR

Gnd

ENRT_EN

IBR

BCCBCC

Vdd

BICSL

Gnd

ENL T_EN

Fault IndicationOutput L

Vdd

CurrentMirror

AmplifierL to R

MIR_L_to_R

Gnd

CurrentMirror

AmplifierR to L

MIR_R_to_L

Gnd

Vdd

IBL =βR IBR

IBL IBR =βL IBL

sub-CUTL sub-CUTR

ISQED - 02


Power Supply DistributionPower Supply DistributionPower Supply Distribution

BCC & BICSs

CUTCUT

T_ENT_EN

V_GndRV_GndL

sub-CUTL sub-CUTR

GndISQED - 02


Multiple Current Sink BCC ImplementationMultiple Current Sink BCC ImplementationMultiple Current Sink BCC Implementation

0 1 0Scan RegisterScan Register

SEL1 SEL2 SELn

1

SEL1 SEL2

T_EN

MIR_L_to_R

Background Current

from sub-CUTR

SELn

W1/L Wn/LW2/L

IBRβL2 IBLIDEF

•• IEEE 1149.1IEEE 1149.1•• IEEE P1500IEEE P1500•• VSIA TST 2 1.0VSIA TST 2 1.0

Background Current

from sub-CUTL

IBL To the BICSR

Current Current MirrorMirror

AmplifierAmplifier ISQED - 02Gnd


Embedded IDDQ TestingEmbedded IEmbedded IDDQDDQ TestingTesting

SCUT 1SCUT 1 SCUT 2SCUT 2 SCUT nSCUT n. . .

VDD

CUT

Pass / Fail

IDDQ RegisterScan In

BICSBICSSDFFSDFF

T/N1 T/N1

VSS

DDDecoder

ENB

T/Nn T/Nn

VSS

T/N2 T/N2

VSS

T/N1 T/N2 T/Nn

VSS

SL

MSL

MN1 MT1 MN2 MNnMT2 MTn. . .

SelectCircuitryVirtual Grounds

REF

ISQED - 03


IEEE 1149.1 Based IDDQ Testing ArchitectureIEEE 1149.1 Based IIEEE 1149.1 Based IDDQDDQ Testing ArchitectureTesting Architecture

CUT

IR Register

Decode LogicTDI

Dev. ID Register

BICSBICS SDFFSDFF

DD

BypassBypass

IDDQ Register

Decoder

TAPController

FFFFENB

Shift_IRClock_IRUpdate_IRReset

Shift_DRClock_DRUpdate_DRRun_Test

TDO

TCK

TMS

TRST

MUX-1

MUX-2

PI PO

....B

SR

BSR

ISQED - 03


IDDQ Testing Flow DiagramIIDDQDDQ Testing Flow DiagramTesting Flow DiagramS T A R T

S c a n - I nT e s t V e c t o r

S c a n - I nI D D Q R e g i s t e r

I D D QS e n s in g

A n o t h e r S C U T ?

A n o t h e r T e s tV e c t o r ?

E N D

Y e s

Y e s

N o

N o

S c a n - O u tS D F F

ISQED - 03


Power Supply DistributionPower Supply DistributionPower Supply Distribution

VSS

CUTCUT

<T/Ni

BICS IEEE 1149.1

. . .

SCUT1

SCUT2

SCUTn

VDD

SL

REF

PASS/FAIL

ENB

SelectCircuitry

TDI TCK TMS TDO

TRST

T/Ni>

MSL

MT2 MN2

MT1 MN1

MTn MNn

ISQED - 03


Memory Testing“The Neighborhood Pattern Sensitive Fault Model”

Memory Testing“The Neighborhood Pattern Sensitive Fault Model”

• A Test Pattern Generation Unit for Memory NPSF Built-In Self Test – ICECS 2000

• A Test Pattern Generation Unit for Memory NPSF Built-In Self Test – ICECS 2000


A Deterministic TPG UnitA Deterministic TPG UnitA Deterministic TPG Unit

ControlCircuitry Gray Counter

Rotate

Submit

ParallelLoad

R_Rot

MSB LSB

P_LoadRot

Update

5

5

EndClk

Reset

TPG

ICECS - 00


FPGA ImplementationFPGA ImplementationFPGA Implementation

ICECS - 00

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