testing4.pdf
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Jan 25, 2008 E0-286@SERC 1
VLSI Testing Fault Simulation
VLSI Testing Fault Simulation
Virendra SinghIndian Institute of Science
E0 286: Test & Verification of SoC Design
Lecture - 4
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Fault Model - SummaryFault Model - Summary
Fault models are analyzable approximations of defects and are essential for a test methodology.For digital logic single stuck-at fault model offers best advantage of tools and experience.Many other faults (bridging, stuck-open and multiple stuck-at) are largely covered by stuck-at fault tests.Stuck-short and delay faults and technology- dependent faults require special tests.Memory and analog circuits need other specialized fault models and tests.
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Fault Simulation
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Simulation DefinedSimulation DefinedDefinition: Simulation refers to modeling of a design, its function and performance.A software simulator is a computer program; an emulator is a hardware simulator.Simulation is used for design verification:
Validate assumptionsVerify logicVerify performance (timing)
Types of simulation:Logic or switch levelTimingCircuitFault
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Simulation for VerificationSimulation for Verification
True-valuesimulation
Specification
Design(netlist)
Input stimuliComputedresponses
Responseanalysis
Synthesis
Designchanges
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Modeling LevelsModeling Levels
Circuitdescription
Programminglanguage-like HDL
Connectivity ofBoolean gates,flip-flops andtransistors
Transistor sizeand connectivity,node capacitances
Transistor technologydata, connectivity,node capacitances
Tech. Data, active/passive componentconnectivity
Signalvalues
0, 1
0, 1, Xand Z
0, 1and X
Analogvoltage
Analogvoltage,current
Timing
Clockboundary
Zero-delayunit-delay,multiple-delay
Zero-delay
Fine-graintiming
Continuoustime
Modelinglevel
Function,behavior, RTL
Logic
Switch
Timing
Circuit
Application
Architecturaland functionalverification
Logicverificationand test
Logicverification
Timingverification
Digital timingand analogcircuitverification
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True-Value Simulation Algorithms
True-Value Simulation Algorithms
Compiled-code simulationApplicable to zero-delay combinational logicAlso used for cycle-accurate synchronous sequential circuits for logic verificationEfficient for highly active circuits, but inefficient for low-activity circuitsHigh-level (e.g., C language) models can be used
Event-driven simulationOnly gates or modules with input events are evaluated (event means a signal change)Delays can be accurately simulated for timing verificationEfficient for low-activity circuitsCan be extended for fault simulation
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Compiled-Code AlgorithmCompiled-Code Algorithm
Step 1: Levelize combinational logic and encode in a compilable programming languageStep 2: Initialize internal state variables (flip-flops)Step 3: For each input vector Set primary input variables Repeat (until steady-state or max. iterations)
Execute compiled code Report or save computed variables
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Event-Driven AlgorithmEvent-Driven Algorithm
2
2
4
2
a =1
b =1
c =1 0
d = 0
e =1
f =0
g =1
Time, t0 4 8
g
t = 0
1
2
3
4
5
6
7
8
Scheduledevents
c = 0
d = 1, e = 0
g = 0
f = 1
g = 1
Activitylist
d, e
f, g
g
Tim
e st
ack
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Time Wheel (Circular Stack)Time Wheel (Circular Stack)
t=01
2
3
4
56
7
maxCurrenttimepointer Event link-list
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Efficiency of Event- driven Simulator
Efficiency of Event- driven Simulator
Simulates events (value changes) onlySpeed up over compiled-code can be ten times or more; in large logic circuits about 0.1 to 10% gates become active for an input change
Large logicblock without
activity
Steady 0
0 to 1 event
Steady 0(no event)
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Problem and MotivationProblem and Motivation
Fault simulation Problem: GivenA circuitA sequence of test vectorsA fault model
DetermineFault coverage - fraction (or percentage) of modeled faults detected by test vectorsSet of undetected faults
MotivationDetermine test quality and in turn product qualityFind undetected fault targets to improve tests
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Fault simulator in a VLSI Design Process
Fault simulator in a VLSI Design Process
Verified designnetlist
Verificationinput stimuli
Fault simulator Test vectors
Modeledfault list
Testgenerator
Testcompactor
Faultcoverage
?
Remove tested faults
Deletevectors
Add vectorsLow
AdequateStop
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Fault Simulation ScenarioFault Simulation Scenario
Circuit model: mixed-levelMostly logic with some switch-level for high-impedance (Z) and bidirectional signalsHigh-level models (memory, etc.) with pin faults
Signal states: logicTwo (0, 1) or three (0, 1, X) states for purely Boolean logic circuitsFour states (0, 1, X, Z) for sequential MOS circuits
TimingZero-delay for combinational and synchronous circuitsMostly unit-delay for circuits with feedback
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Fault Simulation ScenarioFault Simulation Scenario
FaultsMostly single stuck-at faultsSometimes stuck-open, transition, and path-delay faults; analog circuit fault simulators are not yet in common useEquivalence fault collapsing of single stuck-at faultsFault-dropping -- a fault once detected is dropped from consideration as more vectors are simulated; fault-dropping may be suppressed for diagnosisFault sampling -- a random sample of faults is simulated when the circuit is large
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Fault Simulation AlgorithmsFault Simulation Algorithms
Serial
Parallel
Deductive
Concurrent
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Serial AlgorithmSerial AlgorithmAlgorithm: Simulate fault-free circuit and save responses. Repeat following steps for each fault in the fault list:
Modify netlist by injecting one faultSimulate modified netlist, vector by vector, comparing responses with saved responsesIf response differs, report fault detection and suspend simulation of remaining vectors
Advantages:Easy to implement; needs only a true-value simulator, less memoryMost faults, including analog faults, can be simulated
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Serial AlgorithmSerial Algorithm
Disadvantage: Much repeated computation; CPU time prohibitive for VLSI circuitsAlternative: Simulate many faults together
Test vectors Fault-free circuit
Circuit with fault f1
Circuit with fault f2
Circuit with fault fn
Comparator f1 detected?
Comparator f2 detected?
Comparator fn detected?
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Parallel Fault SimulationParallel Fault Simulation
Compiled-code method; best with two-states (0,1)Exploits inherent bit-parallelism of logic operations on computer wordsStorage: one word per line for two-state simulationMulti-pass simulation: Each pass simulates w-1 new faults, where w is the machine word lengthSpeed up over serial method ~ w-1Not suitable for circuits with timing-critical and non-Boolean logic
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Parallel Fault SimulationParallel Fault Simulation
a
b c
d
e
f
g
1 1 1
1 1 1 1 0 11 0 1
0 0 0
1 0 1
s-a-1
s-a-0
0 0 1
c s-a-0 detected
Bit 0: fault-free circuitBit 1: circuit with c s-a-0
Bit 2: circuit with f s-a-1
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Thank YouThank You