Th4H.1.pdf OFC 2016 © OSA 2016

Monolithic Silicon Photonics at 25 Gb/s

J. S. Orcutt1, D. M. Gill

1, J. Proesel

1, J. Ellis-Monaghan

2#, F. Horst

3, T. Barwicz

1, C. Xiong

1, F. G. Anderson

2#,

A. Agrawal1, Y. Martin

1, C. W. Baks

1, M. Khater

1, J. C. Rosenberg

1, W. D. Sacher

1, J. Hofrichter

3†, E. Kiewra

1,

A. D. Stricker1, F. Libsch

1, B. Offrein

3, M. Meghelli

1, N. B. Feilchenfeld

2#, W. Haensch

1, W. M. J. Green

1

1IBM Research, 1101 Kitchawan Road, Yorktown Heights, New York 10598, USA 2IBM Systems & Technology Group, Microelectronics Division, 1000 River St., Essex Junction, Vermont 05452, USA

3IBM Research GmbH, Säumerstrasse 4, CH-8803 Rüeschlikon, Switzerland #currently at GLOBALFOUNDRIES, Essex Junction, Vermont 05452, USA

†currently at ams International AG, Rapperswil, Switzerland

jsorcutt@us.ibm.com

Abstract: Monolithic CMOS photonics seeks to minimize total transceiver cost by simplifying

packaging, design and test. Here we examine 25 Gb/s applications in the context of integrated

transistor performance and demonstrate a 4λx25 Gb/s reference design. OCIS codes: (230.3120) Integrated optics devices; (230.2090) Electro-optical devices

1. Introduction

Silicon photonics has been the subject of wide development as an enabling technology to reduce the cost for 100

Gb/s and above Datacom transceivers. The high yield, large wafer size and existing CMOS toolset enables the

silicon photonic die to be manufactured at low cost. However, the total cost of the transceiver is then dominated by

the cost of other items in the bill of materials, such as laser sources, in addition to the packaging cost.

It is the problem of total transceiver cost minimization that has motivated the development of a monolithic

CMOS photonic platform, labeled as CMOS9WG, that includes passively-aligned fiber attach structures, e-fuse non-

volatile programmability and monolithic electronics to minimize bill of material and assembly costs [1]. This

technology is centered around the O-band wavelength window for datacom applications. A variety of integrated

field effect transistor (FET) options target diverse application needs from 1.2 V to 3.3 V operating supplies. ESD-

protection devices and a digital synthesis library are included to enable full digital system functionality.

The practicality of single-chip transceivers is coarsely dependent on the ratio of the transistor unity current gain

frequency, fT, to the operating line rate. Product-level solutions in the 10 Gb/s parallel-single mode space have been

demonstrated in prior monolithic CMOS work [2]. The monolithic CMOS9WG photonics platform, based upon a

55 nm physical gate length transistor technology with RF-CMOS enhancements, offers improved performance at 10

Gb/s line rates. Further, thermally-tuned coarse wavelength division multiplexing (CWDM) components enable

compliance with advanced transceiver standards. In this work, we examine the suitability of the CMOS9WG

platform for 25 Gb/s line rate applications and present a 4 λ x 25 Gb/s reference design. We will review impacts of

the technology from the perspectives of packaging, transmitter and receiver performance.

2. Packaging impacts

Given that the transceiver module cost for moderate scale silicon photonic transceivers is dominated by packaging,

technology choices must be driven by minimizing packaging costs. To this end, a passively self-aligned fiber-attach

technology has been developed [3] using metamaterial spot-size converters to interface between standard single-

mode fiber and on-chip waveguides. These wafer-integrated packaging structures address the traditional optical

packaging cost drivers where active alignment is typically used to achieve the required micron-scale precision.

The electrical packaging and subsystem integration for transceiver applications is also greatly simplified by

monolithic silicon photonic technology. In wafer-level functional test, full transceiver functionality can be verified

to enable known good die packaging. Integrated e-fuse programmability enables test parameters to determine

operating characteristics of the transceiver to improve yield and performance. The electrical signal routing in the

package is also greatly simplified. The only high speed or analog signals are the input and output data lines. In more

traditional hybrid-integrated silicon photonic transceiver implementations [4,5], all bias point monitoring, power

monitoring, heater control signal, laser bias, and digital communication interface signal routing must be addressed

by the packaging solution. By containing this complexity within a die, not only can the packaging cost be reduced

but also the design functionality can be verified within a single simulation tool set and CAD environment.

3. Transmitter performance

Monolithic transmitters for 25 Gb/s applications have been developed by combining the traditional RF-CMOS

elements with depletion-mode pn-junction phase shifter waveguides to form a travelling wave Mach-Zehnder

modulator (MZM). All supporting blocks of the driver and modulator system are also monolithically integrated,

including AC and DC optical bias-point monitoring and adjustment. The monolithic driver can output up to 1.15

Vpp/MZM arm at 25 Gb/s as shown in Figs. 1(a,b). The resulting relative transmitter penalty [6] is determined by

Th4H.1.pdf OFC 2016 © OSA 2016

the voltage-dependent figure-of-merit (FOM) and limited modulation extinction ratio as shown in Figs. 1(c,d). If

alternative transistor technology was utilized by hybrid integration to increase the drive voltage to 2 Vpp/MZM arm

with this MZM FOM, the relative transmitter penalty could be reduced by approximately 1.5 dB at the expense of

significantly complicating packaging, system design, interface parasitics, yield, and functional test. Fig. 1(d) shows

the baseline design gives < 0.3 dB penalty compared to a drive-optimized design, whose length depends on TX Vpp.

Figure 1: (a,b) Monolithic driver 25.8 Gb/s electrical output into 50 Ω as a function of bias strength settings for a 0.35 Vppd

input data signal. (c) MZM FOM as a function of voltage. (d) Relative transmitter penalty as a function of driver output

voltage for the baseline monolithic design length (3 mm/MZM arm) and for drive-voltage optimized lengths.

4. Receiver performance

The monolithic receiver is enabled by a p-i-n germanium photodetector fabricated by rapid melt regrowth. In this

process, the germanium is deposited by PECVD, encapsulated, and recrystallized by the source-drain anneal. Design

optimization has enabled the high-yield fabrication of a photodiode with < 1 µA leakage across temperature and

>0.55 A/W responsivity across O-band wavelengths at -0.8V bias [1].

Figure 2: (a) Schematic representation of relevant receiver components. Transistor performance is approximated by a weighted

average of NMOS and PMOS as fT,eff to study impact on input referred current noise .(b) Relative receiver performance as a

function of transistor technology (node designations approximate) and integration parasitics relative to CMOS9WG technology.

The photodiode capacitance is modelled by a 10 fF junction capacitance and 3 fF wiring capacitance in the

design kit based on the fits of 2-port s-parameter measurements. This low photodetector capacitance can be directly

leveraged by the low parasitic interface on low metal routing layers to the monolithic CMOS transistors. Hybrid

integration allows the significant advantage of freedom-of-choice for the transistor technology, but introduces

parasitic capacitance associated with vias from front-end to top-metal, top-metal pad capacitance from both chips,

capacitance associated with interfacial connection, and ESD-protection capacitance if required for manufacturing

yield. To understand the tradeoff between front-end parasitic capacitance and transistor speed for a coarse

comparison of hybrid and monolithic integration approaches, the scaling of noise for an optimized transimpedance

amplifier design can be studied as a function of relevant technology parameters. Adapting prior analysis [7], the

minimized input-referred current noise, , is roughly proportional to + , . The total receiver

performance scaling for various packaging technologies can then be calculated as a function of transistor

technology, and be compared relative to CMOS9WG as shown in Fig. 2(b).

(a)

(b)

(c) (d)

0.6 1 1.4 1.8 2.2 2.6 3-8

-7

-6

-5

-4

-3

-2

TX Drive Voltage (Vpp/MZM arm)

Re

lative

Tra

nsm

itte

r P

en

alty (

dB

)

Drive-optimized lengths

Baseline 3 mm length

0.6 1 1.4 1.8 2.2 2.6 313

14

15

16

TX Drive Voltage (Vpp/MZM arm)

Fig

ure

-of-

Me

rit (V

-dB

)

1.6 Vppd

2.3 Vppd

100% strength

50% strength

MZM bias = - (TX Vpp Drive/2)

(a)

100GHz

65nm 45nm

200GHz

32nm 14nm

300GHz

1

1.5

2

Transistor fT,eff

(frequency or node)

Rela

tive I

nput-

Refe

rred N

ois

e(b)

CMOS9WG

Cpd

Cinterface fT,eff

fT,eff

in

photodiode &interface parasitics receiver front end

Th4H.1.pdf OFC 2016 © OSA 2016

5. 4 x 25 Gb/s monolithic reference design demonstration

To demonstrate 25 Gb/s transmitter and receiver functionality in the monolithic CMOS photonic platform, a 4 λ x 25

Gb/s CWDM reference design has been fabricated and tested. The initial demonstration has been carried out in a

loopback characterization chip shown in Fig. 3(a). Optical component and interface circuit design variants in each of

the four CWDM channels are interconnected by the thermally-tuned optical path that includes the fiber-coupled

transceiver polarization management components. The design was verified by full-chip electro-optic layout-vs-

schematic verification and the data path was simulated with complete post-layout extracted parasitics by utilizing

hardware verified electro-optic device models in the CMOS9WG alpha-level process design kit (PDK). The unified

design environment has enabled the successful fabrication of the complete electro-optic transceiver system as

demonstrated by error-free data transmission at 25 Gb/s for PRBS 231

-1 data patterns. Input light was provided by

vertical grating couplers after electrical-only packaging to enable single-channel testing. Eye diagrams for all

channels are shown in Figs. 3(b-i) at 25 Gb/s. The channels differ by a design skew on MZM, PD and RX elements.

Figure 3: (a) Labelled die micrograph for 4 x 25 Gb/s reference design. White overlay depicts integrated electro-optic elements

(PSR = polarization splitter rotator, PD = photodiode). Black boxes denote CMOS functional blocks. (b-i) 25 Gb/s differential

eye diagrams for the electrical-optical-electrical links achieved by thermally tuning wavelength mux and demux blocks.

6. Conclusions

The monolithic transceiver implementation has significant advantages over alternative combinations of electro-optic

device, packaging and transistor technology. Integration of supporting blocks along with the datapath simplifies

design, verification and test while reducing cost. Alternative transistor technology can also be utilized in various

multi-chip and hybrid integration implementations to expand functionality or optimize application performance. For

applications that require high digital content, such as clock data recovery (CDR), separate retimer chips may be

leveraged for improved power efficiency. For high link loss applications, reduced transmitter penalty can be enabled

by higher voltage drivers. Such systems can still benefit from the monolithic platform by integrating supporting

blocks and self-test while optimally partitioning transceiver functionality for a given link application’s needs.

Acknowledgements: The authors are grateful for support from the IBM Microelectronics Technology

Development, Manufacturing Engineering, and PDK Enablement Teams, as well as from the IBM Microelectronics

Research Laboratory and Central Scientific Services. Tim Buchholtz, Ladd Freitag, Ray Richetta, Matt Frank, and

the IBM Rochester team are recognized for their contributions to the development of the reference design.

[1] N. Feilchenfeld et al., “An integrated silicon photonics technology for O-band datacom,” IEDM 2015, paper 25.7.

[2] C. Gunn, “CMOS photonics for high-speed interconnects,” IEEE Micro 26, 58-66 (2006).

[3] T. Barwicz et al., “An O-band metamaterial converter interfacing standard optical fibers to silicon…,” OFC 2015 paper Th3F.3.

[4] D. Feng, B. J. Luff, S. Jatar and M. Asghari, “Micron-scale silicon photonic devices and circuits,” OFC 2014, paper Th4C.1.

[5] F. Boeuf et al., “Recent progress in silicon photonics R&D and manufacturing on 300mm wafer platform,” OFC 2015, paper W3A.1.

[6] D. M. Gill et al., “Demonstration of a high extinction ratio monolithic CMOS integrated nanophotonic…,” IEEE JSTQE 21, 1-11 (2015).

[7] E. Sackinger, “On the noise optimum of FET broadband transimpedance amplifiers,” IEEE Trans. Circuits Syst. I 59, 2881-2889 (2012).