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1 Confidential 1 1 The ARM Architecture 2 2 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA Development Tools

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Page 1: The ARM Architecture - University of Florida · 1 Confidential 1 The ARM Architecture 2 Agenda Introduction to ARM Ltd ARM Architecture/Programmers Model Data Path and Pipelines AMBA

1Confidential

11

The ARM Architecture

222

AgendaIntroduction to ARM LtdARM Architecture/Programmers ModelData Path and PipelinesAMBADevelopment Tools

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ARM Ltd

Founded in November 1990Spun out of Acorn Computers

Designs the ARM range of RISC processor coresLicenses ARM core designs to semiconductor partners who fabricate and sell to their customers.

ARM does not fabricate silicon itself

Also develop technologies to assist with the design-in of the ARM architecture

Software tools, boards, debug hardware, application software, bus architectures, peripherals etc

444

ARM’s Activities

memorymemory

SoCSoC

ProcessorsSystem Level IP:Data EnginesFabric3D Graphics

Physical IP

Software IP

Development Tools

Connected Community

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555

ARM Partnership Model

666

ARM Powered Products

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How many ARM processors?

88

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AgendaIntroduction to ARM LtdARM Architecture/Programmers ModelData Path and PipelinesAMBADevelopment Tools

101010

Architecture Revisions

1998 2000 2002 2004time

vers

ion

ARMv5

ARMv6

1994 1996 2006

V4

StrongARM®ARM926EJ-S™

XScaleTMARM102xE ARM1026EJ-S™

ARM9x6EARM92xT

ARM1136JF-S™

ARM7TDMI-S™

ARM720T™

XScale is a trademark of Intel Corporation

ARMv7

SC100™

SC200™

ARM1176JZF-S™

ARM1156T2F-S™

Cortex A8™

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111111

Cortex family

Cortex-A8Architecture v7AMMUAXIVFP & NEON support

Cortex-R4Architecture v7RMPU (optional)AXI Dual Issue

Cortex-M3Architecture v7MMPU (optional)AHB Lite & APB

121212

Data Sizes and Instruction SetsThe ARM is a 32-bit architecture.

When used in relation to the ARM:Byte means 8 bitsHalfword means 16 bits (two bytes)Word means 32 bits (four bytes)

Most ARM’s implement two instruction sets32-bit ARM Instruction Set16-bit Thumb Instruction Set

Jazelle cores can also execute Java bytecode

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ARM and Thumb Performance

Memory width (zero wait state)

0

5000

10000

15000

20000

25000

30000

32-bit 16-bit 16-bit with32-bit stack

ARMThumb

Dhrystone 2.1/sec@ 20MHz

141414

Processor ModesThe ARM has seven basic operating modes:

User : unprivileged mode under which most tasks run

FIQ : entered when a high priority (fast) interrupt is raised

IRQ : entered when a low priority (normal) interrupt is raised

Supervisor : entered on reset and when a Software Interrupt instruction is executed

Abort : used to handle memory access violations

Undef : used to handle undefined instructions

System : privileged mode using the same registers as user mode

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151515

r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

FIQ IRQ SVC Undef Abort

User Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

Current Visible Registers

Banked out Registers

FIQ IRQ SVC Undef Abort

r0

r1

r2

r3

r4

r5

r6

r7

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

Current Visible Registers

Banked out Registers

User IRQ SVC Undef Abort

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

FIQ ModeIRQ Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

Current Visible Registers

Banked out Registers

User FIQ SVC Undef Abort

r13 (sp)

r14 (lr)

Undef Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

Current Visible Registers

Banked out Registers

User FIQ IRQ SVC Abort

r13 (sp)

r14 (lr)

SVC Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

Current Visible Registers

Banked out Registers

User FIQ IRQ Undef Abort

r13 (sp)

r14 (lr)

Abort Mode r0

r1

r2

r3

r4

r5

r6

r7

r8

r9

r10

r11

r12

r15 (pc)

cpsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r13 (sp)

r14 (lr)

spsr

r8

r9

r10

r11

r12

r13 (sp)

r14 (lr)

spsr

Current Visible Registers

Banked out Registers

User FIQ IRQ SVC Undef

r13 (sp)

r14 (lr)

The ARM Register Set

161616

Vector Table

Exception Handling

When an exception occurs, the ARM:Copies CPSR into SPSR_<mode>Sets appropriate CPSR bits

Change to ARM stateChange to exception mode Disable interrupts (if appropriate)

Stores the return address in LR_<mode>Sets PC to vector address

To return, exception handler needs to:Restore CPSR from SPSR_<mode>Restore PC from LR_<mode>

This can only be done in ARM state.Vector table can be at

0xFFFF0000 on ARM720Tand on ARM9/10 family devices

FIQIRQ

(Reserved)Data Abort

Prefetch AbortSoftware Interrupt

Undefined Instruction

Reset

0x1C0x18

0x14

0x100x0C

0x08

0x04

0x00

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Program Status Registers

Condition code flagsN = Negative result from ALU Z = Zero result from ALUC = ALU operation Carried outV = ALU operation oVerflowed

Sticky Overflow flag - Q flagArchitecture 5TE/J onlyIndicates if saturation has occurred

J bitArchitecture 5TEJ onlyJ = 1: Processor in Jazelle state

Interrupt Disable bits.I = 1: Disables the IRQ.F = 1: Disables the FIQ.

T BitArchitecture xT onlyT = 0: Processor in ARM stateT = 1: Processor in Thumb state

Mode bitsSpecify the processor mode

2731

N Z C V Q

28 67

I F T mode

1623 815 5 4 024

f s x c

U n d e f i n e dJ

181818

ARM instructions can be made to execute conditionally by postfixing them with the appropriate condition code field.

This improves code density and performance by reducing the number of forward branch instructions.

CMP r3,#0 CMP r3,#0BEQ skip ADDNE r0,r1,r2ADD r0,r1,r2

skip

By default, data processing instructions do not affect the condition code flags but the flags can be optionally set by using “S”. CMP does not need “S”.

loop…SUBS r1,r1,#1BNE loop if Z flag clear then branch

decrement r1 and set flags

Conditional Execution and Flags

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191919

Load/Store

Miscellaneous

Classes of Instructions (v4T)

Data Operations

MOV PC, RmBccBLBLX

Change of Flow

202020

Branch : B{<cond>} label

Branch with Link : BL{<cond>} subroutine_label

The processor core shifts the offset field left by 2 positions, sign-extends it and adds it to the PC

± 32 Mbyte rangeHow to perform longer branches?

2831 24 0

Cond 1 0 1 L Offset

Condition field

Link bit 0 = Branch1 = Branch with link

232527

Branch instructions

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Data processing InstructionsConsist of :

Arithmetic: ADD ADC SUB SBC RSB RSC

Logical: AND ORR EOR BIC

Comparisons: CMP CMN TST TEQ

Data movement: MOV MVN

These instructions only work on registers, NOT memory.

Syntax:

<Operation>{<cond>}{S} Rd, Rn, Operand2

Comparisons set flags only - they do not specify RdData movement does not specify RnSecond operand is sent to the ALU via barrel shifter.

222222

Register, optionally with shift operationShift value can be either be:

5 bit unsigned integerSpecified in bottom byte of another register.

Used for multiplication by constant

Immediate value8 bit number, with a range of 0-255.

Rotated right through even number of positions

Allows increased range of 32-bit constants to be loaded directly into registers

Result

Operand 1

BarrelShifter

Operand 2

ALU

Using a Barrel Shifter:The 2nd Operand

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Single register data transferLDR STR WordLDRB STRB ByteLDRH STRH HalfwordLDRSB Signed byte loadLDRSH Signed halfword load

Memory system must support all access sizes

Syntax:LDR{<cond>}{<size>} Rd, <address>STR{<cond>}{<size>} Rd, <address>

e.g. LDREQB

242424

AgendaIntroduction to ARM LtdARM Architecture/Programmers Model Data Path and PipelinesAMBADevelopment Tools

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252525

Multiplier

The ARM7TDM Core

InstructionDecoder

AddressIncrementer

nRESET

nMREQSEQ

ABORT

nIRQnFIQ

nRWMAS[1:0]

LOCK

nCPICPACPB

nWAITMCLK

nOPC

BIGEND

ISYNC

nTRANS

nM[4:0]

D[31:0]

BarrelShifter

32 Bit ALU

DBE

Write Data Register

Read Data Register

Address Register

Register Bank

A[31:0]ABE

and

Control Logic

PC Update

Decode Stage

Instruction Decompression

Incrementer

PC

A

B

u

s

B

B

u

s

A

L

U

B

u

s

262626

Pipeline changes for ARM9TDMI

InstructionFetch Shift + ALU Memory

AccessReg

WriteRegRead

RegDecode

FETCH DECODE EXECUTE MEMORY WRITE

ARM9TDMIARM or Thumb

Inst Decode

Reg Select

RegRead Shift ALU Reg

WriteThumb→ARMdecompress

ARM decodeInstructionFetch

FETCH DECODE EXECUTE

ARM7TDMI

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ARM10 vs. ARM11 Pipelines

ARM11

Fetch1

Fetch2 Decode Issue

Shift ALU Saturate

Writeback

MAC1

MAC2

MAC3

AddressData

Cache1

DataCache

2

Shift + ALU MemoryAccess Reg

Write

FETCH DECODE EXECUTE MEMORY WRITE

Reg Read

Multiply

BranchPrediction

InstructionFetch

ISSUE

ARM or Thumb

InstructionDecode Multiply

Add

ARM10

282828

AgendaIntroduction to ARM LtdARM Architecture/Programmers ModelData Path and PipelinesAMBADevelopment Tools

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High PerformanceARM processor

High-bandwidthon-chip RAM

HighBandwidth

ExternalMemoryInterface

DMABus Master

APBBridge

Keypad

UART

PIO

TimerAHB

APB

High PerformancePipelinedBurst SupportMultiple Bus Masters

Low PowerNon-pipelinedSimple Interface

An Example AMBA System

303030

HWDATA

Arbiter

Decoder

Master#1

Master#3

Master#2

Slave#1

Slave#4

Slave#3

Slave#2

Address/Control

Write Data

Read Data

HADDRHWDATA

HRDATA

HADDR

HRDATA

AHB Structure

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AgendaIntroduction to ARM LtdARM Architecture/Programmers ModelData Path and PipelinesAMBADevelopment Tools

323232

ARM Debug Architecture

ARMcore

ETM

TAPcontroller

Trace PortJTAG port

Ethernet

Debugger (+ optionaltrace tools)

EmbeddedICE LogicProvides breakpoints and processor/system access

JTAG interface (ICE)Converts debugger commands to JTAG signals

Embedded trace Macrocell (ETM)Compresses real-time instruction and data access traceContains ICE features (trigger & filter logic)

Trace port analyzer (TPA)Captures trace in a deep buffer

EmbeddedICELogic

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Keil Development Tools for ARM

Includes ARM macro assembler, compilers (ARM RealView C/C++ Compiler, Keil CARM Compiler, or GNU compiler), ARM linker, Keil uVision Debugger and Keil uVision IDEKeil uVision Debugger accurately simulates on-chip peripherals (I2C, CAN, UART, SPI, Interrupts, I/O Ports, A/D and D/A converters, PWM, etc.)Evaluation Limitations

16K byte object code limitationSome linker restrictions such as base addresses for code/constantsGNU tools provided are not restricted in any way

http://www.keil.com/demo/

343434

Keil Development Tools for ARM

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