The Bit-Banger USB to I2C bridge

Circuit Cellar Design 2K Contest

Entry #D2K127

Overview The BitBanger board and device driver provide a simple method to quickly interface a wide variety of I2C components to a Windows 98 P.C. through a USB port.

The design consists of the USB to I2C bridge hardware (BitBanger Board), and a Windows 98 compatible WDM device driver (BitBang.Sys).

An example Visual Basic application (BitBanger.Exe) is also provided to demonstrate how to communicate with the driver and hardware. The I2C functionality is demonstrated with a simple circuit which provides 16 bits of digital I/O. The 16 bits can be read and written from within the BitBanger.exe example application.

There are many components available that incorporate I2C control interfaces, including eeproms, rams, DACs, ADC’s, multiplexers, digital I/O, USB, etc.

Almost any combination of the currently available I2C components could be controlled by the BitBanger.

Usage The BitBanger is primarily intended for use by technical people such as hardware engineers, software engineers, and electronics hobbyist.

DEVICE #1I2C

BIT-BANGERHOSTP.C.

USB

78LPC764uCONTROLLER

PDIUSBD11I2C/USBINTERFACE

16 BIT I/O

I2C

EXPANDER

PCF8575

I2C

MOREDEVICES

DEVICE #2

I2C

24LC12816KBEEPROM

Date: June 29, 2000 Sheet 2 of 3

Size Document Number REV

A d2k127\cpu.sch A

Title

87LPC764 OTP MICROCONTROLLER

Entry # DK127

Design2k Contest

12345

J1I2C

SCL

Vi2c

2 1

3

JP1I2C PWR

R13.3K

R23.3K

R33.3K

Vdd

+3.3V

nIRQ

PRGCLK

SUSPEND

P1.5/RESET 4

P1.1/RXD 11P1.0/TXD 12

P2.1/X1 6

P2.0/X2 7

P0.0/CMP2 1P0.1/CIN2B 20P0.2/CIN2A 19P0.3/CIN1B 18

VSS 5

VDD 15

P1.7 2 P1.6 3

P1.4/INT1 8

P1.3/SDA 9P1.2/SCL 10

P0.6/CMP1 14

P0.5/CMPREF 16

P0.4/CIN1A 17

P0.7/T1 13

U187LPC764

PRGCLK

nIRQ

SUSPEND

SCLSDA

STATUS

D1

GREENStatus

R4470

SCLSDA

SDA

nIRQVss

Vi2c

Vdd

1 2 3

5

7

9

11

13

4

6

8

10

12

14

J2

I/O

VddP0.7P0.6P0.5P0.4P0.3P0.2P0.1P0.0

P2.0P1.6

P1.0P1.1Vdd

TP2

Vdd

+3.3V

Vdd

+3.3V

TP1

Vss

CX10.1uF

Date: June 28, 2000 Sheet 3 of 3

Size Document Number REV

A d2k127\usb.sch A

Title

I2C to USB

Entry # D2K127

Design 2K Contest

nIRQ

SUSPEND

TP3PrgClk

R94.7K

SUSPEND

nIRQ

Vdd

R5 22

R6 22

SCL 10

SDA 9

3.3V 6

DGND 11

/INT 8

3.3VA 15

AGND 14

VBUS 16

D+ 12 D- 13 SUSPEND 7

CLKOUT 5

XTAL1 3

XTAL2 4

/RESET 2

TEST 1

U2PDIUSBD11

SCLSDA

D-VBUS 1

D- 2

D+ 3

GND 4

SHIELD 5

SHIELD 6

J3USB_B

SCL

SDA

XD-

Vusb

CX20.1uF

R710K

XD+

Vusb

R8100K

D+

USBSENSE

C510uF

CX30.1uF

PRGCLK

+3.3VA

+3.3V

PRGCLK

+3.3V +3.3VA

Notes:

1. Connect +3.3VA and +3.3V at C4.

2. Connect AGND and DGND at C4.

CX40.1uF

Y1

12MHz

C133pF

C233pF

X1

X2

Vss

+3.3V

Vdd Vdd

+3.3V

JP2USB PWR

VI 1

G

2

VO 3

G

4

U3MIC2920A400mA

C310uF

Vusb Vdd

C410uF

+3.3V

Components The heart of the circuit is a Philips 87LPC764 micro-controller. This component is an 8051 derivative featuring 4KB of one-time programmable ROM, 64 bytes of RAM, and an assortment of on-chip resources (timers, UART, I2C, reset, etc.). All of the above features are shoe-horned into a 20 pin package. Because the part implements an 8051 core, a wide variety of development tools are available. The Philips 87LPC764 micro-controller has a wide operating voltage range (2.7V to 6V) which allows it to operate from Vusb (note: Section 7.2.2 of the USB specification shows this voltage can be as low as 4.375V), far below the minimum voltage required by many 5V parts. The datasheet for this device is available at http://www.phillipssemiconductor.com/pip/P87LPC764FD.

The connection to the host computer is achieved with a Philips PDIUSBD11 USB interface. This component features an I2C control interface requiring only three signals from the micro-controller. The device supports full speed USB connections (12Mbps), includes memory buffers for the USB transfers, and has an integrated SIE (serial interface engine) to handle the significant transaction protocol and speed requirements of USB. A SoftConnect (Philips Trademark) feature provides support for disconnection/connection signaling to the USB via software control, and the programmable clock output allows us to keep the crystal count (for the design) down to one (12Mhz). The datasheet for the PDIUSBD11 is available at http://www-us.semiconductors.com/usb/products/interface/pdiusbd11/.

The circuit includes a Micrel 2920A-3.3 voltage regulator for supplying +3.3V to the PDIUSBD11 (USB interface I.C.) when the circuit is operating from USB power or when +5V is supplied via the I2C connector. The regulator has a low dropout voltage of only 370mV at 250mA, burns a mere 140uA of quiescent current, and can source 400mA. The datasheet for the 2920A-3.3 is available at http://www.micrel.com/product-info/products/mic2920a.html.

Power Options The circuitry supports five jumper-configurable, power options:

1. Powered by USB, isolated from I2C power (I2C power used only for I2C signal pull-up resistors).

2. Powered by USB, sourcing Vusb to I2C bus.

3. Powered by USB, sourcing +3.3V to I2C bus.

4. Powered by +5V supplied via I2C bus connector, isolated from USB bus power.

5. Powered by +3.3V supplied via I2C bus connector, isolated from USB bus power.

Initialization At power up, the micro-controller initializes the USB and I2C interfaces.

The processor is clocked by the PRGCLK (programmable clock) signal which is output from the PDIUSBD11. This signal is derived from a 48Mhz clock passed through a programmable divider and defaults to 4Mhz at power up. The divide value for the clock is changed from the default of 12 (48Mhz/12 = 4Mhz) to 3 (48Mhz/3 = 16Mhz) effectively shifting the processor into high gear.

Enumeration After initialization, the firmware enters a forever loop where it waits for events to occur.

The first event (actually a whole series of events) to occur is USB enumeration.

The USB bus is designed to be plug-and-play compatible, requiring a method for detecting and initializing new devices, this method is called “enumeration”.

There are several situations that can result in enumeration (power up, plug-in, reset, etc.) but in this design they are all handled (from a software perspective) as if the device were just plugged in to the USB bus and the computer just detected its presence.

When the host computer detects our device “plug-in” it will initiate a series of USB transactions with the intent of discovering what our device is. The information it obtains from our device during enumeration allows the host computer to determine what drivers it should load to support our device and what the communication features of our device are (things like maximum packet sizes, power requirements, etc.). During the enumeration process, the host assigns the device a unique address (from 1 to 127), all further communications between the host and the device will use the assigned address.

The USB enumeration process is detailed in chapter 9 of the USB specification which is available at http://www.usb.org/developers/data/usb_20.zip

Operation After enumeration, the device is ready to perform it’s intended function as a USB to I2C communications bridge.

The host will send I2C transaction requests to the BitBanger via the USB connection and the device driver calls ReadI2C, WriteI2C, and GetStatus.

The I2C transaction requests specify the type of transfer (no address, 8 bit address, or 16 bit address), the device ID, whether a Read or Write operation is to be performed, and how many bytes to transfer.

The PDIUSBD11 receives the specified I2C transaction requests (packaged up for USB) from the host and signals the processor via the nIRQ signal. The processor then communicates with the PDIUSBD11 via the I2C bus to service the interrupt and read the received requests from the PDIUSBD11’s buffer(s).

The processor then executes the specified I2C transactions, issuing the corresponding Read or Write requests over the I2C bus to the external device(s) attached to J1. In the event of a Read transaction, the read data is returned to the host.

Status information for the last executed transaction can be obtained from the Bit-Banger detailing the success or failure of the last executed transaction, the number of bytes transferred, and whether the device is currently busy.

In addition to the I2C bridge function, the Bit-Banger provides for Read and Write access of any register on the 87LPC764 processor via the ReadReg and WriteReg device driver calls.

A Brief Introduction to I2C I2C is a Master/Slave serial protocol utilizing only two signals, SCL and SDA.

All devices attached to an I2C bus utilize ONLY open collector outputs to drive the signals and the signals are passively pulled high (resistors) whenever the bus is idle.

The SCL signal is the clock provided by the Master in a transaction, and the SDA signal is for the bi-directional data.

Transactions consist of a START sequence, an ID_ADR_MODE sequence, the DATA sequence(s) (each byte followed by an ACK/NAK, except the last), and are terminated by a STOP sequence. The ID_ADR_MODE sequence transfers a byte on the bus containing three pieces of information, a four bit device identification (specific to particular I2C components), a three bit address field (if you have two components with the same device ID, this is where you specify which one), and one mode bit (Read or Write). The ACK/NAK sequence allows the Master to signal that a data byte was received (Read) or the Slave to signal that a data byte was received (Write).

Some devices extend the basic protocol by utilizing a modified (un-terminated) write sequence chained together with another Read or Write sequence. This is common for devices with extended addressing requirements such as eeproms, rams, etc.

In the case of an eeprom, the modified write sequence allows the Master to specify which address it wishes to read from or write to, along with the data. The extended transaction sequence then consists of a START sequence, an ID_ADR_MODE sequence (Mode = Write), the DATA sequence(s) specifying the starting address for the operation (each byte followed by an ACK/NAK, except the last), a second ID_ADR_MODE sequence (Mode = Read or Write), a second DATA sequence(s) for the actual transaction data (each byte followed by an ACK/NAK, except the last), and is terminated by a STOP sequence.

There are many components available that with I2C control interfaces, including eeproms, rams, DACs, ADC’s, multiplexers, digital I/O, USB, etc.

In this design the I2C bus is enhanced by the inclusion of a third signal “nIRQ”. This signal is driven the same way (open collector, passive pull-ups) as the SCL and SDA signals, and provides a mechanism for event signaling from Slave to Master. Without the nIRQ line, a Master would have to continually poll any slaves capable of reporting events (signaling devices). With the nIRQ line, a system with only one signaling device can run in pure interrupt mode, and a system with multiple signaling devices can turn off polling whenever the interrupt line is inactive (this can greatly reduce the processor load).

More information on the I2C bus can be found at http://www-us.semiconductors.philips.com/i2c/ .

Source Code (firmware) The source code files for the firmware are contained in the file “firmware.zip”.

Source Code (Windows WDM device driver) The source code files for the Windows WDM device driver are contained in the file “driver.zip”.

Bill of Materials Item Quantity Reference Part ____________________________________________________________________ 1 4 CX1,CX2,CX3,CX4 0.1uF 2 2 C1,C2 33pF 3 3 C3,C4,C5 10uF 4 1 D1 LED, GREEN 5 1 JP1 JUMPER 3 PIN 6 1 JP2 JUMPER 2 PIN 7 1 J1 CON5 MALE 8 1 J2 CONN IDC 14 9 1 J3 USB Type B 10 3 R1,R2,R3 3.3K 11 1 R4 470 12 2 R5,R6 22 13 1 R7 10K 14 1 R8 100K 15 1 R9 4.7K 16 2 TP2,TP1, TP3 TESTPOINT 17 1 U1 87LPC764 18 1 U2 PDIUSBD11 19 1 U3 MIC2920A-3.3BS, 400mA 20 1 Y1 12MHz

Example Application (I2C I/O) The example application “BitBang.exe” is a simple demonstration of how to access an I2C device using the Bit-Banger. The application demonstrates how to detect the presence or absence of the Bit-Banger device, obtain a handle, and execute I2C transactions calls.

Example Source Code (Visual Basic) The source code files for the Example Visual Basic application are contained in the file exmplapp.zip.

1

1

2

2

A A

B B

XRI0

XRI1

I2C Device Address TableREFU2U3

DEVID10100100

U4 0100

ADDRXXX000001

R/WXX (R)X (W)

Note:Some code examples use an address parameterconsisting of the Device Id and the Address bits(right justified in a byte). This byte value isleft shifted one bit position and then OR'd withthe R/W bit before use. For example, U4 mightbe referred to as 0x21 instead of 0x42.

0x03, // '0' 0x9F, // '1' 0x25, // '2' 0x0D, // '3' 0x99, // '4' 0x49, // '5' 0x41, // '6' 0x1F, // '7' 0x01, // '8' 0x19, // '9' 0x11, // 'A' 0xC1, // 'b' 0x63, // 'C' 0x85, // 'd' 0x61, // 'E' 0x71 // 'F'

Seven Segment DisplayCharacter Map

Note:The display segment mapping is not the same asthat of the Anchor development board and willrequire slight modifcation to the Anchor examplesto substitute the above character table.

Note:Pullup Resistors RX13 and RX14 aretacked on to back of board nearJ1.

Note:The proto boards are fabricated using a 0.062"material. This is too thick to fit in theSimmStick sockets. Though the board can be forcefit into a socket, it is better to mount the boardto the expansion header on the back of a DT-003using a right angle header soldered into the holesjust above the SimmStick card edge conncector.

ActiveWire

Interface

i2ciosio.dsn 1A

I2C I/O and Serial I/O Adapter Board

1 1Saturday, February 26, 2000

A

Title

Size Document Number Rev

Date: Sheet of

SCLSDA

EA2EA1EA0

PC2/INT0

CFG0CFG1

SCL CFG2SDA CFG3

F4

F3

/INTF2

SDAF1

SCL

SCL ASDA B

CDEFG

PC2/INT0

XDSR0XRXD0XRTS0XTXD0

SCLLTXD0

XCTS0SDA

LRXD0XDTR0

LTXD1XSG0

LRXD1

XDSR1XRXD1XRTS1XTXD1XCTS1XDTR1

XSG1

EA0EA1EA2/INT

PC1/TXD0

PC1/TXD0

PC0/RXD0

PC0/RXD0

PC1/TXD0

PC0/RXD0

DP

PC3/INT1

PC3/INT1

PC4/T0

PC4/T0

/RESET_AW

CLK6MHZ_AW

PB6/INT6

PB0/T2

PB4/INT4PB5/INT5

PB1/T2EX

PB3/TXD1

PB0/T2

PB2/RXD1

PB5/INT5

PB2/RXD1

PB2/RXD1

PB6/INT6

PB1/T2EX

PC5/T1

PB7/T2OU

PB3/TXD1

PB4/INT4PB3/TXD1

PC5/T1

PB7/T2OU

CLK24MHZ1_AW

PC6/WRPC7/RDCLK24MHZ2_AW

PWR_SSCI_SSCO_SS

RESET_SS

PA0PA1PA2PA3

PA6PA7

/INT

XCD0

XCD1

SDASCL

PA5/FRD

PA5/FRD

PA4/FWR

PA4/FWR

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

+5V

J2DB9SIO-0

J3DB9SIO-1

S3

S2

S4

S5

S1

R2R3R4

10K

P1(AB.P1)

P2(AB.P2)

R11 390

R9 390R8 390R7 390R6 390R5 390

R1

P3SIMMSTICK

af

ed

c

bg

D1

C10.1uF

C20.1uF

C30.1uF

C40.1uF

C50.1uF

C6 0.1uF

C7 0.1uF

C8 0.1uF

R10 390

R12 390

J1I2C

12345

+C947uF

RX142.2K

RX132.2K

U3PCF8574

P0

SCL

P1A0

P2

SDA

P3

A1

P4VDDP5

A2

P6

VSS

P7

/INT

U4PCF8574

P0

SCL

P1A0

P2

SDA

P3

A1

P4VDDP5

A2

P6

VSS

P7

/INT

U1MAX232A

C1+

C1-

T1I

T2I

R1O

R2O

V+

C2+

C2-

T1O

T2O

R1I

R2I

V-

VCC

GND

U224LCXX

A0A1A2

VSS

VCC

WP

SCLSDA

JP1UART Buffers

1 23 45 67 8