1

The Challenges of Correlating Silicon and Models in High

Variability CMOS Processes

Rob Aitken

ARM R&D

rob.aitken@arm.com

222

©2009Rob Aitken

Outline

§ Background

§ Variability

§ Characterization

§ Library validation

§ Debug examples

§ Conclusions

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Benchmark Results

Google Scholar Citations

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n10 n30 n50 n100 n300

Benchmark

Cit

ati

on

s unmodified

route

benchmark

opportunity

optimal

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Physical IP is more than NAND gates

§ 15+ foundries

§ Up to 8 process generations per foundry

§ Up to 11 variants in each generation

§ 6+ memory generators

§ 900+ standard cells per library

§ 200+ I/Os

§ 10+ views per cell

§ Plus PHY, analog IP, etc.

§ 300+ libraries per year, each with thousands of individual data elements

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Moore’s Law

§ Original Paper:

§ “Cramming more components onto integrated circuits”

§ Electronics, 38-8, 4/19/65

§ Tracks changes from 1959

to 1965 and predicts trend going forward

§ It’s still going…

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Nintendo GameBoy (1989)

CPU: 8-bit Z-80 processor, 1.05 MHz

Screen: 2.6" 160 x 144 LCD 4 b/w

Connectivity: 4 players by serial cable

Introductory price - $169

Nintendo DSi (2008/2009)

CPU: ARM9™ (133 MHz), ARM7™ (33MHz)

Screen: Two 3" 256 X 192 color LCDs

256MB Flash, AAC audio, 2 VGA cameras

Connectivity: Wifi, web browser, shopping

Introductory price - $169

>1000x performance

for the same price

Feedback: Moore’s Law and Consumer Expectations

© Nintendo

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©2009Rob Aitken

Variability trends

§ Non Gaussian behavior

§ Local spread close to global

§ Reduced correlation

1000 Samples of Variation

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0.0002

0.00E+00 2.00E-08 4.00E-08 6.00E-08 8.00E-08 1.00E-07 1.20E-07

Leakage

Idsat

global

local

1000 Samples of Variation

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0.00E+00 2.00E-09 4.00E-09 6.00E-09 8.00E-09 1.00E-08 1.20E-08

Leakage

Idsat

global

local

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90

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Background

§ Classes of test chip:

§ ARM has multiple classes of test chip

§Library qualification chips

§Processor qualification chips

§Experimental test chips

§ Chips:

§ 2 32nm tapeouts since 9/08

§ ~40 Tapeouts in 2008, mainly first group

§ Part of shuttle or multi-project wafer

§ Usually 40-100 packaged chips

§ Challenge:

§ Silicon validation of library elements (standard cells, memory, IO)

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Background cont.

§ The library qualification test chip program objectives

§ Verify basic functionality

§ Validate new architectures in silicon

§ Provide silicon correlation for timing and power measurements

§ Objectives for other programs (not these chips)

§ Serve as yield predictors or measure defect density

§ Evaluate transistor properties or develop SPICE models

§ Study lithography issues

§ Determine the statistical properties of a process (FEOL or BEOL)

§Measure reliability

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Library characterization history

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450475

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900

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100

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300

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.35um .25um .18um .15um .13um 90nm 65nm

Cell Count

Disk Usage

CPU Usage

900*

45nm

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Characterization History

§ Three delay numbers: slow, typ, fast

§ Just too inaccurate

§ Linear delay: f(cap)

§What about slew rates?

§ NLDM: table f(cap, slew), interpolate between points

§Which table? How many points?

§Multiple voltage support complicated

§ Complex interconnects not modeled well

§ Current source models (CCS, ECSM)

§More complex modeling of device behavior

§ Allows for more accuracy, especially at intermediate points

§Giant files

§ Statistical models…

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How much accuracy do you need?

§ Depends on tools, stage of design flow

§ Need for accuracy varies

§ Preliminary floorplanner needs different accuracy than final extraction flow

§ Interconnect modeling needs good, but not perfect accuracy

§ 3D field solver not required, but need more than interpolation between table data points, especially for complex shapes, long distances

§ Accuracy is important, but needs to be defined correctly"0.015667, 0.020832, 0.030359, 0.048810, 0.086296, 0.161212, 0.311795", \

"0.017252, 0.023636, 0.033981, 0.052357, 0.089780, 0.164684, 0.315177", \

These are not “within X% of SPICE”, they are SPICE!

values("7.117695e-03, 1.329720e-02, 3.667810e-02, 4.492980e-02, 5.068780e-02, 5.180790e-02, 5.086270e-02, 4.749920e-02, 5.026640e-02, 4.425650e-02, 2.832520e-02, 2.129720e-02,

1.605390e-02, 9.854060e-03, 5.124280e-03, 2.224300e-03, 1.424661e-03");

So are these.

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§ Interpolation accuracy: 2-3%

§ Temperature, voltage variation handled with current source models

§ Variability: SS versus TT: -20% to 40%

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7

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0.048

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7

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0.512

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0

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1234567

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0.048

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0.14

0.264

0.512

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1

1.05

1.1

1.15

1.2

1.25

1.3

1.35

1.4

SS

TT

Accuracy and precision:NLDM interpolation versus transistor variability

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0.0040.0120.0280.0640.1480.344

0.0003

0.0009

0.0027

0.0083

0.0253

0.0778

0.2387

40%

60%

80%

100%

120%

140%

160%

180%

200%

perf

orm

an

ce

rati

o A

to

B

transition (scaled)

load (scaled)

1.8-2

1.6-1.8

1.4-1.6

1.2-1.4

1-1.2

0.8-1

0.6-0.8

0.4-0.6

“Scaling” of standard cell delay

§ Relative delay

for equivalent cells in two different

technologies A and B

§ Is A slower

than B or

faster?

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Silicon Validation of Libraries

§ Basic idea

§Measure silicon, compare with model prediction

§ Things to measure

§ Delay

§ Power

§Leakage

§Dynamic

§ Challenges

§Where does silicon fit in “corners”

§Measurement accuracy

§ Single point versus table

§Model versus SPICE

§ SPICE versus silicon

§ Parametric variation

§ Presence of “soft” defects

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Overcoming challenges

§ Challenges

§ Where does silicon fit in “corners”

§Oscillator data, test structure data

§ Measurement accuracy

§Understand equipment, measure deltas

§Big challenge for power

§ Single point versus table

§Carefully select design point

§Shmoo across voltage, temperature

§ Model versus SPICE

§Understand characterization issues

§ SPICE versus silicon

§Work with foundries to understand

§ Parametric variation

§Design around local variation

§ Presence of “soft” defects

§Look for trends across chips

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Validation in practice

§ Variability observed for similar objects across chips

§ “Correct” value somewhere in the middle

§ Does this validate it?

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How Close is it to SPICE?

§ Significant difference between simulators

observed

§ Variety of issues represented

§Model file interpretation

§ Performance options

§ Extraction issues

§ Silicon variability

Delay versus Silicon

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130%

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150%

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Instance

Simulator 1

Simulator 2

Remember this thenext time some toolclaims to be within

X% of SPICE

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Number of Contacts (Yield vs Speed)

§Typical questions after early data collection (small number of units)

§3% shift in mean but what is mean – 3σ?

Units 208/304/501 contact experiments

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94%

96%

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100%

102%

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106%

108%

oscila

tor_

inv_x1_cont1

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oscila

tor_

inv_x1_cont1

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oscila

tor_

inv_x1_cont2

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oscila

tor_

inv_x1_cont2

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Sta

ge D

ela

y, n

orm

alize

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Min VDD for Different Design Styles

§ Question: Are any of these designs better?

§ Statistically: No

§ But: More data might give the edge to design 4

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Instance Class

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VD

D

Design 1

Design 2

Design 3

Design 4

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Variability and Validation

§ Look for correlation

§ 65nm data

§ Result: small, but measurable, distance-based effect observed

Delay Correlation vs. Circuit Distance (SEC, RVT, -40C, 1.08V, H2L)

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Circuit block distance (um)

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rre

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icie

nt

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Sources of Variability

§ Lithography

§ Line edge roughness

§ CD variation

§ Influence of neighbors

§ Device

§Well boundary effects

§ Variation between N and P

§ Stress/strain effects

§ Interconnect

§ Dielectric variation

§ Via/contact quality

§Metal width/height variation

§ Deterministic versus Random

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Effects of Variability

§Leakage

§ Variation in L, Vt, µ, tox

§Performance

§ Changes in L, W, R, C, Vt, µ,

§Min VDD

§ Changes in Vt, L, W

§ SRAM bit cell main limiter

§Dynamic power

§ Changes in C

§ Side effect of changes in performance, leakage

§Yield

§ Indirect result of others

§ Parameter goes beyond spec + tolerance

αµ )( tgsoxd VVL

WCI −

⋅≈

+3σσσσ

-3σσσσ

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Local Variation Dominates in VDSM

§ Local variation (within chip) is nearly as much as global variation (between chips) at 45nm

Histogram of Leakage

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global

Histogram of Idsat

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E-0

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44E

-04

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60E

-04

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68E

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76E

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84E

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local

global

1000 Monte Carlo samples, 45nm technology

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Critical Defect Behavior

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18002000good

250ps

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600ps

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<10ps70ps150psSA1Delay

3000200018001700Resistance (Ω)

Nominal delay Worst-case delay

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Critical Variability

§ Designed for a predetermined operating point, plus margin

§ Example: SS Corner, 0.9V, 125C, 0 slack

§ Case 1: TT silicon, 0.9V, 85C

§>2X nominal delay will still function correctly

§ Case 2: SS silicon, 0.9V, 85C

§~20% extra delay will cause failure

§ Influential factors:

§Process, voltage, temperature, slack, noise

§ Expected silicon distribution: SS < 1%, TT(+/-) > 50%

§Might expect a 1-2% yield hit if SS corner just misses timing

§Guaranteed silicon distribution: None (usually)

§Could wind up with no yield 1-2% of the time (1 week per year)

§Or worse…

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Outline

§ Background

§ Variability

§ Characterization

§ Library validation

§ Debug examples

§ Conclusions

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Key to Memory Debug: Bit Mapping

§ Pass/Fail information is adequate for production testing

§ For yield improvement, debug, system bring-up, etc., it is also

useful to be able to identify each failing address and data

pattern

§ Need logical to physical mapping for this also

§ Some common patterns are shown below:

Single Cell Entire Column Half Row

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Learning From Bit Maps

Vertical Pair:

Bit Line ContactPartial Column:

Resistive Bit Line Short

Catastrophic:

Timing circuit

Multi-Row:

Address Decoder

Swath:

CMP ScratchEntire Bit:

Sense amp, I/O

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What can happen?

§ Temperature related leakage problem

§ Root causes

§ 5-10X worst case leakage

§ Circuit marginality

0.001

0.01

0.1

1

Worse case

sub-threshold

current

Normalizedsub-threshold

current

-20 0 20 40 60 80

Temperature

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Lithography troubles

§Early silicon may be affected by

incomplete or improper processing

§This is less common later in

process cycle (memory optimized

first)

§May still be an issue for logic

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Power Design

§ The good and the bad of power connection

§ Memory provider can only account for so much!

§ More margin = less performance

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Analog problem: Read disturb fault

§ Data node voltage increases with successive reads

§ Given time, settles back to zero

§ Root cause: defective ground contact

1st read 250 mV

2nd read 520 mV

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Conclusions

§ Validation is more complicated than you’d think

§ Variation increasingly important

§ Understanding sources of variation helps

§ An effective debug methodology helps when new troubles

arise

§Tools

§Infrastructure (silicon, equipment,

software)

§Experience

§ Feel free to send questions to rob.aitken@arm.com