the cmos vlsi design
TRANSCRIPT
![Page 1: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/1.jpg)
VLSI DESIGNA COMPLETE VISION OF VLSI DESIGN STYLES
Surya Teja Swamy, Vijay VemuriII/IV - B. Tech , ECE,KL University, Guntur.
![Page 2: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/2.jpg)
WHAT IS VLSI ?
• VLSI refers • V : Very• L : Large• S : Scale• I : Integrated Circuits
![Page 3: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/3.jpg)
CONT…
• VLSI is a process of creating an integrated circuit (IC) by combining thousands of transistors into a single Silicon Chip.
• Before VLSI there are other design process* SSI - 10-100* MSI - 100-1000* LSI - 1000-20000* ULSI - 1000000-100lakhs* GSI - >100lakhs
![Page 4: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/4.jpg)
MOORE’S LAW
• Regarding this IC technology “ ” introduced a law
• For every 18 months transistors are doubled.
![Page 5: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/5.jpg)
MOORE’S LAW
• Regarding this IC technology “GORDON MOORE” introduced a law
• For every 18 months transistors are doubled.
![Page 6: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/6.jpg)
Transistors per Chip
![Page 7: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/7.jpg)
VLSI DESIGN
• In present days all the Electronic Devices are made of using these VLSI CHIPS.
• These VLSI are designed by CMOS.• In Earlier they used several types of active devices.
![Page 8: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/8.jpg)
COMPARISON OF AVAILABLE TECHNOLOGY
![Page 9: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/9.jpg)
VLSI DESIGN USING CMOS
• CMOS ---- C M O S
![Page 10: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/10.jpg)
VLSI DESIGN USING CMOS
• CMOS ---- Complementary Metal Oxide Semiconductor
![Page 11: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/11.jpg)
VLSI DESIGN USING CMOS
• CMOS ---- Complementary Metal Oxide Semiconductor• Combination of PMOS and NMOS• The output of the CMOS is Complement.• For getting true value we need to take a “Invertor” at the
output.
![Page 12: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/12.jpg)
TYPES OF CMOS FABRICATIONS
• N-WELL PROCESS• P-WELL PROCESS• TWIN TUB PROCESS
![Page 13: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/13.jpg)
CMOS P-WELL FABRICATION
Steps 1-4
![Page 14: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/14.jpg)
CONT..
CMOS P-well inverter showing VDD and VSS Substrate connections
![Page 15: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/15.jpg)
Formation of n-well regions
Define nMOS and pMOS active areas
Field and Gate Oxidations (thinox)
Form and Pattern Polysilicon
p+ diffusion
n+ diffusion
Contact cuts
Deposit and pattern metallization
Over glass with cuts for bonding pads
MAIN STEP IN A TYPICAL N-WELL PROCESS
![Page 16: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/16.jpg)
DRAWBACKS OF N-WELL &P-WELL
• In both N-WELL and P-WELL we may got come across two problems.Body Effect &Latch Up problem
• To over come this drawback, we are going for “Twin Tub”.
![Page 17: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/17.jpg)
TWIN-TUB PROCESS* It is made with both n-well and p-well region.
* Epitaxial layer: High purity silicon grown with accurately determined dopant concentrations
![Page 18: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/18.jpg)
CONT…
• At present the CMOS technologists are using “TWIN TUB” process.
• As It is giving effective result.• Also it is more efficient.
![Page 19: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/19.jpg)
DRAWBACKS OF CMOS
• CMOS is quite good for all the ELECTRONIC Gadgets.• As they required 0-5V voltage.• But coming to the ANALOG Equipment's … CMOS is poor to
use.• For that problem we are going to use BICMOS technology.
![Page 20: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/20.jpg)
COMPARISON BETWEEN CMOS AND BIPOLAR TECHNOLOGIES
CMOS• Low static power dissipation• High input impedance• High noise margin• High packing density• High delay sensitivity to load• Low output drive current• Low gm• Bidirectional capability• A near ideal switching device• Scalable threshold voltage
BIPOLAR TECHNOLOGIES• High power dissipation• Low input impedance• Low voltage swing logic• Low packing density• Low delay sensitivity to load• High output drive current • High gm• Essentially unidirectional
![Page 21: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/21.jpg)
BICMOS…
• BICMOS BJT + CMOS
![Page 22: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/22.jpg)
BICMOS…
• BICMOS BJT + CMOS• As the drawback of CMOS is output load.• At the output of the circuits we use BJT.• Entire circuit is designed with CMOS.
![Page 23: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/23.jpg)
CROSS SECTIONAL VIEWBi-CMOS(n-p-n Transistor (orbit 2 um CMOS)
![Page 24: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/24.jpg)
n-well BiCMOS fabrication process steps
BICMOS
FABRICATION
PROCESS
![Page 25: THE CMOS VLSI DESIGN](https://reader035.vdocuments.net/reader035/viewer/2022062412/58ecf8221a28abbd078b47e5/html5/thumbnails/25.jpg)