The Continuing Growth of Silicon

Integration Technologies and

Application / System Level Testing

Prompts a Reflection on the EDA to

HVM Highway

Zoë Conroy

Senior Manager – DFT, Test & PE

Component Quality & Technology

Sept 21, 2017

Today’s Reflection

• Electronics market is demanding high growth,

high function, yet cost-effective solutions

• Multi die heterogeneous integrations offer More

than Moore

• Applications are requiring minimal defect rates

• Are today’s development tools enough to sustain

and improve required quality and reliability?

• How will EDA and manufacturing test reshape

themselves to meet these needs?

1

Continuous Innovation: More than Moore

Networking - Graphics - Computing

• 2.5/3D/SiP/WLP

• Optics, photonics

• MEMs, Sensors

• RF, analog

• Power

2

Where is the Industry at Today?

• Applications demand continuous uptime, with

cloud/data-centers allowing more applications

worldwide

• Automotive arena - <<100 DPPM

• More companies adding system level test to get

highest level of test coverage and quality

• Gate counts/ heterogeneous integration and

advanced packaging continue to push boundary

on technologies requiring ‘perfect’, yet cost

effective silicon

3

The Impact of Bad Quality

4

The Impact of the Network

• Our lives NOW DEPEND on the network

• Highest Quality is a MUST, not a nice to have!

5

Hardware is Here to Stay!

Catching Defects - What Comes First?

Fab / Process

DesignWafer / Package

Test

Board / System/

Application Test

Defect Free?

DFT to detect all defects?

Test Pattern coverage to

catch ALL defects?

Application testing to catch

remainder of defects?

Where do Problems Occur?

Fab / Process

DesignWafer / Package

Test

Board / System/

Application Test

• Silicon technology Temp inversion affect

• Memory test gaps• Structural Test gaps

• Power simulation vs. silicon

• T/V sensors do not reflect reality

• Hard to close timing

• Wide power variation chip to chip

• No DFD• Interoperability

margin

• Varying Defects• Process center

movement

EDA to HVM Highway

9

SystemTraffic

test

Pack

Out

Burn

- inSMT ICT

3D X-Ray

Functional Diagnostic

testParametric

Board Build System Integration

Component

Supplier

Equivalent SLT

ComponentDesign &

verification

WaferMfg & Test

Package/Heterogeneous

/stack test

SLT

End To End Manufacturing Flow

ATE to System Differences

• Functional application test

• Complex board / system design

• Multiple components interfacing to

each other

• Noisy environment

• Varying temperatures

• High coverage structural test program

• Low noise DUT-board design

• Low noise floor

• Very accurate power supplies

• Stable temperature

10

Typical networking board: ASICs, uP, FPGA, PHYs,

CDRs, memories (DRAM, SRAM, TCAM, HDD, etc)

Different types of coverage

tests, environments,

11

IP Guardian 10GE

Mac

(XM)

Port Logic

(PL)

Security

(SC)

10GE

Mac

(XM)

Port Logic

(PL)

Security

(SC)

Ingress Packet

Buffer

(IB)

Decision Engine Ingress

(DI)

Filter Block

(FB)

Egress Packet

Buffer

(EB)

Virtual

Output

Queues

(VQ)

Reorder

(RO)

Arbiter

Manager

(AM)

Decision

Engine

Egress

(DE)

Fabric Receive

(FR)

Chico RX

(CR)

Fabric Transmit

(FT)

Chico TX

(CT)Arbiter

Exhange

(AX)

“Packet Storage”

Port Logic

Buffer

1 pkt every 16.79 clk

1 pkt every 16.79 clk

1 pkt every 16.79 clk

1 pkt every

8.39 clk

1 pkt every

8 clk

1 pkt every 4 clk

1 req

every 4 clk

1 pkt every 4 clk (FC)

1 req

every 4 clk

1 gid

every 2 clk

1 gid

every 4 clk

1 pkt every 4 clk

1 pkt every 8 clk (Eth)

1 pkt every 4 clk (FC)

1 pkt every 8 clk (Eth)

1 pkt every 16 clk

1 pkt every 4 clk (FC)1 pkt every 8 clk (Eth)

1 pkt every 16 clk

1 pkt every

8 clk

1 pkt every 16 clk

1 pkt every 16 clk

1 pkt every 16 clk

1 page rls every

8 clk

1 credit

every 2 clk

1 pkt every 16.79 clk

1 pkt every 16.79 clk

1 pkt desc. every 4 clk

Decision Engine

Lookup

(DL)

1 cred rls every 4 clk

System Traffic Test

Ext M

em

BIS

T

Internal

Memory

BIST

IOBIST

TCAM

BIST

JTAG

1149.1

CPU

2JTAG

JTAG

2CPU

Em

bed

de

d In

stru

me

nt

Logic BIST

SerDes PRBS &

1149.6

Scan: SAF, TF,

PD, Ram Seq

Ring

Osc

SerDes PRBS &

1149.6

PLL check

ATE Structural Test

Internal

Memory

BIST

Consequences of ATE and System

Test Differences

• Board functional tests run different data from

ATE BIST and structural testing

• Environmental conditions at system level can

cause fails on marginal devices

• Components marginal for timing, voltage

• ATE test escapes

– Hard to emulate functional environment with a

standalone chip

– Less than optimal structural/BIST coverage

12

*Component Supplier

ATE Test Escapes

system diags

board h/w or mfg

IC design

other

13

Diagnosis of ASIC Fails at System Test

Data from various DPPM Reduction Initiatives 2005-2017

*ATE test escapes

Components that

failed system test for

functional or IC BIST

test, and subsequently

found to have a test

gap at IC ATE test.

• Added coverage to existing test

• Added a new ATE test

• Ported a functional test from system to ATE

• Changed limits on existing Test

ATE Gaps - Breakdown by Test

14

Func

Memory

At-Speed Scan Other

Logic BIST

High speed serial data

Voltage

• ATE tests added

Heterogeneous Functions Drive Growth

15Based on ”IC Insights Report”, Sept 2014, 3DIn-cite.com

Increasing Levels of Integration

interoperability

component to component

(sub-)component

Ext mem

Ext mem

Ext mem

Using Components to Test the Board

• SerDes

• IOBIST

• Internal MBIST

• External MBIST

• Programmable BIST

for application

specific algorithms

• T/V Sense

• PLL Checkers

• Traffic

17

NPUA6

NPUA1

NPUA2

NPUA5

NPUA4

NPUA3

ASICB

ASICB

Ext mem

Ext mem

Ext mem

CPU

FPGA

Ext mem

Ext mem

PCIeswitch

QSFP QSFP QSFP

Ext mem

Ext mem

Ext mem

Ext mem

Gearbox

Gearbox

Gearbox

Gearbox

Gearbox

Gearbox

FabricASIC

FabricASIC

NPU A1-6

NPU A1-6

Reduced Structural Test Point Impact

• Test points reducing with denser routing

• Components BIST becomes critical for board testing*

• BIST can cover:- Board opens/shorts- Trace transitions, - High speed interconnect and SI

*iNEMI BIST Program http://community.inemi.org/bist

EDA Tool Portfolio Opportunities

• SLT addition just keeps the status quo!

• Component applications’ testing manifests

unique coverage gaps in ATE tests

• Denser silicon and heterogeneous integration

requires new types of defect modeling and ways

to isolate defect locations in real time

• Embedded and external memories continue to

be a challenge, with high application fall-out.

19

Connecting Suppliers & EMS Partners

Big Data Analytics CloudMachine to

Machine

End to End CollaborationAutomation

IoE and Adaptive Test to automate End to End Collaboration

ITC 2015, Bert Gab, End to End Adaptive Test, “From system to component and back”, invited paper

Test Data Analytics and Adaptive Test

EMS PartnerComponent Supplier

Big Data Analytics/Machine Learning to predict probability of part failing inSystem Test.

Improved Process/Optimized Test Data Templates

Adaptive Testing:Test only relevant portion of the population to catch 100% failures

System TestComponent Test

Faster Time to Quality

Faster Component FA

24/7Data Loop

Fab

Cloud Based Predictive Analytics

22

SystemTraffic

testICT

Functional Diagnostic

testParametric

Board BuildComponent Supplier

Componentdesign &

verification

WaferMfg & Test

Package/heterogeneous

/stack testSLT

Fab process data

Test

dat

a

componenttest dataData

gateway

Cloud servers

Big dataprediction analytics

Process and test data

Boardtest data

PredictionTest data

test area 2test area 1 test area 3 test area 4Wafer test Pkg test SLTtest

Adaptivetest engine

Feed forward

Unique Die id traceability

EMS PartnerComponent Suppliers

Closing Remarks

• There are gaps in ATE tests - structural tests do not

exercise chips in the same way the application does.

• SLT provides an application test to weed out final defects.

• Actionable data at SLT required to keep closing gap from

system to ATE.

• EDA must keep up with increasing complexities of

designs, integrations, quality requirements.

• Cooperation and bi-directional info exchange across the

entire supply chain is a must.

• Standards for data exchange formats and hand-off

criteria between supply chain partners need to be agreed.