the digital abstraction - dsi.fceia.unr.edu.ar
TRANSCRIPT
Apoyo Unidad 1SistemasCombinacionales <1>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Most physical variables are continuous
– Voltage on a wire
– Frequency of an oscillation
– Position of a mass
• Digital abstraction considers discrete subset of values
The Digital Abstraction
Apoyo Unidad 1SistemasCombinacionales <2>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Born to working class parents
• Taught himself mathematics andjoined the faculty of Queen’sCollege in Ireland
• Wrote An Investigation of theLaws of Thought (1854)
• Introduced binary variables
• Introduced the three fundamentallogic operations: AND, OR, andNOT
George Boole, 1815-1864
Apoyo Unidad 1SistemasCombinacionales <3>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Two discrete values:– 1’s and 0’s
– 1, TRUE, HIGH
– 0, FALSE, LOW
• 1 and 0: voltage levels, rotating gears, fluid levels, etc.
• Digital circuits use voltage levels to represent 1 and 0
• Bit: Binary digit
Digital Discipline: Binary Values
Apoyo Unidad 1SistemasCombinacionales <4>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Perform logic functions:
– inversion (NOT), AND, OR, NAND, NOR, etc.
• Single-input:
– NOT gate, buffer
• Two-input:
– AND, OR, XOR, NAND, NOR, XNOR
• Multiple-input
Logic Gates
Apoyo Unidad 1SistemasCombinacionales <5>
Digital Design and Computer Architecture: ARM® Edition © 2015
NOT
Y = A
A Y0
1
A Y
BUF
Y = A
A Y0
1
A Y
Single-Input Logic Gates
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Digital Design and Computer Architecture: ARM® Edition © 2015
NOT
Y = A
A Y0 1
1 0
A Y
BUF
Y = A
A Y0 0
1 1
A Y
Single-Input Logic Gates
Apoyo Unidad 1SistemasCombinacionales <7>
Digital Design and Computer Architecture: ARM® Edition © 2015
AND
Y = AB
A B Y0 0
0 1
1 0
1 1
AB
Y
OR
Y = A + B
A B Y0 0
0 1
1 0
1 1
AB
Y
Two-Input Logic Gates
Apoyo Unidad 1SistemasCombinacionales <8>
Digital Design and Computer Architecture: ARM® Edition © 2015
AND
Y = AB
A B Y0 0 0
0 1 0
1 0 0
1 1 1
AB
Y
OR
Y = A + B
A B Y0 0 0
0 1 1
1 0 1
1 1 1
AB
Y
Two-Input Logic Gates
Apoyo Unidad 1SistemasCombinacionales <9>
Digital Design and Computer Architecture: ARM® Edition © 2015
XNOR
Y = A + B
A B Y0 0
0 1
1 0
1 1
AB
Y
XOR NAND NOR
Y = A + B Y = AB Y = A + B
A B Y0 0
0 1
1 0
1 1
A B Y0 0
0 1
1 0
1 1
A B Y0 0
0 1
1 0
1 1
AB
YAB
YAB
Y
More Two-Input Logic Gates
Apoyo Unidad 1SistemasCombinacionales <10>
Digital Design and Computer Architecture: ARM® Edition © 2015
XNOR
Y = A + B
A B Y0 0
0 1
1 0
1 1
AB
Y
XOR NAND NOR
Y = A + B Y = AB Y = A + B
A B Y0 0 0
0 1 1
1 0 1
1 1 0
A B Y0 0 1
0 1 1
1 0 1
1 1 0
A B Y0 0 1
0 1 0
1 0 0
1 1 0
AB
YAB
YAB
Y
1
0
0
1
More Two-Input Logic Gates
Apoyo Unidad 1SistemasCombinacionales <11>
Digital Design and Computer Architecture: ARM® Edition © 2015
NOR3
Y = A+B+C
B C Y0 0
0 1
1 0
1 1
AB YC
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
Multiple-Input Logic Gates
AND3
Y = ABC
AB YC
B C Y0 0
0 1
1 0
1 1
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
Apoyo Unidad 1SistemasCombinacionales <12>
Digital Design and Computer Architecture: ARM® Edition © 2015
NOR3
Y = A+B+C
B C Y0 0
0 1
1 0
1 1
AB YC
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
0
0
0
0
0
0
0
• Multi-input XOR: Odd parity
Multiple-Input Logic Gates
AND3
Y = ABC
AB YC
B C Y0 0
0 1
1 0
1 1
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
0
0
0
0
0
1
Apoyo Unidad 1SistemasCombinacionales <13>
Digital Design and Computer Architecture: ARM® Edition © 2015
A logic circuit is composed of:• Inputs• Outputs• Functional specification• Timing specification
inputs outputsfunctional spec
timing spec
Logic Circuit
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Nodes
– Inputs: A, B, C
– Outputs: Y, Z
– Internal: n1
• Circuit elements
– E1, E2, E3
– Each a circuit
A E1
E2
E3B
C
n1
Y
Z
Circuits
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Combinational Logic– Memoryless
– Outputs determined by current values of inputs
• Sequential Logic– Has memory
– Outputs determined by previous and current values of inputs
inputs outputsfunctional spec
timing spec
Types of Logic Circuits
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Every element is combinational
• Every node is either an input or connects to exactly one output
• The circuit contains no cyclic paths
• Example:
Rules of Combinational Composition
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Functional specification of outputs in terms of inputs
• Example: S = F(A, B, Cin)
Cout = F(A, B, Cin)
AS
S = A B Cin
Cout
= AB + ACin + BC
in
BC
in
CLC
out
Boolean Equations
Apoyo Unidad 1SistemasCombinacionales <18>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Complement: variable with a bar over it
A, B, C
• Literal: variable or its complement
A, A, B, B, C, C
• Implicant: product of literals
ABC, AC, BC
• Minterm: product that includes all input variables
ABC, ABC, ABC
• Maxterm: sum that includes all input variables
(A+B+C), (A+B+C), (A+B+C)
Some Definitions
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Digital Design and Computer Architecture: ARM® Edition © 2015
Y = F(A, B) = AB + AB = Σ(1, 3)
A B Y
0 0
0 1
1 0
1 1
0
1
0
1
minterm
A B
A B
A B
A B
minterm
name
m0
m1
m2
m3
• All equations can be written in SOP form• Each row has a minterm• A minterm is a product (AND) of literals• Each minterm is TRUE for that row (and only that row)• Form function by ORing minterms where output is 1• Thus, a sum (OR) of products (AND terms)
Sum-of-Products (SOP) Form
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Digital Design and Computer Architecture: ARM® Edition © 2015
Y = F(A, B) = (A + B)(A + B) = Π(0, 2)
• All Boolean equations can be written in POS form• Each row has a maxterm• A maxterm is a sum (OR) of literals• Each maxterm is FALSE for that row (and only that row)• Form function by ANDing maxterms where output is 0• Thus, a product (AND) of sums (OR terms)
Product-of-Sums (POS) Form
A + B
A B Y
0 0
0 1
1 0
1 1
0
1
0
1
maxterm
A + B
A + B
A + B
maxterm
name
M0
M1
M2
M3
Apoyo Unidad 1SistemasCombinacionales <21>
Digital Design and Computer Architecture: ARM® Edition © 2015
• You are going to the cafeteria for lunch
– You won’t eat lunch (E)
– If it’s not open (O) or
– If they only serve corndogs (C)
• Write a truth table for determining if you will eat lunch (E). O C E
0 0
0 1
1 0
1 1
0
0
1
0
Boolean Equations Example
Apoyo Unidad 1SistemasCombinacionales <22>
Digital Design and Computer Architecture: ARM® Edition © 2015
O + C
O C E
0 0
0 1
1 0
1 1
0
0
1
0
maxterm
O + C
O + C
O + C
O C E
0 0
0 1
1 0
1 1
0
0
1
0
minterm
O C
O C
O C
O C
E = (O + C)(O + C)(O + C)
= Π(0, 1, 3)
E = OC
= Σ(2)
SOP & POS Form
SOP – sum-of-products
POS – product-of-sums
Apoyo Unidad 1SistemasCombinacionales <23>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Axioms and theorems to simplify Boolean equations
• Like regular algebra, but simpler: variables have only two values (1 or 0)
• Duality in axioms and theorems:
–ANDs and ORs, 0’s and 1’s interchanged
Boolean Algebra
Apoyo Unidad 1SistemasCombinacionales <24>
Digital Design and Computer Architecture: ARM® Edition © 2015
Boolean Axioms
Number Axiom Dual Name
A1 B = 0 if B ≠ 1 B = 1 if B ≠ 0 Binary Field
A2 0 = 1 1 = 0 NOT
A3 0 • 0 = 0 1 + 1 = 1 AND/OR
A4 1 • 1 = 1 0 + 0 = 0 AND/OR
A5 0 • 1 = 1 • 0 = 0 1 + 0 = 0 + 1 = 1 AND/OR
Dual: Replace: • with + 0 with 1
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Digital Design and Computer Architecture: ARM® Edition © 2015
Boolean Theorems of One Variable
Number Theorem Dual Name
T1 B • 1 = B B + 0 = B Identity
T2 B • 0 = 0 B + 1 = 1 Null Element
T3 B • B = B B + B = B Idempotency
T4 B = B Involution
T5 B • B = 0 B + B = 1 Complements
Dual: Replace: • with + 0 with 1
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Digital Design and Computer Architecture: ARM® Edition © 2015
1 =
=
B
0B
B
B
• B 1 = B
• B + 0 = B
T1: Identity Theorem
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Digital Design and Computer Architecture: ARM® Edition © 2015
0 =
=
B
1B
1
0
• B 0 = 0
• B + 1 = 1
T2: Null Element Theorem
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Digital Design and Computer Architecture: ARM® Edition © 2015
B =
=
B
BB
B
B
• B B = B
• B + B = B
T3: Idempotency Theorem
Apoyo Unidad 1SistemasCombinacionales <29>
Digital Design and Computer Architecture: ARM® Edition © 2015
= BB
• B = B
T4: Identity Theorem
Apoyo Unidad 1SistemasCombinacionales <30>
Digital Design and Computer Architecture: ARM® Edition © 2015
B =
=
B
BB
1
0
• B B = 0
• B + B = 1
T5: Complement Theorem
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Digital Design and Computer Architecture: ARM® Edition © 2015
# Theorem Dual Name
T6 B•C = C•B B+C = C+B Commutativity
T7 (B•C) • D = B • (C•D) (B + C) + D = B + (C + D) Associativity
T8 B • (C + D) = (B•C) + (B•D) B + (C•D) = (B+C) (B+D) Distributivity
T9 B • (B+C) = B B + (B•C) = B Covering
T10 (B•C) + (B•C) = B (B+C) • (B+C) = B Combining
T11 (B•C) + (B•D) + (C•D) =(B•C) + (B•D)
(B+C) • (B+D) • (C+D) =(B+C) • (B+D)
Consensus
Boolean Theorems of Several Vars
Warning: T8’ differs from traditional algebra: OR (+) distributes over AND (•)
Apoyo Unidad 1SistemasCombinacionales <32>
Digital Design and Computer Architecture: ARM® Edition © 2015
Simplifying an Equation
Reducing an equation to the fewest number of implicants, where each implicant has the fewest literals
Recall:
– Implicant: product of literals
ABC, AC, BC
– Literal: variable or its complementA, A, B, B, C, C
Also called minimizing the equation
Axioms and theorems are useful for simplifying equations.
Apoyo Unidad 1SistemasCombinacionales <33>
Digital Design and Computer Architecture: ARM® Edition © 2015
DeMorgan’s Theorem: Dual
The complement of the product is the
sum of the complements.
Dual: The complement of the sumis the
product of the complements.
# Theorem Dual Name
T12 B0•B1•B2… = B0+B1+B2…
B0+B1+B2… = B0•B1•B2…
DeMorgan’sTheorem
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Y = AB = A + B
• Y = A + B = A B
AB
Y
AB
Y
AB
Y
AB
Y
DeMorgan’s Theorem
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Backward:– Body changes
– Adds bubbles to inputs
• Forward:– Body changes
– Adds bubble to output
AB
YAB
Y
AB
YAB
Y
Bubble Pushing
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Digital Design and Computer Architecture: ARM® Edition © 2015
AB
C
D
Y
• Begin at output, then work toward inputs
• Push bubbles on final output back
• Draw gates in a form so bubbles cancel
Bubble Pushing Rules
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Digital Design and Computer Architecture: ARM® Edition © 2015
AB
C
D
Y
bubble on
input and outputAB
C
D
Y
AB
C Y
D
Y = ABC + D
no output
bubble
no bubble on
input and output
Bubble Pushing Example
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Two-level logic: ANDs followed by ORs
• Example: Y = ABC + ABC + ABC
BA C
Y
minterm: ABC
minterm: ABC
minterm: ABC
A B C
From Logic to Gates
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Inputs on the left (or top)
• Outputs on right (or bottom)
• Gates flow from left to right
• Straight wires are best
Circuit Schematics Rules
Apoyo Unidad 1SistemasCombinacionales <40>
Digital Design and Computer Architecture: ARM® Edition © 2015
0
A1
A0
0 00 11 01 1
0
00
Y3Y2
Y1
Y0
0000
0011
0100
A3
A2
0 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A0
A1
PRIORITY
CiIRCUIT
A2
A3
Y0
Y1
Y2
Y3
• Example: Priority CircuitOutput asserted
corresponding to most
significant TRUE input
Multiple-Output Circuits
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Digital Design and Computer Architecture: ARM® Edition © 2015
A1
A0
0 00 11 01 1
0000
Y3Y2
Y1
Y0
0000
0011
0100
A3
A2
0 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A3A
2A
1A
0
Y3
Y2
Y1
Y0
Priority Circuit Hardware
Apoyo Unidad 1SistemasCombinacionales <42>
Digital Design and Computer Architecture: ARM® Edition © 2015
A1
A0
0 00 11 01 1
0000
Y3Y2
Y1
Y0
0000
0011
0100
A3
A2
0 00 00 00 0
0 0 0 1 0 00 10 11 01 10 0
0 10 10 11 0
0 11 01 01 10 00 1
1 01 01 11 1
1 01 11 11 1
0001
1110
0000
0000
1 0 0 01111
0000
0000
0000
1 0 0 01 0 0 0
A1
A0
0 00 11 XX X
0000
Y3Y2
Y1
Y0
0001
0010
0100
A3
A2
0 00 00 00 1
X X 1 0 0 01 X
Don’t Cares
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Boolean expressions can be minimized by combining terms
• K-maps minimize equations graphically
• PA + PA = P
C00 01
0
1
Y
11 10AB
1
1
0
0
0
0
0
0
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
B C0 0
0 1
1 0
1 1
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
0
0
0
0
0
0
Y
Karnaugh Maps (K-Maps)
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Digital Design and Computer Architecture: ARM® Edition © 2015
C00 01
0
1
Y
11 10AB
1
0
0
0
0
0
0
1
B C0 0
0 1
1 0
1 1
A0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
0
0
0
0
0
0
Y
• Circle 1’s in adjacent squares
• In Boolean expression, include only literals whose true and complement form are notin the circle
Y = AB
K-Map
Apoyo Unidad 1SistemasCombinacionales <45>
Digital Design and Computer Architecture: ARM® Edition © 2015
C 00 01
0
1
Y
11 10AB
ABC
ABC
ABC
ABC
ABC
ABC
ABC
ABC
1
B C Y0 0 0
0 1 0
1 0
1 1 1
Truth Table
C 00 01
0
1
Y
11 10ABA
0
0
0
0
0 0 0
0 1 0
1 0 0
1 1 1
1
1
1
1
K-Map
3-Input K-Map
Apoyo Unidad 1SistemasCombinacionales <46>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Complement: variable with a bar over it
A, B, C
• Literal: variable or its complement
A, A, B, B, C, C
• Implicant: product of literals
ABC, AC, BC
• Prime implicant: implicant corresponding to the largest circle in a K-map
K-Map Definitions
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Every 1 must be circled at least once
• Each circle must span a power of 2 (i.e. 1, 2, 4) squares in each direction
• Each circle must be as large as possible
• A circle may wrap around the edges
• A “don't care” (X) is circled only if it helps minimize the equation
K-Map Rules
Apoyo Unidad 1SistemasCombinacionales <48>
Digital Design and Computer Architecture: ARM® Edition © 2015
01 11
1
0
0
1
0
0
1
101
1
1
1
1
0
0
0
1
11
10
00
00
10AB
CD
Y
Y = AC + ABD + ABC + BD
0
C D0 0
0 1
1 0
1 1
B0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
0
1
1
1
YA0
0
0
0
0
0
0
0
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
0
0
0
0
0
4-Input K-Map
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Digital Design and Computer Architecture: ARM® Edition © 2015
0
C D0 0
0 1
1 0
1 1
B0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
0
X
1
1
YA0
0
0
0
0
0
0
0
0 0
0 1
1 0
1 1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
X
X
X
X
X
X
01 11
1
0
0
X
X
X
1
101
1
1
1
1
X
X
X
X
11
10
00
00
10AB
CD
Y
Y = A + BD + C
K-Maps with Don’t Cares
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Multiplexers
• Decoders
Combinational Building Blocks
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Selects between one of N inputs to connect to output
• log2N-bit select input – control input• Example: 2:1 Mux
Multiplexer (Mux)
Y
0 0
0 1
1 0
1 1
0
1
0
1
0
0
0
0
0 0
0 1
1 0
1 1
1
1
1
1
0
0
1
1
0
1
S
D0
YD
1
D1
D0
S Y
0
1 D1
D0
S
Apoyo Unidad 1SistemasCombinacionales <52>
Digital Design and Computer Architecture: ARM® Edition © 2015
2-<52>
• Logic gates– Sum-of-products form
Y
D0
S
D1
D1
Y
D0
S
S00 01
0
1
Y
11 10
D0
D1
0
0
0
1
1
1
1
0
Y = D0S + D
1S
• Tristates– For an N-input mux, use N
tristates
– Turn on exactly one to select the appropriate input
Multiplexer Implementations
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Digital Design and Computer Architecture: ARM® Edition © 2015
2:4
Decoder
A1
A0
Y3
Y2
Y1
Y0
00011011
0 0
0 1
1 0
1 1
0
0
0
1
Y3
Y2
Y1
Y0
A0
A1
0
0
1
0
0
1
0
0
1
0
0
0
• N inputs, 2N outputs
• One-hot outputs: only one output HIGH at once
Decoders
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Digital Design and Computer Architecture: ARM® Edition © 2015
Y3
Y2
Y1
Y0
A0A1
Decoder Implementation
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Discrete voltages represent 1 and 0
• For example:
– 0 = ground (GND) or 0 volts
– 1 = VDD or 5 volts
• What about 4.99 volts? Is that a 0 or a 1?
• What about 3.2 volts?
Logic Levels
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Digital Design and Computer Architecture: ARM® Edition © 2015
• Range of voltages for 1 and 0
• Different ranges for inputs and outputs to allow for noise
Logic Levels
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Digital Design and Computer Architecture: ARM® Edition © 2015
Driver Receiver
Forbidden
Zone
NML
NMH
Input CharacteristicsOutput Characteristics
VO H
VDD
VO L
GND
VIH
VIL
Logic High
Input Range
Logic Low
Input Range
Logic High
Output Range
Logic Low
Output Range
High Noise Margin: NMH = VOH – VIH
Low Noise Margin: NML = VIL – VOL
Noise Margins
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Digital Design and Computer Architecture: ARM® Edition © 2015
VDD
V(A)
V(Y)
VOH
VDD
VOL
VIL, V
IH
0
A Y
VDD
V(A)
V(Y)
VOH
VDD
VOL
VIL
VIH
Unity Gain
Points
Slope = 1
0V
DD / 2
Ideal Buffer: Real Buffer:
NMH = NML = VDD/2
DC Transfer Characteristics
NMH, NML < VDD/2
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Digital Design and Computer Architecture: ARM® Edition © 2015
Forbidden
Zone
NML
NMH
Input CharacteristicsOutput CharacteristicsV
DD
VO L
GND
VIH
VIL
VO H
A Y
VDD
V(A)
V(Y)
VOH
VDD
VOL
VIL
VIH
Unity Gain
Points
Slope = 1
0
DC Transfer Characteristics
Apoyo Unidad 1SistemasCombinacionales <60>
Digital Design and Computer Architecture: ARM® Edition © 2015
• In 1970’s and 1980’s, VDD = 5 V
• VDD has dropped– Avoid frying tiny transistors
– Save power
• 3.3 V, 2.5 V, 1.8 V, 1.5 V, 1.2 V, 1.0 V, …– Be careful connecting chips with different
supply voltages
VDD Scaling
Apoyo Unidad 1SistemasCombinacionales <61>
Digital Design and Computer Architecture: ARM® Edition © 2015
Logic Family VDD VIL VIH VOL VOH
TTL 5 (4.75 - 5.25) 0.8 2.0 0.4 2.4
CMOS 5 (4.5 - 6) 1.35 3.15 0.33 3.84
LVTTL 3.3 (3 - 3.6) 0.8 2.0 0.4 2.4
LVCMOS 3.3 (3 - 3.6) 0.9 1.8 0.36 2.7
Logic Family Examples
Apoyo Unidad 1SistemasCombinacionales <62>
Digital Design and Computer Architecture: ARM® Edition © 2015
CMOS Gates: NOT Gate
NOT
Y = A
A Y0 1
1 0
A Y
VDD
A Y
GND
N1
P1
A P1 N1 Y
0 ON OFF 1
1 OFF ON 0
Apoyo Unidad 1SistemasCombinacionales <63>
Digital Design and Computer Architecture: ARM® Edition © 2015
A
B
Y
N2
N1
P2 P1
NAND
Y = AB
A B Y0 0 1
0 1 1
1 0 1
1 1 0
AB
Y
A B P1 P2 N1 N2 Y
0 0 ON ON OFF OFF 1
0 1 ON OFF OFF ON 1
1 0 OFF ON ON OFF 1
1 1 OFF OFF ON ON 0
CMOS Gates: NAND Gate
Apoyo Unidad 1SistemasCombinacionales <64>
Digital Design and Computer Architecture: ARM® Edition © 2015
537410
= 5 × 103 + 3 × 102 + 7 × 101 + 4 × 100
five
thousands
10
's c
olu
mn
10
0's
co
lum
n
10
00
's c
olu
mn
three
hundreds
seven
tens
four
ones
1's
co
lum
n
11012 = 1 × 23 + 1 × 22 + 0 × 21 + 1 × 20 = 13
10one
eight
2's
co
lum
n
4's
co
lum
n
8's
co
lum
n
one
four
no
two
one
one
1's
co
lum
n
• Decimal numbers
• Binary numbers
Number Systems
Apoyo Unidad 1SistemasCombinacionales <65>
Digital Design and Computer Architecture: ARM® Edition © 2015
• 20 = 1
• 21 = 2
• 22 = 4
• 23 = 8
• 24 = 16
• 25 = 32
• 26 = 64
• 27 = 128
• 28 = 256
• 29 = 512
• 210 = 1024
• 211 = 2048
• 212 = 4096
• 213 = 8192
• 214 = 16384
• 215 = 32768
Powers of Two
Handy to memorize up to 29
Apoyo Unidad 1SistemasCombinacionales <66>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Binary to decimal conversion:– Convert 100112 to decimal
– 16×1 + 8×0 + 4×0 + 2×1 + 1×1 = 1910
• Decimal to binary conversion:– Convert 4710 to binary
– 32×1 + 16×0 + 8×1 + 4×1 + 2×1 + 1×1 = 1011112
Number Conversion
Apoyo Unidad 1SistemasCombinacionales <67>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Base 16
• Shorthand for binary
Hexadecimal Numbers
Apoyo Unidad 1SistemasCombinacionales <68>
Digital Design and Computer Architecture: ARM® Edition © 2015
Hexadecimal Numbers
Hex Digit Decimal Equivalent Binary Equivalent
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 4 0100
5 5 0101
6 6 0110
7 7 0111
8 8 1000
9 9 1001
A 10 1010
B 11 1011
C 12 1100
D 13 1101
E 14 1110
F 15 1111
Apoyo Unidad 1SistemasCombinacionales <69>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Hexadecimal to binary conversion:– Convert 4AF16 (also written 0x4AF) to binary
– 0100 1010 11112
• Hexadecimal to decimal conversion:– Convert 4AF16 to decimal
– 162×4 + 161×10 + 160×15 = 119910
Hexadecimal to Binary Conversion
Apoyo Unidad 1SistemasCombinacionales <70>
Digital Design and Computer Architecture: ARM® Edition © 2015
• Bits
• Bytes & Nibbles
• Bytes
10010110nibble
byte
CEBF9AD7least
significant
byte
most
significant
byte
10010110least
significant
bit
most
significant
bit
Bits, Bytes, Nibbles…
Apoyo Unidad 1SistemasCombinacionales <71>
Digital Design and Computer Architecture: ARM® Edition © 2015
10010101+
1110
1
10110110+
10001
111
• Add the following 4-bit binary numbers
• Add the following 4-bit binary numbers
Overflow!
Binary Addition Examples