The GANDALF Multi-ChannelTime-to-Digital Converter (TDC)

Sebastian Schopferer

University of Freiburg

TIPP 2011, Chicago

June 13, 2011

GANDALF module

TDC concepts

TDC implementation in the FPGA

measurements

Sebastian Schopferer 2

The GANDALF module

June 13, 2011

VME64x Interface

USB 2.0

S-Link Interfaceto DAQ

VITA 41.0VXS Interface

TCS

Memory:

144 Mbit QDRII+,

4 Gbit DDR2

Virtex-5 SX95T FPGA for Data Processing:

60k CLB flip-flops,

8 Mbit Block RAM,

640 DSP Slices,

500 MHz

mezzaninecard slot 1

Generic Advanced Numerical Device for Analog and Logic Functions

mezzaninecard slot 2

Virtex-5 LX30T FPGA for Memory Control

& Data Output:

20k CLB flip-flops,

1.2 Mbit Block RAM,

500 MHz

Sebastian Schopferer 3

The GANDALF module

June 13, 2011

GANDALF transient recorder• 16 analog inputs for A/D conversion (500 MS/s @ 12 bit)• optional time-interleaved mode: 8 channels with 1000 MS/s• real-time pulse shape analysis with online feature extraction (time resolution up to 10 ps)

GANDALF with digital inputs / outputs• 128 differential inputs or outputs• module functionality is free programmable in the FPGA• e.g. time-to-digital converter, scaler, mean-timer, coincidence matrix, pattern generator• combinations of these functionalities are possible for cost efficient design

Sebastian Schopferer 4

Digital Mezzanine Card (DMC)

June 13, 2011

• buffer card to convert signal levels and

protect FPGA from short circuits and ESD

• 2 x 32-channel VHDCI connectors

• 64 differential inputs (e.g. LVDS, LVPECL) or

64 differential outputs (LVDS)

• 1x NIM input, 2x NIM outputs

• jitter < 20 ps (including FPGA inputs)

Sebastian Schopferer 5

GANDALF TDC design objectives

June 13, 2011

more about the GANDALF module:http://hadron.physik.uni-freiburg.de/gandalf/

128 TDC channels per board

time resolution better than 100 ps rms

leading and/or trailing edge sensitivity

multi-hit capability

10 ns double hit resolution

18 bit dynamic range

20 µs look-ahead / look-back hit buffer

programmable trigger window

dead-time free data readout

Sebastian Schopferer 6

TDC concepts

June 13, 2011

Shifted Clock Sampling

equidistant delay of data signal ∆tdelay = 1/(n*fclk )

same clock signal at all flip-flops

equidistant phase shift of clock signal φdelay = 2π/n

same data signal at all flip-flops

Delayed Data Sampling

sampling of data signal TDC bin width = 1/fmax ≈ 2 nsfmax : 500 MHz (Virtex-5)

reduce TDC bin width by:

Trivial concept of TDC

Sebastian Schopferer 7

Shifted Clock Sampling

June 13, 2011

bit pattern “11000000” hit detected!

time(TDC bin) = clk_counter * 8 + ‘bitswap’ position

Hit

8 phase shifted TDC clocks

8 TDC flip-flops

data signal

check for ‘bit pattern’ ≠ “00000000” or “11111111”

output register

Sebastian Schopferer 8

Partitions

June 13, 2011

eight different clock domains- register outputs are not stable simultaneously- readout not possible at a single point in time

“partitions” are introduced to merge the clock domains

in a two-stage process

1

2

5

6

7

3part

itio

n 1

‘overlap’ avoids loss of hits!

part

itio

n 0

0

4

Setup & hold

Setup & hold readout

readout

012345670

Sebastian Schopferer 9

Implementation

June 13, 2011

Challenge accuracy of TDC bin width influenced by

clock „phase error“

„routing delay“ of data signal

8 TDC-flip-flops

rout

ing

re

sou

rce

sro

utin

g

of d

ata

sign

al

to T

DC

fli

p-flo

ps

placement is user-controlled by scripts

auto-router finds appropriate connections

Sebastian Schopferer 10

Implementation

June 13, 2011

clock 0ºclock 90ºclock 180ºclock 270º

clock 45ºclock 135ºclock 225ºclock 315º

PLL 1

PLL 2

Phase-shifted clocks produced by two PLLs

Sebastian Schopferer 11

Trigger Matching

June 13, 2011

time stamp measurements

select only hits within a time window around a trigger signal

trigger signal can be related to data in the past (“look-back”) or

in the future (“look-ahead”)

hit data storage inside FPGA needed

max. latency: 20

µs

HIT FIFO depth: 1k

Sebastian Schopferer 12

TDC overview

June 13, 2011

TDC register (8 flip-flops)

clk0 clk3clk1 clk4clk2 clk6clk5 clk7

partition 0 partition 1

Hit Buffer

RAM

TriggerTrigger Matching

Output FIFO

TD

C c

han

ne

l

Clock Counter

Data

merge 128 channels

DAQ

Sebastian Schopferer 13

FPGA resource usage

June 13, 2011

average resource usage per TDC channel

1 TDC channel

Sebastian Schopferer 14

Measurement Setup

June 13, 2011

Pattern Output(LVDS)

TDC Input(LVDS)

TCS in

TDC GANDALF(input)

Pattern Generator (output)

clock frequency 388.8 MHz

8 phase-shifted clocks

TDC bin width: 320 ps

Sebastian Schopferer 15

Measurements

June 13, 2011

no

t o

pti

miz

ed:

op

tim

ized

:

PLL1

PLL2

Differential Nonlinearity

Sebastian Schopferer 16

Extension to 16 TDC bins

June 13, 2011

part

itio

n 1

partitio

n 0

12

5

67

3

0

4

12

5

67

3

0

4

rising-edge-triggered

falli

ng-e

dge-

trig

gere

d

clock frequency 388.8 MHz

2 flip-flops per slice

8 phase-shifted clocks

+ 8 inverted clocks

TDC bin width: 160 ps

Sebastian Schopferer 17

128 channels with 16 TDC bins

June 13, 2011

Differential Nonlinearity

Sebastian Schopferer 18

TDC time resolution

June 13, 2011

RMS of the time stamp difference between ‘channel n’ and the mean of all other channels:

TDC time resolution < 0.5 * LSB = 80 ps

for comparison:resolution of ideal TDC =1 / sqrt(12) * LSB = 46 ps

Sebastian Schopferer 19

Conclusion

June 13, 2011

design objectives achieved:

128 TDC channels in the GANDALF Virtex-5 FPGA

TDC bin width: 160 ps

DNL < 0.2 LSB = 32 ps

time resolution < 80 ps rms

under progress:

integrate 128 scaler channels into the same design

inter-board communication via VXS for fast trigger decisions

design migration to Artix-7 or Kintex-7 (front-end solution)

more about the GANDALF module:http://hadron.physik.uni-freiburg.de/gandalf/