THE INSTITUTION OF ENGINEERS, SRI LANKAIESL ENGINEERING COURSE

PART II EXAMINATION - JULY 2012

210 ELECTRON[CS

Instructions: This question paper contains eight questions In ten pages. Answer fivequestions only. Tentative mark allocation for each part is shown in brackets for guidanceonly.

Time: Three hours.

Question 01

a) Sketch and label the typical V-I characteristic of a typical diode and indicate thebreakdown voltage, reverse saturation current, cutting voltage, knee current, rectifierdiode region and zener diode region.

[6 marks]

b) Consider the circuit of Figure Q.l (b). The capacitors are very large, so they dischargeonly a very small amount per cycle. Sketch the voltage at point A vs. time .Find thevoltage across the load. What is the peak inverse voltage across each diode?

[6 marks]

+A

V Sin(wt)m

+C

LR

LD1

Figure Q.l (b)

c) In the circuit shown in Figure Q.l (c) the zener diode is used to protect theGalvanometer which has 200flA fall scale rating and 5600 internal resistance. Itshould show full deflection when V; = 20v and if V, is increased beyond 20v, the

current in the galvanometer should remain constant at 200 flA. Find the value ofR, and R2•

[8 marks]

Page 1 of 10

v

V =16Vz

Im

200llA

Figure Q.l (c)

Question 02

a) Explain the function of each component (R" R2, Rc, Re, C" C2 and Ce) as shown in theFigure Q.2 (a).

[6 marks]

•

Vout

Figure Q.2 (a)

Page 2 of 10

[6 marks]

b) Consider the circuit shown in Figure Q.2 (b). Find RJ and Rc, if a bias point ofVCE=5V and Ic=2mA is required.

c) Consider the common-emitter amplifier of Figure Q.2(c). Draw the DC equivalentcircuit and find IcQ. Find the value of r, Then calculate values for Av, Avo, Zin, A, Gand ZOo Assume operation is in the mid-band region for which the coupling and bypasscapacitors are short circuits.

[8 marks]

+15V

R c

RI lOkQ 10--..C1+ '-':1[= O.7V

jF·IOO

V RLout

V in R2 4.7kQ

IOOkQ

-15V

1.1(;. Rs

ioon

+15V

V:1E= O.7V~=IOO

Figure Q.2 (b)

Figure Q.2(c)

Page 3 of 10

Question 03:

a) List the characteristics of an ideal Op-Amp and define the term common mode rejectionratio (CMRR) of a differential amplifier. Why is it desirable for an Op-Amp to have aCMRR?

[6 marks]

b) Figure Q.3 (b) shows a version of the inverting amplifier that can have high gainmagnitude. Derive an expression for the voltage gain under the ideal op amp assumption.Also, find the input impedance and output impedance. Evaluate the results for R, = R3 =1kQ and R2 = R, = 10 kQ.

[6 marks]

+

Vin+ y.

\ .. 1RL

1 -:- -:-

Figure Q.3 (b)

c) Calculate the overall voltage gain for the instrumentation amplifier in Figure Q.3 (c),where VI = 10 mV, V2 = 10 rnV, R =1SkQ, R, = 1S0Q, R2 = 33kQ. Also determine thecurrent and voltage levels throughout the circuit when +1V common mode input (V eM) isgiven along with the ± 10m V signals. Explain the voltage level at point A.

[8 marks]

Page 4 of 10

+

V I

t. RR,

R RI

/\+

RV .-

RI 1R2

+ .-----------------~

v~

1Figure Q.3 (c)

Question 04

a) Explain the selection of a Q-point on FET dc load line, and discuss the limitations on theoutput voltage swing.

[6 marks]

b) Draw the small-signal mid-band equivalent circuit to the given MOSFET amplifier circuitin Figure Q.4 (b). Assume that rd = <.X) and derive expressions for the voltage gain, input

resistance, output resistance and evaluate the expressions, where R = IOOkO,RJ = IOOkO, RD = 3kO, RL = IOkO, VDD = 20V , V,o = 5V and K = ImAIV2.

[8 marks]

Page 5 of 10

+vDD

[6 marks]

Figure QA (b)

c) Find the values of gm and rd for the characteristics of Figure QA (c) at a Q point of

VCSQ = 2.5V and VDSQ = 6V .

i (m.A)D

12.0

10.0VGS=14·0 ~--

.: ~I

3.5I; /

/ ~ I:

II 3.0 ;

i!

J,V ,2.5 j

"" It •...v!

1.5 iI

8.0

6.0

4.0

2.0

o 2 10 124 6 8Figure QA (c)

Page 6 of 10

a) Negative feedback is produced by feeding a portion of an amplifier output back to theinput where it behaves as an additional signal. List at least two advantages of usingnegative feedback. Derive an equation for the overall voltage gain of the feedbackamplifier shown in the Figure Q.5 (a), in which Vi is amplified to produce Va. Av and Brepresent open loop gain and feedback factor respectively.

Question 05

+._------iv.'1

[6 marks]

+

B

Figure Q.5 (a)

b) Calculate the closed-loop gain for the negative feedback amplifier shown in the FigureQ.5 (a). Also calculate the closed loop gain when the open-loop gain is changed by ±50%.Note that Av = 100000 and B = 11100.

[6 marks]

c) The Wein bridge oscillator in Figure Q.5 (c) has the following components:

R, = R2 = R4 = 5.6kQ. R3 = 12kQ. C1 = C2 = 2700pF. Calculate the oscillating frequency.

[8 marks]

Page 7 of 10

v,>-----. V

"

C2

Figure Q.5 (c)

Question 06:

a) Describe programmable array logic (PAL) and Programmable logic array (PLA) devices.[4 marks]

b) Using PAL, show how you can implement the minimized sum of product function for thefollowing.

F(A,B,C,D)= I(O,1,2,3,7,8,9,ll,12,15)

[8 marks]

c) Define Fan-out, Fan-in, and Propagation Delay. Given the network in below FigureQ.6(c),what is the worst case propagation delay?

f:.J; = IOns

f:.f2 = 20ns

f:.f3 = 25ns

f:.f4 = IOns

[8 marks]

Page 8 of 10

r-------------------------------·II

II.- I "/f\...••. . csI 1IIII 1'1 !---I w 4I

I

II \/- D ?-- I

.tJ

II -I ~f I .-I ..•.- 3 I- . II I

[6 marks]

IIL ~

Figure Q.6 (c)

Question 07

a) Find the minimum sum of products (SOPs) and product of sums (POSs) form of thefollowing functions using Karnaugh maps:

I. F(A,B,C,D) = ~)1,3,5, 7,9,11)

II. F(A, B, C, D) = L (5, 7, 9, 10,11) +de- terms(2, 13, 15)

(de. terms = don't-care terms)[6 marks]

b) Design a 2-bit full adder with minimum hardware using standard 2-input gates available inlogic families. Clearly show the steps of your design.

c) Implement the following logic function using a 4-input multiplexer with a rmrumumnumber of basic logic gates (AND, OR, NOT).

F(A, B, C, D) = L (5, 7, 9,10,11) +de· terms(2,13,15)[8 marks]

Page 9 of 10

Question 08

a) Carry out the following conversions.i. Convert a J-K Flip-Flop to a D Flip-Flop.

II. Convert a J-K Flip-Flop to a T Flip-Flop.[4 marks]

b) A master-slave J-K flip-flop is shown in Figure Q.8 (b). Assuming that the initialcondition of the flip-flop is J=K=Qm = Q, = 0, trace the logic levels through the diagramfor the following changes (N.B. changes in J and K take place in the time intervalsbetween clocks pulse).

i. J,O ~ l;k,O ~ 0 clock pulse 1 appliedII. J,1 ~ O;k,O ~ I clock pulse 2 applied

III. J,O~O;k,I~O clock pulse 3 appliedIV. J,O ~ l;k,O ~ 0 clock pulse 4 applied

Draw a timing diagram displaying the J,K,Qm,Q, waveforms for the period of four clock

pulses.

[8 marks]

Figure Q.8 (b)

c) Design a decade counter usmg a four stage shift register having the following statesequence.0000 ~ 000 I ~ 00 I I ~ 0 II 1~ 1 I 1 1~ 1110 ~ I 101 ~ I 010 ~ 01 00 ~ 1000

[8 marks]

Page10of10