The Instruction Set Architecture Level

Dept. of Computer ScienceVirginia Commonwealth University

CMSC 312 Computer Organization 2 Hongsik Choi

ISA level

Interface between the software and hardwareCommon intermediate form

Build H/W, execute ISA program directly

Build compiler Build compiler

CMSC 312 Computer Organization 3 Hongsik Choi

5.1. properties

Defined by how the machine appears to a machine language programmer

Memory model, registers, data types and instructions, etc

CMSC 312 Computer Organization 4 Hongsik Choi

5.1.2 Memory Models

Memory: collection of addressable cells

Byte: ASCII

Unicode

CMSC 312 Computer Organization 5 Hongsik Choi

5.1.2 Memory Models

Aligned?

Single Linear address space?

Memory semantics

Data ProgramRead/write

Serialized/Sync instruction

CMSC 312 Computer Organization 6 Hongsik Choi

5.1.3 Registers

Registers – visible to micro architecture level

Some are visible to ISA Level (\TOS, MAR)

special purpose (SP, PC)

control registers for kernel mode

PSW (Program Status Word)

condition codes (bits in PSW)

N,Z,V,C,A,P

general purpose (local variables, etc)

CMSC 312 Computer Organization 7 Hongsik Choi

5.1.3 Instructions

Load, store

MoveArithmetic

Logic

CMSC 312 Computer Organization 8 Hongsik Choi

5.1.5 Pentium 4 ISA level

Level 0 : kernel mode

Level1:

Level2:

Level 4: User mode

232

0 213 -1

CMSC 312 Computer Organization 9 Hongsik Choi

5.1.5 Pentium 4 ISA level

Main arithmetic register

Good for holding pointers

Play a role in looping

For * and /

Pointer(M) to the source

Pointer(M) to the destination

Base of current stack frame

Stack pointer

Segment registers

Instruction Pointer (PC)

PSW

CMSC 312 Computer Organization 10 Hongsik Choi

5.1.6 UltraSPARC III ISA Level

RISC machine

264

32 64bit GPR and 32 bit floating point registers

FP: Frame pointer

SP: stack pointer

CWP: current window pointer

Multiple GPRs set

Only STORE, LOAD can

access memory

CMSC 312 Computer Organization 11 Hongsik Choi

5.1.6 UltraSPARC III ISA Level

1. Emulate stack w/ Procedure call

2. Fast parameter passing

8 Global registers

CMSC 312 Computer Organization 12 Hongsik Choi

5.1.7 8051 ISA Level (embedded system)

One chip with CPU, memory and I/O controller

64K for data

64k for programs ROM

RAM

For rapid interrupt

processing

8 bit R0 to R7

128

255Special registers

Such as accumulator (240)

CMSC 312 Computer Organization 13 Hongsik Choi

5.2 Data Types at the ISA level

,meaning data types supported by hardware

Numerical data types, (232-1, or 231-1,

Non numerical data types,

Data types on the Pentium 4, SPARC and 8051

n = f x 10e , fraction( or mantissa), exponent

3.14 = 0.314 × 101 = 3.14 × 1000.000001 = 0.1 × 10−5 = 1.0 × 10−61941 = 0.1941 × 104 = 1.941 × 103

CMSC 312 Computer Organization 14 Hongsik Choi

5.2.1. Numerical data types

Integer( unsigned 232-1, or signed 231-1) n = f x 10e , fraction( or mantissa), exponent

3.14 = 0.314 × 101 = 3.14 × 1000.000001 = 0.1 × 10−5 = 1.0 × 10−61941 = 0.1941 × 104 = 1.941 × 103

F = 3 digit in the range of 0.1 <= f < 1, e = zero and signed 2 digit

-0.999x1099, -0.100x10-99, 0, 0.100x10-99, 0.999 x 1099

Real N = continuum

Floating P N = 2* 179100 + 1

Rounding (nearest number)

0.9998x1099 vs 0.999x1099

CMSC 312 Computer Organization 15 Hongsik Choi

5.2.2. Nonumerical data types

ASCII(7) vs UNICODE(16)

Boolean

Machine address

CMSC 312 Computer Organization 16 Hongsik Choi

5.2.3. Pentium, Sparc, and 8051

CMSC 312 Computer Organization 17 Hongsik Choi

5.3. Instruction Format

CMSC 312 Computer Organization 18 Hongsik Choi

5.3.1 Design criteria for instructionFormats

Size of instruction?

n-16 bit instruction vs n -32 bit instruction

Memory size, fetch speed vs harder to decode, more time to decode and execute

Accommodate all the operation desired.

2n operation with n-1 bit?

Size of address field?

Memory (232 bytes)

If 8bit byte as a basic unit of word vs 32 bit word vs 1 bit (Burroughs B1700)

Resolutionshorter address means shorter instruction vs.

Waste space,

Extra comparison

CMSC 312 Computer Organization 19 Hongsik Choi

5.3.2 Expanding Opcodes

(n+k) bit instrcution

If 2n memory cell, we have only 2k opcodes

With 16 registers

What if we have15 three address instn, 14 two address instn, 31 one address instn and 16 no address instn?

Size of instruction n-16 bit instruction vs n -32 bit instruction

Memory size, fetch speed vs harder to decode, more time to decode and execute

CMSC 312 Computer Organization 20 Hongsik Choi

5.3.2 Expanding Opcodes

We have variable size opcode to make the unit size instructions.

Variable size instruction is hard to decode, even hard to align on byte boundaries

CMSC 312 Computer Organization 21 Hongsik Choi

5.3.3. case studies

1,2,3 byte