the instruction set architecture level...reverse polish notation figure 5-20. each railroad car...
TRANSCRIPT
The Instruction SetArchitecture Level
Chapter 5
ISA Level
Figure 5-1. The ISA level is the interface between the compilers and the hardware.
Memory Models
Figure 5-2. An 8-byte word in a little-endian memory. (a) Aligned. (b) Not aligned. Some machines
require that words in memory be aligned.
Registers
Condition codes for PSW:
N—Set when the result was Negative.
Z — Set when the result was Zero.
V—Set when the result caused an oVerflow.
C — Set when the result caused a Carry out of the leftmost bit.
A — Set when there was a carry out of bit 3
P — Set when the result had even Parity.
Overview of the Core i7 ISA Level
Figure 5-3. The Core i7’s primary registers.
Overview of the OMAP4430 ARM ISA Level
Figure 5-4. The version 7 ARM’s general registers.
Overview of the ATmega168 AVR ISA Level
Figure 5-5. On-chip register and memory organization for the ATmega168
Data Types on the Core i7
Figure 5-6. The Core i7 numeric data types. Supported types are marked with ×. Types marked with ‘‘64-bit’’ are only supported in 64-bit mode.
Data Types on the OMAP4430 ARM CPU
Figure 5-7. The OMAP4430 ARM CPU numeric data types. Supported types are marked with ×.
Data Types on the ATmega168 AVR CPU
Figure 5-8. The ATmega168 numeric data types. Supported types are marked with ×.
Instruction Formats
Figure 5-9. Four common instruction formats: (a) Zero-address instruction. (b) One-address instruction (c) Two-address
instruction. (d) Three-address instruction.
Design Criteria for Instruction Formats
Figure 5-10. Some possible relationships between instruction and word length.
Expanding Opcodes (1)
Figure 5-11. An instruction with a 4-bit opcode and three 4-bit address fields.
Expanding Opcodes (2)
Figure 5-12. An expanding opcode allowing 15 three-address instructions, 14 two-address instructions, 31 one-address
instructions, and 16 zero-address instructions. The fields marked xxxx, yyyy, and zzzz are 4-bit address fields.
The Core i7 Instruction Formats
Figure 5-13. The Core i7 instruction formats.
OMAP4430 ARM CPU Instruction Formats
Figure 5-14. The 32-bit ARM instruction formats.
ATmega168 AVR Instruction Formats
Figure 5-15. The ATmega168 AVR instruction formats.
Immediate Addressing
Figure 5-16. An immediate instruction for loading 4 into register 1.
Register Indirect Addressing
Figure 5-17. A generic assembly program for computing the sum of the elements of an array.
Indexed Addressing (1)
Figure 5-18. A generic assembly program for computing the OR of Ai AND Bi for two 1024-element arrays.
Indexed Addressing (2)
Registers needed for program of 5-18:
R1—Holds accumulated OR of Boolean product terms.
R2—Index, i, used to step through arrays.
R3—Constant 4096, lowest value of i not to use.
R4 — Scratch register for holding each product as it is formed.
Indexed Addressing (3)
Figure 5-19. A possible representation of MOV R4,A(R2).
Stack AddressingReverse Polish Notation
Figure 5-20. Each railroad car represents one symbol in the formula to be converted from infix to reverse Polish notation.
Reverse Polish Notation (1)
Figure 5-21. Decision table used by the infix-to-reverse Polish notation algorithm
Reverse Polish Notation (2)
The numbers in chart of 5-21 refer to the following situations:
Car at switch heads toward Texas
Most recent car on Texas line turns, goes to California
Both car at switch and most recent car on Texas line diverted, disappear (deleted)
Stop. Symbols now in California represent reverse Polish notation formula when read left to right
Stop. Error has occurred. Original formula not correctly balanced.
Reverse Polish Notation (3)
Figure 5-22. Some examples of infix expressions and their reverse Polish notation equivalents.
Evaluation of Reverse Polish Formulas
Figure 5-23. Use of a stack to evaluate a reverse Polish notation formula.
Orthogonality of Opcodes and Addressing Modes (1)
Figure 5-24. A simple design for the instruction formats
of a three-address machine.
Orthogonality of Opcodes and Addressing Modes (2)
Figure 5-25. A simple design for the instruction formats of a two-address machine.
The Core i7 Addressing Modes (1)
Figure 5-26. The Core i7 32-bit addressing modes. M[x] is the memory word at x.
The Core i7 Addressing Modes (2)
Figure 5-27. Access to a[i].
Discussion of Addressing Modes
Figure 5-28. A comparison of addressing modes.
Dyadic Operations (1)
Use AND with a mask to extract bits from a word.
Dyadic Operations (2)
Use of OR with mask to pack bits into a word
Monadic Operations
Shifting or rotating bits
Comparisons and Conditional Branches
Three-bit binary numbers can be
ordered in one of two ways. From smallest to largest:
Loop Control
Figure 5-29. (a) Test-at-the-end loop. (b) Test-at-the-beginning loop.
Input/Output (1)
Three different I/O schemes are in current use in PCs:
• Programmed I/O with busy waiting• Interrupt-driven I/O• DMA I/O
Input/Output (2)
Figure 5-30. Device registers for a simple terminal.
Input/Output (3)
Figure 5-31. An example of programmed I/O.
Input/Output (4)
Figure 5-32. A system with a DMA controller.
The Core i7 Instructions
Figure 5-33. A selection of the Core i7 integer instructions. (1 of 4)
The Core i7 Instructions
Figure 5-33. A selection of the Core i7 integer instructions. (2 of 4)
The Core i7 Instructions
Figure 5-33. A selection of the Core i7 integer instructions. (3 of 4)
The Core i7 Instructions
Figure 5-33. A selection of the Core i7 integer instructions. (4 of 4)
The OMAP4430 ARM CPU Instructions
Figure 5-34. The primary OMAP4430 ARM CPU integer instructions. (1 of 2)
Comparison of Instruction Sets
Figure 5-35. The ATmega168 AVR
instruction set. (1 of 3)
Comparison of Instruction Sets
Figure 5-35. The ATmega168 AVR
instruction set. (2 of 3)
Comparison of Instruction Sets
Figure 5-35. The ATmega168 AVR
instruction set. (3 of 3)
The OMAP4430 ARM CPU Instructions
Figure 5-34. The primary OMAP4430 ARM CPU integer instructions. (2 of 2)
Sequential Flow of Control and Branches
Figure 5-36. Program counter as a function of time (smoothed). (a) Without branches. (b) With branches.
Procedures (1)
Figure 5-37. Initial configuration for the Towers of Hanoi problem for five disks.
Procedures (2)
Figure 5-38. The steps required to solve the Towers of Hanoi for three disks. (1 of 4)
Procedures (2)
Figure 5-38. The steps required to solve the Towers of Hanoi for three disks. (2 of 4)
Procedures (2)
Figure 5-38. The steps required to solve the Towers of Hanoi for three disks. (3 of 4)
Procedures (2)
Figure 5-38. The steps required to solve the Towers of Hanoi for three disks. (4 of 4)
Procedures (3)
Figure 5-39. A procedure for solving the Towers of Hanoi
Procedures (4)
Figure 5-40. The stack at several points during the execution of Fig. 5-39.
Coroutines (1)
Figure 5-41. When a procedure is called, execution of the procedure always begins at the first statement of the procedure.
Coroutines (2)
Figure 5-42. When a coroutine is resumed, execution begins at the statement where it left off the previous time,
not at the beginning.
Interrupts (1)Hardware Actions:
• Device controller asserts interrupt line on system bus to start interrupt sequence
• When CPU is prepared to handle interrupt, it asserts interrupt acknowledge signal on bus
• When the device controller sees interrupt signal acknowledged, puts small integer on data lines to identify itself. This number called interrupt vector
• CPU removes interrupt vector from bus, saves temporarily
Interrupts (2)
• CPU pushes program counter and PSW onto stack
• CPU removes interrupt vector from bus, saves temporarily. Then CPU pushes program counter and PSW onto stack
• CPU locates new program counter by using interrupt vector as index into table in low memory
Interrupts (3)
Software Actions:
• Interrupt service routine saves all registers for restoration later
• Each interrupt vector shared by all devices of a given type, so
not yet known which terminal caused interrupt. Terminal
number can be found by reading some device register
• Other information about interrupt, can now be read in
Interrupts (4)
• Global variables, ptr and count, are updated. Former is incremented, to point to next byte, latter decremented, to indicate 1 byte fewer remains to be output. If count is still greater than 0, more characters to output. Copy one now pointed to by ptr to output buffer register
• If required, special code output to tell device or interrupt controller that interrupt has been processed.
• Restore all the saved registers
• Execute RETURN FROM INTERRUPT instruction, putting CPU back into mode and state it had just before interrupt happened. Computer then continues from where it was
Interrupts (5)
Figure 5-43. Time sequence of multiple-interrupt example.
The Towers of Hanoi in OMAP4430 ARM Assembly Language
Figure 5-44. The Towers of Hanoi for the Core i7. (1 of 3)
The Towers of Hanoi in OMAP4430 ARM Assembly Language
Figure 5-44. The Towers of Hanoi for the Core i7. (2 of 3)
The Towers of Hanoi in OMAP4430 ARM Assembly Language
Figure 5-44. The Towers of Hanoi for the Core i7. (3 of 3)
The Towers of Hanoi in OMAP4430 ARM Assembly Language
Figure 5-45. The Towers of Hanoi for the OMAP4430 ARM CPU. (1of 2)
The Towers of Hanoi in OMAP4430 ARM Assembly Language
Figure 5-45. The Towers of Hanoi for the OMAP4430 ARM CPU. (2of 2)
Instruction Scheduling (1)
Figure 5-46. The Itanium 2’s registers.
Instruction Scheduling (2)
Figure 5-47. An IA-64 bundle contains three instructions.
Reducing Conditional Branches: Predication (1)
Figure 5-48. (a) An if statement. (b) Generic assembly code for (a). (c) A conditional instruction.
Reducing Conditional Branches: Predication (2)
Figure 5-49. (a) An if statement. (b) Generic assembly code for (a). (c) Conditional execution.
Reducing Conditional Branches: Predication (3)
Figure 5-50. (a) An if statement. (b) Generic assembly code for (a). (c) Predicated execution.
End
Chapter 5