The ISA Level

• The Instruction Set Architecture (ISA) is positioned between the microarchtecture level and the operating system level. Historically, this was the only level. It is the interface between the software and the

hardware. Programs written in high-level languages (C,

C++, FORTRAN 90, etc.) are compiled into a common intermediate form - the ISA level -which the hardware executes directly.

The ISA Level

The ISA level is the interface between the compilers and the hardware.

The ISA Level

How do we decide what the ISA should support?

• Ideally, ask both hardware and software engineers the features they would like to have and reach a compromise.

• In practice, the most important feature is backward compatibility.

• A good ISA should should define a set of instructions that can be implemented effectively in current and future technologies.

• It should also provide a clean target for compiled code.

The ISA Level

For some architectures, the ISA level is specified by a formal defining document (e.g. both V9 SPARC and JVM).

• This allows different implementations of the same architecture.

• Such defining documents contain normativesections, which impose requirements, and informative sections, that are intended to help the reader but are not part of the formal specification.

• There is no formal defining document for the Pentium 4.

The ISA Level

There are at least two modes at the ISA level:• Kernel mode is intended to run the operating

system and allows all instructions to be executed.• User mode is intended to run application programs

and does not permit certain sensitive instructions to be executed.

All computers divide memory up into cells that have consecutive addresses.

• The most common cell size is 8 bits (called a byte).• The reason for using 8 bits is that ASCII codes are 7

bits (add one bit for parity).

Memory Models

Bytes are grouped into 4-byte (32 bit) or 8-byte (64 bit) words with instructions available for manipulating entire words. Many architectures require words to be aligned

on their natural boundaries.• This allows more efficient memory operations.• Reading words at arbitrary addresses requires extra

logic on the chip, making it bigger and more expensive.

• The Pentium 4 does not require alignment in order to retain compatibility with the 8088.

The ISA Level

An 8-byte word in a little-endian memory. (a) Aligned.(b) Not aligned.

Some machines require that words in memory be aligned.

Registers

• All computers have some registers visible at the ISA level. These control execution of the program hold temporary results are used for other purposes

• ISA level registers can be divided into two categories: special-purpose (PC, SP, etc.) general-purpose (local variables, etc.)

Registers

• One control register that is a hybrid kernel/user is the flags register or PSW (Program Status Word). This register contains various condition bits: N - Set when the result was Negative Z - Set when the result was Zero V - Set when the result caused an oVerflow C - Set when the result caused a Carry out of the leftmost

bit A - Set when there was a carry out of bit 3 (Auxiliary

carry) P - Set when the result had even parity

Pentium 4 ISA Level

The Pentium 4 has three operating modes, two of which make it look like an 8088. In real mode, features added since the 8088 are turned off.

• An application error causes the machine to crash.

Virtual 8086 mode makes it possible to run old 8088 programs in a protected way.

• A special isolated environment that acts like an 8088 is created, except that if the program crashes, the operating system is informed.

• Used when an MS-DOS window is opened.

Protected mode has four privilege levels controlled by bits in the PSW

Pentium 4 Registers

The first four registers are general-purpose:• EAX is the main arithmetic register.• EBX is good for holding pointers• ECX plays a role in looping• EDX is needed for multiplication and division

(holding half of the 64-bit products and dividends) These registers contain 8- and 16-bit registers

in the low-order bits for manipulation of 8- and 16-bit quantities, respectively.

Pentium 4 Registers

The next three registers are general-purpose:• ESI and EDI hold pointers into memory, especially

for the hardware string manipulation routines.• EBP is a pointer register (typically to the base of the

current stack frame, like LV in JVM).• ESP is the stack pointer.

CS through GS are segment registers. EIP is the program counter EFLAGS is the PSW.

Pentium 4 Primary Registers

The Pentium 4’s primary registers.

UltraSPARC III

• The SPARC architecture is a RISC architecture based on the research done at Cal-Berkeley.

• The memory structure is a linear array of 264

bytes (more than can currently be addressed).

• The UltraSPARC III has two groups of registers: 32 64-bit general-purpose registers 32 floating-point registers

UltraSPARC III General Registers

The UltraSPARC III’s general registers.

UltraSPARC III Register Windows

The UltraSPARC III actually has more than 32 general-purpose registers, although only 32 of them are visible to the program at a time.

This feature, known as Register Windows, is intended for the efficient support of procedure calls.

There are multiple sets of registers, which emulate the use of a stack.

The register CWP (Current Window Pointer) keeps track of which registers set is currently in use.

Register renaming is used to efficiently pass parameters.

UltraSPARC III Register Windows

Operation of theUltraSPARC IIIregister windows.

Pentium II Data Types

The Pentium II supports two’s complement integers, unsigned integers, binary coded decimal numbers, and IEEE 754 floating-point numbers It handles 8 and 16 bit integers as well. Operands do not have to be aligned in memory,

but better performance is obtained if they are. There are also instructions for manipulating 8-

bit ASCII character strings: copying and searching.

Pentium 4 Numeric Data Types

The Pentium 4 numeric data types. Supported types are marked with ×.

UltraSPARC III Data Types

The UltraSPARC III supports a wide range of data formats.

• For integers it supports 8-, 16-, 32-, and 64-bit operands, both signed and unsigned.

• Signed integers use two’s complement.• Floating point operands conform to the IEEE 754

standard.• BCD numbers are not supported.• All operands must be aligned in memory.• Character and string data types are not supported by

special instructions.

UltraSPARC III Numeric Data Types

The UltraSPARC III numeric data types. Supported types are marked with ×.