the mixed-signal modelling language vhdl-ams and its semantics (icnacsa 1999)

The mixed signal modelling languageVHDL-AMSand its semantics

P.T. BreuerUniversidad Carlos III de Madrid, ES [email protected]

8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 1

Contents1. What is this talk about?2. Core Language/Denotation3. Problems4. Simulator5. Conclusions8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 2

What is this talk about?

Q What is VHDL, what is VHDL-AMS, and what are XYZ semantics?A1 VHDL is an industry standard language for describing digital circuits.A2 VHDL-AMS is an IEEE extension for analog circuits.A3 Semantics are important for contractual reasons at leastI'll try and tell you about all of these, and emphasize the last.Why?8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 3

Semantics?� Formal semantics clarify and demystify� Form a basis for� further language development� implementations (compilers, interpreters, : : : )� Allow desirable properties to be formally veri�ed� such as: VHDL is extended conservatively� : : : reality is a scheduler �xpoint� : : :� Allow undesirable properties to be detected� ambiguity? parallelism is benign?� : : :8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 4

A strategy for programming language research

1. De�ne a spanning \core language" for VHDL-AMS2. Give it a denotational semantics3. : : : and an approximation semantics4. : : : and an abstract interpretation3. Reason about it4. Test ideas and correctness with implementations8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 5

What is a denotational semantics?It does not describe what a program does, except implicitly.It does not describe how it does it.It assigns a meaningful interpretation [e] to every element e ofthe programming language, and describes how they combine.Example: Variables \are" addresses in the memory space of a com-puter. Programs \are" sequences of machine instructions. Modules\are" digital circuits.Example: [x := 1] = ldA #1; stA [x];Example: [p1; p2] = [p1]; [p2].8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 6

What is VHDLIEEE std. 1076-1987. A baroque language loosely modelledon ADA.Features:Imperative! -like pascal, fortran or CLevels -behavioural, RTL, : : :Packages -pluggable circuits\Digital Signals"-a basic type/conceptParallelism -all works at onceMacros -recursive, yet, for layered structuresSheduling -signals have a timewise componentAn elaborated VHDL \model" is a set of \process" de�nitions.Processes do not contain other processes, just imperative codeand signalling.8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 7

More about VHDLHardware component = processWire (content) = signalWire (conection) = import/exportProcess bodies contain ordinary imperative language con-structs plus two special kinds of scheduling statement.signal assignment C <= transport (not C) after dlywait statement wait on C,D,E until X=1 for 10nsprocess nanosecond oscillator (C out)beginC <= transport not C after 1ns ;wait on C ;end8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 8

VHDL semanticsStatements a�ect Schedule,maybe non-deterministically.[Statement] = Sched$SchedSched=(WorldLine,TimePoint)Each World is \a state of themachine" at that moment.WorldLine = Time!StateState = (Var[Signal)!ValTimePoint = TimeX=0

X=0

X=0

X=0

X=1

T=1

T=2

T=3

X=0X=0 T=0

X=0X=0 T=-1

X <= transport 1.0 after 2 ns

X=1

Time

Initial Worldline Final Worldline


VHDL wait semanticsX=0X=0

X=1

T=1

T=2

T=3

X=0X=0 T=0

X=0X=0 T=-1

X=1

Time

Initial Worldline Final Worldline

wait until X=1

X=1

X=1


VHDL sequential semanticsX=0

X=1

X=0

X=0

X=1

Final Worldline

wait until X=1

X=0 T=1

T=2

T=3

X=0 T=0

X=0 T=-1

X=1

X=1

X=0 T=1

T=2

T=3

X=0 T=0

X=0 T=-1

Time

Initial Worldline Intermediate Worldline

X=0

X=0

X<=1 after 2 ns8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 11

VHDL: running a processX=0

X=1

X=0

X=0

X=1

X=0 T=1

T=2

T=3

X=0 T=0

X=0 T=-1

X=1

X=1

X=0 T=1

T=2

T=3

X=0 T=0

X=0 T=-1

Time


X=0

X=0

X=0

Final Worldline

X=0

Time


X=0

X<=not X after 2 ns

X<=not X after 2 ns

X=1

X=1

X=1

X=0

X=0

X=0

X=0

X=1

X=1

process

begin X <= transport not X after 2 ns ; wait on X ; end

wait on X

wait on X

T=1

T=2

T=3

T=4

T=5 T=5

T=4

T=3

T=2

T=1


VHDL: running two processeswait on X

Y <= X after 1 ns

wait on X

process

begin

X <= not X after 2 ns;

end

process

begin

Y <= X after 1 ns;

wait on X;

end

wait on X;

X <= not X after 2 ns


VHDL: two-process semanticsX=0

X=1

X=0

X=1

Final Worldline

X=0 T=1

T=2

T=3

X=0 T=0

T=-1

X=1

X=1

X=0 T=1

T=2

T=3

X=0 T=0

T=-1

Time


wait on XY<= X after 1 ns

X=1

X=1

X=1

X=1 X=1

Y=1

Y=1 Y=1

Y=1

Y=0

Y=0

Y=0

Y=1

Y=1

Y=1

Y=1

Y=1

Y=0

Y=0

Y=0


VHDL semantic equationsSequential and susPension statement semanticsS[-],P[-]: Statement ! ((WL,TP)$(WL,TP))S[a; b] = S[a]; S[b]P[a; b] = P[a] [ S[a]; P[b]S[ajjb] = S[a] \ S[b]P[ajjb] = P[a] \ P[b]S[while(true)do a end] = f gP[while(true)do a end] = x = P[a] [ (S[a]; x)8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 15

Wait & Signal assignment semantics

(w0; t0)S[wait until p](w1; t1) = w0 = w1 ^ wt1 j= p^ 8 t 2 [t0; t1) :wt 6j= p(w0; t0)P[wait until p](w1; t1) = w0 = w1^ 8 t 2 [t0; t1] :wt 6j= p(w0; t0)S[x <= y after � ](w1; t1) = t0 = t1^ w1 = w0 � f(t;w0t� f(y; [y]w0t0)g)jt > t0+ [� ]w0t0gP[x <= y after � ] = f g8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 16

Lingusitic sumsElaborated behavioural VHDL+ quantities (decl. and ref.)+ di�erential equations+ break statement+ extended waitVHDL-AMS� resolution functions� nonsimple DEs+ import/export of quantities+ \relax"\Core Language"8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 17

Core Language Syntaxprog ::= p1 p2 p3 : : :proc ::= process n1(d1;d2;d3;: : : )e1; e2; : : :begin s1; s2; : : : enddecl ::= qout q1[=k1], q2[=k2], : : : | qin q1[=k1], q2[=k2], : : :| out g1[=k1], g2[=k2], : : : | in g1[=k1], g2[=k2], : : :| var v1[=k1], v2[=k2], : : :eqn ::= d q1/dt == x1expr ::= k1 | -x1 | x1+x2 | x1*x2 | f1(x1,x2,: : : ) | v1 | g1| if b1 then x2 else x3 fibool ::= T | F | b1 && b2 | x1 < x2 | : : :stmt ::= if b1 then s1;: : : else s2;: : : fi| while b1 do s1;s2;: : : od| do s1;s2;: : : until b1| null| wait [on x1] until b1| send g1 <= x1 [after x2]| break q1 => x1| v1 := x1| relax8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 18

Core Language Example Code

process ball(qout: s=1, v=0; var g = 9.8, a = 0.1)d v/dt == -g - sign(v) * a * v^2;d s/dt == v;beginwait until s < 0break s => 0;break v => -v;endThe bouncing ball under gravity with air resistance


Core Example Simulation


Example Cont.Height

Speed�t = 0:068'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 21

Example Cont.Program rewritten to correct for numerical errrors:proc [qty s := 1.0, v := 0.0, g := 9.8, a := 0.1 ]ds/dt == v;dv/dt == -g - sign(v) * a * v^2;beginwait until s < 0;v := sqrt(2.0) * (g * s + 0.5 * v^2)^0.5 ;s := 0 ;endThe numerical error due to overshoot can be ~30%.8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 22

Denotational DomainsTime = (<,N )State = Id ! <WL = Time ! StateS = (WL,TP) causal ! (WL,TP)P = (WL,TP) causal ! (WL,TP)Semantics = (S,P)In VHDL, Time = (N ,N ): 0;00;000; : : :1;10;100; : : :In VHDL-AMS, Time has continuous �rst ordinate, discrete secondordinate.8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 23

Termination Semantics`Oracle' encapsulates ODEs, predicts statespace trajectoriesOracle = (State,Time) ! Time ! StateS[-] :: stmt ! Oracle ! SSS[s1;: : : ;sn]O = S[s1]O; : : : ; S[sn]OS[v1 := x1]O(w,t) = f(w',t)gwhere w' = w � ft'7!w t'�fv1 7![x1](w t)gjt'�tgS[send g1 <= x1 after x2]O(w,ti) = S[relax](w',ti)where d = [x2](w t)w' = w�ft'7!w t'�fg1 7![x1](w t)gjt'�t+dg, d>0= w�ft'7!w t'�fg1 7![x1](w t)gjt'>tg, d�0S[relax]O(w,t) = f(w',t)gwhere w' = w � ft'7!O(w t)t'jt'>tg8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 24

Suspension SemanticsP[-] :: stmt ! Oracle ! SPP[s1;s2]O = P[s1]O[ S[s1]O;P[s2]OP[v1 := x1]O(w,t) = fgP[send g1 <= x1 after x2]O(w,ti) = fgP[break q1 => x1]O(w,t) = fgP[wait until b1] = P[do wait on q1'breakjj: : :until b1 until b1]P[wait on x1 until b1]O(w,ti) = f(w,�)jti��<t'gwhere t' = minf�>ti j [b1](w �) _ [x1](w �)6=[x1](w t)g8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 25

Di�cult points1. Synchronous parallelism (intersection of relations) is easy tospecify but di�cult to implementP[-] :: prog ! Oracle ! SPP[p1 : : :pn]O= P[p1]O\ : : :\ P[pn]O2. initialization semantics is non-obvious. Inputs are scheduledonce, outputs scheduled for all timeS[qout q1=k1]O(w,t) = f(w�f� 7!w ��fq1 7!k1gj� �tg,t)gS[qin q1=k1]O(w,t) = f(w�ft 7!w t�fq1 7!k1gg,t)g3. building an oracle (to solve ODEs) is not easyD[-] :: (eqn;: : : ;eqn) ! Oracle ! OracleD[d q1/dt == x1;: : : ; d qn/dt == xn]O= O'where O'(s,t)t' = if t'>t then s' else swhere d s'qi/dt' = [xi]s'8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 26

Unresolved areas

1: Implementation of the parallel composition of pro-cesses if quantities are shared between processes2: Errors in the analog solver may require us to rewriteour program3: The proper execution of the analog solver in � timewhen the processes are in parallel


Process algebraic analysis��

��

��

��

Ai

Aj

ΣjΣi

ΣjPj’

Pi’

Pi

Pj

Ki

Kj

Σi

��

��

��

��

AS

Ai

Aj

ΣjΣi

ΣjPj’

Pi’

Pj

Ki

Kj

Σi

Pi


Process algebraic analysis (II)��

��

��

��

��

��

��

�� iΣ

Σ j

’iΣ

’jΣ

K’iΣ

Σ

QAS

QAS

KAj

KAi

Pi

Pj

Ai

Aj K’j

Pj’

Pi’


Process algebra for VHDLAlphabets Laws�(K) = A t clk t��(Pi) = Ai t� t clk A = Fi Ai�(Ki) = Ai t�i t clk K = jjji Ki�(P0i) = � t clk P0i = (Pi j[Ai t�i t clk ]j Ki)( jjji Pi ) jj K = jji P0i8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 30

Process algebra for VHDL-AMS

Alphabets Laws�(KA) = A t�0 t clk KA = jjji KAi�(K0) = A t�0 t clk KA = K0 jjAS�(AS) = �0 t clk �0 = � tQ�(KAi) = Ai t�0 t clk KAi = K0i j[�0 t clk ]jAS�(P0i) = �0 t clk P0i = (Pi j[Ai t�0 t clk ]j KAi)nAi( jjji Pi ) jj KA = jji P0i8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 31

DeductionsProposition 1 Without quantities, if all signal delays are truncatedor rounded on writing and time is rounded or truncated on access,all external signals change only at integer times, then a VHDL-AMScore language code behaves as though it were running in VHDL.Proposition 2 If the solutions to the ODEs over an interval dependuniformly on the inputs, then, as a time-wise computation mesh getsuniformly �ner, the behaviour of a code executed over the meshtends uniformly to its ideal behaviour over every closed interval notcontaining an ideal exit from a wait.Proposition 3 Parallelism in the core language is benign: every ob-servable value is always either capable of taking every possible valueor uniquely de�ned.Proposition 4 The history of a simulation run is a scheduling �xedpoint: if it is used as an initial schedule, the same history will result.8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 32

Implementation1. Regard single processes as initial schedule to �nal history trans-formers.2. Transformation is causal and deterministic in the process-controlled outputs, therefore a stream-to-stream transformer.3. Multiple processes act as a set of mutually interconnectedproducers/consumers.4. They jointly produce a �nal history that is also consumed byeach process.5. The functionality is very sensitive to delays { requires quantityvalues to be transmitted with one delta delay, like signals.6. The maximumnumber of deltas must be �xed in advance withthis approach.8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 33

Summary- Denotationally based semantics for VHDL-AMS- Extends known denotational semantics for VHDL- Allows "theorems in the large"- Exploration and understanding- Leading to a prototype VHDL-AMS implementation


Bibliography- P.T. Breuer, C. Delgado Kloos, N. Mart��nez Madrid. Computa-tional Description of Analog Systems, chapter 5, pages 95-127New Methods for Hardware Design, Eds. B. M�oller, J. Tucker.Springer LNCS 1546, December 1998- P.T. Breuer, C. Delgado Kloos, N. Mart��nez Madrid, A. L�opezMarin, L. S�anchez. A Re�nement Calculus for the Synthesis ofVeri�ed Digital or Analog Hardware Descriptions in VHDL. ACMTransactions on Programming Languages and Systems (TO-PLAS) 19(4):586{616, July 1997- C. Delgado Kloos and P.T. Breuer, editors. Formal Semantics forVHDL. ISBN 0792395522. Kluwer Academic Press, December1994. 250 pages.8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 35

Bibliography cont.- P.T. Breuer, et al. Reasoning about VHDL and VHDL-AMS usingDenotational Semantics. In Proc. Design, Automation and Testin Europe, DATE'99. Munich, Germany, 9-12 Mar. 1999.- N. Mart��nez Madrid, et al. A core language and a simple formal de-notational semantics for VHDL-AMS. In Proc. 1998 IEEE/VIUFInternational Workshop on Behavioral Modelling and Simulation,BMAS'98. Orlando, FL, 27-28 Oct. 1998.- N. Mart��nez Madrid, P.T. Breuer, C. Delgado Kloos. A semanticmodel for VHDL-AMS. In Hon F. Li and Davaid K. Probst, ed-itors, Advances in Hardware Design and Veri�cation, Proc. Con-ference on Correct Hardware Design and Veri�cation Methods,CHARME'97, October 16{18, 1997, Montreal, Canada, pages106{126. IFIP Chapman and Hall, 1997.8'th Intl. Colloq. NACSA, Plovdiv, Bulgaria - Aug. 1999 36

the mixed-signal modelling language vhdl-ams and its semantics (icnacsa 1999)

Education

vhdl ieee

baroque language

denotational semantics

vhdl hardware component

ordinary imperative

elaborated vhdl model

a3 semantics

formal semantics