resistance and collector capacity are found tobe necessary. The relative advantages of linearand circular structures are considered both forbase resistance and for collector capacity.Parameters, which are expected to affect thefrequency behavior, are considered, includingemitter depletion layer capacity, collectordepletion layer capacity and diffusion transittime. Finally the parameters which might beobtainable are compared with those needed fora few typical switching applications."

The Planar Process

The development of oxide masking by Froschand Derick [9,10] on silicon deserves specialattention inasmuch as they anticipated planar, oxide-protected device processing. Silicon is the keyingredient and its oxide paved the way for MOSFETintegrated electronics [22]. An account of theirrevolutionary development and utilization of SiO2 asthe vital foundation of today's 1C industry has beendescribed by Holonyak [22]:

"In building our various experimental devices,we were in contact with various groups andindividuals, but above all with Carl Frosch.Frosch was a consummate process chemist whowas familiar with many types of processingprocedures and had been working, with histechnician Derick, on impurity diffusion intosilicon for several years. In spite of hisconsiderable experience, Frosch, with dry gasdiffusion procedures utilizing N2 or H2,regularly reduced many of our silicon wafers to"cinders, " particularly at higher temperatures

Because we had mastered building a diff used-base alloyed-emitter silicon p-n-p transistor (inspite of our problems with diffusion), one ofthe p-n-p-n configurations that we couldexplore was simply a modification of the p-n-ptransistor: We could fabricate the diffused-basealloyed-emitter p-n-p on one side of a p-typesubstrate wafer after it first was prepared withan n-type diffused region (symmetrical) onboth sides of the wafer. Either side could bechosen to form the p-n-p. The result was a p-n-p-n switch, in fact, the p-n-p-n switch ofexample (b) as described in [19]. (Thecomplementary version of this exact structure,an n-p-n-p with Ga diffused into both sides ofan n-type silicon wafer and then a Au-Sbemitter alloyed on one side, was laterintroduced at General Electric as the first

commercial silicon controlled rectifier, today'sthyristor. This later work was also based on our1956 research [19].

In the process of diffusing the p-type substratewafer into an n-p-n configuration for the firststage of p-n-p-n construction, particularly in theredistribution "drive-in" phase of the donordiffusion at higher temperature in a dry gasambient (typically > 1100°C in H2), Froschwould seriously damage our wafers. The wafersurface would be eroded and pitted, or eventotally destroyed. Every time this happened theloss was apparent by the expression onFrosch's face, not to mention, on ours (N.H.).We would make some adjustments, get moresilicon wafers ready, and try again.

In the early Spring of 1955, Frosch commentedto Holonyak, "Well we did it again," meaningthe wafers were again destroyed. But then hesmiled and displayed the silicon wafers - niceand green in color (in further instances alsopink). He and his technician Derick hadswitched from a dry-gas (typically N2 or H2)impurity diffusion to a wet-ambient (H2O vapor+ carrier gas) diffusion, a consequence of anaccident of the exhaust H2 igniting and flashing-back into the diffusion chamber (because of gasflow fluctuations) and causing H2O to cover,react with, and protect the silicon samples withoxide. The "wet" ambient, which was thenimmediately evaluated and adopted, created aprotective oxide on silicon. It could beselectively removed for gaseous diffusion intothe bare regions, which could then be resealedwith oxide for higher temperature anneals orfurther diffusion. Many processing sequencescould be devised for use of the protective oxide,which, of course, prevented crystal pitting anderosion. Frosch and Derick quickly found outwhich impurities were blocked from diffusioninto silicon by the natural protective oxide (SiO2)created in an H2O-vapor ambient and whichimpurities would permeate the oxide (e.g., Ga).It was easy, once the issue of the oxide wasknown, to devise various schemes to diffuse intoor to block impurity diffusion into silicon. Theprocess was so flexible that planar n-typeregions of any desired pattern could be preparedon a p-type substrate silicon, or the opposite, p-on-n diffused regions could be prepared on n-type silicon. All other diffusion procedures weresuddenly rendered obsolete. We readilyconverted the Frosch-diffused silicon n-p-n intoa working p-n-p-n switch [19]."

12

Holonyak [22] noted "what Frosch and Derickhad done was to set the basis for a revolution. Infact, it is the oxide on silicon that is the basis, thevital foundation of today's 1C chip, and of all of thesilicon devices so critical to the electronics industry.Because of our (Holonyak) exploratory silicondevice work and our involvement with Frosch, wewere close observers and witnesses of his work. Forexample, on p. 15 of an extensive BTLmemorandum [177], Frosch wrote:"

"Thin silicon slices also were diffused withSb for N. Holonyak for preliminary devicedevelopment investigations. These werediffused for 2, 5 and 16 hours respectivelyat 1300°C in N2 saturated with water vaporat room temperature. After diffusion, theseslices were green in color with an excellentsurface appearance. These layers werereported to have resistivities of from 10 to20 ohms per square. The diffusion layerswere reported to be uniform in thicknessbeing 0.26, 0.39 and 0.76 mils respectivelyfor the 3 heating times. An additional runwas made for Holonyak to produce layers ofsomewhat higher resistivity. In this run thethin silicon slices were heated for 1 hour at1200°C followed by 16 hours at 1300°C inN2 saturated with water vapor at roomtemperature. These samples again weregreen in color with excellent surfaceappearance. These were reported to haveresistivities of 45 to 90 ohms per squarewith a diffusion depth of 0.66 mils. Thehigher resistivity values obtained indicatenot only a lower solubility of the Sbcompound in the quartz envelope at 1200°Cthan at 1300°C but also the essentialabsence of Sb compound vapor in thecarrier gas when the temperature was raisedto 1300°C. Holonyak was able to producevery promising cross-point switches fromsome of these Sb diffusions."

Holonyak [22] continues by saying "we knewFrosch's work at first hand, and realizedimmediately what he and Derick had done. All ofus near this work, which was just a few at first,realized its importance, but, in truth, none of us,least of all Frosch, in his exceeding modesty,projected it to its true future scale. Frosch evenwrote (p. 20) the following statement in his BTLmemorandum [177]:"

"In addition to the possibilities of processsimplification, the protective quartz envelope

added during the heating may be useful forprotecting an electrical device fromatmospheric conditions. For example, thedevice might prove more stable if leftenclosed in such a quartz envelope.However, it may not be possible to make allof the necessary electrical contacts throughthe quartz. In these cases some protectionmay be retained by the removal of a smallarea of the envelope for the application of thecontacts."

Holonyak has summarized Frosch's innovationby "Frosch had, indeed, anticipated planar, oxide-protected device processing. He appreciatedimmediately the importance of the oxide. It isquestionable if anyone else's contribution had asmuch to do with the existence of the "chip" andtoday's electronics as Frosch's oxide. This is easilyseen by simply raising the question: Remove theoxide, say it doesn't exist, and then what wouldthere be? Silicon itself is, of course, the criticalingredient followed by its unique natural oxide. Insome sense it could be said that Si and itstechnology (its oxide) "invented" the 1C" (italicsentered by the author).

The benefits of SiO2 on the surface propertiesof silicon were concurrently, or shortly thereafter,assessed by Attala's group [11,178]. They believedthat growing an oxide under clean and controlledconditions, on a properly cleaned silicon wafer,would lead to both a reduction of surface statesand passivation of the silicon surface. The planardiffused transistor developed by Hoerni [12-15] ofFairchild Semiconductor Corporation in the late1950's pulled together a number of these strands asregards the benefits of SiO2 and was in productionby 1959. These included the concept that the SiO2masking layer, utilized in the fabrication ofdiffused silicon transistors, be left in place for thepassivation of p-n junctions intersecting thesurface in the case of the grown junction, alloy anddiffused mesa transistors, without the necessity ofgrowing a passivating oxide under meticulouslyclean conditions [179], per the insight of Hoerni[12-15] as well as ensuring a dielectric layer forsupporting metallic conductor overlayers in the 1Cera [16]. The Si-SiO2 diffusion technology had, inpoint of fact, been transferred from BTL toShockley Semiconductor, to FairchildSemiconductor Corporation and, from there led tothe creation of Silicon Valley [180]. Numeroustestimonies as to the efficacy of the planarapproach have been presented [122,158,181].Sparkes noted [159]:

13

"Victor Grinich of the Fairchild Corporationpresented graphs of the change with time ofcurrent gain, base-emitter voltage and cut-offcurrent of planar transistors which were somuch better than anyone had seen before thatit was quite obvious that if they were genuinea real breakthrough had been achieved. Afterseveral hours' discussion with Grinich itbecame clear to me that the planar processwas the process of the future. It was anunpalatable conclusion, since, just at that time,many companies had recently invested largesums of money in the double-diffused, thealloy-diffused or micro-diffused process withthe hope of achieving a clear production runof a few years."

To more fully appreciate the significance ofpasssivating the p-n junction intersecting thesurface in the mesa transistor such as fabricated byAT&T, one may consider Moore's assessment[122]:

"In mesa transistors, the emitter-basejunction is exposed on the top surfacebetween the metal contacts, while the base-collector junction intersects the sides of themesa (see Figure 3). The regions of highelectric fields where the junction comes tothe surface are sensitive to contamination.Contamination of the emitter-base junctioncan decrease the gain of the transistordramatically. In the case of the collectorjunction, the breakdown voltage andleakage characteristics can change. Wenoted a problem that some of the transistorspackaged in hermetically sealed cans in drynitrogen showed very unstable collectorjunction characteristics. Breakdownvoltages sometimes decreased by severaltens of volts and became unstable whenobserved on an oscilloscope, potentially amajor reliability problem. We formed a taskforce to try to understand and correct theproblem. One of our technicians, B.Robson, carefully cut the can off one of thebad devices and examined it under amicroscope. He noticed a spot of lightemitted from the side of the mesa when thetransistor was biased into breakdown. Heshut off the power and saw a tiny particleon the side to the mesa at the point of thelight emission. Carefully removing theparticle and reapplying power, he found thatthe original high breakdown voltage wasrestored. The particle, evidently attracted by

the high electrical field where the junctioncame to the surface, was causing thepremature breakdown of the junction. Nowwe knew the cause of the low breakdown.All we had to do was eliminate all thesources of particles."

The planar process introduced extremeflexibility in the fabrication of junction transistors,since the "tooling up" to fabricate different devicesinvolved changing the mask set, diffusion profilesand doping levels and, as appropriate, the resistivityof the starting material. The planar processadditionally facilitated the fabrication of a double-diffused transistor essentially planar with theoriginal wafer surface, without the necessity of amesa structure. A photomicrograph of the firstplanar transistor is shown in Figure 4 [122]. Chin-Tang (Tom) Sah, Harry Sello and Tremerepublished the first quantitative analysis of the oxidemasking thickness and related time and temperatureprocessing to ensure blockage of the diffusingimpurity in the oxide masked region [182]. It wasespecially important that these planar transistors hadthe base contact completely surrounding the emitterso as to eliminate any chance of the base inverting,as was the case for the original bipolar junctiontransistors [183,184]. With the advent of the planartechnique, cut off frequencies in the range of 10GHz could now be achieved, approaching valuesachieved for vacuum tubes [185]. Indeed, theexodus of Bob Noyce, Gordon Moore, Jean Hoerni,Jay Last, Julius Blank, Victor Grinich, EugeneKleiner and Sheldon Roberts 1957 from ShockleySemiconductor Laboratory, established in 1955[69,122], and their subsequent formation ofFairchild Semiconductor Corporation with the statedgoal of fabricating double-diffused transistors forcommercial gain (the original goal of ShockleySemiconductor before Shockley redirected its effortto the p-n-p-n diode [174]) was the major stimulusto the invention of the planar transistor, SiliconValley and the development of the fledglingelectronics industry. On the other hand, it should benoted that Shockley, Noyce, Moore et al. werecognizant of developments at BTL as regards SiO2and were quite receptive to its advantages in thefabrication of silicon junction transistors. In fact, theentire diffusion technology at BTL was madeavailable to Shockley to help facilitate his ambitionto derive a measure of success in the business worldbased on the transistor technology he had helped todevelop. Shockley was not, however, to achieve hisbusiness goals but contributed, inadvertently, to theexodus from Shockley Semiconductor which, inconjunction with Stanford University's graduates, led

14

to the Silicon Valley phenomenon. Indeed,Shockley has been referred to as the "Moses ofSilicon Valley" [186].

established the basis for the utilization of thealuminum metallization system [22]:

Figure 4. Photomicrograph of the first planar transistor. The diameter of the circle that forms most of theoutside ring is 0.030 in. The light areas are aluminum emitter and base electrodes. (From "A SolidState of Progress," Fairchild Camera and Instrument Corporation, 1979) [122]. Reproduced bypermission of the IEEE, Inc.

As noted earlier, the critical elements for thefabrication of the transistor and thryristor and,subsequently, the 1C electronics era (oxidation,diffusion, photolithography, aluminummetallization and thermocompression bonding)were now all available. Jules Andrus and Bondshowed that certain photoresists, when depositedon SiO2, would protect the underlying SiO2 duringetching processes [180,187,188]. Optical exposureof the resist using contact masks in the late 1960'sand early 1970's, projection masks in the middle1970's and stepper mask methodologies beginningin the later 1980's was used to create precisewindow patterns (open regions) in the oxide and,therefore, precise control of diffusion areas.Aluminum metallization was utilized to formohmic contacts to both p- and n-type material.While the former was expected due to Al being agroup III dopant, the latter was achieved since thecontact was subsequently identified to form atunnel diode with the n-type silicon, the tunneldiode characteristic being linear (and, therefore,simulating an ohmic contact) for both smallpositive and negative voltages about the origin.Moore and Noyce received a patent for thealuminum metallization [189]. Holonyak hasdescribed the experiments conducted at BTL which

"Satisfactory Al evaporation on Si did notexist when our work started. Moll obtainedpermission from Tanenbaum for us to use hisevaporator, and we quickly solved theproblem of evaporating Al on Si, on "hot" oron "cold" Si, and were able to realize preciseshallow alloyed p-type contacts or shallow "p"on "n" p-n junctions. We were able to showthe various conditions under which uniformevaporated Al contacts could be realized onSi: (1) If the Si substrate was 660°C or hotter,the evaporated Al (mobile Al) nucleated atrandom sites that grew into larger diameterislands with more evaporated Al, and formeda discontinuous regrown region. (2) In thetemperature range between the Al-Si eutectic(577°C) and the melting point of Al (660°C),uniform sticking and wetting of the Aloccurred and formed continuous metallizedand alloyed-regrown p-type Si without furtherheating. (This was nothing more than Hall's"local" liquid phase epitaxy LPE [139,140].(3) For the Si substrate at temperature 577°Cor lower, the evaporated Al merely adhered(uniformly) on the Si, and subsequently couldbe alloyed or could be left as a Schottkybarrier. By late 1954, Goldey and Holonyakhad solved the problem of metallizing Si and

15

forming uniform shallow p-n (or n-p)junctions, or if desired, shallow ohmiccontacts. Holonyak soon wrote a BTLmemorandum on Al metallization and shallowjunction formation on Si [190] and Goldeyincorporated this material and some furtherresults in a report published later [191]."

Contacts from the junction transistor to theheader were usually made by thermocompressionbonding, developed at BTL by O.L. Anderson, H.Cristensen and P. Andreasch [4]. Typically, gold(melting point 1063°C) was brought in contact withthe aluminum bonding pad (melting point 660°C) in areducing atmosphere under pressure. The gold-aluminum eutectic formed at about 350°C which,upon cooling, formed a strong, reliable bond. It wassubsequently observed that a phenomenon referred toas "purple plague" often developed due to undesiredreactions between the gold wires and the aluminumbonding pads at the upper range of temperatureswhere silicon transistors operate. The aluminum andgold formed a series of colored intermetallics (i.e.,the purple plague) that ultimately caused devicefailure [43]. Rectification of this yield degradationwas subsequently achieved by restricting thetemperature range of operation (also required for theplastic packages then utilized), utilization of allaluminum systems using aluminum leads, wires andaluminum coated package connections [43]. Goldmetallization systems such as the beam lead method[192] and multilevel metallization schemes [193,194]were also developed.

The benefits of the planar research inconjunction with Hoerni's insights resulted in thefirst meaningful description of the MOSFET device

(formation of an inversion layer, i.e., enhancementmode) by Dawon (David) Kahng and Attala in 1960[195-198], also summarized by Sah [44]. Kahngwrote an extensive BTL technical memorandum onthe silicon/silicon dioxide device in 1961 [199].Steven Hofstein and Frederick Heiman of the RadioCorporation of America (RCA) followed with anMOS 1C consisting of 16 silicon n-channel MOStransistors in 1963 [200]. It should also be notedthat J. Torkel Wallmark of RCA took out a patenton an FET in 1957 [201] but apparently did nofurther work in the field while Paul Weimerconstructed an FET using CdS as the dielectricmaterial on an insulating substrate in 1959 [202].Although these structures were minority-carrierdevices, the Metal-Semiconductor Field EffectTransistor (MESFET) and the Junction Gate FieldEffect Transistor, see Figure 5 [4], first describedand patented by Shockley [203,204] and built byGeorge Dacey and lan Ross [205] were majoritycarrier devices [44,206,207].

MOSFET Transistor Fabrication

The description of the oxidation process andmethodologies for controlling the electrical propertiesof the silicon/silicon dioxide interface in the late1950's were essential for the successfulcommercialization of the MOSFET andimplementation of the DRAM memory era in the1970's (see the Integrated Circuit section.) Deal andGrove described the oxidation kinetics of silicon [23],followed by Dennis Hess [208], Eugene Irene [209],Hisham Massoud [210] and Stanley Raider [211] andtheir colleagues who extended this research. RichardWilliams [212] and Akos Revesz [213] also made

Figure 5. Schematic of the junction field-effect transistor [4]. Reproduced by permission of the IEEE, Inc.

16

significant contributions to the understanding of thesilicon/silicon dioxide interface while GeorgeSchnable [214] advanced our understanding of a hostof dielectric film deposition methodologies forIntegrated Circuit (1C) applications [8].

Device reliability studies by Ed Snow, Grove,Deal and Sah at Fairchild Semiconductor identifiedthat sodium contamination in SiO2, introduced by theheated tungsten filament [215] for aluminumevaporation, was mobile under voltage stress, causeddevice parametrics to drift under operating bias andwas exacerbated by increased operating temperature.The Fairchild team also observed that electron-beamevaporation did not introduce the sodium [215],thereby developing techniques for controlling thesodium and, furthermore, developed an extensiveunderstanding of the phenomena taking place in themetal-oxide-silicon system that is basic to all modernMOSFET systems. Deal described the silicon/silicondioxide electrical interface stability and associatedeffects in silicon dioxide in terms of 17 types ofcharge mechanisms and introduced the standarddescription for the charge notation associated withthermally oxidized silicon [24-30]. The reduction ofmobile charges, fixed charge (Qf) and interface statecharge (Dit) as well as the control of the growthprocess (oxide thickness) was of paramountimportance in ensuring threshold voltage control andthe successful commercialization of MOS deviceproducts [216]. While most of the industry initiallychose to fabricate PMOS devices, some companieselected to fabricate NMOS because of the higherchannel mobility for electrons, compared to holes.However, positive charge control is a more seriousissue in NMOS technology. Post-oxidation and post-metallization anneals were developed in the 1960's tominimize both fixed and interface charge [31,32].The mobile charge, such as Na and K, also requiredstringent control.

Techniques were developed for the passivationof surface states introduced at the silicon/silicondioxide interface during thermal processing. PieterBalk described in 1965 the significance of a postSiO2 anneal in a hydrogen bearing ambient [31] and anitrogen anneal in the case of the Al-SiO2-Si system[32] to stabilize the Si-SiO2 interface and reduce thefixed charge, Qf. Molecular hydrogen was suggestedto anneal the surface states by bonding with thedangling silicon and oxygen bonds [31,32]. Kooi ofPhilips Research Labs in Eindhoven confirmedBalk's research [217]. Sah has noted that Balk'shydrogen annealing methodology has withstood thetest of time for more than 30 years and is afundamental aspect of the MOSFET 1C processingmethodology [44]. Sah has quoted from Balk's

abstract [31] (Sah's comments are added in curlybrackets):

"The main effect of the H2 treatment appearsto be the annihilation of fast states {anothername for interface states}. If these states arerelated to vacancies, accompanied bychemically unsaturated bonds {has beenknown as dangling bonds} and unpairedelectrons near the interface, the H2 {nothydrogen ion or proton as some think}annealing may be in effect the chemicalsaturation {now known as hydrogenation}with H atoms of these bonds at the vacancies.The low state density obtained upon steamoxidation is probably caused by hydrogen,evolved during oxidation, and retained in theoxide. The similarity in action between H2 andAl remains as yet unexplained."

Balk clarified the unresolved issue as regardsthe similar benefit between a H2 and an N2 anneal ofAl later that year in 1965 [32]. Sah [44] again quotesBalk:

"The similarity of the annealing behavior ofthe electrical interface properties of Si-SiO2 inH2 and Al-SiO2-Si in N2 around 300°Csuggests that the same mechanism is operativein both cases. Hydrogen released in a reactionbetween Al and hydroxyl groups in the oxideis proposed as the active agent in the Al-SiO2-Si case. This model is supported by theabsence of any annealing effects on 'ultra-dry'oxide."

It was suggested that residual H2O, releasedfrom the Al during thermal processing, reacts withthe hydroxyl groups to yield hydrogen. Sah furtherpoints out the beneficial effect of annealing in H2 orforming gas (95% N2/5% H2) [218]:

"Balk's hydrogen bond model of passivatingand deactivating the interface traps has alsobeen the chemical-atomic base for thecharacterization of the generation, annealingand charging kinetics of the interface andoxide traps due to silicon and oxygen danglingbonds."

Balk's insight was extremely important duringthe early 1970's, when Al was still the dominant gateelectrode, before the introduction of the polysilicon gateelectrode and the fabrication of the IK and, in somecases, the 4K dynamic random access memory (DRAM)

17

1C. The last thermal process step (before packaging)was a 30 minute or so anneal between 400°C or 450°Cto ensure sufficient reaction of the aluminum with thesilicon for good contacts; the release of H2 from thealuminum during the 450° C anneal was instrumentalin passivating the interface states and recovering thedesired threshold voltage. The role of hydrogenannealing and passivation in the broader context ofthe plasma deposited overlayer of silicon oxynitrideas a seal over the entire circuit has also beendiscussed [219].

Dalton and Dorbek of AT&T [220]demonstrated that an overlayer of Si3N4 could alsoprovide an effective seal against sodium ions; toavoid the concurrent trapping of hydrogen ionsresulting in threshold voltage instabilities, siliconoxyitride was subsequently utilized. Indeed, a plasmadeposited overlayer of silicon oxynitride is used as aseal over the entire circuit structure, except for thecontact pads [4]. The nitride film is also veryeffective in reducing pinholes in the SiO2 dielectric.Concurrently, Kerr and Don Young of IBM weredeveloping the utilization of a phosphosilicate glass(PSG) deposited on top of the MOS gate dielectricsilicon dioxide to getter the Na and K and stabilizethe oxide film [221,222]. This approach wasespecially important for aluminum gate electrodes,utilized prior to the phosphorus doped polysilicongate technology to be discussed below. Snow andDeal [223], followed by Pieter Balk and JeromeEldridge [224], showed that the threshold voltageshifts of MOSFET's, induced by polarization in thePSG layer on the SiO2 surface, could indeed becontrolled. Stabilization of the surface was alsobeneficial for bipolar transistors for operation at lowcurrents or high voltages where deterioration of thecurrent gain and leakage current due to surfaceinstabilities degraded device performance and yield.

Concurrently, Rudolf Kriegler championed anin-situ furnace gettering methodology in the early1970's, to remove sodium as well as other deleteriouscontaminants such as metals and transport thesemobile ions and lifetime-killing metallic impuritiesfrom the wafer to the gaseous ambient. Thisprocedure became an especially prevalent industrialtechnique [225-227]. Typically, about 3% gaseousHC1 or C12 in the O2 oxidation ambient [227] wasutilized, similar to Robinson and Heiman [228]. CarlOsburn studied the improvement of gate oxideintegrity (GOI) via these Cl methodologies [229] aspart of an extensive series of analyses in the VeryLarge Scale Integration (VLSI) laboratory of ArnoldReisman [230]. TCE (trichloroethylene) [231] andTCA (trichloroethane) [232] were subsequentlyutilized with similar benefits, but without the

corrosive effect of the HC1 ambient on the furnacemetal plumbing.

Gettering was initially believed to occur byformation of volatile metal chlorides, although theGibbs free energy of formation of most metalchlorides was not negative. The Cl, however, wasalso interpreted as removing interstitials, asevidenced by the shrinkage of oxidation inducedstacking faults (OISF) at sufficiently hightemperature by Hiromitsu Shiraki [233], Cor Claeys[234] and their colleagues. Shih-Ming (Jimmy) Hushowed that the shrinkage (retrograde growth) ofOISF at sufficiently high temperatures in the absenceof HC1 was dependent on both the surface orientationand ambient [235]. The early utilization of these Clambients was in conjunction with the oxidationambient during high-temperature processing. The Clincorporated in the SiO2 also trapped and immoblizedthe sodium at room temperature. It was suggested byKreigler and Osburn, furthermore, that it might bemore advantageous to clean the furnace quartz tubein the presence of the Cl bearing species but not toincorporate the Cl into the SiO2 film, per se, due toSiO2 reliability considerations [227,229].

The subsequent capacitance-voltage (C-V)diagnostic analysis of the Si-SiO2 interfaceelectrical properties by Moll [236] and Terman[237], was expanded upon by Grove, Snow, Dealand Sah [238] and formulated in a set of usefulcharts for fabrication engineers by Zaininger andHeiman [239]. Edward Nicollian and AdolfGoetzberger's conductance analysis [240-243]quantified the description of the silicon/silicondioxide interface electrical properties while the p-njunction under non-equilibrium conditions wasdescribed by Grove and Fitzgerald [244]. Thedescription of oxidation kinetics by Deal and Grove[23] and the local oxidation of silicon (LOCOS)process developed by Kooi and colleagues in thelate 1960's [245-247], which was instrumental inthe fabrication and achievement of superior MOS 1Ccharacteristics (see Figure 6) [247], set the stage forthe initiation of the MOSFET Dynamic RandomAccess Memory (DRAM) era in the early 1970's.The LOCOS process has been the mainstay forCMOS 1C fabrication for more than 30 years andonly now is shallow trench isolation seriouslychallenging its utilization [248].

The mesa and planar processes described abovenow paved the way for the fabrication of the 1C byJack Kilby (utilizing the mesa methodology) [8,33-36,43] and Robert Noyce [8,37-39,43] (utilizing theplanar procedure), in 1958 (see Integrated CircuitBeginnings section) and, subsequently, themicroprocessor [40-42].

18

!b*

i Oxidation* ' ' ̂ fe >SW$;

Si

Figure 6. Conventional LOCOS procedures. A pad oxide (SiO2) under the nitride oxidation mask relievesstress, but results in the formation of "bird's beaks" at the oxide edges. Fully recessed oxide patterns(right) exhibits complete "bird's heads" [247]. Reproduced by permission of The ElectrochemicalSociety, Inc.

Integrated Circuit Beginnings

The challenge after implementation of thejunction transistor era in the 1950s was to not onlyemulate the vacuum tube in as many applications aspossible (without the excessive power generation andreduced operating lifetime), but to exploit theinherent advantages of solid-state electronics to newarenas. The smaller device dimensions required toachieve higher frequency operation in the junctiontransistor was confronted, however, with the inherentchallenge of the limited power-handling capabilitydue to the device's small size. The goal of achievinghigher operating frequency and higher power-handling capability seemed to be at odds with eachother. Ross described the situation as follows [4]:

"In the meeting on that day, we were, as wasfrequently the case, discussing our problemsin emulating the vacuum tube. R. Wallacesuddenly said:

"Gentlemen, you've got it all wrong! Theadvantage of the transistor is that it isinherently a small size and low power device.This means that you can pack a large numberof them in a small space without excessiveheat generation and achieve low propagationdelays. And that's what we need for logicapplications. The significance of the transistoris not that it can replace the tube but that it cando things that the vacuum tube could neverdo!"

"And this was a revelation to us all. Werealized that in chasing the vacuum tube, wehad the wrong emphasis.... The net result wasthat the semiconductor community began torelax about replacing the tube and focused ondeveloping the transistor in its own right. Thetransistor did eventually replace the tube in allbut a few special applications, the magnetronbeing one outstanding example. But it tookdecades. In the meantime, semiconductortechnology opened up important new fieldsthat the tube could never have supported....Having the clear goal of an application for aninvention is a powerful stimulus forinnovation. But frequently, the originalapplication turns out not to be the mostimportant."

In a similar vein, Robert Lucky has recently noted"moreover there is no a priori way to determine whatwill tip a market. It's a fundamental instance of chaosin-group dynamics. And that makes it fundamentallydifficult to predict future societal behaviors in theadoption of technologies [249]."

Until the invention of the 1C, electronicsystems were comprised by individuallyconnecting the various components (vacuum tubesor transistors, diodes, capacitors, resistors andinductors) together. The common feature of theseendeavors was the wiring together of discrete andseparately packaged device components. Ofcourse, it was essential that these components bespaced sufficiently close so that the systempropagation delay did not become the factorlimiting the system speed. This required the

19

miniaturization of the system, not just the devicecomponents. Two major system concerns surfacedwhich required rectification. This involved theassembly yield and reliability of a system withthousands of device components, which might beunacceptably low. Additionally, even if the devicecomponents had no errors, there would be a multitudeof connections, resulting in the infamous "tyranny ofnumbers" [35,36,250-253].

Lester Hogan reviewed what may be the earliestattempts to rectify the "tyranny of numbers"conundrum [254]; that is, the patents filed by bothDarlington [255] and Oliver [256] in 1952.Darlington and, apparently, Oliver used a grownjunction transistor; both patents integrated severaltransistors on one piece of germanium or silicon,although they included no passive components.Geoffrey Dummer of the Royal Radar Establishment(RRE) at Malvern, England initiated his solution tothe integration challenge in 1952 [257] andsubsequently described his work at the MalvernComponents Symposium in 1957 [258] andelsewhere [259]. Runyan and Bean [43] have quotedDummer's 1952 status as "an integrated approachusing a monolithic block comprising" [258,259]:

"...layers of insulating, conducting, rectifyingand amplifying materials, the electricalfunctions being connected directly by cuttingout areas of the various layers."

Hogan [254] has also quoted a portion ofDummer's presentation at the 1957 meeting [258]:

"... a transistor flip-flop with two emitterfollower outputs—a total of four transistors allcontained in a chip of silicon 125 mils by 375mils. The semiconductor was doped to form ap-n-p structure and had various sectionsremoved to leave thin bridges of material withrelatively high resistances. These high-resistance paths formed the collector andemitter loads of the transistors connected tocommon power supply rails. Other resistorswere provided by films of resistive materialdeposited on the surface of the silicon, whilecapacitors were constructed from thin metalliclayers with insulators between."

Concurrently, Harwick Johnson of RCA wasalso developing his solution to the integrationchallenge [260]. Hogan [254] described Johnson'scontribution:

"As early as 1953, Harwick Johnson of RCAconceived of a complete phase shift oscillator

built in a single chip of n-type germaniumwhere p-n junctions supplied the necessarycapacitance, the body resistance of the pieceof germanium supplied the resistive elementsand an alloy transistor at one end of thefilamentary piece of germanium supplied thenecessary amplification."

"The significant point is that only two yearsafter the first junction transistor was reported[reference added [66], research people werealready trying to combine resistors, capacitors,(diodes) and transistors into one piece ofsemiconductor material in order to reducesize, to reduce the number of interconnectsand to improve reliability."

The alloy junction transistors utilized byJohnson as well as the other, multi-faceted,approaches by personnel familiar with the state-of-the-art in the attempts to build an integrated circuit inthe mid 1950's was perhaps best described byDummer to be "pioneering stages" ... not capable ofproduction [261]." Dummer's review of the work inGreat Britain and Western Europe is also of interest[262].

Runyan and Bean [43] have commented aboutJohnson's contribution:

"The figures included in a patent ... byHarwick Johnson ... (reference [260] added)bear a superficial resemblance to an integratedcircuit. However, as expressed in the firstsentence of the patent, both the discussion andclaims relate only to a transistor phase-shiftoscillator: This invention pertains tosemiconductor devices and particularly tosemiconductor phase-shift oscillators anddevices.' Component isolation was notconsidered so that even if the concepts of thepatent were extended to devices other than thephase-shift oscillator, the class of devices thatcould be made would be very limited."

It was Kilby of Texas Instruments,Incorporated, however, who filed a patent applicationon February 6, 1959 [8,33-36,43] explicitly"describing a concept that allowed, using relativelysimple steps, the fabrication of all the necessarycomponents of the desired circuit, both active andpassive, in a single piece of semiconductor and theirinterconnection in situ" [43]. Kilby's initial proof ofconcept was a phase shift oscillator, built with aboutten components, in germanium for expediency [43]on September 12, 1958. Wire bonding was utilized to

20

interconnect the components within the chip (seeFigure 7).

material, the junctions of such components beingnear and/or extending to one face of the body,

Figure 7. The first integrated circuit, a phase shift oscillator fabricated in germanium by the mesa process,invented by Jack S. Kilby of Texas Instruments in 1958, courtesy of Texas Instruments Incorporated.

A few weeks later, a flip-flop circuit was madeand a patent application covering both germaniumand silicon was prepared and filed (February 6,1959). The first commercially available 1C, intendedfor binary counter, flip-flop or shift registerapplications, was fabricated in silicon and announcedin March, 1960 by Texas Instruments. Runyan andBean [43] have extracted several relevant portions ofKilby's patent [33], with appropriate commentary:

"In contrast to the approaches to miniaturizationthat have been made in the past, the presentinvention has resulted from a new and totallydifferent concept for miniaturization.... Inaccordance with the principles of the invention,the ultimate in circuit miniaturization is attainedusing only one material for all circuit elementsand a limited number of compatible processingsteps for the production thereof... "

Up to this point, the goals are perhaps not muchdifferent from those expressed in 1952 by Dummer.However, to continue with the Kilby patent:

"In a more specific conception of the invention,all components of an electric circuit are formedin or near one surface of a relatively thinsemiconductor wafer characterized by a diffusedp-n junction or junctions...."

"It is a primary object of the invention to providea miniaturized electronic circuit wherein theactive and passive circuit components areintegrated within a body of semiconductor

with components spaced or electrically separatedfrom one another as necessary in the circuit...."

"Figures l-5a (in reference 33 added byauthor) illustrate schematically various circuitcomponents fabricated in accordance with theprinciples of the present invention in order thatthey may be integrated into, or as they constituteparts of, a single body of semiconductormaterial:"

Runyan and Bean [43] continue, 'The figures andtext describe bulk resistors, diffused resistors, pnjunction capacitors, MOS capacitors, transistors, anddiodes. In the press coverage of the March 1959announcement of the Kilby concept, this set of standardcomponents was stressed [263]. The patent textcontinues:"

"Because all of the circuit designs describedabove can be formed from a single material, asemiconductor, it is possible by physical andelectrical shaping to integrate all of them into asingle crystal semiconductor wafer containing adiffused p-n junction, or junctions, and toprocess the wafer to provide the proper circuitand the correct component values...."

With the subsequent planar process patentsubmission by Hoerni of Fairchild SemiconductorCorporation on May 1, 1959 [15] and due to manner inwhich the interconnection was described in Kilby'spatent [33] compared to Noyce's 1C patent application,filed on July 30, 1959 [37], Noyce was actually awarded

21

a patent before Kilby's (April 25, 1961 compared toJune 23, 1964). Figure 8 is a photomicrograph of oneof the first planar integrated circuits made atFairchild Semiconductor Corporation [122];subsequent evolutionary trends have been

then referencing the relevant portion of the Noyceclaims [37]:

"... an electrical connection to one of saidcontacts comprising a conductor adherent to

Figure 8. Photomicrograph of one of the first planar integrated circuits made at Fairchild (in silicon). This is aflip-flop circuit (with two transistors). Some of the aluminum interconnection metal has beendamaged during the etching operation to form a circular chip of silicon to place into a transistor canmodified to have more leads. (From "A Solid State of Progress," Fairchild Camera and InstrumentCorporation, 1979) [122]. Reproduced by permission of the IEEE.

described for ICs [44]. The Texas Instruments 1Cwas developed utilizing the mesa process whileIntel utilized the subsequent planar process. Thelegal battle that ensued between Texas Instrumentsand Fairchild Semiconductor centered around thewording associated with the interconnectionscheme. Runyan and Bean [43] have summarizedthe essence of the point of contention between theKilby and Noyce patent dispute, quoting Kilby'spatent [33]:

"Instead of using the gold wires 70 inmaking electrical connections, connectionsmay be provided in other ways. Forexample, an insulating and inert materialsuch as silicon oxide may be evaporatedonto the semiconductor circuit waferthrough a mask either to cover the wafercompletely except at the points whereelectrical contact is to be made thereto, or tocover only selected portions joining thepoints to be electrically connected.Electrically conducting material such asgold may then be laid down (italics enteredby author) on the insulating material tomake the necessary electrical connections."

said layer (italics entered by author) ...." Thedisagreement centered around whether "laiddown" was equivalent to "adherent to." TheBoard of Patent Interference, ruling in Kilby'sfavor, asserted that it was. However, asubsequent ruling by the Court of Customsand Patent Appeals (Noyce v. Kilby; Kilby v.Noyce, decided November 6, 1969) reversedthe previous rulings and allowed the Noyceclaims. (The Supreme Court then refused toreview the case.) Contrary to assertions bysome, the ruling did not depend on whethergold could or could not be made suitablyadherent to silicon oxide. The Courtspecifically commented on that aspect. Theruling depended on the Court's assessment ofwhether or not someone reading Kilby'sstatement would be inevitably drawn to theconclusion that the lead should be adherent."

Runyan and Bean then continue [43]:

"Probably the most balanced assessmentof Kilby's and Noyce's relativecontributions is contained in the citations ofthe Franklin Institute's 1966 BallantineMedal award, which they shared. Kilby wascredited for 'conceiving and constructingthe first working monolithic circuit in1958,' and Noyce for 'his sophistication

22

of the monolithic circuit for morespecialized use, particularly in industry.' "

Implementation of the 1C concept wassomewhat slow in consideration of the anticipatedyield of an 1C containing, say, 100-1000, transistors.That is, the reliability of a chip was anticipated toapproximate the reliability of a discrete transistordegraded by a power to the number of transistors orcomponents [4,264]. It turned out, however, thatneither the yield or reliability was determined byrandom events degrading the transistor uniformity,per se, due to the batch method of silicon 1Cprocessing [4]. In point of fact, there tended to belarge areas of a silicon wafer where the yield wasclose to 100% while the yield in other areas tendedto zero [265]. Thus, if the 1C chip area was smallcompared to the area on the wafer with highyielding ICs, the yield would be essentiallyindependent of the chip size and the number ofchips per wafer. With this realization, the stage wasset for the 1C explosion. Ross [4] has quoted Kilbyin discussing the buildup of 1C production [34].

"It should be noted that one of the greatstrengths of the integrated circuit concept hasalways been that it could draw on themainstream efforts of the semiconductorindustry. It was not necessary to developcrystal growing or diffusion processes tobuild the first circuits, and new techniquessuch as epitaxy would be readily adapted tointegrated circuit fabrication. Similarly, newdevices such as MOS transistors andSchottky barrier diodes would be phased inas they became available. Even today, it isdifficult to identify a process that is usedonly for integrated circuits.

Another strength of the concept was that itcould draw on existing circuit technology toproduce a broad range of useful devices....

Because of the commonality with existingprocesses, integrated circuits moved rapidlyinto a production status."

It might be appropriate, however, to note thatdevelopments in 1C fabrication to enhance deviceperformance and scaling have significantly expandedthe spectrum of processes uniquely developed for 1C

fabrication, including, for example, self-alignedstructures and the lightly doped drain (LDD)configuration (see Integrated Circuit Scaling section).

While the use of epitaxy had been an importantdesign consideration for discrete transistors, its realimpact occurred with the introduction of the bipolar1C. Prior to epitaxy, component isolation within thebipolar 1C was achieved by reverse-biased p-njunction isolation techniques (introduced by Lehovecon April 22, 1959 [266,267]) such as by diffusion(consider boron) from both the front- and back-surfaces of the wafer until the diffusion fronts met inthe center of the n-type wafer, leaving n-type wells inthe masked regions. Runyan and Bean have reviewedthe p-n junction isolation technique, includingLehovec's contribution to the interconnectionmethodology as well as the isolation techniquesutilized by Kilby and Noyce [43]. Kenneth Bean hasalso described his epoch research on dielectricisolation for Bipolar ICs with Paul Gleim andRunyan [268,269]. The advent of epitaxial structures,however, offered a new design flexibility incomponent isolation. For example, one could utilize athin n-type epitaxial layer (say 3 jim, for example) ona p-type substrate wafer. Component isolation couldreadily be achieved by boron diffusion through theepitaxial layer. Additionally, the fabrication ofstructures with a high concentration of dopant in thecollector, to decrease transistor collector resistance,was achieved by the localized diffusion of an n-typedopant into a p-type substrate wafer prior to thegrowth of an n-type epitaxial layer [166-169].

Integrated Circuit Fabrication

Although the bipolar transistor exhibited betterperformance characteristics such as switching speedthan the MOSFET transistor, the process simplicityand smaller 1C chip size of the latter made it thepreferred choice for implementation of leading edgedesign rule applications [270-272]. The first massproduced commercial MOS DRAM design wasIntel's 3-transistor silicon-gate PMOS, IK DRAMannounced in 1970. Terman [273] and Hodges [274]have reviewed a number of these memorydevelopments prior to 1972, often referred to as thesmall-scale integration (SSI) era (see Table 2 for anapproximate taxonomy of the evolving DRAM).

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TABLE 2: DRAM Process and 1C Evolution (circa 1992)Parameter

Bits/chipDesign RulePower-delay

productMask levelsChip areaa

Storage cellcapacitor

equivalent oxidethickness

Junction depth

Units

Number|LimPJ

Numbermm2

(nm)

|nm

ULSI

10' -10*<1

<10'2

15-2050 - 2803.5-12.5

0.04 - 0.2

VLSI

Vf - 10'1-3

10'2 - 1

8-1525-5012.5-40

0.2-0.5

LSI

10j - 10'3-51-10

6-1010-2540-90

0.5-1.2

MSI

102 - 103

5-1010 -102

5-610

90-120

1.2-2

a) Chip area (or more specifically, active device area) significantly impacts 1C yield in conjunction with the defectdensity per cm2 per critical lithographic level (for the number of critical levels).

The transition to the self-alignedaluminum gate and then the self-alignedphosphorus doped polysilicon gate adjacent tothe source and drain junctions via ionimplantation of the junctions, reducing theMiller capacitance [275-279] and the transitionto the silicide metalization scheme [280] weresignificant achievements enhancing 1Cperformance. An additional device innovationwas Heiman's utilization of a four-terminalconfiguration for the MOSFET by applying anegative dc voltage to the substrate [281] whichmodified the threshold voltage of the MOSFET(increased the threshold voltage for an n-channel MOSFET) and is referred to as the"body effect." This may be seen in thethreshold voltage, VT, expression in equation 3for an n-channel transistor (with no ion implantfor VT adjust) [282]:

V T = -NA)1/2(2<|>F- xl/2

+(l/Cox) (2 esie0 q(3)

where:

Qf= Fixed positive interface charge per unitarea at the silicon-silicon dioxideinterface. The positive charge contributeselectrons to the p-type silicon at thesurface, thereby making it easier toinvert the p-type bulk silicon to an n-typesurface inversion channel (i.e., lowerVT)

Cox = Gate oxide capacitance per unit area§F= Bulk Fermi energy relative to the the

intrinsicholes/cm3

Fermi energy$F = - 0.29 V)

(for 10

= Work function difference between thephosphorus doped polysilicon gate andthe p-type silicon substrate (taking theFermi energy in the phosphorus dopedpolysilicon at the edge of the conductionband, <htf = - 0.84V)

- Dielectric constants of silicon (1 1.7) andvacuum, respectively

VBB = Substrate back-gate bias (VBB = - 5 V forthe 4K and 16K DRAM when thistechnique was popular). Substrate bias alsoreduces the junction capacitances of thesource, drain and channel, an importantperformance advantage.

The body-effect technique also alloweddetermination of the bulk substrate doping, NA, at theedge of the surface space charge region (SSCR) forcomparison with that deduced by capacitance- voltage(C-V) analysis via equation 4:

NA= [(Cox)(4)

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Physically, the substrate near the surface isreverse biased by the negative VBB body bias,thereby negating, somewhat, the influence of theelectrons donated by the fixed positive charge, Qf atthe interface and increasing VT to the desired range.It should be noted that the 20F term does not scalewith device scaling.

The larger number of device functions on agiven MOSFET 1C chip and the larger number ofMOSFET 1C chips for a given wafer diameter wereinstrumental in ensuring the eventual dominance ofthe MOSFET 1C. Fairchild announced a 64 bitSRAM (six transistor cell design), enhancement-mode p-channel MOSFET in 1964 [44] followed byRCA's annoucement and production of anenhancement mode n-channel MOSFET, also in1964, based on Hofstein and Heiman's research[283]. Frank Wanlass and Sah of FairchildSemiconductor Corporation disclosed theComplementary MOS (CMOS) 1C in 1963[284,285] followed by RCA Corporation later in theyear [286]. Wanlass's initial demonstration circuit, atwo transistor inverter, consumed a few nanowattsof standby power, compared to milliwatts ofstandby power for equivalent bipolar and PMOSgates [287]. Interestingly, Wanlass utilizedHeiman's back-bias methodology [281] to achievean n-channel enhancement mode device (due to thedifficulty of uncontrolled surface charges at thatstage of technology to fabricate an n-channelenhancement-mode MOS transistor) to work inconjunction with the conventional PMOSenhancement-mode transistor [287].

CMOS eventually became the ultimateMOSFFET technology, since both p-and n-channelenhancement-mode transistors are normally off,drawing only quiescent power; that is, only duringthe switching process is significant power dissipated[286,288-290]. The DRAM memory array in CMOSICs was fabricated in NMOS while the peripheraldrivers were fabricated in CMOS. U.S. companiestended to use the same design rule for both theNMOS memory array and the CMOS peripheraldevices, accentuating the latch-up phenomenon,thereby requiring the use of epitaxial structures tominimize latch-up (the coupling of an n-p-n MOStransistor with an adjacent p-n-p MOS transistorforming an n-p-n-p or p-n-p-n thrysistor [289,290].It appears the Japanese used a larger design rule forthe CMOS circuitry, thereby avoiding the use ofepitaxial wafers. The Japanese approach was lesscostly to fabricate since polished, rather thanepitaxial, silicon wafers were used. Although therewere less chips per wafer due to the larger chip size,increased yields often negated the geometricallimitation. MOSTEK, Incorporated, formed in 1968,

was the first semiconductor company exclusivelydevoted to the fabrication of MOSFET ICs. Shortlythereafter, the 256 and IK DRAM MOSFET 1C wasintroduced by Texas Instruments in 1970 and 1972,respectively. Intel introduced the IK PMOSFETDRAM in 1970 [291]. Indeed, Intel's IK p-channel(PMOS) DRAM (polysilicon gate), based on athree-transistor cell design, initiated the beginningof the MOS memory take-over of the ferrite corememory market by its implementation at computermaker Honey well, Inc. [292].

The MOSFET 1C revolution, however, reallyexploded when IBM chose the n-channel siliconMOSFET (NMOS), instead of the slower p-channelsilicon MOSFET, for its mainframe memorycomputer (IBM-370/158) that was delivered in1973. The access time of the NMOS was in therange of nsec while magnetic core memory's accesstime was about one |is. Intel and MOSTEK wereearly suppliers followed by TI in 1974. TFs designwas based on the one-transistor DRAM cellstructure of Bob Dennard [45] and described byothers [293,294], also summarized by Sah [44].Texas Instruments and MOSTEK utilized a single-metal-word-line/single-diffused-bit line [44,295-297], where the metal was Al and the source anddrain were formed by diffusion. Texas Instrumentsutilized POC13 in forming the diffused source anddrain. The 4K NMOS DRAM cell built by Intel wasa single-poly-word-line/single-metal (Al)-bit line[44,295-297].

The 16K DRAM was announced in 1976, withthree significant changes made compared to the 4KDRAM, noted by Sah [44]. These were a reduction ofthe design rule from the 7-8 jam regime for the 4KDRAM to about the 5 Jim range for the 16K DRAM;the removal of the source diffusion which becameknown as the merged one-transistor DRAM cell andan overlapping double polysilicon gate, one for thesourceless transistor (the pass gate) and the secondfor the charge storage capacitor, thereby forming themerged one-transistor DRAM cell [44,295-297]. Thewafer diameter was also subsequently increased tothree-inches and, later, changes to larger diametersbecame commonplace when the number of DRAMchips became less than about 100 per wafer [298].The subsequent transition to the 64K DRAM around1979 did not result in any change in the cell design,although the design rule was reduced to the 2-3 Jimrange and the part was subsequently implemented onfour-inch diameter wafers [298]. Four significant 1Cprocess changes were discussed by Sah [44]. Theseincluded a parallel plate storage capacitor, rather thanstorage in a surface inversion layer, to give a highercharge storage capacitance (about 32 fF to store «106

electrons at 5V VDD) from the small area of the one-

25

transistor DRAM cell, since higher capacitance wasrequired to reduce the soft errors due to noise electronsgenerated by alpha particles from the package materialsof the chip, cosmic rays and other noise sources [44]; adual dielectric for the charge storage capacitor, utilizingthe higher dielectric constant of silicon nitride formedby chemical vapor deposition (CVD) on thermallygrown silicon dioxide to enhance the composite storagemedium's dielectric constant and to reduce pinholes inthe thinner silicon dioxide (not all DRAMmanufacturers utilized this option); plasma etchtechnology to produce steeper walls or trenches toreduce tapered structures which take up silicon realestate (chip area) and an optical wafer stepper to reducethe design rules from three to less than two microns.Rideout [296] and Chatterjee [299] have also reviewedthese DRAM advances.

The 256K DRAM further reduced the design ruleto the 1.5-2 |nm range and introduced refractory metalsilicides to reduce the interconnect wiring delay [44]and aluminum metal for double and triple polysilicontechnologies. The M-bit DRAM era, initially a shrinkof the original 2 u.m 256K DRAM design, approached1 |iim design rules (see Table 2); more importantly,however, was the introduction of two three-dimensional (3-D) trench charge storage capacitors(see Figures 9 and 10). Sah has noted that the goal ofthese 3-D capacitor designs was to reduce the planararea of the storage capacitor while maintaining thestorage capacitance at more than 32 fF to hold morethan 106 electrons at a VDD of 5V to limit soft errors[44]. In the stack capacitor design, multilayers ofconductors (poly Si or Al) and insulators (silicondioxide and silicon nitride) are stacked on top of thepass transistor. In the trench capacitor design, a trenchis etched in the silicon and an MOS storage capacitoris fabricated in the trench, adjacent to the passtransistor which remains on the planar surface. In this

case, the trench depth is about 10 jum and the spatialarea is about 6-9 Jim2. Chatterjee and colleagues atTexas Instruments introduced a structure which placedthe pass transistor inside the trench to further conservesilicon real estate [300,301].

The 4M DRAM era introduced the sub-microndesign rule regime at 0.8 ju,m with 3-D storagecapacitors. The types and features of storage celldesigns have subsequently proliferated [44,302,303].The decreasing design rules result in higher speedand reduced power-delay product as a result of lowercapacitance and current [44]. The power-delayproduct is additionally reduced by reducing VDD [44].

The DRAM became the test vehicle parexcellence to advance the silicon 1C processtechnology because of its repetitive memorystructure. In more recent years, however, especiallyafter the U.S. makers retreated from a significantposition in the manufacture of DRAMS, theirexpertise in the fabrication of microprocessors haspropelled the logic and microprocessor family as testvehicle drivers. Nevertheless, the DRAM continuesto drive the extendibility of personal computers (PCs)vis-a-vis the memory content.

Integrated Circuit ScalingGordon Moore's remarkedly prescient assessment

of memory component growth in 1965, initially basedon bipolar and then MOS memory density, observedthat a semilog graph of the number of bits on a memory1C versus the date of initial availability was a straightline, representing almost a doubling per year [50-53].Accordingly, a quadrupling was deduced every twoyears (consistent with the needs of the system houses)and subsequently modified to ~ 3 years around the mid-later 1970s and currently taken as 3-4 years based on a1995 assessment [53]. This analysis became enshrined as

Figure 9. One Mbit CMOS DRAM chip, courtesy of Texas Instruments Incorporated.

26