1

The RAINBOW Silver Chip Specifications

Ge6rge Wang

Atari SeMiconductor Group

Steve Saunders & Robert Alkire

Atari Sunn~vale Research Laborator~

Januar~ 23, 1984.

2

TABLE OF CONT.f:NTS

1. General Description••••••••••••••••••••••••••••••••••• 7

Z • Feat •J res •••••••••••••••••••••• + • • • • • • • • • • • • • • • • • • • • • • • 7

3. E:lock DiagraM ••••••••••••••••••••••••••••••••••••••••• 7

tt. Pin AssignMent •••••••••••••••••••••••••••••••••••••••• 7

5. Pin Descriptions•••••••••••••••••••••••••••••••••••••• 8

6. Functional DescriptionS•••••••••••••••••••••••••••••• 13

6.2

6.3

6 •. q

Overview •••••••••••••••••••••••••••••••••••••••• 13

General terMinolog~··••••••••••••••••••••••••••• 14

6.2.1

6.2.2

6.2.3

6.2.5

6.2.6

General

F'ict,ure data forMa-t,. + • • + + • • • • • + + • + • + + • • + •

Object priorities•••••••••••••••••••••••• 15

Object transparenc~•••••••••••••••••••••• 15

Object paraMeters•••••••••••••••••••••••• 17

dat;:; fOT'Mat + • • + + + + + • + • + • • + + • + ~ + • • ~ • 21

Co 1 ot' 1'1ap • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 22

block descr ipticm. • + • • • • • + • • + • • • • • + • • • • • 23

Line obJect active logic•••••••••••••••••••••••• 26

Y paraMeter logic•••••••••••••••••••••••• 26

6.4.2 Length paraMeter logic••••••••••••••••••• 29

Seal€·~ Y lo

6.6

6.7

6.8

6.9

6.5.4

6.5.5

6.5.6

6.5.7

Object

6.6.1

6.6.2

6.6.3

Pi:-:el

3

TABLE OF CONTENTS

·--· -~ ·• - ~~- . .

TABLE OF CONTENTS CCon't)

6.10 Origin update sequencer bl(JCJ.: ........................ 72

6.10.1 Origin and stride logic••••••••••••••••• 72

6.1 :L Address generation logic block•••••••••••••••••• 75

6.1:L.1 Link register & link counter •••••••••••• 75

6.11.2 Pixel word counter logic•••••••••••••••• 76

6.12 ParaMeter load logic block•••••••••••••••••••••• 79

ParaMeter load request logic•••••••••••• 79

ParaMeter load sequencer logic•••••••••• 81

6. 1~~ Data and status bus interface logic••••••••••••• 86

Data bus interface logic•••••••••••••••• 86

Status line outputs••••••••••••••••••••• 86

6.14 Rainbow s~steM configuration•••••••••••••••••••• 91

7. ParaMeter Register organization••••••••••••••••••••••• 93

7.1 Addressable register•••••••••••••••••••••••••••• 93

7.2 ParaMeter block la~out•••••••••••••••••••••••••• 95

B • M a~< i M u 1"1 Rat i n g • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • • 1 0 4

9. Capaci·t:.ance •••••••••••••••••••••••• ~•••••••••••••••••• 10~i

1 (). o.c. Characterestics •••• • • • • • • • ~ + • • • + + • • • • • • • • • • • • + + • • 106

11. A.C. Characterestics•••••••••••••••••••••••••••••••••• 107

. - ~:

5

TAE:LE OF I_LLUSTF~ATIONS

Ftqur'e 1 An exaMple of object transparenc~··••••••••••••••••• 16

Fiqure 2 Functions of Origin, stride, X and Y - ~araMeter •••••• 18

Figure 3 F•.•nction of Link register •••••••••••• • • •• • • • • ~ • • • • • • 20

Figure 4 Principal functional blocks of Silver chiP•••••••••• 25

Figure 5 Principal functional block diagraM of line object active logic•••••••••••••••••••••••••••••••••••••••• 37

Fi

6

TABLE OF ILLUSTRATIONS

7

1 • GENE:f\~tb· DESCf\IF'TION

PIUS -

The Rainbow-Silver chip contains eight ObJect processors. Each ObJect processor is responsible for requesting inforMation froM video MeMor~, processing it and delivering it line b~ line to the Gold chip. All ObJect processors are func~ionall~ identical with onl~ different. displa~ priorit:ies. To perfor-M the graphics displa~~~ capabilit~ it requires that. the Rainbow-Silver chip wol'ks t·))J-~ w i ·t.h the Rainbow-Go 1 d chip t..o.g..e-i:;h-e-r • ~

@. 1 'I t:mt~rrt-i-Ftl3-Ct10S techno 1 og~. @ Access to 1M b~tes of MeMor~ over 16 bit bus. @ On-chip Direct MeMor~ access functions. @ ObJect Transparenc~. @ Modular hardware allows eas~ expansion. @ Independent Video/CPU clocks @ Independent Horizontal and Vert:ical Magnification. @ MiniMal CPU intervention. @ SiMple prograMMing Model for paraMeter and displa~ data.

PIXEL OJ.KC1' ACTI VE

,r_

Pll+t.POH!

('f'(N

PJ)((L AODiit£'SS

STATUS

PIUS

•••

tHPDT

IUF'FER

...

ST#InJ51'DATA sa-sc: na-115 AD0/VE0

AD1/VE1 AD2/VE2 AD3/VE3 AD4/VE4 AD5/VE5 AD6/VE6 AD7/VE7 AD8/VD0 AD9t"VD1

AD10/VD2 AD11/VD3 AD121'VD4 AD131'VD5

vee RDS S0 S1 S2 DA AS WDs>RCR 'PR PG RRO RRI EVI ODI

JiUS LIN( OD J E:CT £H$o[HS2~H9S -f--··-~·-tH_>_US--+---'1 &~::~~~OH AD141'VD6 Eyo - OA:fGJH UPIJATC ACT I 'I[

L.OGtC ..__"""_"_ ... ~--- UOUEHCU 1

,

I I Hill

AD1S/VD7 ODO -.A16 OVDS A1'7 EVDS A18 SCLK GHD A19

(~[) 0 /~)E 0

AD7 I'JE7

AD8/VDO

AD1~'i/VD7

A1(:,-A1El A1.9

GND

I/D 1 ·-·8

I/0 9-16

-I/0 17--19

21

I 20

8

Function

The·s ~:: 1 :i.!-,t-:~s con s t:i. .J( the t i ,"le -Multiplexed Address bus AD to A7, Data bus DO to D7 and Video Even pixel bus VEO to VE7. The Address bus and Data bus are valid inputs when the Processor Grant pin PG is LOW. The CPU uses these lines to to write data into the Silver chip. While the status pins SO to SZ indicate Pixel Active or Link Load Active conditions, the Address bus will be used as outputs to fetch pixel data or paraMeter block into the Silver chip. Video Even pixel bus lines VEO to VE7 are valid outputs when the Status lies SO to SZ indicate video pixel condition being active.

These lines constitute the tiMe Multiplexed Address bus AS to A15 Data b u s DB to D15 and Video Odd Pixel bus VDO to VD7. The function and validilit~ of the Address bus and Data bus are described in the above sc~ct:icm. Video Odd pixel bus lines are valid outputs when the Status pins SO to SZ indicate video pixel condiction being active-?.

These Address bus are inputs when the Processor Grant pin PG is LOW. While the Status input pins SO to 82 indicate Pixel active or Link Load active conditions, these Address bus will be used as outputs.

Ground.

9

SCLK I 22

EVDS I/0 23

OVDS I/0 24

ODO 0 25

Function

Silver Chip Clock; the clock provides the basic tiMing ~or the Silver chip.

Even pixel video data strobe; i~ this Silver gets the even pixel priorit~ EVI HIGH and the even pixel is active in this chip, then EVDS is asserted to LOW whenever this even pixel is processed and read~ to be strobed. In addition, both EVDS and OVDS together provide a signal internall~ to in~orM the chip that it can proceed to process next pair o~ pixel. In Most tiMe, this is an input. Onl~ when the Evi input is high and the priorit~ is not passed to the next Silver chip, then this pin becoMe an output.

Odd pixel video data strobe; i~ this Silver gets the even pixel priorit~ ODI HIGH and the even pixel is active in this chip, then OVDS is asserted to LOW whenever this odd pixel is processed and read~ to be strobed. In addition, both EVDS and OVDS together provide a signal internall~ to inforM the chip that it can proceed to process next pair of pixel. In Most tiMe, this is an input. Onl~ when the ODI input is high and the priorit~ is not passed to the next Silver chip, then this pin becoMe an output.

Odd pixel priorit~ out; when this output is HICH, the Silver chip passes its odd pixel priorit~ to the next chip which has an input ODI connected to this output.

E.in Description(con't)

EVO 0 26

ODI I 27

EVI I 28

I 29

0 30

10

Function

Even pixel priorit~ out; when this output is HIGH, the Silver chip passes its Even pixel priorit~ to the next chip which has an input EVI connected to this o•.•t.p•..Jt.

Odd pixel priorit~ in; when this input is HIGH,it Means the Silver gets priorit~ to process the odd pixel i¥ an~ obJect is active in the chip. Otherwise, it will pass the priorit~ to the next chip through the ODO pin.

Even pixel priorit~ in; when this input is H~GH, it Means the Silver chip gets the priorit~ to process the even pixel if an~ obJect is active in the chip. Otherwise, it will pass its priorit~ to the next chip

' through the EVO pin.

Video bus Release InCincludes both odd and even pixel bus); the HIGH level of this input indicates the Video bus is released b~ the high priorit~ Silver chip and this chip can access MeMor~ s~steM through the Video bus.

Video bus Release Out; the HIGH level of this output indicates the the video bus is released b~ this chip and granted it to the next chip whose input pin RRI connected to this output.

~-~~~~ .:... ·. . . ... ... _, :. . .. . ......... -~ ... -· -~ -· . .

Pi...o.._Q~scription

12

E:Jn D~!scriptiorr(con~t)

F' :i.r:L!

DA I/0 35

sz-so 0 36-38

FWS I/0 39

\.'CC I 40

funct:i.on

, -

Data Acknowledge; it ~s used as an output to in~orM CPU that data trans~er is coMpleted. It is used as an input to indicate that a MeMor~ read c~cle is ~inished and valid data is on the Data bus.

These status lines ~roM the Gold chip provide inf~Mation to the Silver chip as follows:

sz S1 so Oeser iptior.!.

0 0 0 F~efresh Actiw~ 0 0 1 No op er at, :ion 0 1 0 Abort Met1or~ c~c:l1~ 0 1 1 r~ese·t:. 1 0 0 Top of screen in Ever. field 1 0 1 Top of screen in Odd ~ield 1 :L 0 Pb~el ActivE~ 1 1 1 - Load Active ..

(Ovv~.ev Read Data Strobe; the Silver chip will use this pin as output to read video data or paraMeter block froM MeMor~ into itself. CPU Ma~ use this input to read data ~roM the Silver chip such as data in the Link register. However,this input is used as a Read Data Strobe b~ CPU onl~ when both Processor Request PR and Processor Grant PG are LOW. Otherwise, this pin is an output Most tiMes.

VCC is the +5V power suppl~.

~:z=~e~ _:_ ~ · ·- --- ·~ -----· .. -. --- . --

13

6. FUNCTIONAL DESCRIPTIONS

6.1 [tV(-?"f''!'i•2W It The Rainbow video graphics s~st,eM is obJect based. fJ{l displa~ activit~ is described in Movabl&~, variable-sT-:z:.e, MultiMode objects. An object is like a sprite, but More general, like a coMbination of Antic's pla~field and pla~ers. ObJec~ are not liMited in size, and can be reused in vertical sequence. Thus the displa~ horizontal coMplexit~ is liMite~ to the nuMber of hardware objects supplied in the Silver chip ("~ object processors are contained in the chip now), but is not liMited vertical!~.

The screen is organized as an arra~ of square pixels. The standard resolution for NTSC displa~ is 610 horizontal b~ qao vertical. All graphics and ·text fonts are represented in terM of pixels of this size. The reduced space-resolution Modes Ma~ turn out to be far More often usedt but this fine grained ,~ description is chosen as a standard that should cover all our ~ ' r ( P" ''st;mdard-video" needs, on NTSC, PAL and f

'··

14

6.2 ~eneral TerMinolog~

Rainbow's doMain of coMpetence is translation of MeMor~represented graphics into screen-displa~ed graphics. The graphical space is "Z 1/Z" DiMensiont i.e. Mar.~ Z-D objects that Move independent!~ and overla~ and obscure each other. The MeMor~ representation . The data in a source pixel represents not an absolute color but a selection frDt'1 a color Map. A portion of th~? picture, called the "window" t is selected for displa~ed at an~ one tiMe. The picture can be of arbitar~ size which Ma~ be Much larger than the screen. The window can be the entire picture, or onl~ a piece of it, located an~where on the picture . Pixel data froM the selected window is fetched and trans·f'orMed b~ the "Object processor" ir·,to a streaM of video data to be sent to the CRT. The fetching and interpretation of pi: wa• s "bit,'1ap" and "runcode". E:it1'1ap r

15

6.2.2 ObJect priorities

full screen Rainbow displa~ is coMposed of obJects. F~ainbow to-Jill be capable of processing as Man~~~ight ob j t::cts on th,~ saMe sca n 1 irH? as trH?r e are ·: ,.'"'?·G-·:t,-obJect processor Modules included in the hardware

J:J_f.i_ •.•rat,ion of the Si ver chi Object Processor ..s can be vertical!~ reused, and.J wi 11 in fact) reload itself at the end of a window with the paraMeter ~'5r for its next obJect without CPU intervention.

T~picall~ one object will serve as the background analogous to .~NTIC"s "pla~field", and others will be sMaller Moving pla~ers, Missles, trees 1 faces, text areas, or whatever is required. If the screen is split into upper and lower sections, the background as well as the other objects Ma~ be reloaded at the boundar~. The background will usuall~ be the lowest priorit~ object. Priorit~ is in a fixed sequence aMong object processors. If priorit~ aMong objects needs to be rearranged, the object paraMeters can be swapped between the object processors. This is accoMplished b~ swapping the paraMeter block pointers in MeMor~. Moving or cop~ing the contents of the blocks is not required.

6.2.3 Q~Ject transparenc~

It is soMc~tit'\es desirable~ to put 11 holes" into objects thus allowing obj8cts norMall~ obscured to appear through the holes. This feature is called transparenc~. Each object processor has a transparent paraMeter which can redefine the interpretation of the .pixel data value so that instead of displa~ing a color, a hole is Made in its place.

An exaMple of transparenc~ is shown in Figure 1 where two objects are partiall~ overlapping. Object processor 12 is displa~ing a window froM picture II and object proeessor +1 is displa~ing a higher priorit~ iMage with transparenc~ froM picture II. At point A, no object is active so background is displa~ed. At point 8, Object 2 becoMes active and is displa~ed. At point C, Object 1 becoMes active and will obscure Object 2 since it is of higher priorit~. At point D, Object 1 begins r·eading pi~

16

Figure 1. An exaMple of Object transparenc~.

\ i

VIDEO MEMORY !

PICTURE

PIC1URE ii

WINDOW

CRT

, ~. :, ·.

17

Object 1 then ~ields priorit~ to others. In this case Object 2, which is the next lower priorit~ object, begins displa~ing its own pixel data.

6.2.4 Object paraMeters

The paraMet

18

Figure z. Functions of origint stridet X and Y paraMeters.

VIDEO MEMORY

PICTURE

X y

ORIGIN WINDOW 1

OBJECT LENGTH

,_____,j 1l

WIDTH

STRIDE CRT

19

pixel or each line, the nuMber of tiMes given b~ the scale factor. Here 0 value Means no scaling. IMpleMenting this effect in the Y direction with interlaced scan requires thateach line be repeated half as Man~ tiMes in each field. For s cale Y = 3

20

Figure 3. Function of Link register

· :~~:

21

6.2.5 Pixel data forMat

Pixel data -- the actual contents of pictures -- is stored in Z-diMensicnal arra~s of 16-bit words. Each word of a Picture arra~ has the saMe forMat, deterMined b~ the coding and Depth paraMeters as followsr

CODING = a: BITMAP DATA

DEPTH 15 e

0

P14 I P12 I P10 I P8 I P6 I P4 I P2 I P0 I

2 P12 I P8 I P4 I P0

3 PS I P0

CODING 1: RUHCODED DATA

15 8 7 e

~------R-U_N_c_o_D_E_L_E_N_G_T_H ______ _.I._ ________ P_I_X_E_L_D_A_T_A __________ f

22

6.2.6 Color Mill?..

Colors to be generated b~ rainbow are stored in a 256-location Mr~i"l01'':J called t!1e "Color Map 11 which is a separate chip in the Rainbow S';JsteM. Thus a r~airabow screenful can have •-•P to 256 di-stinct colors (unless the CPU reload the color Map within a field). Each location contains twelve bits of color infroMation so that the total range of the accessible colors is ~096. Four bits data in the color Map specif':J the level of each of red, green and blue. Shades of gra':J will be generated b':J equal values for each calor, giving 16 gra';J levels (including black and white levels).

The color Map holds, besides the color values, 4 bits in each. location far flags. One of the flag bits is to be used b':J external circuitr';J to be enable external video data, so that Rainbow-generated and external iMages (froM a video disk, for instance) can be coMbined an a pixel-b~;J-pixel bais. Other flags Ma':J be used to enable external texture-generation signals or sMoothing filters.

Other encadings of color values are posssible, and Rainbow does not prevent their use. The choice of color and flag encoding will be Made b':J S':JSteMs designer, will be based on the relative virtues of each encoding (perforMance, ease of Manipulation, and COMP3tibil:i.t':J)+

The color Map bit allocations are:

15 14 13 12 11 10 9 8 7 6 5 ~ 3 2 1 0

I -· -- ------ I I -·-------- I l ________ l l ________ l

Flag F~ed Green

23

6.3 General Block Description

The silver chip contains several functional blocks such as pixel object active, line object active, object active priorit~, origin update seqr_rencel''t pi:

24

The Origin Update Sequencer is responsible for updating the origin which is used as a pointer to a MeMor~ word of the left-Most pixels of the obJect. It will be updated b~ adding one stride or two stride value to origin on a line to line base, This logic circuit is designed for one per each Object processor.

The Pixel Address Counter is responsible for~etecting if an~ an~ pixel needs to be fetched and deterMining ~hether a pair of new pixels or just a new odd pixel has to be fetched. This logic circuit is designed for one per each ObJect processor.

The Pixel Processor is responsible for processing pixel data, adding the color index, detecting the transparenc~ and strobing the even and odd pixel data to the Gold chip. Based on the value of Depth and pixel offset paraMeter, each pixel data will be extracted froM a word

0 w (/) (/) :z: :z:

26

6.4 Lin~;) ob.ject. active logic

The line object active logic is responsible for deterMining if an~ of the objects are active an~where within the scan line en a line b~ line basis. It contains Y, Scale Y and Length paraMeters to find if an object is active withira a line and to be scaled in the displa~. The Y paraMeter deterMines when the top Most line of an object is active, the length paraMeter deterMines the nuMber of lines after and including the active top line that the object is active and the Scale Y paraMeter deterMines how Man~ tiMes that the saMe line has to be repeated in the displa~. Figure 5 shows the detailed block diagraM of the Line Object Active Logic.

Each object is processed sequential!~ for line object active state

27

If Odd~ = Oddfield then topline := Y = linecount

28

If Y is odd and an even field is being processedt then topline is Y+1 = linecount. Adding 1 to an odd Y results in More bits Modified than Just the LSB. Thereforet we use the Method described above to avoid an actual hardware addition.

If OddY and not Oddfield then to~line := Last

CoMbining the three precding algorithM we have:

If not Odd~ or Oddfield then topline != Y = linecount else topline := LastCY = linecount

The hardware used to find topline is the Y paraMeter register arra~, line counter, Y/line equalit~ coMparator, Ylag register and a portion of the line object active decoder. The line object active decoder is AND-OR-NOT coMbinatorial or PLA st~le logic. The Y paraMeter register arra~ is a10 bit b~ 12 object arra~ with data inputs froM PBus lines 0 to 9. Data is strobed in b~ paraMeter load pulse Pld5. Bit 0 of the output or OddY goes directl~ into the LOA decoder. Output bits 1-9 are coMpared b~ a equalit~ coMparator to the output bits o •• B of the line counter. This perforMs the operation of Y = linecount. The output CTL) of the equalit~ coMparator goes directl~ into the LOA decoder and into the input of a sta~e register YLAG. The output CDTL) of the state register, selected b~ LOSELt goes to the LOA decoder which perforMs the function of Last

_ ·~z~_: ..

29

Truth table of Topline is:

EvenF OddY Tl.. DTL Top line

I 1 1 X 1 L- 1 1 1 X 0 I 0 0 X 1 X I 1 0 X 0 X I 0 X 0 1 X I 1 X 0 0 X I 0

The length paraMeter represents the nuMber of lines in a fraMe that an obJect is active starting at the Y position. The length extends froM 0

" - -- . .::.

30

In hardware, the Length/2 is obtained froM bits 1 to 9 of the length counter. The addition to length/Z is accoMplished b~ coMparing the length counter to one less than what would be norMall~ coMpared to. This "procPastinates" tt1e add:L ·t-.:inn to th(-? length counter' into the length counter's terMinating count. The length procrastination bit is then the Le-ngth/Z's increMent or COddlen AND 1 or Length/2 = LPB.

Scale Y, Origin and Stride paraMeters control the MechanisM for the pixel address to the beginning of the next line of the object.

The Seal

31

The iMpleMentation of scale Y is soMewhat coMplicated b~ interlaced scanning. An even scale

32

If the repeats are controlled b~ a counter, then the counter woule be loaded with scale ~/2, decreMented ever~ line and the terMinal count would be 1 for scale ~/2 and 0 for scale ~+1 12. The repeat sequence c~n be expressed in terMs of the terMinal count:

scale '3+1 I

odd odd odd odd even

:·' - don't,

terMinal ~ I field I count

even even (0,1.):« even odd

~-:

33

For Y = 0, stride = 1 and Origin = 100:

I CurrE!nl 0-r- i

34

Input:

evenf odds tl dtl l ast tc oddscale I tc

----------------------------------------------1~--------x X X X X 0- I 0 0 0 1 X X 1 I 1 0 1 1 X X 1 I 0 1 0 1 X X 1 I 0 1 1 X 1 X 1 I 1 0 X 0 X 0 1 I 1 X 0 0 X 0 1 I 1 1 1 X 0 0 1 I 1 0 X 0 X 1 1 I 0 X 0 0 X 1 1 I 0 1 1 X 0 1 1 I 0

The scale s logic consist of a 6 bit seal~ y paraMeter register , a 5 bit counter and the pixel data pointer update decoder. The scale y paraM~ter register is loaded by the paraMeter data load signal Pld7 ~roM data bits 10 through 15. The last significant bitt oddscale, goes to the line object active decoder ~or terMinal count and to the pixel data pointer update decoder for part of scale s =0. The5 Most significant bits o~ the scale s register represe~t the value and if zero, then the least significant bit (sc=O> will coMpare to bitwise to terMinal count.

Scale s counter - 0 Scale s counter - 1

+-·-. -· t -·

scl=O AND NOT scO sci::::Q AND scO

The pixel data pointer update decoder contains the decision Making process to update the scale y counter and terMinal count and control the origin/stride update circuit. The inputs are: object_active_on_line f __ Obji~ct (topl:i.n

35

The outputs that control the scale ~ counter are load counter (lds~) and decreMent counter Csc-1) and next next terMinal count state (ntc) which causes terMinal count to pass to the next state. The output for the Origin/stride logic are: enable Origin+ stride CENS), and enable Origin+ . The algorithM that represents th

. """ .. . .... ; -.. .. - . ..

36

F'b:el data poin·ter update truth tablft

Input:

loa topline sr=O tc scl=O scO I ens en2s ntc Ids~ sc-1

-----------------------------------~---------------------------0 X X X X X I 0-0 0 0 0 1 1 1 1 X X I 0 1l 1 0 0 1 1 1 0 X X I 1 0 1 0 0 1 1 0 X X X I 0 0 1 1 0 1 0 1 X X X I 0 1 0 0 0 1 o o o 1 o I 1 o 1 1 o 1 o o 1 1 o I o o o o 1 1 o o o 1 1 I o o o o 1 1 o o 1 1 1 I 1 o 1 1 o 1 0 0 X 0 X I 0 0 0 0 1

PBUS

OSEL

PLD7

PBUS

OSEL

PLD5

37

Principal functional block of Line ObJect Active logic.

SCALE Y

REGISTER

1~~. ___ ...

PBUS

OSEL

PLD7

LCNT

ODDSCALE

OSEL

LDSY

SY-1

ueu

NEWLINE

SR=0

SCALE Y COUNTER

see

SHORT

"0"

L2=0

L1

La

EVEF BIT0

TL

TOPSCREEH------~

DTL LINE CLEAR COUNTER

OSEL

PIXEL DATA PTR

UPDATE

SEQUENCER

LOA

LIHE OBJECT

ACTIVE

DECODER

NEXT SHORT

OSEL LDE

ENS

EHS2

LD9

LDSY

SY-1

TOPLIHE

OD

LCHT

SHORT

38

6.5 Pixel object active block

The Pixel object active block is the first stage of the three stage pipeline archicture. This stage is responsible for deterMining within a video line if and when an object is active, update the source pixel address for bit Mapped data, and control the fetching of run length encod~~data. There is a pixel object active circuit foreach each ObJect processor. It uses the X, Width, Scale X and Coding paraMeters to creat the outputs: Object active to the second stage of pipline ObJect Active Priorit~ block, Pixel address increMent to the Pixel Address counter and run length encoded data f~tch signals to the MeMor~ Sequencer. Each ObJect processor 1 s active statet address and run length encoded fetch inforMation MUst be deterMined independent!~ and at pixel colock speeds; therefore, the pixel object active logic Must be replicated for each object processor. Basicall~t this block contains X paraMeter logict Width paraMeter logict Scale X logic and the Run length logic. Figure 6 shows the principal functional block diagraM of the Pixel ObJect Active logic.

The X paraMeter specifices the position of the object on the screen in the horizontal direction. The paraMeter represents the nuMber of screen pixels froM the left of the screen to the left edge of the object. If X is specified greater than the offset the pixel on the right side of the screent the object will not appear at all. The range of the X paraMeter is froM 0 to 1023.

Width is the horizontal size of an object, Measured in scren pixels. If Width is zerot the object will not bt! displa~:F:>d. If "~Hdth plus X" iMPl~; that, part, of the object is off the right side of the screen, that part is not processed or displa~ed, The range of the Width paraMeter is froM 0 to 1023.

The Scale X factor Magnifies an object in the horizontal dirction. Each source pixel will appear Scale X +1 tiMes in succession. Magnification is achieved b~ repeating each pixel the nuMber of tiMes given b~ the Scale X factor. Scale X is ignored for run length encoded data. The range of the Scale X paraMeter is froM 0 to 63.

39

The coding paraMeter selects coding forMat of the source pixel data, cleared for bitMap-at~le data (further described b~ Depth paraMeter) or set for run length encoded data ( r·uncoc·ied) •

6.5.2 P._ipel!5

Each horizontal line scans at a period of 63.4 usecs. For 640 pixels, we need to average about 99 nsecs per pixel. This includes fetching, processing (bit field extraction and color index add) and transfer to line buffer. It should be painfull~ clear that there are a nuMber of serious bottle necks that affect the perforMance of Rainbow (for that Matther an~ other IC's atteMpting siMilar perforMance). These botlenecks are the MeMor~ bandwidth < the MeMor~ speed tiMes nuMber of parallel bits), process speed of Rainbow and transfer speed of pixel data to the line buffer cess i n

.lJO

6.5.3 Functions of the Pixel obJect active logic

The POA logic for each object processor Must deterMine, for both the even and odd pixels in a dipel, if an object is active. It produces object active even OAE and object active odd OAD signals which og to their respective. Object Active priorit:1 block. Each pricrrit'::1 circuit deterMines which Object processor has the-highest priorit'::1• The highest priorit~ processor then goes about processing and transfering the pixel data to the line buf·fer.

The source pixel data is pointed to b'::1 a pixel bitf:ield address. In order to progress froM one source pixel to the next, we Must increMent the pixel address. Converse!~, to repeat a pixel we leave the pixel address unchanged. The Scale X paraMeter tells how Man~ tiMes a pixel address to be used before increMenting. If the coding paraMeter is cleared to bit Mapped Made, the the POA logicupdates the bit field addresses of a dipel b~ providing the pixel address counters with even and odd increMent signals PO+l, PO+Z, PE+l and PE+2. The pixel address counters Must be held current at all tiMes and and updated whether the object is being dispal~ed or not. The pixel address counters are increMented b~ one or two bit fields or not at all.

If the Coding paraMeter is set to run length encoded Mode, then the POA logicsends the MeMor~ sequencer run code fetch control signals. The logic will deterMine whether run coded d8ta is needed for the even or odd pixel and sends load run code even or load run code odd signals

ttl

6.5.1 Object active

An object is defined as being active within the rectangular region bounded b~ pixel position >=X and pixel position < X+Hidth in the horizontal direction and b~ line position >= Y and line position < Y+Length in the vertical direction. Rainbow uses the line obJect active (LOA) logic to get active on a line state. The LOA logic is described in detail in the last section 6.1. Suffice it to sa~ that the POA logic with an active on a line state. The rectangular region is Measured b~ pixel increMents and requires conversion to dipel increeMents for Rainbow.

The region bounded in the horizontal direction in dipel increMents is dipel position >= floor(X/2) and dipel position< celing((X+Width)/2). The obJect is active for both even and odd pixels within the region and inactive for the dipel position outside it, ex~ept for the following two exceptions. If X is odd and dipel position is equal to floor(X/2), then the object just becoMes active for the odd pixel onl~. If X+Width is odd and the dipei position is equal to CeilingCCX+Width)/2), then the obJect goes inactive for the odd pixel onl~. Having onl~ one pixel active in a dipel creates special cases in the start ~nd end of the object's active region for pixel address increMent and the runcoded fetch MechanisM.

6.5.5 E.hlel address incrE~Ment

If the object is active for both even and odd pixels of the dipelt then the pixel address increMent is deterMined b~ Scale X bein~ zero, one or greater than one. If Scale X is 0 (no pixels are repeated), then the increMent fo rboth even and odd pixel addresses is b~ two fields. That is, for the even pixel to advance to the next even pixel requires skipping past the odd pixel. If the Scale X is onet where each pixel is repeated once, the increMent is b~ one bitfield. Scale X greater than one requires a counter MechanisM which is initiall~ loaded with Scale X and counted down for each pixel. When the counter reaches zero or terMinal count, it is reloaded with Scale X. The pix~l address is not increMented when terMinal count is encountered in a dipel. If terMinal count occurs in the odd dipel, then both the even and odd pixel address counters are increMented b~ one. If terMinal count occurs during an even pixel,

then the previous odd pixel address required increMenting b~ a bitfield and the current even pixel address requires increMenting b~ a bitfield.

For exaMple, here are three exaMples for Scale X of 0, 1, and 2 for 5 dipels. AssuMe that the dipel address begins at 0 and the bitfield width is 1. The address for each pixel is directl~ under the '~'. Th ebitfield increMent for both even and od pixel addresses is between the curren dipel and the next dipel. The scale X count is shown for in the case of Scale X of 2.

C>XIx~J [)1(1:1KJ [)Kill!el address

0 1 1 0 1 1 0 1 even/odd

The case when the obJect just becoMes active for onl~ the odd pixel in a dipel requires exceptions to update the pixel address for the starting dipel. For Scale X equals to O, the even pixel address is increMented b~ one bitfield and the pixel address is increMented b~ two bitfields. For Scale X euqals to 1, onl~ the od pixel address is increMented b~ one bitfield. Neither pixel address is increMented for Scale X greater than 1 +

For the start dipel with onl~ the odd pixel active are three exaMples for Scale X of 0, 1 and 2 for 2 dipe1s. Again assuMe that the pixel address begin at 0 and the bitfield width is 1.

[ IlK:! [lKI)!(J DiP€·:1 0 0 1 '? ·- F' i :-:

C I y,(J Scale X=2 0 0

.tt3

[:l

44

and load the Scale X counter with z. Since Lag is set when going to dipel 4, the terMinal count of Z is interpreted as a terMinal count of 1 or ending on an odd pixel. Both even and odd pixel addresses are increMentedt Lag is reset and the Scale X counter is reloaded.

1 z 3 4 5 [~j}K] [~j}l(J t>:

.q5

We then use a register called FE (fetch even) to hold the state of predicted even pixel fetch. FE is initialized set so that the first dipel will fetch the first runcode fa rthe even pixel when the obj2ct becoMe active. An exception to this is if the first dipel onl~ has odd pixel active, then onl~ the odd pixel is fetched for.

The following table illustrates thedecision Making process for runcode fetching.

Dipel Run Code state Transition Table

Current State I Next state

---------------------~----------------·---------------------FE

ScaleX.cnt = Lag

ScaleX. cnt ·-· ScaleX.cnt =

l+Lag l+Lag

1 I I I I I I

Do even fetch, Do even pixel run codr.~ state

Do odd fetcht Do odd pixel run code stat 0

1 I Set FE, Reset Lag I Set Lag

Even Pixel Run Code State Transition Table

Current State I Next state

---------------------~-------------------------------------ScaleX.cnt, - 0

Scal~?X. cnt ·- 1 S c

46

Since the run length is grater than 1, thelogic progesses to the next dipel. In dipel 3, terMinal count occurs on the even pixel, indicating a ~etch is required ~or the odd pixel. LRCO is set and the ~etch occurs giving a run length of 1. Lag is set to coMpensate for thefetch occuring on the odd pixel just as it would for thebitMapped pixel address increMent. At dipel 4, because lag is set, the terMinal count o~ 1 is interpreted as a terMinal count of 0 resulting in a ~etch for the odd pixel. Since the run length o~ the odd pixel is O, FE is set again.

The runlengths used forthis exaMple are K I >t::l [:»:!:«] C:.KI:«J [»::1:«:1 Dipel

0 0 1 1 2 2 2 3 H•~•ncode address 1 2 0 1 0 0 Seal£~ X counteT' 0 0 0 1 0 0 Lag 1 0 0 1 0 1 FE

6. 5. 7 Pi ;.:e 1 ob ,i ec·L

47

Figure 6 Principal functional block diagraM of Pixel Object Active Logic.

PBUS -:

OSEL - SCALE X

PLD 4 ----: REGISTER

l lr .. 0 ..

... PBUS

_j OSEL -; X

REGISTER

PBUS _j

LOA

CODE

] IHDTH l REGISTER J OSEL PLD6

i

I I

RUN-LENGTH REGISTER

1-I---CNF"

lr

I SLAG ~ LAG RLAG I REGISTER

LDSX

LJ=---pJ --..-..,.Lr:-.J_ ·a .. SCALEX ~

._--~~ /RUN CODE COUNTER

SX-1 SX-2

ODDSCALE

1·~"0" X/WIDTH ·

COUNTER S/!-l=0

ir LOA _]

LAG

I

PIXEL OBJECT

ACTIVE

DECODER

NEXT PIXEL

-+---SLAG -f--- RSLG

-1---LDSX -f---LDX/1-J

-1----S/W-1 -1---W-2

-1---PO+l -+---PE+1 -I---P0+2 -+---PE+2

-+---OAE -1----0AO

-1----SX-1 -+---SX-2

48

Figure 7. The diagraM of pixel obJect active decision t.ree.

LINE OBJ ACTIVE?

X=la? OA--FF

1.1=0? X/U-1 r---L-. OA--FF

... , IN

OA--FF X ODD?

5=0?

OA--FT l.l--W-1

PE--PE+1 PO--P0+2

OA--FT OA--FT J.l--W-1 w--1.1-1 s--s-1 s--s-1

PO--P0+1

J.l=1?

OA--TF S=LAG?

l

SR=0?

OA--TT OA--TT w--w-2 1.1--W-2 RLAG LDSX

PE--PE+2 SLAG PO--P0+2 PE--PE+l

S=l+LAG?

l

OA--TT u--1.1-2 LDS RLAG

PE--PE+1 PO--PO+l

S=2+LAG?

OA--TT OA--TT 1.1--w-2 w--w-2 s--s-2 s--s-2

PO--P0+1

49

Th e ObJect acti ve priorit~ block i s the second stage of the three stage pipeline architecture. This stage is responsible for deterMining the highest priorit~ Object aMong active Objects which coMe froM the result of the first stage. If pixel data of the highest priorit~ object is transparent, then the next highest priorit~ active object will be deterMined within that c~cle. Because the pipeline structure, this stage will be frozen when the third stage is perforMing a MeMor~ fetch. In other words, the object active priorit~ logic will not proceed to process next pair of pixels when the present two pixels in the Pixel Processor Logic are obsolete and the Silver chip need to fetch pixel data to update its pixel data register. Figure 8 provides the principal functional block diagraM of the Object Active Priorit~ logic

6.6.1 Input port

The input to this block coMes fr~M the first stage of pipeline--the Pixel Object active which deterMines ObJect Active aMong Object Processors. These object active inforMation will be loaded into this Object Active Priorit~ block during phase-one clock. The loading will be coMpleted before the third stage (pixel processor) detects the transparenc~ of previous pair pixels. Once The pipeline is frozen, the ObJect Active inforMation will not be loaded in.

6. 6. 2. Q.!:~±,p ut p DT' -t~

The output froM this block provides Object Select signals indi c ated the highest priorit~ object. AMong these signals onl~ one is active at one tiMe which will be used to select the correct pixel data register in un the Pixel Processor block. The Object Select · in~orMation is provided during the phase-two clock of this pipeline stage.

; o

6.6.3 Priorit~ deterMination

The highest priorit~ obJect is deterMined through the Priorit~ Arbiter 1 in the Non-transparent case and through the Shadow register and Priarit~ Arbiter Z in pb~el transparer..-1:. case. The input obJ~st active will be arbitrated during the Phase-one clock-and sent out during the phase-two clock. Meanwhile, the input will be latched into the Shadow register during the saMe phase-two clock. Due to the pipeline archture, howevert the highest priorit~ object active stored in the Shadow register will be cleared in the phase-one clock and the Pixel Processor will feedback the pixel transparenc~ condition in the phase-two clock. If pixels in the present highest priorit~ obJect is transparentt the next highest priorit~ obJect will be deterMined b~ data in in the Shadow register and Priorit~ Arbiter 2.

The ObJect Active Priorit~ block is designed for both even and odd pixel object. The present Silver chip will pass its pixel priorit~ to the next Silver chip if there no object active in the input port latch or all active object has tl'ansparent pi:-:t-~1!:; in the chip. Th

FROM ACTI

OBJACT

OBJECT ~E LOGIC

SCK

TRAHStl

TO PRIORITY CHAIN LOGIC

0

LATCH

..... ,_ .

SHADOW

I REGISTER I I

PRIORITY 1--ARBITER

#1

'-fll

r--: MUX

PRIORITY - 1-ARBITER I-

#2

CLEAR

'1 1-'·

!.0 c .., (j)

())

J>"D r) ..,

-?~:~~ .

6. 7 E:.i :

53

For exaMple, the distance between even pixel of the last dipel and the even pixel of the current dipel is two pixels if the Scale X paraMeter is zero. If sca le X is gr a ter than ze r o , then the pixel address counter need not be updated until the pixel is repeated scale x tiMes and then is increMented b~ one 'bit field'. The depth paraMeter deterMines what the- '-bit ·field' width is ind it is depth and increMent signals Pe+1, Po+l, Pe+Z or Po+Z froM the Pixel obJect active logic that ultiMatel~ deterMine the actual increMent of the pixel address counters. The Pixel Address counters can beincreMented b~ 1, 2, 4, 8, or 16. When the coding paraMeter is set for runlength encoded pixel data, the Pixel Address counter are b~passed and the Pixel word address counters are increMented b~ one ~or each ~etch. This is the saMe as increMenting the pixel addresss counter b~ 16. Ths ~allowing table illustrates the address counter increMents:

Depth IncreMent Signal Pb:el address

counter incret'lent

0 Pe/o + 1 1 0 Pe/o + 2 2 1 Pe/o + 1 2 1 Pe/o + 2 ..q ,, L. Pc=!/0 + 1 4 2 Pe/o + 2 8 3 Pe/o + 1 8 3 Pe/o + 2 16 ~·! runlf-"ngth encoded 16

The 4 bit output of the pixel address counter associated with the obJect to be displa~ed is passed to the bit splitter uses these output Padr 0 to Padr 3 to select which bit field to use.

Each of the Pixel address counter produce a carr~ out of the ifth cc>urd:.~·H' sta

54

The Odd carr~ COC) for each object also sets the data obsolete register associated with all except the select obJect. The odd carr~ also serves as a increMent for the Pixel Word Addres counter for each object.

6.7.2 Data obsolete register

The data obsolete register is used b~ the pixel fetch decoder to deterMine if the data in the pixel data register is curfent. It is a single bit registert one for each objectt which is set b~ a odd carr~ for all object not selected and reset b~ a pixel data load for a selected object. Data in the Pixel Data register becoMes obsolete when the pixel address overflows froM the bit to the word boundar~. It becoMes current when the word is fetch froM MeMor~. The output of the data obsolete bits are selected to pass to the even pixel fetch decoder (as DOe) b~ the even pixel object active select COSELe) and to the odd pixel data fetch decoder Cas DOo) b~ the odd pixel obJect active select OSELo).

6. 7. 3 E.i· :·:e 1 f

·- ... _:. _ ' ,. ~ :2~Ji~ :

,..

'

55

The Even pixel fetch decoder translates the carries of both even and odd pixel address counters and data obsolete (selected b~ OSELe) into the shadow CS) and even pixel f C' t c h ( [) e ) ·::; t

56

The inforMation froM carries used b~ the pixel fetch translation table indicates when word boundaries cross the current dipel. If word boundar~ cross before ( 8 c ondition) the current dipel, both the even and odd carries will be set. If the word boundar~ occurs during CO condition) the current dipel then onl~ the odd carr~ will be set. If the word boundar~ occurs after

OS

OSE

CYo INIT1

us

D2

) .

.... I I PIXEL

REGISTER ~ ~

ir

0-J

IHIT1

... '---j DATA

I OBSOLETE I REGISTER

I lr

DLD

-~ ·- I ECe EVEN PIXEL

OCe I COUHTER DOe ADDRESS l·n

DSO lr PADRe I

~!:1 J+l Pe+2

. . ...-:

ECo

ODD PIXEL OCo COUNTER

~ ADDRESS I-f- PADRo I 1•1-CYo DSO

~CI1. lr I

Po+l

s I EVEN PIXEL T I

fETCH De I DECODER

LDfS PIXEL

fETCH ENES

SEQU PfR

Do

ODD PIXEL

fETCH DECODER

- -SCK

'Tl 1-'· tD c -:S tD

'.J

OJ -o o_-:S 0.. 1-' • -:S :J m n !,(1 1-'· l!'l u

ill f) I-'

0 c -!) ::J ·= c+:J m n -:Sc+ . 1-'•

0 :J OJ 1-'

r:r 1-' 0 G ~

D.. 1-'• OJ L() -:S OJ 3

0 -!;.

c+ :r fl)

..... ·-· 1-'· " ,., fl) .....

trl '.J

\f·.; ~ j~

J ,. ,,

58

6. 8 E:i.1:.~e l_f'r ocessor b 1 ock

The Pixel Processor block is the third stage of the three stage pipeline architecture. This stage is responsible for processing the pixel data froM MeMor~ to the Gold chips line buffer. The packed pixel data is loaded into the · pixel data register during a MeMory fetch and the data is then unpacked b~ the bit splitter intobit fields defined b~ the Depth paraMeter. The unpacked pixel data is added to the contents of the color index register and passed to the A/D/V (address/data/video) bus. At the saMe tiMe that the pixel data is being SUMMed with color index registert the data is also tested for zero value. If data value is zero and transparenc~ bit is set, then the pixel processor will provide data transparent infoMation to wherever is needed.

There are two sets of bits splitter, color index adder and transparenc~ logic to process two pixels

59

The purpose of the Even Shadow Register is used to teMporaril~ save pixel data which is alread~ in the Pixel Data Register but will be overwritten soon b~ a new Odd pixel Data whenever a MeMor~ fetch is

The Even shadow Register output bits 0-7 are additional!~ Multiplexed with even pixel data output bits 0-7 and 8-15 and this goes to the input f even pixel bit splitter. The Enable Even Shadow CENES) signal selects the output of the Even Shadow Register when asserted b~ the MeMor~ Sequencer during T and S Mode pixel data fetches. If the ENES is not asserted, then either the upper or lower b~te b~te of the even pixel data Register outputs pass to the Even bit splitter. The Odd data output b~te goes to the input of Odd bit splitter.

The Even Shadow Register is loaded froM the Even pixel data register output b~ the Even Shadow strobe signal CLOES). LEOS is asserted b~ the MeMor~ Sequencer during a T or S Made pixel data fetches.

6. 8. 2 t:_i t sp 1 i t~~Sl.t..

There are two bit splitter which are usee for extracting bit fields froM the 16 bit word of the Pixel Data register. The nuMber of bits in the extracted bit field is controlled b~ the Depth paraMeter. The lower order ~ bits of the pixel counter CPADRo3-PADRoO and PADRe3-PADRe0) FroM the Pixel Address Counter block controls the position of bit field within the packed pixel data word. The extracted bit field is justified to the least significant bits and balance of bits which are Make a full b~te out of the bit field are set to zero. The resulting 8 bit field output froM the bit splitter goes to the input of the Color Index suMMer.

The first stage of the bit splitter is an octal 3 to 1 MUX

60

is the unpacked bit 0. A 4 to 1 MUX selected b~ PADRx 1 and PADRx 2 is the unpacked bit 1. Two 2 to 1 MUXes selected b~ PADRx 2 is the Unpacked bit 2 and 3. Unpacked bits 4-7 are froM the first stage bits 4-7 I f depth is o, 1 or 2, the unpacked bit 4-7 ar e gated to zero. If depth is 0 or 1, then unpacked bits 2 and 3 arf:) zeroed. For depth 0 ttH? unpacY..ed-bit 1. is zeroed.

Figure 11 shows the design structure of the Bit splitter.

6.B.3 De.E..th regis ·t.er

The Depth Register is a 2 bits wide register and one regi~.;ter f

\;Jill, • • ...

~~~~:

61.

TPansparenc~ sele~ts whether a pixel data with a value of zero is interpreted as relinquishing displa~ priorit~ to a low priorit~ object or as a zero offset to the color index into the color Map. The transparenc~ paraMeter serves as a Mask to the test for zero of bit splitters' output. If a transparenc~ is encountered and the transparent paraMeter is set, then the Object Active Priorit~ block will delete the current object froM being active and rearbitrate for next highest priorit~ object.

The Transparenc~ Register is a single bit register and one fro each register. Its data input is froM PBus bit 15. The registers are loaded during a paraMeter load sequence when data and OSELe are stable and the paraMeter load 3 CPld3) signal is asserted. The Transparenc~ Register has two separate output buffers which will be selected b~ OSELo and OSELe. The output selected b~ OSELe and OSELo are AND gated with the corresponding pixel data equal to zero coMparator and the resultant flags the even and/o~ odd Object active Priorit~ block that a transparent pixel(s) occured.

LDES .__. I

DLD -7 DATA I --

PADRo3

SCK

SELe

SELo

SCK

BIT

s:LIT:ERI

PADRe

I DEPTH I

PADRo

BIT SPLITTER

SCK

..... r--L:_ . I

-

PBUS

PLD3 --4 COLOR t-' PLD3 INDEX

SUM

SCK

i LATCH ~

SCK

I

fTRANSPAR.

SCK

I

TRANSe

ADV BUS BITS 0"-7

ADV BUS BITS 8"-15

TRANSo

11 ..... ;.0 0: -:I tiJ

..... 0

I-'"D 0 -:I ;.0 ..... ;-a.t (') i) + .....

"'0 OJ 1-'

-1)

c :J (') o-. c+ I'.J ..... 0 :J OJ 1-'

r::r i-' 0 (') ;::-

0 -1)

c+ :r m

"D ..... X ro 1-'

"iJ "':1 0 (') li) l,.t'! Ul 0 "':1

t~ ';l·

~ .-' ..

Figure 11..

63

The architecture of Bit Splitter.

BIT7

BIT3

BIT6

BIT2

BIT7 9 BITS BITS

BIT3

BITl

PADR3

BIT7

BITG

BIT:S

BIT4

BIT3

BIT2

BITl

BIT0

PADR2

PADR2

DEPTH_BIT2 DEPTH_BITl

DEPTHJI-T2

DEPTH_BIT2 DEPTH-BITl

PADR1"'2

OUT _BIT3

BIT SPLITTER

OUTPUT 0"-8 OUT _BIT2

OUT -BIT1

OUTJIT0

(

64

6 + 9 t1~M£~r ':i seguenc~?r b 1 ock

The COMMunication between the CPU and the Silver chip includes the "F~oot·-JtJr i te" and the 11 F~oot·-r ead" in it :La ted b'3 CPU to ~..Jl" i te o -;-· .,, e '""' c.i F

65

The Pixel data fetch can be classified into four cases, naMel~, the DE, the DO, the S and the Runcode case. As the~ were described in the Pixel Address Counter section, the DE case Means that the pixel data to be fetch e d is the fo r the even pix e l of the current dipel. SiMilarl~, the DO case is for fetching the odd pixel data. When both pixels in the current dipel are froM the saMe object and the odd pixel to be fetched, thsi is the S case. In the S case, the valid data for the even pixel would be saved in the Shadow register less it should be destro~ed b~ the new data. For Runcode case, the length of code runs down to zero for the present pixel and Silver chip has to fetch a new b~te of Runcode for the next pixel. When status indicates Pixel Active, the A/D/V bus is available and silver needs to fetch new dipel, the Address Strobe AS and Read Data Strobe RDS signals will be asserted in order. The appropriate addresss will be provided b~ the Address Generation LOgic block. Then the MeMor~ s~steM will provide Data Acknowledge DA signal to infor the Silver chip that data on bus line is Valid. Figure 15 provide the tiMing diagraM of pixel fetch sequence.

To avoid the contention of the Mentioned MeMor~ c~cle, priorites are assigned to these MeMor~ c~cles. The highest priorit~ is assigned to the CPU Root-write/ Root-read operations. The Root-write or Root-read can happen during the pixel active period or the paraMeter load period. However, the Root-write or Root-read c~cle will not start until the current pixel data fetch or paraMeter block fecth is coMpleted. There is no contention probleM between the pixel data fetch and paraMeter load MeMor~ c~cles. Since both MeMor~ c~cles onl~ occur when the Status line indicates the appropriate status.

The MeMor~ sequencer includes three chaining control signals to resolve the arbitration probleM, naMel~, the RRI/RRO chain, EVI/EVO chain and ODI/ODO chain. FurtherMore, two broadcasting t~pe networks, the Even video d a ta strobe EVDS and Odd Video Data Strobe networks are included in the M eMor~ Sequencer block.

66

Two priorit~ chain EVI/EVO and ODI/000 have the saMe kind of functions. If EVI input is High, the chip gets priorit~ for Even pixel. If EVI input is LOw, no Matter which ObJect Processor is active in the chip for even pixel th2 Pixel Processor will not process the Even Pixel. For the EVI is High case, if none of Object processor is active in the chip or Even pixel data is transparent for all active ObJect, then rhe Silver chip will pass priorit~ to the next chip through the EVO pin.

The RRI/RRO chain r8solves the bus contention of accessing the Address/data/video bus. If the chip get RRI input High, it does Mean that the chip obtain the right to use the A/D/V bus to access MeMor~ s~steM. Otherwise, the chip can not access the MeMor~. Several conditions to release the bus Mastership b~ asserting High in the RRO pin includes:

1> Runcode request froM the next priorit~ chip, but present chip does not need to fetch data.

( RRI is High; EVI, ODI are High; EVO, 000 are Low; RCF~ i !:> Low )

2) Bus is available and both Priorit~ are released to to the next chip. < RRI is High, EVO and ODD are High)

3) Bus is available; either priorit~ chain is released to the next chip and no need to fetch the pb~el data. ( RRI is High; EVI CODI> is High, EVO COOO) is

Hi C:lh >

4) Bus is available; either priorit~ chain is released to the next chip and present pixel data fetch is coMpleted. ( RRI is High; EVI COOI) is High, EVO (000) is

High; but wait for present MeMor~ fetch is finished)

5) Bus is available; when link load active status is is off and refresh active 1s en.

FroM the above conditions, we can conclude that input RRI Must be High first, then either or both priorit~ chain has been passed to the nxt priorit~ chip or the low priorit~ chip generates runcode request, then the chip can release the RRO chain to the next chip.

67

The Video Data Strobe network includes two networks; one for Even data strobe and the other for Odd data strobe network. Each has pin

68

Figure 12. Principal functional block d i a graM of the MeMor~ s e qu e ncer.

))))Q))lr)

E j ~ 0 l ~ L ~ L ~ L < L

cY~ r~~r< r~ r~ r~r~ ~ ~ ~

I I I I I I I I I I l ... X

X I . I u E ... I l T e ~ ~ : A ~ 5 A

E . . \ ~

~ . -. ; ~ ~ ~ . ~ ~

E )l . 0 0 0 X 0 X 0 ~ II( . . ~ ~

lrr r~r~r~~r~rr l r~r~ r~ -I'

r-

l .;

T 0 0 0

~ ~ " ~ ~ ~ ~ ~ . 0 e ~ " Q ~ : . . A 5 .,. : A ~ : 1T ( O( ooc ooo6 0

L I

0 = ~ ~ I ~ i ~ ~ ~ ~ ~ l 0 ( () () ( ~ :

A i . .

r t

Figure 13.

69

TiMing diagt'aM of the "Root/read" or "Root/write" MeMor':l C':lcle.

~------------------~ PG

I I ADR/DATA ~---------~A~D~D~R~E~SS~-- VALID DATA

(FOR IJR ITE:>

l-IDS liE

DA

ADR/DATA (FOR READ)

RDSll!

DA

----~_j I I

ADDRESS VALID DATA

* THIS TIMING DIAGRAM IS FOR FIRST HALF ROOT. THE SECOND HALF ROOT READ/1-lR I TE JUST REPEATS THE SAME T H1GS.

~-- .• • - ""'\ .6

--:-~~~~

LINK LOAD

ACTIVE I

RRI

AS*

ADDR/DATA

RDS*

DA

70

TiMing di~graM of ParaMeter block load c~cle.

--------------------------------~

Dfl TO D15 I I

ADDRESS VALID DATA

I _____ __.

* THIS TIMING DIAGRAM IS FOR FIRST ~ORD OF PARAMETER LOADING. THE OTHER SEVEN WORDS HAS THE SAME TIMING DIAGRAM • .

PIXEL ACTIVE

RRI

ASll!

ADDR,.DATA

RDSll!

DA

71

TiMing diagraM of Pixel fetch MeMor~ C:lClet

~------------------------~

DB TO D15 I I

ADDRESS VALID DATA

72

6 • 1 0 Q_r_Lqj...!::!._j,!_esJ. ate s e que n c e r b 1 o c k

The Origin Update Sequencer block is a ver~ siMple logic circuit block. Its Main purpose is to provide the update origin inforMation to the Address Generation Logic block 2 3 the starting address for fetching a pixel data of a new scan line. This block contains two registers: Origin and Stride registers and a one bit adoe.r. Figur·e 16 shows the principal functional block diagraM of the Origin update Sequencer.

6.10.1 Origin and Stride lclS.i.£

The Origin register is a 20 bits register containing the Origin paraMeter which is a pointer to the upper left hand corner of the window. This register will loaded b~ the MeMor~ sequencer through the ParaMeter Bus in two consecutive words. The low word (froM bit 4 to bit 15) is loaded b~ signal Pld2 and upper word (froM bit 0 to 6) is loaded b~ signal Pld3.

The Stride register is a 12 bit register containing the Stride paraMeter which is thedistance in words froM a pixel in the picture to the pixel directl~ below it. This register is loaded b~ the MeMor~ sequencer in a word fetch. Onl~ froM bit 4 to bit 15 of the word is loaded b~ signal Pldl through the ParaM~?ter bus.

At the beginning of each line the Origin Update block will receive a signal called INIT1 which will trigger the contents of Origin and Stride are added together ~it b~ bit seriall~ through a one-bit adder. Whether Origin will be added one Stride or two tiMes Stride depends on the inputs control signal ENS or EN2S which coMes froM the Line obJect Active block.

In the case of adding one stridet ever~ bit in the Origin register is added the corre~ponding bit in the the Stride register one b~ froM the least significant bit 0. whenever a carr~ occurs in the add operation, the carr~ will store in the Carr~ register and carr~ to the next bit addition. The adding operation will repeat 20 tiMes for 20 bits.

73

In the case of ENSZt the content of the Stride register will be shift one bit position ( which is the saMe as 2 tiMes stride)t then added to the Origin bit b~ bit.

Sine~ the updated Origin is used as the starting adddress for Silver chip to fetch a new line, so the addition is needed to be done o~e line ahead+ Although the adding operation is done bit b~ bitt the operation has a full scan line tiMe to be coMpleted.

FiguT'e 16

-MSiit=

'" ~SA=

"" ~SCK

PLUA

PL11311

..... ~>~a,.

Pt.JUII

......-..._1")5&-l:S --::::: ::::: :::: PU3 -

C) .... ;:'

l ....__

L

I

L

7't

Functional block diagraM of the Origin Update Sequencer.

l ~

• QO~IJ-a ., L •• QRIR£& • '"" I--SL C< Oltl&IH II:CGJSTI:R I CIDDC£tl.

HCK

PLUL .....---- CIH

il PL>H

•• • GS1'1t9 .-----:::: • • .. . '--.. •• SL t:Yit£1 SL STRR£6 ~IC '"srn c< RST ..,. SUID£ •E&tsTU tHS

tH2S

PL>

~

75

Th e r espon si bili t~ of tl1e Add res s Gen e ration logic bloc k is to set up the s~steM bus for the inforMation excl1a nse be t ween the Rainbow chip and the CPU as well as between the Rainbow chip and the MeMor~. The CPU has to write into the Rainbow Silve r chip a Root address for the Silver chip to load ParaMeter block for a particular object.

The address presented on the s~steM bus b~ the Silver chip coMes froM three sources. The first source of the address is froM the Origin update sequencer block which provides the MeMor~ address for the first pixel of a line. The second source of address coMes froM the Pixel Word Counter which points to the MeMor~ address for the next pixel word of the current line. The third source of address is froM the Link register which is used as a pointerto load a set new paraMeters for a new object.

The Address Generation logic block contains various register and counter for holding paraMeter and generating new address. It contains Link register, Link counterand Pixel Word counter. Figure 17 shows the principal functional block diagraM of the Address generation logic.

6.11. :l Link ~_t~c,U.s·t

..,. >-'· • . ·~~~~~.;..:

a new paprMeter. Each Object processor will need eight tiMes accessing MeMor~ to coMplete a whole paraMeter block fetching. The link counter is counted up one word for one MeMor~ fetch.

6. 1 :L. 2 P i>~e 1 ~·wr d count,er' 1 o~d. c

The Pixel Word Counter is a 24 bits counter which consists of two parts, naMel~, the upper 20-bit Pixel address counter and the lower 4-bit pixel offset counter. The 20 bit pixel address counter keeps the MeMor~ address of the next MeMor~ word fetch in the current line. The 4-bit offset counter contains the offset position of the current pixel within a word.

The 4-bit counter will be able to increMent b~ various nuMber depending on the Depth ParaMeter. The increMental value will be 1, 2, 4 or 8, if the Depth value is 0 1 1, 2 or 3, respective!~.

Instead of iMpleMenting the counter straightforwardl~ b~ adding different valu~, an alternative iMpleMent is adopted to save hardware circuits. Initiall~t the Pixel offset couhter will be loaded with a value which is the Pixel offset value divided b~ 1, 2, 4 or 8 depending on the thc0 value of Dt.~pth. The "division" of the pixel offset value is siMPl~ a right shift operation.

Each tiMe a Next Pixel signal is asserted, the Pixel offset counter is increMented b~ one. If the current word boundar~ is reached, a Carr~ out signal will be generated. This Carr~ signal will serve as a signal to increMent the 20-bit Pixel word counter and an indication for a new MeMor~ word fetch if More pixel are needed to be displa~ed for the san>Me object.

The long 20-bit pixel address counter should be able to count as fast as possible for evers word fetch to MiniMizing the gates propagation tiMe. Instead of increMenting the Addresss counter right after the 1-bit offset counter rea ches the word boundar~t the increMent of the Pixel Address counter will be c>veT' 1 ap p i'~l.'.l ~" i th th(·~ data f~?tch op er at ion. Dncf? the s~steM bus is available, a internal address strobe signa will latch the content of the Pixel Addresss counter into the addre s s latch. On the rising edge

77

of the following s~steM clock, the 20-bit pixel address counter will start to increMent. This increMenting operation has to be finished in one and a half clock so that a new address can be read~ for fetching the next pixel word. In terMs of hardware, the counter is designed as a parallel counter in a 7-bit group and a ripple counter in 3 gr·oups.

78

Figu~e 17. Functional block diagraM of the Address generation logic block.

0

~~ ! 8 D

. ~ ~

~- % ~

~ u . -,....., z

~ """'•C"N-~ •=a= a c:a=""

D ~

1111111 D ~

. *

~ u ~

X -..._, w X 0 z :; Q

"'"'"•"t~.~-a IIOIJ:I=R=QAA

I t §

I) =-~

I

~ '1 ~

n

~ ~ ~ a u ~

I %

~I) ()

79

During a scan line tiMe, there are three statuses giving the Rainbow sssteM what would be doing during that status

One of the status is the Link Load Active s tatus whcih indicates that the Silver chip can per~orM the paraMeters block fetch in this period. The paraMeter load logic block is responsible for taking the request froM each Object Processor for paraMeter loading, encoding the priorit~ and generate the proper paraMeter load sequence.

The ParaMeter load logic block consists of a ParaMeter load Request state Machine, ParaMeter load Sequencer state Machine, priorit~ encoder and other coMbinational circuits. Figure 18 shows the principal ~unctional block diagraM of thw ParaMeter load logic.

The paraMeter load request logic is basicall~ a state Machine. This state Machine contains three states, naMel~t the Quiescent state, Root half written state and ParaMeter load request state. When is power on reset, the chip is in the Quiescent state. CPU will write the first half Root Ca word data) into the Silver chip. On the conditions of both Root Write RTW and Al address bit ~re Low, the state Machine enters the Root half written state. Then CPU writes the second hal~ Root into the chip. On the conditions of Root Write RTW, Al address bit are High and the Link register just being written is noi zero CLINK= 0 not true>, the state Machine will enter the ParaMeter load request state. In the paraMeter load request state, it will generate ParaMeter load request signals PLR to the priorits encoder and AONL to the ParaMeter load Sequencer state Machine. Once the paraMeter load is operation is done, the state Machine goes back to the Qui escc-?nt ~::.tat(-?.

When a ObJect Processor has just coMpleted the displa~ of a object, the ParaMeter load request state Machine will receive a object done OD signal for this particular processor. If the content of Link register of this Object Processor is zero and object done OD signal is created, then the state Machine will enter froM the Quiescent state to the praMeter load requesent

80

state. after the paraMeter load operation is coMpleted

8:l

T h ·~·' F' a-~~ aM e t e r 1 o a rj seq_ u en c (·:! r 1 o C.i i c i

fl2

The truth table of this state Machine is listed as follows and the state diagraM is shown in the Figure zo.

f'res. stat:t state

IRESETIANOLIPLSTIPLDONEIPLHALTI IRO IR1 I IRO IR1 I IPLACTILDLORILDLCI l _ ____ l ____ l ____ l ______ l ______ l l ___ l ___ l l ___ l ___ l l _____ l _____ , ____ ,

I 1 I X I X I X I X II X I X II 0 I 0 II 0 I 0 I 0 I I 0 I 1 I X I X I X II 0 I 0 II 0 I 1 II 0 I 1 I 1 I I 0 I X I 0 I X I X II 0 I 1 II l. I 1 II 0 I 0 I o I I 0 I X I 1 I X I X II 0 I :1. II :1. I 0 II 1 I 0 I o I I 0 I Xli I X I X 11:1.1111110111 I 010 I I 0 I X I 0 I 0 I 0 II :l I 0 II :1. I 1 II 0 I 1 I 0 I I 0 I X I X I 1 I X II 1 I 0 II 0 I 0 II 0 I 0 I 0 I I 0 I X I X I X I 1 II 1 I 0 II 1. I 0 II 0 I 0 I 0 I

Sta·tc~ 0 < F~O=:O, FH==O): No object requir'e!? load State :l

RTW

LINK =0

OD

RADR

PLDONE

ABORT

RESET

1

.: ._ . · ..

... I

I I PARAMETER

LOAD REQ UEST

STATE MACHINE

I SCLK

83

Principal functional block diagraM of the ParaMeter load sequenceP.

3:8 DECODER

PLH MUX 611 I--

PLR PRIORITY LOAD OBJ ~-REGISTER ENCO DER

-

K>J lr y <

PARANETER LDLOR

PLST LOAD SEQUENCER PLACT PLDONE

I STATE RESET MAC HINE

LDLC AONL -,

SCLK

a.q

Figure 19. The state Machine diagraM of the ParaMeter load request,.

. RESET 'I ABORT V LINK=O ;

RTiv A Al=l A LINK=O

8 r.:· -.}

Figure zo. The state Machine diagraM of the ParaMeter load sequenc~~ r.

RESEr

PI.OONE V PLHALT

PIST

0\ ·- .") ....

86

6. 1::l !d..It:ta and status bus in"t,

J

87

C"? 2.!::. Sl so Status DescT' i p t :i. DfJ.

0 0 0 F~efrt:~sh Active

0 0 :1. ~ -!o ClPE~r-at:i.IJf"l

0 1 0 Abort, M~?i"lOT' '3 C'jC 1 (7~

0 1 1 F~eset

1 0 0 Top of screen in Evc~n field

1 0 1 Top of screen in Cldd field

1 1 0 F' i )·(f:·~ 1 Ac ·t- i ve

1 1 1 Link Load Active~

In general, the whole scanning tiMe of a horizontal scan line ~an be divided into three active intervals. Thes are "f"~efr esh ~,cti ve 11 , 11 Pi :-~f:) 1 Active 11 and 11 Link Load ActiV(7:- 11 •

The 11 F~efY'i~~~;h ~,ct:io..le 11 r'le~ans th~? MeMor'j s'jsteM is re·freshed during this interval. This Refresh active interval starts right at the falling edge of the Horizontal S'jnc. The duration of this interval is approxiMate 10 Gold clocks c'jcles. During this interval, the Gold chip provides MeMOT''3 refresh address and refresh initiating signal AS (Address Strobe) to the external MeMors refresh circuit. Then the MeMors refresh circuit will generate Row Address Strobe RAS and respond with an DAData Acknowledge. The Gold chip will provide five MeMors addresses sequentialls during the entire Refresh Active.

The 11 F' i :-~e 1 Act, i vi::: 11 t'l

88

During the video pixel loading period ( i.e. froM one scan line before starting the displa~ to one line before ending the displ~a on tRT), the correct sequence of status generated b~ the Gold chip in order are Refresh Active, Pixel Active and Link load Active. When loading of Lin e buff e r is in c oMplete , then status onl~ o c curs Refresh Active and Pixel Active.

During noloading of video pixel period C ~.e. a whole field period Minus the pixel loadine period), the correct sequence in order is Refresh Active t then link Load Active. However, at two scan lines before data actuall~ displa~ed on CRT, the Gold chip inserts the Top of Screen in

B9

Figure 21. principal functional block diagraM of the data/status bus interface.

INPUT

BUrrER

DATA0-DATA15 DATA0-DATA15

OUTPUT

:BUFFER

REFRESH ACTIVE I

LINK LOAD ACTIVE

PIXEL ACTIVE

RESET

ABORT

TOP OF" SCREEN OF EVEN FIELD

r I ' STATUS

' I L sa

S1

S2

TOP Ot SCREEN OF ODD tlELD · T

90

Fis11..1Pe Raibow Status tiMings diagraM.

HSYNC

H:BLANK

I

PIXEL ACTI VE REGION

I

PARAMETER LOAD ACTIVE REGION

FIELD BIT ~ ~ ~------------------~,

1.!:1 :z: ..... ~ :z:

~:

91

The MiniMal Rainbow s~steM is Made froM two -ehips Silver and Golt.1. Th

"T1 .... !.0 r: . '"" . ... . ... ' ... . uee . ..128 ' U41 ' .&.161 ' •tea • U!il\l . U!ZG .., !I) .

. N

. n= II

. ~ nU f= SCLK SCl.ll! 'CLIC I -"' £YO 108 t U2& t t141 t tt .. ' UBI ' ,.2111 ' 1't21 " L '

93

The object's paraMeter block contains inforMation specif~ing the object's displa~ representation in MeMor~, the object's l oc a ti o n on the screen, its color and its spatial properties. Par a Meters are linked in a list structure. begins on a word boundar~.

To CPU the Link register is the onl~ addressable paraMeter in the Silver chip. The rest of paraMeters in the ParaMeter block are onl~ accessed internall~.

Link is the absolute address of the beginning of the next ParaMeter block to be displa~ed. Root is the address of the start of the first paraMeter block and represents the onl~ value written to an object processor b~ the CPU. Both Link and Root value share the saMe register called link register. The onl~ difference between the Link and Root is the Root points to the start position of the first paraMetr block t but the Link points to the next paraMeter block for the saMe Object processor. If the Link or Root of an Object processor is zero, no further object will be interpreted b~ that Object procesor until a new root is written. The paraMeter are coMpletel~ reloaded either a non-zero Root is written or at end of displa~ of the current object7s window.

Each Link paraMeter is a 20 bit inforMation which occupies two word MeMor~. The first 16 bits locate in the lower word and the four Most significant bits are in the higher word. Since there are eight Object processors in the Silver chiPt each object processor has its own Link register. Each Link register is assigned two consecutive addresses ( the lower value is for the lower word and the higher value is for the hi

94

FigurE~ 2't. Link registers and its assigned address.

LINK REG. BASE ADDRESS OBJECT 0

r LINK REG. BASE ADR+1

OBJECT 1 LINK REG. BASE ADR+2

1 LINK REG. BASE ADR+3 LIHK REG. BASE ADR+4

OBJECT 2

r LINK REG. BASE ADR+5 LINK REG. BASE ADR+6

OBJECT 3

i LIHK REG. BASE ADR+7 LINK REG. BASE ADR+S

OBJECT 4

J LINK REG. BASE ADR+9

LINK REG. BASE ADR+10 OBJECT 5

l LINK REG. MSE ADR+11 LIHK REG. BASE ADR+12

OBJECT 6

1 LINK REG. BASE ADR+13

LINK REG. BASE ADR+14 OBJECT 7

i LINK REG. BASE ADR+15

-·- . .... -

95

A general view of the paraMeter block is shown in the Figure 25. To CPU, onl~ the Link p araMeter register of the Silver is ar.:kir-essablt:~ and is described in t.he last section. To Gold chip, this paraMeter block ~s stored in e:d,i~r na 1 Met·wr \j and \.-J i 11 be fetched i rd:.o t!1e i nl:.er na 1 registers bs eight consecutive fetches (word addresses). The Root address is the starting address of the paraMeter block and will be written into the Gold chip b\j CPU during the initialization and/or the vertical blanking tiMe. Bit description of each paraMeter is described as follows!

The Link paraMeter is a pointer to the next object paraMeter block in MeMor\j ( word pointer, not a b\jte address). The · Object processor reloads paraMeters upon the coMpletion of the displa\j of the current obJect . This paraMeter is stored in the MeMOr\j word address as Root addresss, Root + 2.

15 14 13 12 11 10 9 8 7 6 5 4 3 e 1 . 0

LK15 LK14 1_K13 LK12 LK11

1 ~'i·-· 0

LK10 LK9 LKS LK7 LK6 LK5 LK4 LK3 LK2 LKl LK0

LK19 LK18 LK17 LK16

P

96

The la~out of the paraMeter block.

15 14 13 12 11 113 9 9 7 6 5 4 3 2 0 REGISTER

LINK REG. R0

Rl

R2

R3

R4

R5

R6

R7

15 14 13 12 11 10 8 7 6 5 4 3 2 1 e REGISTER

LK15 LK14 LK13 LK12 LK11 LK10 LK9 LKS LK7 LK6 LKS LK4 LK3 LK2 LK1 LK0 R0

ST11 ST10 ST9 STS ST7 ST6 ST5 ST4 ST3 ST2 ST1 ST0 LK19 LK18 LK17 LK16 Rl

OR12 ORll OR10 OR9 ORB OR? OR6 ORS OR4 OR3 OR2 OR1 P3 P2 Pl P0 R2

CI7 C16 CIS CI4 CI3 CI2 Cil CI0 OR19 OR18 OR17 OR16 OR15 OR14 OR13 R3

T0 RSVD D1 ne RSVD C0 X9 xa X7 X6 xs X4 X3 X2 Xl Xl3 R4

Y9 YB Y? Y6 Y5 Y4 Y3 Y2 Y1 Y0 RS

SXS SX4 SX3 SX2 SX1 sxe W9 wa W7 W6 ws W4 W3 W2 Wl we R6

. SY:J SY4 SY3 SYc SY1 SY0 1.9 1.9 L7 L6 LS L4 L3 L2 L1 L0 R7

97

1·11e s tr i d e pa ra Me te r is t he d lsta ~c e i~ wo rd s froM a p i xel in the picture to the pi xel directl~ below i t. Thi s i s a 12 bits paraMeter which is stored in the MeMor~ word address: F~oot + 2.

15 14 13 12 11 10 9 8 7 6 4 3 2

ST12 ST11 STHI ST9 STB ST7 ST6 ST5 ST4 ST3 ST1 ST0

STl:l ·-·STO Stride bits; ST:ll is the Most signi~icant bit and STO is the least signi~icant bits. These bits are located in the internal regi~d·,

98

It 15 a pointer to the upper left hand corner of the window. ·r ~- ·: :i. -=; '-/ :oi lu ::.-:· i -:; ,--,\ a 1.:! ·=-· u p u f . :2 0 f.'.'l :i. t. a rJ d r 0•

99

It gives horizontal position of a object's left edge. It is Me a su r e d in s c r een p i x el s f r oM l e ft of th e sr e en, this p a r· a 1"1 E! t

100

Q.§J?J..l.l.__E_ a r aM e t, e T'

It selects nuMber of bits used to resprent each source pixel. The relationship betwen Depth, pixels per word and the nuMber of different colors that a pixel could assuMe is:

Depth F' h~e 1 /f..Jor d bi ts/p b~el colors

3 2 8 256 2 .£t .q 16 1 8 2 .q 0 16 1 2

This paraMeter contains two bits value which is stored in the MeMor~ word address: Root + 8.

15 14 13 12 11 10 9 8 7 6 5 4 3 1

I I I Dl I ··I I I I I I I I I I I I I

:ta-·12 Dl·-00 Depth bits: 01 is the Most significant bit and DO is the least significant bit. These bits are stored in the internal r~gister R4.

101

::C t ''-c·l c-~

:l02

This paraMeter specifies the horizontal size of a window of a displa~ed obJect. If no scaling , this valu2 is equal to the horizontal size of an actual displa~ed window which Might not be equal to the horizontal size of a obJect tiMes scale factor. This paraMeter contains 10 bits value which is stored in the MeMor~ word address: Root +12.

9-0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

I I I I I I "' I ws I W> I .. I ws I "' I "3

I .. I "' I .. I Descript~icm

Width bits; W9 is the Most significant bit and HO is the least significant bit. these bits are stored in the internal ri·?g:isd·,f:::-r R6.

This paraMeter specifies the horizontal scale Magnification factor of a object. Each pixel of source pixels will appear Scale X +1 tiMes Ci.e. value 0 Means full horizontal resolution>. It contains 6 bits which is the MeMor~ word address: Root + :l2 and the MaxiMUM value is 63.

15 14 13 12 11 10 9 8 7 6 5 4 3

:l ~'.'i-·1 0 SX~j··-bX 0

I I I I I I IJ Scale X bits; SX5 is the Most significant bit and SXO is the least significant bit.

103

This paraMeter specifies the vertical size of a window of ~ displa~ed object. I f no scaling, this value is equal to th e vertical size of a obJect. If scaling, this nuMber is t,hE! length of an actual displa~ window b•Yl Mil3-ht, no·t, be value of scale factor tiMes vertical length of a object. This is a ten bits value which is stored in the MeMor~ word address: Root + 14.

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 e

I I I l l I I L9 l LS I L7 I L6 I LS I L4 I L3 I L2 l L! l LO I Bit

'!-· 0 L9- LO Length bits; L9 is the Most significant bit and LO is the least significant bit. Thses bits are stored in the internal T'egisti~r F~7.

This paraMeter specifices vertical scale Magnification factor. Each line of source pixels will appear Scale Y + 1 tiMes (i.e. value 0 Means full vertical resolution). Interlaced scan is taken into account. This is a six bits value which is stored in the MeMor~ address: Root + 14.

:l ~.'i··· · :l 0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 e

t)'(5 ·-·f:)'(0

I I l I l I l I Scale Y bits; SY5 is the Most significant bit and SYO is the least significant bit. These bits are stored in the internal T'E·~ gi~:;t,::·r F~7.

104

Storage TeMperature .--65 t,o +150 C

AMbient TeMperature under Bias 0 to +70 C

Voltage at Pin releative to Ground -·0.5 to +7 c

Power Dissipation 750 MW

note: be~ond the MaxiMuM ratings useful life Ma~ be iMpc.dr·t=::d.

105

AMbient TeMperature ParaMeters: TA=25 c; V ::::GND=OV cc

I Min I Max I Units I Test Cond+l

I c. 1n I Input Capacitance

I Cout I Output Capacitance I

I 1. o

I l.5

F p