the study of field programmable gate array based …qdg/publications/graduatetheses/...the study of...

The Study of Field ProgrammableGate Array Based Servos in Atomic,

Molecular and Optical PhysicsExperiments

by

Shi Jing Yu

B.ASc., The University of British Columbia, 2014

A THESIS SUBMITTED IN PARTIAL FULFILLMENT OFTHE REQUIREMENTS FOR THE DEGREE OF

MASTER OF APPLIED SCIENCE

in

The Faculty of Graduate and Postdoctoral Studies

(Engineering Physics)

THE UNIVERSITY OF BRITISH COLUMBIA

(Vancouver)

April 2017

c© Shi Jing Yu 2017

Abstract

The use of Field Programmable Gate Array (FPGA) is becoming increasingly popular in new

designs for instrumentation tools. Among them, the FPGA-based servo is emerging as a replace-

ment for the traditional analog servo as a more versatile, automated and remotely controllable

alternative. Despite the demonstration of FPGA servos for the control of lasers in the literature,

the practical constraints of an FPGA servo have not yet been fully investigated. This work

presents an open-source FPGA servo design that is capable of reaching a total signal latency

of 200 ns including both conversion delay and computation delay. This work also investigates

various limitations inherent in a digital implementation of a servo arising from the computation

precision of an Infinite Impulse Response (IIR) filter and the effect that signal quantization

has on the transfer function that a digital servo can implement. These technical details are

not widely discussed, but are important both for the design and the operation of the FPGA

servo. Applying the FPGA servo in an intensity stabilization application allows direct tests

of these limitations. In particular, this work compares the performance of the FPGA servo

and a high-performance commercial analog servo with a focus on key specifications including

the closed-loop bandwidth, noise floor and the resolution of the transfer functions. For closed-

loop control scenario with a bandwidth below 1 MHz, we achieve better performance with the

FPGA servo than the analog servo through the use of more complex transfer functions including

a Proportional and Integral Cubed (PI3) and a Proportional Integral and Integral (PII) with

lag-lead.

ii

Preface

All the work presented in this thesis was conducted at the Quantum Degenerate Gas (QDG)

laboratory at the University of British Columbia. The author was heavily involved through-

out the development of the FPGA servo and its application in a cold atom experiment, as

described by this thesis. The early design of the analog front-end circuit (Section 2.3) and the

investigation of the performance of the FPGA servo based on the Development and Education

board 3 (DE3) (Section 4.2.6 and Section 4.2.6) was completed upon collaboration with Emma

Fajeau; the investigation of noise floor of the two FPGA servos based on the Development and

Education board 2 (DE2) and the DE3 (Section 4.1) was completed upon collaboration with

Lin Qiao (James) Liu. The remaining work in Chapter 2, 3 and 4, include the hardware and

the firmware design of the FPGA servo, the design of the intensity stabilization setup and the

servo verification is independent and unpublished work by the author S. Yu.

The study on the relationship between the active intensity stabilization and evaporation

efficiency of trapped atoms was carried out independently by the author but was based on

a cold atom apparatus that have been built and maintained by members of the QDG lab.

(Details on this apparatus can be found at Will Gunton’s thesis [53]) The final result that

demonstrates the use of passive stability of the trap laser as the final solution to improve

evaporation efficiency (Section 5.4.4) is the result of the investigation by multiple members

that worked on the apparatus, including Will Gunton, Gene Polovy and Mariusz Semczuk (a

visitor at the time).

iii

Table of Contents

Abstract . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ii

Preface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii

Table of Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iv

List of Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii

List of Figures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . x

Glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xix

Acknowledgements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxiii

1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

2 FPGA Servo Hardware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.1 Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5

2.2 FPGA Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7

2.2.1 Selection Criteria . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

2.2.2 Compatibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9

2.3 Analog Frontend Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.1 Design Rationale . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10

2.3.2 IC Selection Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . 11

2.3.3 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

2.3.4 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17

2.4 Conversion Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

iv

Table of Contents

2.4.1 ADC and DAC Selections . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

2.4.2 Single-Ended to Differential Conversion . . . . . . . . . . . . . . . . . . . 22

2.4.3 Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.4.4 Bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24

2.4.5 Noise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

2.5 Servo Transfer Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3 FPGA Servo Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28

3.1 Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29

3.2 IIR Module . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.1 Controller Representation . . . . . . . . . . . . . . . . . . . . . . . . . . . 31

3.2.2 First-Order IIR Filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36

3.2.3 Implementation Details . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38

3.2.4 Verification and Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.2.5 Characterization: Pole and Zero Resolution . . . . . . . . . . . . . . . . . 49

3.2.6 Characterization: Resource Allocation . . . . . . . . . . . . . . . . . . . . 54

3.2.7 Comments on Computation Delay . . . . . . . . . . . . . . . . . . . . . . 57

3.2.8 Comments on PII . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58

3.2.9 More on Filter Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

3.3 Arbitrary Waveform Generator . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.3.1 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65

3.3.2 Coefficients, Residual Error and Verification . . . . . . . . . . . . . . . . 66

3.3.3 Alternative Designs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.3.4 Future Improvements . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.4 Proposal on Feature Expansion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

3.4.1 Lock-in Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69

3.4.2 Auto-Lock Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

3.4.3 Plant Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 70

4 Servo Performance and Intensity Stabilization . . . . . . . . . . . . . . . . . . 71

4.1 Self Lock Benchmark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

v

Table of Contents

4.1.1 Locking Performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72

4.1.2 Noise Suppression . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74

4.1.3 Loop Gain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.1.4 Corner Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76

4.1.5 Gain Distribution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

4.1.6 The Optimal Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80

4.2 Intensity Lock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81

4.2.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.2.2 A Note About Noise Units . . . . . . . . . . . . . . . . . . . . . . . . . . 82

4.2.3 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83

4.2.4 PII Comparison . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88

4.2.5 PI3 Improvement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90

4.2.6 PII + Lag-Lead Improvement . . . . . . . . . . . . . . . . . . . . . . . . 90

4.3 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93

5 Case Study: Evaporation in a Dipole Trap . . . . . . . . . . . . . . . . . . . . . 94

5.1 Motivation and Background . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94

5.2 Dipole Trap and Trap Frequency . . . . . . . . . . . . . . . . . . . . . . . . . . . 95

5.3 Loss Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97

5.3.1 Background Scattering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.2 Loss Due to Resonant Scattering . . . . . . . . . . . . . . . . . . . . . . . 98

5.3.3 Parametric Heating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.4 Study . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99

5.4.1 Heating Rate of Existing Trap . . . . . . . . . . . . . . . . . . . . . . . . 100

5.4.2 The Effect of Intensity Stabilization . . . . . . . . . . . . . . . . . . . . . 100

5.4.3 Passive Stability . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.4.4 Improved Evaporation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

5.5 Future Work . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104

6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

vi

Table of Contents

Bibliography . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109

Appendices

A The Servo Daughter Card . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

A.1 Power Supply . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115

A.2 Pending Design Changes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

A.3 Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 116

B The Variable Attenuator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 136

B.1 Design Details and Pending Changes . . . . . . . . . . . . . . . . . . . . . . . . 136

B.2 Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

B.3 Assembly . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

B.4 Design Files . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137

C Register Address of FPGA Peripheral . . . . . . . . . . . . . . . . . . . . . . . 141

D PC-Side Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

D.1 Command Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 144

D.2 IIR Coefficients and Screening of Transfer Functions . . . . . . . . . . . . . . . . 144

D.3 Slow DAC Calibration Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

vii

List of Tables

2.1 A summary of various servo used in the study. . . . . . . . . . . . . . . . . . . . 7

2.2 Viable ADC and DAC options, their pipeline delay, resolution, etc . . . . . . . . 22

3.1 A summary of filters implemented in various FPGA platform in this work. The

format Qx.y means that the Fixed Point (FP) representation of the coefficient

has x integer bits and y fractional bits. In the case of the Q3.28 format, a total

of 32 bits are needed to represent 1 sign bit, 3 integer bits and 28 fractional bits.

In the case of the Q5.10 format, a total of 16 bits are needed. . . . . . . . . . . . 41

3.2 Test values for the IIR filter used in the DE2 servo, where FP representation of

the the IIR coefficients, B0, B1, B2, B3, A1, A2 and A3, all have 10 bits (the

relationship between the FP numbers and the IIR coefficients can by found in

Equation 3.25 and 3.26). The implementation details of a first order IIR filter

can be found in Figure 3.4. The input width and the output width of the IIR

filter are both 14-bit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45

3.3 A summary of the computation footprint of various IIR filters with different

depth and coefficient widths, quantified by the number of 18 × 18 multipliers. . 56

3.4 Comparison of computation resources in various FPGA platforms . . . . . . . . . 57

3.5 The best fit parameters to implement a sine or a Gaussian waveform. The Ar-

bitrary Waveform Generator (AWG) is implemented as 4th order fixed point

polynomial. The parameters related to the ramp (“min”, “max” and “incre-

ment”) are 32-bit FP numbers with 16-bit fractional resolution. The parameters

for the polynomial, A0, A1, A2, A3 and A4, are 16-bit FP numbers with 10-bit

fractional resolution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66

viii

List of Tables

4.1 The expected output noise from sources in the loop in two limits assuming

G1G2 = 0.5 and all other components in the loop have unity gain. . . . . . . . . 75

A.1 The bill of material of the servo daughter card . . . . . . . . . . . . . . . . . . . 128

B.1 The bill of material of the variable attenuator unit. . . . . . . . . . . . . . . . . . 140

C.1 The address at which the IIR coefficients can be accessed in the general purpose

IIR filter tested on the DE2 FPGA. The coefficients are signed. . . . . . . . . . 142

C.2 The address at which the IIR coefficients can be accessed in the IIR filter designed

for the DE3 FPGA. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142

C.3 The register address of the Finite Impulse Response (FIR) filter. . . . . . . . . . 142

C.4 The register address for the Serial Peripheral Interface (SPI) module that is used

to control the slow Digital to Analog Converter (DAC)s in the FPGA servo based

on the DE2 and the custom-made servo daughtercard. In the daughtercard, two

Integrated-Circuit (IC)s are connected in a daisy chain fashion. To communicate

to the second IC in the chain, data has to be sent out in multiples of 3 bytes.

The SPI module is generated from Altera’s toolbox. . . . . . . . . . . . . . . . . 143

C.5 The register address of the AWG module . . . . . . . . . . . . . . . . . . . . . . 143

ix

List of Figures

2.1 A typical control loop consists a servo (also referred to as a controller), an actu-

ator (also referred to as a plant or a process) and a detector (also referred to as

the feedback). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4

2.2 The design architecture of the FPGA servo. The servo is composed of the follow-

ing modules, in the order of appearance in this chapter a) FPGA development

board b) offset circuit c) gain circuit d) slow DAC e) ADC driver f) ADC g) DAC 6

2.3 Schematics of the variable offset circuit. Both the current compensation scheme

(C306) and the voltage compensation scheme (C307) are shown. . . . . . . . . . 11

2.4 Schematics of the variable gain circuit. . . . . . . . . . . . . . . . . . . . . . . . . 13

2.5 Noise model of the offset circuit. The input noise at the op-amp Ninput is small at

1.7 nV/√

Hz. The noise from the offset voltage varies. For the input offset circuit,

Noffset is 3 nV/√

Hz and the noise level of the external offset. For the output

offset circuit, Noffset is 60 nV/√

Hz. Nmeasurement varies between 10-100 nV/√

Hz

depending on signal amplitude. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2.6 Noise level of the adder circuit highly depends on noise in the offset voltage, as

it is shown in the change in noise floor in frequencies <1 kHz. In frequencies >1

kHz the noise floor is limited by the measurement noise floor. . . . . . . . . . . . 15

2.7 Noise model of the variable gain circuit. The input noise of the Variable Gain

Amplifier (VGA) is small at 1.3 nV/√

Hz. The noise at the control input(Ngain)

is 3 nV/√

Hz in voltage, which correspond to an error of 120 ndB/√

Hz in gain. . 16

x

List of Figures

2.8 Noise at the output of the AD603 at various gain setting, with the input of the

AD603 terminated to ground. The Vector Network Analyzer (VNA) input range

is set to -44 dBV. In frequencies < 200 Hz, the effect of the input noise of the

AD603 can be observed to vary with gain. In frequencies >200 Hz, the output

noise of the AD603 can be observed as it is independent of the gain at a level of

about -142 dBV/√

Hz (this is equivalent to 79.4 nV/√

Hz). . . . . . . . . . . . . . 17

2.9 AD829 bandwidth as affected by external compensation capacitance in the cur-

rent compensation mode. The optimal capacitance is 2-4 pF for the negative

feedback configuration of AD829 with a gain of 4, feedback resistance of 4 kΩ

and feedback capacitance of 1 pF, which agrees with manufacturer’s recommen-

dation. It is important to note that the capacitance in the feedback network

affects the optimal compensation capacitance. . . . . . . . . . . . . . . . . . . . 18

2.10 AD603 has a constant bandwidth over the whole range of gain, tested between

-10 dB and 30 dB at 10 dB intervals. . . . . . . . . . . . . . . . . . . . . . . . . . 20

2.11 The technology landscape of Analog to Digital Converter (ADC)s, provided by

Analog Devices . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

2.12 Schematics of the ADC driver. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23

2.13 Investigation in the noise of signal conversion (ADC/DAC) section of the DE2

servo prototype. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26

2.14 Servo transfer function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27

3.1 The general structure of the System on Chip (SOC) design in an FPGA servo.

The exact composition of an SOC design and the interface between the FPGA

and the ADC and the DAC (represented in dotted lines) vary on a per platform

basis. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30

3.2 The Direct Form I (DFI) (left) and Direct Form II (DFII) (right) representation

of a second order IIR. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35

xi

List of Figures

3.3 An incorrect implementation of a first order IIR filter with FP coefficients (B0,

B1 and A1) with 10-bit fractional resolution. The FPGA implementation is made

up of simple operations like multiplication (×), addition (∑

), division (÷) by

the power of 2 implemented as a shift operation, saturation logic ( ) and clock

delays ( ). the width of internal path is noted in grey next to the path. The

placement of the ÷210 operation has a large effect on the effectiveness of the

implementation. The difference between the incorrect implementation and the

correct implementation shown in Figure 3.4 is highlighted here in red. . . . . . . 40

3.4 A correct implementation of a first-order IIR filter with FP coefficients (B0, B1

and A1) with 10-bit fractional resolution. The placement of ×210 and ÷210 has

a large effect on the width of the internally stored values and subsequently the

correctness of the IIR implementation. The FPGA implementation is made up

of simple operations like multiplication (×), addition (∑

), division (÷) by the

power of 2 implemented as a shift operation, saturation logic ( ) and clock

delays ( ). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40

3.5 Implementation of a 1st order IIR with a built-in gain of 1/2. The coefficients

are FP with 10-bit fractional resolution. The difference between the gain of

1/2 implementation and the unity gain implementation is highlight in red. The

division of 2 is placed at the output of the filter but the width of the internally

stored values are increased to compensate for the potential loss of the output

range. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42

3.6 Two methods for expanding the order of IIR, depth-wise (left) and length-wise

in cascaded form (right) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43

3.7 Simulation scheme of IIR in a) open-loop and b) closed-loop. Both simulation are

implemented in Hardware Description Language (HDL) and in C++ to 1) verify

the implementation of the IIR in FPGA and 2) to provide better understand of

IIR filters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47

xii

List of Figures

3.8 The closed-loop simulation with white noise as disturbance. This data shows the

spectrum at the input of the closed-loop for two versions of IIR filter: the version

of the IIR with the error in Least Significant Bit (LSB) handling (in red) and

the correct version (in blue). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48

3.9 The effect of noise amplitude on noise suppression. This shows simulation of

different level of noise injected until the servo break out of lock. . . . . . . . . . 49

3.10 Transfer function measurement (with SR780) of a Proportional and Integral (PI)

filter with chirp input of different amplitude. The measured transfer function

approach the ideal shape as the chirp signal becomes smaller in amplitude. This

suggests that the non-ideal behaviour of the implemented PI transfer function is

due to clipping at the output of the IIR filter or the FPGA servo. . . . . . . . . 54

3.11 Transfer function measurement that demonstrates the frequency resolution of

a zero in a PI filter, where coefficients has 10 bit fractional resolution. The

coefficients are set to B0 = 1024, A1 = 1024 and B1 = −1021, B1 = −1022 and

B1 = −1023 for each filter. The corner frequency of the PI filters can be found

as the 3 dB frequency (intersection with the dashed line) and are respectively 22

kHz, 14 kHz and 7.1 kHz. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55

3.12 Comparison between DE2 (left) and DE3 (right) computation resources . . . . . 55

3.13 The open-loop simulation of the PI filter and the PII filter in cascaded form,

showing the offset at the output of the PI filter and the ramp at the output of

the PII filter in cascade. As it can be observed in this figure, the input to the

filter is a sine wave with no offset. . . . . . . . . . . . . . . . . . . . . . . . . . . 59

3.14 The open-loop simulation of a second-order IIR filter configured as a PII filter.

The PII in this configuration fails to saturate at its boundary, as opposed to its

expected behaviour in Figure 3.13 with a PII filter in cascaded form. Instabilities

occur at the clock frame 6.6 · 104 (shown in the inset), 8.0 · 104, 8.8 · 104 and

9.5 · 104. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61

xiii

List of Figures

3.15 Comparison of three different digital filters all implementing a notch filter with

center frequency at 0.1fclk. Only the bandstop filter designed with the bilinear

method (lag-lead) is suitable for used in closed-loop, because the elliptic bandstop

filter changes sign at 0.7 fclk and 0.14 fclk and the FIR bandstop filter has

excessive delay. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64

3.16 A block diagram of the arbitrary waveform generator, implemented as a counter

followed by a 4th order polynomial. The counter produces a 32-bit triangular

waveform and can be controlled through internal registers: “max”, “min”, “inc”

and “prescaler”. The triangular wave at the output of the first module has a

range between “max” and “min” control and a slope of fclk · (inc/prescaler). The

polynomial coefficients are implemented as 16-bit FP numbers with 10 fractional

bits. Signal responsible for external trigger are “rst” and “trig”. . . . . . . . . . . 65

3.17 The sine and Gaussian waveform output of the AWG, with their respective resid-

ual error. The AWG has two trigger mode, a single trigger modes (in black) and

a continuous-trigger mode (in grey). . . . . . . . . . . . . . . . . . . . . . . . . . 67

3.18 An implementation proposal of lock-in amplifier in the FPGA servo. The servo

logic is divided in to demodulation, servo and modulation (what is not shown

here is the rest of the servo and the laser configured in closed-loop. Both in-phase

component (x) and 90 degree out-of-phase component (y) are recovered from the

input signal and they must be combined as complex numbers (rather than as

simple addition of the amplitudes) to generate the error signal. . . . . . . . . . . 69

4.1 The self-lock configuration is a closed-loop feedback system formed by the FPGA

servo and no other detectors or actuators. This is a convenient method for

evaluating the performance of a servo. . . . . . . . . . . . . . . . . . . . . . . . . 72

xiv

List of Figures

4.2 The self lock data of the DE2 servo and the DE3 prototype servo. The minimum

noise floors of the two servos are -152 dBV/√

Hz and -159 dBV/√

Hz. They are

equivalent to 25 nV/√

Hz and 11 nV/√

Hz respectively. The self-lock spectrum

is optimized according to techniques discussed in sections 4.1.3 - 4.1.6. Addi-

tionally, the origin of the spikes in frequencies between 60 Hz and 40 kHz more

visible on the DE2 spectrum is covered in Section 2.4.5. . . . . . . . . . . . . . . 73

4.3 The model used for analysing the noise suppression in a closed-loop servo system

based on an FPGA servo. For a simpler analysis on noise suppression regarding

gain distribution, the non tunable gain in the circuit. . . . . . . . . . . . . . . . . 74

4.4 The effect of loop gain on noise suppression. As loop gain increases the width

of the suppression band also increases. However, once the amplitude of the loop

delay resonance (at frequencies above 1 MHz) exceed the input range of the ADC,

the closed-loop system amplifies rather suppresses noise. . . . . . . . . . . . . . . 77

4.5 The effect of corner frequency on noise suppression. As the corner frequencies

of the PII filter increase the width of the suppression band also increases. The

limitation of this optimization technique is covered in the text. . . . . . . . . . . 78

4.6 The effect of G1 and G2 on noise suppression. When loop gain is kept constant,

a higher G1 leads to an improvement in noise suppression in frequencies where

noise suppression is limited by N1 (the ADC) in the noise model. . . . . . . . . 79

4.7 The effect of G2 and logic gain on noise suppression. When loop gain and G1

are kept constant, decreasing gain through the servo logic in the FPGA and

increasing G2 (the gain between the DAC and the servo output) increases the

maximum amplitude of noise that the closed-loop system can correct. . . . . . . 80

xv

List of Figures

4.8 The opto-electrical system used to study intensity stabilization. The intensity

stabilization consists of a Radio Frequency (RF) source (RF1), a variable attenu-

ator (VAtt1), an Acoustic Optical Modulator (AOM) (AOM1), a photo-detector

(PD1) and an analog or an FPGA servo. To study the performance of the in-

tensity stabilization system on various level and type of intensity noise, a noise

modulation system is constructed from a RF source (RF2), a variable attenuator

(VAtt2), an AOM (AOM2) and a noise generator. Finally, the out-of-loop detec-

tion of intensity noise of the system is accomplished via a second photo-detector

(PD2). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84

4.9 Diagram of the variable attenuator circuit with the AD829 configured in current

compensation mode. A snapshot of the layout and additional details can be

found in Appendix B. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.10 Control voltage versus transmission through the variable attenuator. It is im-

portant to note the variation in the response to input voltage and in maximum

RF suppression. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86

4.11 Transfer function of the variable attenuator + AOM + PD system. The loop

delay is about 400 ns. As the delay is dominated by the distance between the

laser beam and the ultrasonic source in the AOM, this delay is modified at various

point of the intensity stabilization study due to small positional changes but is

kept to a range of 200-400 ns. The modulation bandwidth is in excess of 3 MHz.

This opens up the use of this system in high speed intensity modulation. . . . . 87

4.12 Alternative baseline comparison of DE2, DE3 and Vescent servo for the intensity

stabilization study. All servos realize a PII transfer function to match Vescent.

The gain and corner frequencies of all servos are tuned to optimize the noise

suppression. The origin of the spikes in frequencies between 60 Hz and 40 kHz

visible on the DE2 spectrum is covered in Section 2.4.5. . . . . . . . . . . . . . . 89

4.13 Demonstration of the DE3’s ability to implement an additional integrator and

its effect on noise suppression. The corner frequency of 70 kHz is used for all

3 poles. The suppression slope changes from 40 dB/decade to 60 dB/decade as

expected. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91

xvi

List of Figures

4.14 The transfer function of the lead-lag and the lag-lead filer with center frequency

at 1 MHz and a bandwidth of 1.5 MHz. The lead-lag filter is composed of zeros

at 250 kHz and 4 MHz and poles at 500 kHz and 2 MHz. The lag-lead filter is

composed of zeros at 500 kHz and 2 MHz and poles are 250 kHz and 4 MHz. . . 92

4.15 Demonstration of the DE3’s ability to implement lag-lead filter at center fre-

quency of 700 kHz. The lag-lead filter has two effects 1) suppression of loop

resonance of the servo system 2) allowing increase in gain and thus widening of

the noise suppression band . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92

5.1 Side view of a focused Gaussian beam (left), the Gaussian-shaped potential, in

the cross section (middle) often approximated as a harmonic potential in the

deep trap limit and the top view of crossed focused beam (right). . . . . . . . . . 97

5.2 heating rate of the atom cloud when SPI held at 10W. The heating rate corre-

spond to a e-folding time of 1.9 s. this is also a screenshot not a proper plot . . . 101

5.3 Side by side comparison of Relative Intensity Noise (RIN) level responsible for

measured heating rate and RIN of laser. The constant heating rate line show

20 dB/decade slope. It appears that active intensity stabilization should reduce

heating rate. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102

5.4 Evaporation efficiency of the sample without (yellow) and with (red) intensity

stabilization. It is possible to see a small improvement in efficiency for end trap

power of 50, 25 and 12 W, but the evaporation still cannot reach the desired trap

depth. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103

5.5 passive stability of fiber laser at various power settings in RIN. . . . . . . . . . . 104

xvii

List of Figures

5.6 The atom number versus final power in the evaporation ramp using the SPI

at near its maximum power setup (where the passive stability of the laser is

relatively good) and an AOM to control the power delivered to the atoms showed

a highly efficient evaporation (η = 10). The atom number shows an apparent

drop when the ensemble is imaged at zero magnetic field since Feshbach molecules

are forming at powers below 1 W and are not imaged at low magnetic fields. The

images taken at high magnetic field show that the ensemble is still present and

still evaporating very efficiently down to powers below 100 mW. . . . . . . . . . . 105

D.1 Example output of the Personal Computer (PC) software. In this case, the user

input are zeros at -70 kHz and -1 MHz and poles at 0 and -10 MHz and the

underlying servo logic is implemented as a single IIR filter. The input forms an

Proportional Integral and Derivative (PID) controller, but IIR filter with different

coefficient resolution emulate the transfer function with different accuracy. The

resulting transfer function from the IIR filter with 16-bit coefficient (Q5.10) fails

to implement the integrator. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 146

xviii

Glossary

ECDL External Cavity Diode Laser

AO Analog Output

DDR2 Double Data Rate 2

LE Logic Element

ASIC Application-Specific Integrated Circuit

MCU Microcontroller Unit

DC Direct Current

LNA Low Noise Amplifier

ADC Analog to Digital Converter

DAC Digital to Analog Converter

ROM Read-Only-Memory

RAM Random-Access-Memory

GPIO General-Purpose Input Output

IO Input Output

PWM Pulse-Width Modulation

RC Resistor-Capacitor

PLL Phase-Locked Loop

xix

Glossary

HSMC High Speed Mezzanine Card

ADDA Analog-Digital Digital-Analog

ADA Analog-Digital-Analog

SRAM Static Random-Access Memory

SDRAM Synchronous Dynamic Random-Access Memory

HPS Hard Processor System

GBP Gain-Bandwidth Product

AMO Atomic, Molecular and Optical

QDG Quantum Degenerate Gas

FPGA Field Programmable Gate Array

PC Personal Computer

AWG Arbitrary Waveform Generator

DE0 Development and Education board 0



DE1-SOC Development and Education board 1 System on Chip

SOC System on Chip

PID Proportional Integral and Derivative

PIID Proportional double-Integral and Derivative

PD Proportional and Derivative

PI Proportional and Integral

xx

Glossary

HP High Pass

LP Low Pass

P Proportional

I Integral

D Derivative

PII Proportional Integral and Integral

PI3 Proportional and Integral Cubed

IIR Infinite Impulse Response

FP Fixed Point

FIR Finite Impulse Response

DFI Direct Form I

DFII Direct Form II

HDL Hardware Description Language

FFT Fast Fourier Transform

LSB Least Significant Bit

LUT Look-up Table

PDH Pound-Drever-Hall

NIST National Institute of Standards and Technology

AOM Acoustic Optical Modulator

LC Inductor-Capacitor

IC Integrated-Circuit

xxi

Glossary

PCB Printed-Circuit-Board

TeO2 Tellurium Dioxide

ESA Electrical Spectrum Analyzer

NEP Noise-Equivalent Power

RIN Relative Intensity Noise

TOF Time-of-Flight

MOT Magneto-Optical Trap

VNA Vector Network Analyzer

SNR Signal to Noise Ratio

RF Radio Frequency

VGA Variable Gain Amplifier

CPU Central Processing Unit

IO Input Output

ROM Read Only Memory

RAM Random Access Memory

DSP Digital Signal Processing

GUI Graphical User Interface

HDL Hardware Description Language

DDS Direct Digital Synthesizer

SPI Serial Peripheral Interface

NOP No Operation

xxii

Acknowledgements

I would like to thank my supervisor prof Kirk Madison for his unconditional support towards

my thesis project, prof David Jones for helpful conversations, Emma Fajeau, James Liu for

collaborating on the FPGA servo project and William Bowden, Mandana Amiri and Pavel

Trochtchanovitch for their insights on laser controllers, FPGA and analog circuits, respectively.

I would also like to acknowledge the Altera (now Intel FPGA) University Program for providing

free samples of the DE3 and the ADC/DAC that was used to build the DE3 servo.

Thanks to everyone at the lab who are involved in training me on tuning lasers and running

the cold atom experiments. They are, my supervisor (of course), prof James Booth, Will

Gunton, Gene Polovy, Janelle Dongen and Mariusz Semczuk. Also thanks to my peers, Kahan

Dare and Kais Jooya for adding a touch of social aspect to graduate level courses.

I would also like to thank my boyfriend, now fiance and soon husband, Jonathan Fraser

and his parents, Cindy and Peter, for their support, and most importantly, my parents, Wen

Song (Vincent) Yu and Xiu Ju (Judy) Wang, for all the foresight and sacrifice that went into

enabling me with a great education.

xxiii

Chapter 1

Introduction

The Field Programmable Gate Array (FPGA) is a rapidly developing technology that has en-

abled a broad array of applications in both basic science and industry. An FPGA chip has

the advantage of both speed and flexibility. It can achieve similar speeds to a Microcontroller

Unit (MCU) or an Application-Specific Integrated Circuit (ASIC), but unlike the MCU and

ASIC, the FPGA digital circuitry is not hardwired but can be programmed and re-programmed.

In the infancy of this technology, implementing digital logic produced circuits that ran slower,

consumed more space and were less energy efficient than competing technologies, but the ad-

vantage of flexibility and a shorter development cycle kept the FPGA in demand [1]. Over the

years, significant improvements regarding speed, space consumption and energy consumption

have been made. Additionally, more sophisticated routing mechanisms and Digital Signal Pro-

cessing (DSP) computation resources have also been implemented on FPGAs (a survey on the

FPGA technology up to 2008 can be found at [2]). These benefits and advancements have, in

turn, been enjoyed by both industrial and the scientific communities.

Like most research communities, the Atomic, Molecular and Optical (AMO) experimental

community has a strong demand for versatile instrumentation and computational tools. AMO

experiments rely on precise control of lasers including their wavelength, phase, polarization and

intensity. To accomplish this, an array of instrumentation tools are needed. The laser servo is

an instrument used to form a closed feedback loop control system to make corrections to the

laser with an actuator and a detector. (The term servo is in analogy to the use of the term

“servo in motion control.)

Traditionally, laser servos, also sometimes referred to as loop-filters, are built from analog

components like opamps and impedence networks. The design of an analog servo can be found

as early as John Hall’s original paper on the Pound-Drever-Hall (PDH) modulation method in

1

Chapter 1. Introduction

1989 [3]. In this paper, the phase detector is constructed as a mixer and the control mechanism

(servo), in the form of a Proportional Integral and Derivative (PID) filter, is built from two

cascaded op-amp stages, each implementing an integrator and a differentiator. Traces of John

Hall’s servo design can be observed in published works with references to the “Jila loop-filter”

[4] and commercial stand-alone units based on the Hall design have now become available.

Migration of instrumentation systems from op-amp based analog systems to digital designs

naturally follows from the advancement of digital technologies.

The development of an FPGA-based servo was reported in published work as early as 2002

[5]; however, the high cost of the FPGA hardware at the time meant that adoption of this

approach was not immediate and widespread use of FPGAs for servos would happen much

later. Today, phase locked loops, lock-in detectors, and arbitrary waveform generators have all

been realized in the digital domain including, recently, FPGA based implementations [6], [7].

The question of how quantization error affects digital servos has not yet been fully addressed

and is one of a main topics of investigation in this work. This question of quantization error

is embedded in similar questions regarding the use of digital designs for feedback control: how

does a digital servo implemented in an FPGA compare with a high-performance analog servo?

Similarly, is there any trade off made with gaining versatility and automated control? The use

of an FPGA servo spans may applications including the locking of an External Cavity Diode

Laser (ECDL) in atom/ion trapping experiments [8], [9] for spectroscopy [10] and for atom

interferometry [11], [12]. The advantage of digital system is its flexibility since, as it is often

argued, it requires no soldering to be reconfigured with a different transfer function.

Naturally, the need to understand and quantify the role of quantization error follows the

introduction of digital systems. In the implementation of lock-in logic in a digital form, it was

clear that the sampling quantization error has an effect on the Signal to Noise Ratio (SNR) of

the lock-in detector [13], and thus should be handled with care.

The question of how quantization error affects digital servos has not yet been fully addressed

and is one of the main topics of investigation in this work. This question of quantization error

is embedded in similar questions regarding the use of digital designs for feedback control: how

does a digital servo implemented in an FPGA compare with a high-performance analog servo?

Similarly, is there any trade off made with gaining versatility and automated control?

2

Chapter 1. Introduction

In the attempt to answer some of these questions, this work started with the development of

an FPGA servo. The hardware developed by this work focuses on the high performance aspects

offered by the FPGA technology. Similar work that focuses on high-performance FPGA servos

are relatively few [14] and should be differentiated from digital servo designs with bandwidths

<100 kHz, suitable for low bandwidth applications that also need servos in large quantities

[6], [15], [16]. This work is also interested in understanding how to push the performance of

an FPGA servo beyond what is capable with an analog servo, and this necessitates testing

in a closed-loop application. In this work, we chose intensity stabilization as our application

for closed-loop studies, and, with it, we achieved a closed-loop bandwidth of 1 MHz. This

application allowed us to benchmark the FPGA servo in a high bandwidth setting and to

explore some of its advantages over a high-performance analog servo including its ability to

fine tune the transfer function to achieve optimal performance. It also allowed us to identify

previously unrecognized limitations and areas of particular concern with FPGA servos

This thesis follows the development of our FPGA servo. Each chapter covers topics in the

various stages of our development efforts in the following order: hardware design, firmware

design, closed-loop performance tests and, finally, the application of the FPGA-based servo

in a cold atom experiment. The theoretical background pertinent to the various topics is

covered in each chapter. The thesis is meant to acquaint a new designer with all aspects in the

development an FPGA servo, and, therefore, it is explicit with describing mistakes made during

the development of the FPGA servo. This work may also be of interest to researchers that are

interested in using recently developed FPGA servo products, such as Digilock by Toptica (200

ns total signal delay) [17], as this work investigates some of the considerations and limitations

one should be aware of when using an FPGA based servo. Moreover, we believe this work

provides some insight into the present state and the development bottle necks of FPGA based

servo technology.

3

Chapter 2

FPGA Servo Hardware

The hardware of the FPGA is the development platform for all servo logic and signal process-

ing related elements used in a closed-loop control application. Thus, the hardware plays an

indispensable role in determining the performance of an FPGA based servo. The underlying

hardware, therefore, affects whether an FPGA servo is suitable to replace existing analog servos

in many applications. This chapter focuses on the design and specification of a complete set of

FPGA servo hardware elements. Later chapters discuss the development and implementation

of the servo logic and signal processing units.

Two design specifications are important for a servo design and thus are recurring throughout

this thesis. They are the closed-loop bandwidth and the noise floor. The closed-loop bandwidth

of the servo is important because it determines the highest frequency that the servo can correct

for. As it is shown in Figure 2.1, a typically control loop consists of a servo/controller that

is responsible for generating correction to a quantity under control, an actuator/plant respon-

sible for carrying out the correction and a detector that monitors the quantity under control

and provides feedback to the servo. It makes little sense to use a actuator/plant that has a

extremely high closed-loop bandwidth of, for example, 10 MHz, if the servo can only respond to

disturbances up to 100 kHz. In this scenario, the closed-loop bandwidth of the overall system

would be dominated by the servo because the closed-loop bandwidth is determined by the sum

of delay in all the component. Hence, the closed-bandwidth of the FPGA servo limits its use

with actuators/plants and its applications.

Servo Actuator

Detector

Setpoint Output

Figure 2.1: A typical control loop consists a servo (also referred to as a controller), an actuator(also referred to as a plant or a process) and a detector (also referred to as the feedback).

4

2.1. Architectural Overview

The other design specification, the noise floor of the servo, is important because it determines

the signal level that the servo can correct at. We are rather familiar with the typical noise

sources in an analog circuit such as the input-derived op-amp noise and Johnson noise. One

initial concern in the addition of digital system to the servo is the quantization errors at the

Analog to Digital Converter (ADC) and the Digital to Analog Converter (DAC). As later

experimentation shows, quantization error at the ADC or the DAC is not neccessarily an issue

for the noise floor of an FPGA servo, expecially when the signals can be over-sampled and

averaged, as the effect is explained at some external sources [18]. It is nevertheless important

to keep in mind that the quantization affects a digital servo in areas besides the noise floor,

and the details are covered in more detail in Chapter 3.

Based on these general considerations, this work was carried out under the intuitive assump-

tion that a faster and quieter servo is in general more useful. To explore the best FPGA servo

that the current technology has to offer, we set out to design the FPGA servo “from scratch”,

while knowing that the final hardware needs to be competitive against existing analog servos

with 10 MHz closed-loop bandwidth and 10 nV/√

Hz noise floor [19].

The design specification on speed and noise floor is addressed by each component of the

servo. The chapter starts with the architectural overview and then describes the particular

design challenges in individual sections in detail.

2.1 Architectural Overview

The FPGA servo is a mixed-signal system, as illustrated in Figure 2.2, that can be divided

into a digital section, an analog front-end section and a signal conversion section. Reduction

of noise and optimization in bandwidth are important in each section although subtly different

design objectives are present in each module.

The digital section, mainly consisting of the FPGA, is responsible for high-speed signal

processing and the implementation of the servo logic. This work relies on commercially available

FPGA platforms to access high-performance FPGAs that would otherwise take too long to

design and test on a Printed-Circuit-Board (PCB). It is nevertheless important to ensure

that the FPGA can accommodate an on-board MCU and intensive signal processing. The

5

2.1. Architectural Overview

+ +

Remote PC

PID

Micro-controller

DAC

DACslow

DACslow

DACslow

DACslow

ADC

a)

b) c)

d)

e) f) g)

Fast data pathSlow data path

Figure 2.2: The design architecture of the FPGA servo. The servo is composed of the followingmodules, in the order of appearance in this chapter a) FPGA development board b) offsetcircuit c) gain circuit d) slow DAC e) ADC driver f) ADC g) DAC

requirement for an on-board MCU, whether it is in the form of a softcore MCU or a hardcore

MCU, is advantageous for feature expansion. Additionally, the requirement for computation

capability is necessary to implement the servo logic and other DSP tool in the FPGA, which is

required to accomplished the primary objective of this work. The hardware description of the

FPGA in Section 2.2 provides more details.

The analog front-end is responsible for conditioning the signals at the input/output of the

servo to match the voltage range of the ADC and DAC. The design of the analog front-end

produced by this work provides extensive flexibility with the use of a variable gain circuit and

a variable offset circuit on each of the input/output of the servo. Digital control of these

conditioning circuits is provided by an array of slow-updating DAC directly accessible by the

FPGA. This design allows the FPGA servo to be remotely controlled in a wide range of control

applications.

Finally, the signal conversion section, mainly consisting of the ADC and the DAC, is re-

sponsible for converting an analog signal to the digital domain and vice versa. In the signal

conversion section, the optimization for closed-loop bandwidth is equivalent to reducing the

conversion latency through the ADC and the DAC. In contrast to our initial impression, the

latencies through many high-speed ADCs and DACs is much higher than what the clock speeds

of these devices suggest.

6

2.2. FPGA Section

Development Timeline

Two FPGA servos, based on the Development and Education board 3 (DE3) FPGA platform

[20] and the Development and Education board 2 (DE2) FPGA platform [21], are first con-

structed as prototypes from modular pieces, as shown in Table 2.1. In the prototypes, the analog

front-end is designed and tested as a PCB that consistings a variable offset circuit followed by

a variable gain circuit. The slow DAC needed to control the variable gain and variable offset

circuit is based on an existing 8-channel Analog Output (AO) design by Todd Meyrath [22].

The signal conversion sections of the prototypes are based on commercially available cards that

have to be modified to accommodate Direct Current (DC) signals. The prototype servos allow

us to verify the closed-loop performance of FPGA servos on two different FPGA platform, the

DE2 and the DE3.

Table 2.1: A summary of various servo used in the study.

FPGA Conversion Offset and Gain Slow DAC

DE3-Prototype DE3 [20]AD/DAby Altera [23]

Custom PCBPCB

DE2-Prototype DE2 [21]THDB-ADA by Todd Meyrath[22]by Altera [24]

DE2-Final DE2 Custom PCB as shown in Appendix A

Once the performance of the servos is confirmed, we compiled the electronics design onto a

custom daughtercard compatible with the DE2, DE3, a few of the other Altera FPGA develop-

ment boards. The servo design based on the custom daughtercard is easily replicated and more

convenient to use than the prototypes. The final servo design is characterized and provide most

of the supporting data in this chapter unless it is otherwise specified.

2.2 FPGA Section

The FPGA section is responsible for high-speed signal processing and the implementation of

the servo logic. This section describes the selection criteria of the FPGA in detail and the

compatibility of our FPGA daughter card design with other existing FPGA platforms.

7

2.2. FPGA Section

2.2.1 Selection Criteria

IO Interface

The Input Output (IO) interfaces of the FPGA development board need to support high-speed

parallel signals for use with the ADC and DAC. Two types of IO are popular among the

Altera development boards, with one being the High Speed Mezzanine Card (HSMC) high-

speed connection and the other one being the 2×20 General-Purpose Input Output (GPIO)

connectors. The HSMC connector is suitable for high speed signals and is available on the DE3

board among other high-speed research development boards. The GPIO connector is available

on a wider range of development board, including the DE3, DE2, Development and Education

board 0 (DE0) and Development and Education board 1 System on Chip (DE1-SOC). Both

interfaces seem to be supported by many of Alteras boards including some data acquisition

daughter cards. For the FPGA servo prototypes realized in this work, the DE3 platform is

paired with the Analog-Digital Digital-Analog (ADDA) card with HSMC interface and the

DE2 platform is paired with the Analog-Digital-Analog (ADA) card with the GPIO interface.

The two types of interfaces are not directly compatible but conversion can be made using a

commercially available converter.

MCU Unit

The second consideration is the support for a MCU in the digital system. It is becoming more

common for FPGA designs to accommodate a MCU rather than co-processor as a separate chip.

Less urgent tasks can be more quickly implemented in the MCU rather than in the FPGA, so

the use of an softcore or a hardcore MCU reduces to development time needed for feature

expansion. The more recent FPGA are equipped with Hard Processor System (HPS), but the

DE2 and DE3 platform that this work uses do not contain HPS but rather contain sufficient

number of Logic Element (LE)s to instantiate a NIOs II softcore MCU provided by Altera.

Besides sufficient number of LEs to instantiate an MCU inside the FPGA, other platform

requirements include sufficient run-time memory in the form of Random Access Memory (RAM)

and non-volatile storage of both the FPGA configuration binary and the MCU executable. The

DE3 is equipped with 1 GB external RAM in the form of Double Data Rate 2 (DDR2) RAM,

8

2.2. FPGA Section

but the memory bits that are built-in to the FPGA of a total of 5,499 kbit and is sufficient to

run the Nios II MCU. The DE2 FPGA doesn’t have enough on-chip memory to run the Nios

II MCU, so the design uses 512 KB of Static Random-Access Memory (SRAM) or 8 MB of

Synchronous Dynamic Random-Access Memory (SDRAM) for run-time memory. In terms of

keeping nonvolatile configuration of the FPGA and the MCU on the development board, the

EEPROM serial configuration Integrated-Circuit (IC) on each of the platforms, EPCS16 (DE2)

and EPCS128 (DE3), are sufficient, as the FPGA image and the MCU image can be combined

into the same image and stored onto the same chip (the commands for doing this can be found

here [25]).

DSP Units

The final consideration is the computation capability of the FPGA. In the case of the DE3, 384

18-bit by 18-bit multiplier is available on the Stratix III EP3SL150 FPGA on the development

platform. However, in the case of the DE2 the number of multiplier is more scarce at 35 18-bit

by 18-bit multipliers. This is why, after computation resources needed for a FPGA servo is

investigated in Section 3.2.6, the study come to the conclusion that the DE2 isn’t the most

suitable for an FPGA servo design and rather recommends an FPGA development platform

with more computation resources (refer to Section 3.2.6 for more details) for future development.

While it is true that regular LEs in an FPGA can be configured as multipliers but are certainly

slower due to the additional length of wires need to configure LEs into multipliers compared to

a hard-wired multiplier.

2.2.2 Compatibility

Because a servo daughtercard is designed to be easily reproducible for future use, it is important

to note its future-proof-ness and compatibility with other FPGA development board. Because

Altera’s line of FPGA development board has moderate compatibility with one another due to

its common expansion header, a daughtercard designed to be compatible with one development

board needs very little modification to be used with another development board. This is

certainly true with the daughtercard originally designed for the DE2 and that means the DE3

and the more recent DE1-SOC is also compatible with the servo daughter card design by this

9

2.3. Analog Frontend Section

work. This compatibility matrix makes it is rather effortless to upgrade to a newer FPGA

platform from a hardware standpoint as long as Altera continues to support the format of the

GPIO header. The servo firmware is also written with future migration in mind to the best of

our ability. Information on compatibility of the servo logic with other FPGA can be found in

Chapter 3.

2.3 Analog Frontend Section

The analog front-end is responsible for conditioning the signals at the input/output of the

servo to match the voltage range of the ADC and the DAC. This section describes the design

rationale, IC selection criteria and the characteristics of the analog front-end circuit in detail.

2.3.1 Design Rationale

An FPGA servo needs to work with a wide range of measurement devices and laser controllers,

but voltage ranges of the ADC and the DAC are rather limited (0-3.3 V in this design). This

motivates the design of the analog frontend. When designing the analog front-end, the variety

of measurement devices and actuators, like the photodetector, frequency discriminator, laser

current driver and piezo driver can all be simply regarded as an input/output voltage range,

with common voltage ranges like 0-10V, ±10V, 0-3.3V and 0-5V.

Tunable gain and offset is useful when working with different voltage range and signal sizes.

A tunable gain circuit can be used match the amplitude of the measurement signal to the ADC

or the DAC voltage range to the laser controller. The tunable offset can be used to remove

any DC component in the signal that contains little information about the signal but takes up

valuable operation range of the ADC or the DAC. The offset circuit at the input of the servo

also controls the setpoint that the servo locks to. Modulation of this input offset signal adds

modulation capability to a closed-loop system.

Remote tunability of the analog front-end is accomplished by the use of slow DAC to control

the offset and the gain at the input and the output of the servo. This tunablity is complimentary

to the ability for the FPGA servo to implement various transfer functions (Chapter 3).

10


2.3.2 IC Selection Considerations

The choice of three ICs is specially important for the performance of the analog frontend. The

ICs are the op-amp for the offset circuit, the amplifier used for the gain circuit and the slow

DAC used for digitally controlling the offset and the gain. This section covers the selection

criteria for each chip and some alternative designs that are rejected in the design process.

Variable Offset Stage

The variable offset circuit is simply an op-amp configured in the adder configuration, as shown in

Figure 2.3. The adder configuration does not restrict the selection of op-amps, but requirement

for speed and noise does. The design uses the AD829 for a bandwidth of 12 0MHz, a slew rate

of 230 V/µs and low input noise of 1.7 nV/√

Hz, as indicated by its datasheet. The more

commonly used LM741 and OP37 were briefly considered although their were finally rejected

due to to their lower slew rate, 0.5 V/µs and 17 V/µs respectively, and rather high input noise

of 20 nV/√

Hz in the case of the LM741.

The AD829 opamp requires external compensation in the picofarad range to operate at full

speed. It is therefore not wise to prototype this circuit on a breadboard/stripboard because

the parasitic capacitance in a breadboard/stripboard can affect the slew rate of the op-amp.

The schematics shown in Figure 2.3 shows the configuration for both voltage compensation

(C307) and current compensation (C306), as the compensation schemes are defined by the

AD829 datasheet. The external compensation scheme is finally decided to be the current

compensation, (C306) after the AD829 is tested on a PCB.

R306

R300

C300

R309

AGND C306C307

AGND

OFFSET_INPUT

SIGNAL_IN

SIGNAL_OUT

2

36

5COMP

AD829JR

Figure 2.3: Schematics of the variable offset circuit. Both the current compensation scheme(C306) and the voltage compensation scheme (C307) are shown.

11


Variable Gain Stage

The variable gain stages are needed to scale the input/output signal of the servo to fit in the

operating range of the the ADC or the DAC. A few implementation schemes for a variable gain

stage are available, so some work went into searching for a suitable Variable Gain Amplifier

(VGA) design.

Potential designs for the variable gain stage include the use of digital potentiometers or

rheostats, which are resistors that can be digitally programmed. The limitation of this technol-

ogy is resolution and bandwidth. The chipsets that represent the state-of-the-art technology

are the Analog AD514x and AD512x series, with bandwidth of 3 MHz and resolution of 8 bit.

It is possible to mitigate the lack of resolution with a network of digital potentiometers, but

bandwidth limitation can not be overcome and that leads to the rejection of this design scheme.

Other rejected designs are VGAs with a discrete selection of gain and ADCs packaged with

VGAs in single ICs. The former can be troublesome to tune as it does not provide a continuous

range of gain. The later is rejected for its obscurity and a lack of high speed options.

Within the selection of VGA with continous range of tunable, we found it important to test

the VGA to make sure that the IC is rated for DC. One unsuccessful example is the use of the

AD8367, a VGA that represents a class of multi-hundred MHz VGAs that are not rated for DC

signals. In the case of the AD8367, the gain is constant over two distinct frequency regions but

has a change of 3 dB in gain between the two frequency regions. This renders the IC useless

for closed-loop servo applications. Accordingly, we proceeded by carefully selecting and testing

high speed VGAs from the selection table provided by manufacturer to avoid similar problems

[26].

After surveying the whole design space, this work came up with the single variable gain op-

amp AD603 that has 40 dB of tunability, a constant passband of DC - 91 MHz and a tunable

gain of 40 dB. The design of the variable gain stage is very simple as shown in Figure 2.4.

Besides the signal input to and output from the amplifier, the VGA takes a control input of

±0.5 V. A voltage divider is installed to accept a voltage input range of ±10 V. The voltage

divider also doubles as a low-pass filter and is used to suppress noise in the slow-DAC at high

frequencies.

12


+5V

-5VAGND

GAIN_INPUT

GAIN_CTRL

18k

R321

1KR324

1uFC325

AGND

GAIN_CTRL

499R311

AGND

SIGNAL_INSIGNAL_OUT

12

3

4

5

6

7

8

COMM

IN

G-G+

FBAD603AR

Figure 2.4: Schematics of the variable gain circuit.

Slow DAC Selection

The use of the slow DAC in controlling the gain and offset of the analog front-end allows the

servo to be tuned digitally. The speed requirement on the slow DAC is rather relaxed compared

to the ADC and the DAC that are directly responsible for the servo action. This allows the

communication interface of the slow DAC to be serial to reduce the total IO usage on the

FPGA.

The design consideration behind the slow DAC is an economic one because a total of 8 DAC

channels is needed for the dual-channelled FPGA servo (one tunable offset and one tunable gain

on each of the input/output of a servo channel).

The implementation of the 8-channel DAC is different in the prototypes and the final design

of the servo daughter card. In the case of the servo prototypes, the slow DAC channels are

controlled by a separate FPGA platform that interfaces with the 8-channel DAC card designed

by Todd Meyrath [22]. The DAC card is based on 2 DAC7744 ICs and exposes a parallel

interface and it is controlled by an USB-to-parallel converter that this work commissioned on

another FPGA platform. A total of two FPGAs are used in constructing each servo prototype

that we used to test out understanding about the FPGA servo. The construction is unnecessarily

bulky and that motivated the design of the servo daughtercard.

In the case of the servo daughter card, the number of unused IOs on the GPIO header is

small. This necessitates serial communication and sharing of signals between the slow DAC

13


ICs. The slow DAC IC used in the daughtercard design is a serialized version of the IC used

in Todd’s design, with ±10 V output range and a noise level of 60 nV/√

Hz. This means

that measurements made on the prototype servos apply to the daughtercard. This work also

considered the use of AD5669, an 8-channel DAC, but the lower SNR of the IC (120 nV/√

Hz

with an output range of 0-5 V) degrades the performance of the servo, so it is subsequently

rejected.

Another feature of the slow DAC section is the synchronous latching of the control param-

eters, enabled the connection between the latching signals on the slow DACs and the FPGA.

We speculate that updating all servo parameters at the same time causes less disturbance in

the servo loop and can be very useful in feature developments in the future.

2.3.3 Noise

Offset Circuit

The work in reducing noise in the analog front-end circuit does not stop at the use of low noise

amplifiers. A noise model for the offset circuit is helpful in identifying and eliminating noise

sources.

The noise model for the offset circuit is based on the adder configuration, as shown in Figure

2.5. Noise sources include the noise in each branch of the adder and the input derived noise

of the op-amp. The thermal noise of the feedback resistors (in the range of 1-10 kΩ which is

responsible for 4-12 nV/√

Hz of thermal noise) is neglected which lead to a less accurate but

still sufficient model. It is to note that the noise floor of the measurement can limit the quality

of the noise measurement. The SR780 Vector Network Analyzer (VNA) used the study has

a minimum noise floor of 10 nV/√

Hz but can have a higher noise floor when the sampling

window is increased to measure a larger input signal.

The dominating sources of noise in the offset circuit is the offset voltage from the slow DAC,

rather than the op-amp input noise. Reduction of noise from the slow DAC improves the noise

floor of the offset circuit substantially. In the case of the offset circuit at the input of the servo,

the slow DAC voltage of ±10 V is reduced to a range of ±0.6 V with a 19:1 voltage divider.

This should in theory reduce noise of the slow DAC from 60 nV/√

Hz to 3 nV/√

Hz. The result

14


+ +

Ninput

Noffset Fixed Gain

+

Nmeasurement

+

Figure 2.5: Noise model of the offset circuit. The input noise at the op-amp Ninput is smallat 1.7 nV/

√Hz. The noise from the offset voltage varies. For the input offset circuit, Noffset

is 3 nV/√

Hz and the noise level of the external offset. For the output offset circuit, Noffset is60 nV/

√Hz. Nmeasurement varies between 10-100 nV/

√Hz depending on signal amplitude.

of this improvement is illustrated in Figure 2.6 where noise level after improvement is below

the noise floor of the measurement.

10 1 10 2 10 3 10 4 10 5

Frequency [Hz]

-140

-135

-130

-125

-120

-115

Noi

se[d

B(V

pk=p

Hz)

]

Noise Spectral Denisty, Offset Circuit

Offset circuit with slow DAC,without the 19:1 voltage dividerOffset circuit,slow DAC by-passed

Figure 2.6: Noise level of the adder circuit highly depends on noise in the offset voltage, as itis shown in the change in noise floor in frequencies <1 kHz. In frequencies >1 kHz the noisefloor is limited by the measurement noise floor.

In the absent of this input offset, the servo locks to 0 V. The final design of the servo allows

the slow DAC to be turned off and it allows the use of an external offset. The user must then

be careful with selecting the offset source, as any noise in the offset voltage can degrade the

noise performance of the offset circuit.

15


In the case of the offset circuit at the output of the servo, the range of ±10 V in offset is

needed to accommodate a wide range of laser applications. The divider is then absent in the

output offset circuit. The decision is justified by the ability of a servo to suppress noise at its

output, as it is demonstrated in Chapter 4.

Gain Circuit

A noise model is also built for the VGA to investigate noise sources in the variable gain circuit.

As shown in Figure 2.7, noise is present at the signal input and the signal output of the amplifier

and at the control input for the gain. The input noise of the amplifier is small at 1.3 nV/√

Hz.

The noise in the control signal is originally 60 nV/√

Hz from the slow DAC but is reduced after

a voltage divider of 19:1. The control input is responsible for an error in gain of 120 ndB/√

Hz.

In the worse case scenario when the input signal or the output signal saturate at either rail

of the AD603 (maximum output range of ±3 V), the error in gain converts to a theoretical

maximum noise level of 41 nV/√

Hz.

Ninput

Ngain Nmeasurement

Noutput

+ + ++

Figure 2.7: Noise model of the variable gain circuit. The input noise of the VGA is small at1.3 nV/

√Hz. The noise at the control input(Ngain) is 3 nV/

√Hz in voltage, which correspond

to an error of 120 ndB/√

Hz in gain.

The noise source at the output of the AD603 is a significant source of noise as it is demon-

strated by the set data shown in Figure 2.8. In the measurement, the input to the AD603 is

terminated to ground and the gain is set to three settings that are 10 dB apart. The noise floor

in frequencies >200 Hz is not dependent on the gain, and this suggests that the noise source

is at the output of the amplifier. The possibility of the limiting factor being the measurement

noise is carefully eliminated, which lead to the conclusion of the presence of about 80 nV/√

Hz

noise at the output of the AD603 amplifier. We decided that this noise does not necessarily

degrade the performance of the servo, because the noise is similar in amplitude as the noise

16


level in the ADC region. We simply move on to different part the the servo design with the

knowledge of this issue.

10 1 10 2 10 3 10 4 10 5

Frequency [Hz]

-145

-140

-135

-130

-125

-120

-115

-110N

oise

[dB

(Vpk=p

Hz)

]

Noise Spectral Denisty, Gain Circuit

AD603, Gain = 31AD603, Gain = 10AD603, Gain = 3.3

Figure 2.8: Noise at the output of the AD603 at various gain setting, with the input of theAD603 terminated to ground. The VNA input range is set to -44 dBV. In frequencies < 200Hz, the effect of the input noise of the AD603 can be observed to vary with gain. In frequencies>200 Hz, the output noise of the AD603 can be observed as it is independent of the gain at alevel of about -142 dBV/

√Hz (this is equivalent to 79.4 nV/

√Hz).

2.3.4 Bandwidth

Offset Circuit

The AD829 opamp needs to be configured with external capacitance in the pidofarad range to

operate at full speed. The optimal compensation scheme for a fixed gain of 1 or 4 is investigated

in the first PCB design of the analog frontend design, which allows both external compensation

schemes (current and voltage) to be tested. After the compensation scheme is decided, the

speed of the offset circuit in the final design of the servo is characterized over a range of

external capacitances. The purpose of the test is to optimize the speed of the offset circuit in

the final servo design and to ensure that similar speed can be reproduced over the tolerance

17


variance of the capacitors. The result of this test is shown in Figure 2.9.

-50 0 50 100 150 200

Time (ns)

-0.5

0

0.5

1

1.5

2

2.5

3

3.5

4

Vol

tage

(V

)

AD829 Current Compensation Mode, Large Signal Response

Input SignalC

comp = 2 pF

Ccomp

= 3 pF

Ccomp

= 4 pF

Ccomp

= 9 pF

Ccomp

= 12 pF

Ccomp

= 18 pF

Ccomp

= 25 pF

Figure 2.9: AD829 bandwidth as affected by external compensation capacitance in the currentcompensation mode. The optimal capacitance is 2-4 pF for the negative feedback configurationof AD829 with a gain of 4, feedback resistance of 4 kΩ and feedback capacitance of 1 pF, whichagrees with manufacturer’s recommendation. It is important to note that the capacitance inthe feedback network affects the optimal compensation capacitance.

The input to the circuit is generated from a digital output of an FPGA, which approximates

a step function with the exception of some ripples due to impedance mismatching at the termi-

nals. The response at the output of the opamp is measured with an oscilloscope and the delay

through coaxial cables to and from the circuit is calibrated away. A set of step response with

variation in compensation capacitance (current compensation) is shown in Figure 2.9. The use

of large signal response helps to reveal the slew rate of the op-amp. It is worth noting that

all step response shown is the current compensation mode as we are not able to reproduce

similar speed in the voltage compensation configure as described by the AD829 datasheet in

any iteration of the analog front-end design.

When a gain of 4 and a feedback capacitance of 1 pF is used, the optimal compensation

capacitance is 2-4 pF. The result agrees with manufacturer’s recommendation. In the data, the

18

2.4. Conversion Section

variation of 2-4 pF in capacitance results in a very small variation in slew rate. This suggests

that the bandwidth performance in a larger production of the servo daughtercard will not vary

much from the results obtained by this work.

Gain Circuit

For designers who are familiar with the constant Gain-Bandwidth Product (GBP) of an op-

amp, the ability for the AD603 to maintain a constant bandwidth of 90 MHz over a 40 dB

range of gain can be surprising. This unique property of the AD603 is accomplished using

high bandwidth digital potentiometer followed by an Low Noise Amplifier (LNA). The digital

potentiometer is responsible for varying the gain by a range of 40dB when the gain through the

LNA remains fixed. The gain in the LNA is determined by an externally configured feedback

loop where in this design is set to the lowest gain setting to produce the highest bandwidth

(DC-90 MHz).

The measurement of bandwidth shown in Figure 2.10 is accomplished with step input and

an oscilloscope as described in the step response measurement of the offset circuit. The response

of the AD603 over different gains confirms that a high bandwidth is maintain over the entire

range of gain settings. The small amount of variation in response time with a spread of roughly

1 ns is likely due to the presence of ripples in the trigger signal and the shot-to-shot variation

in the shape of the ripples.

2.4 Conversion Section

The conversion section is the bridge between the analog front-end and the FPGA in the design

of an FPGA servo. It is also a main source of delay in the FPGA servo. This section describes

the selection criteria for the various ICs that fulfill the function of the conversion and their

overall characteristics, both in terms of noise and latency.

2.4.1 ADC and DAC Selections

The key selection criteria for the ADC and the DAC are signal latency and resolution. These

two criteria are almost the opposite of each other since a high resolution ADC or DAC typically

19


-10 0 10 20 30 40 50 60 70 80 90

Time (ns)

-0.05

0

0.05

0.1

0.15

Vol

tage

(V

)

Small Signal Response of AD603 at Various Gain

Input SignalGain = 0.33Gain = 1Gain = 3.3Gain = 10Gain = 31

Figure 2.10: AD603 has a constant bandwidth over the whole range of gain, tested between -10dB and 30 dB at 10 dB intervals.

has a high latency and and a low latency ADC or DAC typically has a smaller bit depth. This

trend can be observed from the technology landscape of ADCs made by Analog Devices, as

shown in Figure 2.11. The available ADCs requires choosing a resolution of 16-bit or lower to

keep the sampling rate above 10 MHz, a must for a digital servo to compete with traditional

analog servo technology with close-loop bandwidth of >10 MHz (laser servo D125 by Vescent).

It is worth noting that the absolute delay through the ADC is not necessarily proportional

to the inverse of the sampling rate since multiple clock cycles are often needed to completely

convert an analog signal into the digital domain. For example, the AD9254 ADC used in DE3

prototype has a maximum clock speed of 150 MHz, but its 12 clock cycles of clock delay makes

it less favourable than the ADC LTC2195 used in the National Institute of Standards and

Technology (NIST) servo design [14] with a lower clock speed of 125 MHz but also a lower

pipeline delay of 7 cycles. Unfortunately, the number of clock cycles required by each ADC or

DAC to complete the conversion is often not part of the search criteria in search engines for

ADCs and DACs. This makes it rather cumbersome to find suitable ADC and DAC to be used

20


in an FPGA servo.

Figure 2.11: The technology landscape of ADCs, provided by Analog Devices

Since the latency through the conversion section is an important characteristic of a digital

servo, a survey is conducted on suitable ADCs and DACs for use in a servo design. Part of

the survey is shown in Table 2.2, where ADCs and DACs used in three FPGA servo platforms

are listed, including a recently published work on high-bandwidth FPGA servo by NIST [14].

The minimum conversion latencies in each of the FPGA servos, in the order of the DE3 servo

prototype, the DE2 servo prototype and the recently published servo design is respectively 95

ns, 108 ns and 70 ns.

The use of commercially available ADC and DAC daughtercards compatible with the DE2

and the DE3 in designing the FPGA servos greatly reduces the development time. This also

means that the selection of ADC and DAC is limited to two daughtercards and their respective

ADC and DAC options. It is worth noting that out of all the ADCs and DACs listed in Table

2.2, the ADC/DAC combination that would produce the minimum conversion delay is the

ADC LTC2193 (NIST paper) and the DAC AD9766 (DE2 platform) with a total delay of 56

ns. Reduction of delay in the conversion section can be worthwhile as it lead to an increase of

servo closed-loop bandwidth.

The Oversampling Effect

A higher clock speed has other advantages, although it may not indicate the the total conversion

delay through an IC. With the appropriate DSP tools, precise control of the timing of a signal

21


Table 2.2: Viable ADC and DAC options, their pipeline delay, resolution, etc

IC Resolution Type MaxClock(MHz)

Latency(clk)

TotalPipelineDelay(ns)

Note

ADC AD9254 14 SAR 150 12 80 DE3 Servo Proto-type

AD9248 14 Pipeline 65 7 108 DE2 PrototypeFinal Design

LTC2195 16 125 7 56 NIST paper [14]

DAC DAC5672 14 - 275 4 15 DE3 Servo Proto-type

AD9767 14 - 125 0 0 DE2 PrototypeFinal Design

AD9783 16 - 500 7 14 NIST paper [14]

can be traded off for signal resolution and vice versa with the use of oversampling. In analog-to-

digital conversion, oversampling and averaging can lead to higher accuracy in the data as long

as sufficient amount of white noise is present in the input signal. Similarly, in digital-to-analog

conversion, Pulse-Width Modulation (PWM) is the use of a 1-bit DAC (a digital output) with

high-accuracy timing control to produce a high resolution analog output. Additional reading

may be very helpful on this subject and this reference provides the reasoning on why for every

4 times in over-sampling the resolution of the sampled signal can be improved by a factor of 2

[18].

2.4.2 Single-Ended to Differential Conversion

ADCs and DACs with high resolution often have differential analog inputs and outputs for

better noise immunity. Conversion between single-ended signals and differential signals needs

to be carefully handled to prevent signal contamination.

The differential DAC outputs are relatively straightforward to convert to a single-ended

signal. The key is to make sure that the DAC differential outputs have matched load (25 Ω

resistors) to ground. The “+” signal of the differential pair can be used as an single-ended signal

and the “−” signal can be disregarded. This is the recommended practice by the manufacturer

for DC-coupling the differential DAC outputs [27].

On the other hand, an amplifier with differential output is required to interface with the

22


differential inputs of an ADC. The ADC driver AD8137 is used and configured according to the

schematics shown in Figure 2.12. The ADC driver is also used as the anti-aliasing filter before

the ADC to suppress noise components that is higher in frequency than the Nyquist frequency

(1/2 of the sampling frequency) of the ADC. The corner frequency of the anti-aliasing filter is

determined by passive components, C301 and R301, in the feedback path of the ADC driver.

They form a low pass filter around 25 MHz. It is to note that the exact Resistor-Capacitor (RC)

time constant is often changed to match the Nyquist frequency of the system in the prototyping

stage of the servo. Another low-pass filter formed by R305 and C302 at the output of the ADC

driver is also used to suppress noise at high frequency, but the cut-off frequency of this low-pass

filter is chosen to be a few times larger than that of the anti-aliasing filter to prevent additional

decrease in loop bandwidth.

270

R305

270

R313

56pC302

56pC304AGND

1K1

R303

1K1

R314

1K1

R316

1K1

R301

9p1

C301

9p1

C308

SIGNAL_OUT+

SIGNAL_OUT-

VOCM

SIGNAL_IN

-IN

VOCM+OUT

-OUT+IN

AD8137

AGND

Figure 2.12: Schematics of the ADC driver.

2.4.3 Latency

The latency through the conversion section needs to be carefully optimized for a high loop

bandwidth even when ICs with low latency are used. This section describes the techniques

used in identifying the causes of delay and how to eliminate them.

Delay can be categorized into propagation delay and pipeline delay. It is helpful to distin-

guish between the two, because eliminating each type of delay takes a different strategy.

Pipeline delay can be used as an umbrella term for delays that scale with the clock frequency.

The ADC, the DAC and the FPGA all have a moderate amount of pipeline delay. It is often

helpful to measure the number of clock cycles in the pipeline delay in a system by making

23


latency measurement at a few different clock frequencies. To ensure that the ADC and the

DAC can operate at their rated maximum frequencies, any infrastructure carrying high-speed

signals to and from the ICs also need to be properly rated. This ultimately motivated the use

of commercially available FPGA platforms and ADC/DAC daughtercards in the prototyping

stage of the servo. In the design of the custom servo daughtercard commissioned by the end of

this thesis, signals in each 14-bit wide digital bus are carefully length-matched to the respective

clock and latch signals, with the Altium trace length matching tool.

The master clock frequency of the servo also affects the total pipeline delay. One design

constraint is the maximum clock speed of the ADC and the DAC, which are often not the same,

as shown in Table 2.2. Clocking the ADC, the FPGA and the DAC at multiples of a master

clock frequency can produce a better result than clocking them all at the maximum frequency

of the slowest IC. For example, the DE3 servo prototype produces a lower delay of 97 ns when

the ADC and the DAC are each clocked at 150 MHz and 225 MHz than if both ICs are clocked

at 150 MHz. A second constraint is the capacity of the Phase-Locked Loop (PLL) in the FPGA

because a PLL has a defined set of clock multipliers and dividers. In the case of the DE2, 65

MHz cannot be derived from a 50 MHz source. This prevents the DE2 servo from achieving

the theoretical minimum conversion delay of 108 ns.

The other type of delay, the propagation delay, can be used as an umbrella term for delays

that do not scale with the clock speed. Both analog signals and, somewhat surprisingly, digital

signals can produce propagation delay. The typical method to reduce propagation delay is to

reduce any unnecessary internal or external signal paths. This applies to coaxial cables, PCB

traces and etc although the propagation speed in each median is different from one another.

The delays of a few ns can quickly add up to 10-20 ns even after extensive optimization.

2.4.4 Bandwidth

The bandwidth of ADC driver dominates the bandwidth of this section as its corner frequency

is deliberately set to be low to act as the anti-aliasing filter. The optimal corner frequency

of this filter changes as the clock frequency of ADC changes, so modification to this corner

frequency is typically made after the clock frequency of the ADC is fixed.

24


2.4.5 Noise

Compared to the noise level of < 10 nV/√

Hz in the analog front-end section, the conversion

section is noisier at the 100 nV/√

Hz level and it is susceptible to noise spikes introduced by

poor grounding practices. In this work, the noise level in the conversion section is measured at

the DAC output with a low frequency spectrum analyser SR780, and the conversion section is

configured in three different ways to reveal information about the circuit.

The first configuration, as shown in the inset of Figure 2.13, establishes the noise level at

the output of the DAC at 32 nV/√

Hz by holding the DAC output at a constant value. The

second configuration measures the noise floor of the ADC with terminated inputs, by configuring

the FPGA in the “follower” mode (where the DAC relays the ADC data). This measurement

reveals that the ADC noise floor is higher than the DAC and that some frequency spikes appear

between 60 Hz and 10 kHz, as shown in Figure 2.13. The frequency spikes worsens in the final

configuration, where the ADC is driven by the ADC driver with a terminated input. The

frequency spikes can be seen in many of the noise spectrum data throughout this work. We

investigated in this issue extensively.

Since the amplitude of these frequency spikes observed in the signal conversion section can

potentially make the use of these FPGA undesirable, we thoroughly investigated in the matter

and developed a few techniques to eliminate the spikes. First, it is often helpful to improve

the ground connection of the circuit. That means to eliminate ground loops and to reduce

the impedance to ground by, for example, connecting the optical table to the power supply

chassis. Secondly, we find that the ground setting on the spectrum analyser used to make the

measurement greatly affects the appearance of these spikes. Setting the ground configuration

on the spectrum analyser to “floating” typically helps. Finally, the output of loop measurement

of a closed-loop controlled quality almost never show these spikes. This observation strengthens

our speculation that the spikes are associated with the grounding configuration, as the out-of-

loop measurement provides electrical isolation between the servo circuit and the measurement

circuit. Although we often use these techniques to eliminate the frequency spikes, this thesis

did not go into great length to retake all existing data. So some inconsistency in the appearance

of these spike is present in this chapter and Chapter 4.

25


101 102 103 104 105

Frequency [Hz]

-150

-140

-130

-120

-110

-100

-90

-80

Noise Spectral Denisty, Conversion Section, DE2 Prototype

Limited by measure-ment noise floor

DAC, midrangeADC, DACADC Driver, ADC, DAC

DACFPGA

DACADC FPGA

DACADC FPGA

Figure 2.13: Investigation in the noise of signal conversion (ADC/DAC) section of the DE2servo prototype.

26

2.5. Servo Transfer Function

This work takes the indirect approach to identify the noise sources in the ADC and the

ADC driver. The direct approach would be to make Fast Fourier Transform (FFT) analysis of

the ADC data directly. This can be accomplished either by the FPGA or off-line in a computer.

The development of an FFT module in the FPGA can add a useful tool in the FPGA servo.

2.5 Servo Transfer Function

The overall servo transfer function is characterized with a network analyser. As illustrated the

transfer function in Figure 2.14, the FPGA servo has constant gain at low frequency and a

high-frequency drop off at 10-20 MHz. The phase response is also constant at low frequencies

and phase response of a constant latency of about 200 ns becomes visible at >100 kHz.

Figure 2.14: Servo transfer function.

The closed-loop bandwidth of the servo is at the 180 degree phase shift of the servo. In

the comparison between the FPGA servos and the analog servo in Figure 2.14, the bandwidth

of the FPGA servos are significantly lower at 2-3 MHz compared to the 10 MHz of the analog

servos. The difference in closed-loop performance is visible when the total latency of the plant

and the detector is very small. Despite a slightly reduced bandwidth, the FPGA servo is still

useful in closed-loop applications that involve Acoustic Optical Modulator (AOM), fast piezos

and current modulation of lasers, where the closed-loop bandwidth of the plant is typically

<500 kHz.

27

Chapter 3

FPGA Servo Firmware

The FPGA servo design is motivated by the opportunity to replace an analog servo controller

based on op-amps with a digital servo that can be controlled and monitored remotely. In order

to replace analog servos already in use in AMO experiments, the digital FPGA servo needs to

achieve a similar transfer function and performance as the analog servo. The bandwidth and

noise floor is addressed by the previous chapter on servo hardware. This chapter focuses on the

FPGA firmware with the goal of maintaining a good stability and noise level.

The servo logic is implemented in the form of a Infinite Impulse Response (IIR) filter similar

to what was described in various published work [12], [14]. The work of this thesis is aimed at

a demonstration of viability and the exploration of the practical constraints of implementing

servo logic in the form of an IIR filter. The issues addressed in this work include the precision

with which the poles and zeros can be placed, the computation resources needed in an FPGA

to implement IIR filters of various precision, and the effects of computation delay. This work

also discusses the details of the verification of an IIR filter.

This work also looks into various ways of implementing an Arbitrary Waveform Generator

(AWG) as an added feature to the FPGA servo. The FPGA servo hardware can be used as

a high-speed waveform generator without needing any circuit modification, with similar data

rate (50 MHz - 135 MHz) as the DS345 function generator (30 MHz).

The implementation of other useful servo tools such as a lock-in detector input stage, an

auto-locking algorithm and a transfer function identification system are discussed at the end of

this chapter as potential future expansion features to the servo. Besides the proposed feature

expansion, the FPGA servo hardware is a high performance platform and many more features

can be added without hardware changes.

28

3.1. Overview

3.1 Overview

In realizing the FPGA servo as a toolbox for control applications in AMO experiments, the

work produces a number of System on Chip (SOC) solutions applicable to common experimental

applications. This section covers the design of the SOCs and the organization of the FPGA

firmware. Here with the word “firmware” we refer to all designs that reside in the FPGA

including both the configurable circuitry and the assembled C program inside the Central

Processing Unit (CPU) built into the FPGA. This is different from the vocabulary used in

white pages by FPGA manufacturers such as Altera, where FPGA circuitry is referred to as

hardware and the assembled C program is referred to as software. In this work, however, the

term hardware is reserved for the hardware design described in Chapter 2; the term software is

reserved for programs on the Personal Computer (PC) which is discussed in Appendix D.

This thesis investigates the use of two FPGA platforms, the DE3 and the DE2, in designing

laser servos. The DE3 is a high-performance FPGA and the DE2 is an economic option,

both offered by Altera. For both FPGA platforms, this work included SOC designs with the

structure illustrated in Figure 3.1. Each SOC was composed of a CPU in the form of a Nios II

processor and several specialized signal processing units like the IIR filter, the Finite Impulse

Response (FIR) filter and the AWG. The work conducted in this thesis adheres to the principle

of modularity so it aims to produce individually testable modules. The advantage of this design

is that it produces not only well tested code but also designs that can be rather effortlessly

transferred into other applications. The following sections discuss the design of servo logic in

the form of the IIR filter (Section 3.2), implementation of the FIR filter (Section 3.2.9) and the

AWG (Section 3.3) in detail. These modules share a common control interface that includes a

clock, an asynchronous reset, a parallel bidirectional data port, an address port for accessing

internal registers and simple read/write signals. This control interface is compatible with not

only the master bus of the Nios II processor controls (the Avalon bus) but also the AXI bus

of the hardcore ARM processor embedded into the DE1-SOC FPGA among other CPU bus

standards.

The softcore CPU, implemented as a NIOS II MCU provided by Altera, is tasked with

handling communication to the host computer, interpretation of commands and passing down

29

3.1. Overview

SPI(Slow DAC) AWG

(Waveform)

IIR(Servo)

Serial

Nios II(master)

FIR

Avalo

n B

us

DACslow

DACslow

... DAC

ADCPC

IIR(Servo)

Figure 3.1: The general structure of the SOC design in an FPGA servo. The exact compositionof an SOC design and the interface between the FPGA and the ADC and the DAC (representedin dotted lines) vary on a per platform basis.

commands to the specialized signal processing units that interact more closely with the elec-

tronic hardware. These messaging tasks are insensitive to delay and can be generated from the

Altera toolbox or implemented in C directly. These design tools allow effortless implementation

of human readable commands like “set 1 1024” through the serial port and allow the production

of designs that can be easy replicated on another platform like the DE1-SOC. When the CPU

and the specialized signal processing units are assembled together to form an SOC, the internal

addresses of all the signal processing units are also combined to form a coherent memory space.

The memory layout as seen by the CPU is detailed in Appendix C on a per module basis.

We note here that the Quartus 13.1 design suite was used to design the firmware in the

DE3 whereas Quartus 13.0 was used for the DE2 firmware design. In the case of the DE2, the

associated FPGA Cyclone II was depreciated in later versions. This also prompted our interest

in porting DE2-related development into a more recent platform, the DE1-SOC. This thesis

tries to make explicit the FPGA used for each study, and it also comments on the compatibility

of the design with other FPGA platforms, especially the DE1-SOC whenever applicable.

30

3.2. IIR Module

3.2 IIR Module

The servo logic of the FPGA servo is implemented an IIR filter or set of filters. This is because an

IIR filter can describe transfer functions of various levels of complexity and has a mathematical

representation that is straightforward to implement in an FPGA. This section covers the use

of IIR filters in FPGA servos in detail. It starts with the representation of controller logic in

the IIR format and subsequently covers the computation precision, delay and footprint of an

IIR filter.

3.2.1 Controller Representation

PID control is a common form of controller. The PID controller and the variations of a PID

controller, such as the Proportional and Derivative (PD) controller and the Proportional and

Integral (PI) controller, cover a large range of applications. Extension of PID into a more

complex controller such as a Proportional Integral and Integral (PII) controller, a Proportional

and Integral Cubed (PI3) controller or a PI controller with lag-lead compensation is possible

and often offers improvement in control performance. The derivation of PID into its IIR form

is covered in detail here, although the FPGA implementation of the servo, an IIR filter, isn’t

limited to the PID alone.

The Proportional (P), Integral (I) and Derivative (D) parameters used in various PID tuning

procedures usually refer to one of the three most common PID forms. They are the standard

form, the series form or the parallel form [28, p.159-162], with the following expressions.

Cstandard(s) = Kp

(1 +

1

Tis+

Tds

τDs+ 1

)(3.1)

Cseries(s) = Ks

(1 +

Iss

)(1 +

Dss

γsDss+ 1

)(3.2)

Cparallel(s) = Kp +Ips

+Dps

γpDps+ 1(3.3)

Here, the letters I and D refers to the integral gain and the derivative gain in the respective

PID form with the subscript “p” for parallel and “s” for series. The letter K represents either

31

3.2. IIR Module

the overall gain (in the case of the standard PID form and the series PID form) or only the

gain for the proportional component (parallel PID). As an alternative expression, integral and

derivative components are expressed by their corresponding time scales as the integral (reset)

time (Ti) and the derivative time (Td) in the standard form. The PID forms are all second

order systems each representing two poles, with one of them at s = 0 and two zeros. The

non-zero pole is omitted in some references for brevity [29], equivalent to setting τD, γs, and γp

in equation 3.1, 3.2 and 3.3 to zero (these parameters are technically needed to limit the gain

of the transfer functions as frequencies approach infinity). From a practical standpoint, the

variety of PID forms are motivated by their similarity with various underlying implementation

structures. The series form is often associated with an analog PID circuit based on op-amps,

where each component implements part of the transfer function and are cascaded in stages to

form the PID. The parallel form is often seen in MCU implementation of PID where integral,

derivative of error and the error itself are weighted separately and summed at the end of each

“for” loop.

The PID form most suitable for the IIR implementation in the FPGA servo can be described

by the following relationship.

CFPGA(s) = K(s− ωz0)(s− ωz1)

(s− ωp0)(s− ωp1)(3.4)

Here, the poles and zeros are explicitly stated as ωp0,1 and ωz0,1 . The poles and zeros are labelled

such that |ωp0 | ≤ |ωp1 | and |ωz0 | ≤ |ωz1 |. This implies that the low frequency pole, ωp0 is at

s = 0 and it refers to the integral term. The expressions for ωz0 and ωz1 can be obtained in the

limit when τD, γs, and γp are close to 0, and is given by the following relationships.

ωz0,1(standard) =−Ti ±

√T 2i − 4TiTd

2TiTd(3.5)

ωz0,1(series) = −Is,−1

Ds(3.6)

ωz0,1(parallel) =−Kp ±

√K2p −DpIp

2Dp(3.7)

32

3.2. IIR Module

The assumption of τD, γs, and γp being close to 0 does not affect the shape of the transfer

function in the region s |ωp1 |. This is because the assumption is equivalent to omitting the

high frequency pole ωp1 , and in a PID controller, the corner frequency of the poles and zeros are

typically arrange to be 0 = |ωp0 | |ωz0,1 | |ωp1 |. In this approximation, the high-frequency

pole ωp1 in equation 3.1, 3.2 and 3.3, responsible for limiting controller gain at high frequency,

are removed. The value of this high-frequency pole can be directly obtained from equation 3.1,

3.2 and 3.3 as the following,

ωp1 = − 1

τD

standard

= − 1

γsDs

series

= − 1

γpDp

parallel

(3.8)

resulting in a transfer function gain of the following.

K =KpTdτD

standard

=Ks(γs + 1)

γs

series

=Kp

γp

parallel

(3.9)

When τD, γs, and γp are zero, the gain take on the value of the following.

K = Kp

standard

= Ks ·Ds

series

= Dp

parallel

(3.10)

In the above expressions, the zeros and poles are explicitly written to have a negative real part,

indicating that all the poles and zeros of the PID controller are on the left-hand-side of the

s-plane. The collection of poles and zeros in the s-domain can be mapped into the z-domain,

with the following relationship.

z = esT (3.11)

Here, T is the sampling time, inversely related to fs, the sampling frequency. The sampling

frequency is also sometimes referred to as the clock frequency fclk. This relationship is derived

from the definition of Laplace transformation and Z-transformation. Reference can be found in

various texts [30], [31]

Because the PID controller has 2 poles and 2 zero in the s-domain, its corresponding z-

domain representation should also have 2 poles and 2 zeros, in the format of the following

33

3.2. IIR Module

relationship,

CFPGA(z) = K(z − z0)(z − z1)

(z − p0)(z − p1)(3.12)

This relationship can be expanded like the following,

CFPGA(z) = K1− (z0 + z1)z−1 + (z0z1)z−2

1− (p0 + p1)z−1 + (p0p1)z−2(3.13)

Here, the z-domain poles and zeros are related to the s-domain poles are zeros with the following

relationships.

z0,1 = eωz0,1/fs , p0,1 = eωp0,1/fs (3.14)

Here, the s-domain poles and zeros, ωz0,1 and ωp0,1 , have been defined previously in Equations

3.5 - 3.8.

To convert the z-domain representation of the PID controller in the form of an IIR filter, a

final transformation is needed to cover the z-domain relationship into a discrete-time domain

relationship. The transformation converts z−1 in z-domain to a single clock delay in the discrete

time domain. This transform the previous z-domain relationship into the following.

Kx[n]−K(z0 + z1)x[n− 1] +K(z0z1)x[n− 2] = y[n]− (p0 + p1)y[n− 1] + (p0p1)y[n− 2] (3.15)

Here, x[n] and y[n] are the time domain input and output for CFPGA(z). By introducing the

IIR coefficients, we arrive at the typical form of an IIR filter.

b0x[n] + b1x[n− 1] + b2x[n− 2] = y[n] + a1y[n− 1] + a2y[n− 2] (3.16)

Here, the IIR coefficients, b0, b1, b2, a1 and a2, are defined according to the convention of the

Direct Form I (DFI) and the Direct Form II (DFII) as shown in shown in Figure 3.2.

34

3.2. IIR Module

z-1Σ

z-1

z-1

z-1

b0

b1

b2

-a1

-a2

Σ

z-1

z-1

-a1

-a2

Σb0

b1

b2

DFI DFII

Figure 3.2: The DFI (left) and DFII (right) representation of a second order IIR.

The IIR coefficients has the following relationship to z-domain transfer function.

b0 = K

b1 = −K(z0 + z1)

b2 = Kz0z1

a1 = −(p0 + p1)

a2 = p0p1

(3.17)

The graphical representation of an IIR in DFI shown in Figure 3.2 corresponds to the FPGA

implementation almost exactly. Details of the IIR implementation are discussed in section 3.2.3.

Bilinear Transformation

In general, an arbitrary transfer function in the s-domain can be converted into the z-domain

by first extracting the gain, poles and zeros as illustrated in Equation 3.4 and then applying

the transformation relationship between the s-domain and the z-domain described by Equation

3.11. Other variations of this transformation exist and the most widely used variation is the

bilinear transformation. The bilinear transformation is the first order approximation of the s-

to-z transformation described by Equation 3.11. The bilinear transformation has the following

expression.

s =1

Tln(z) ≈ 2

T

z − 1

z + 1(3.18)

35

3.2. IIR Module

This expression can be used to perform a “substitution of variable” to convert an s-domain

transfer function into its z-domain equivalent. The approximation has good accuracy when all

poles and zeros in the s-domain are much smaller than the sampling frequency. [32, p.221226].

The bilinear transformation has the advantage of being much less computationally intensive

than the exact transformation and is available in both MATLAB’s control system tool box and

Scipy’s Signal Processing library. Both tools can be helpful for generating and verifying IIR

coefficients.

In addition to the exact pole-zero mapping and the bilinear transformation method, other

ways of generating IIR coefficients are investigated for the use in a servo system. Section 3.2.9

elaborates on the varying degrees of success of this endeavour.

3.2.2 First-Order IIR Filters

Many commonly used filters can be realized with a first-order IIR filter. This section describes

the formulation of 4 filters: the pure integrator,the PI filter, the Low Pass (LP) filter and the

High Pass (HP) filter. The IIR representation of these filters can can be obtained from their

s-domain transfer functions followed by an s-to-z transformation; however, this section provides

an alternative interpretation for each filter in an attempt to promote an intuitive understanding

of the IIR filters.

The pure integrator is a filter that integrates continuously. The following is an IIR filter

that implements a pure integrator.

y[n] = b0x[n]− a1y[n− 1] (b0 = 1, a1 = −1) (3.19)

Here, the definition of the IIR coefficients is according to Equation 3.16, with the coefficients

b1, b2 and a2 set to 0. Equation 3.19 can be treated as a recursive relationship between the

input and the output of the IIR filter for a more intuitive perspective. By converting the

recursive relationship into a direct relationship between the input and the output of the IIR

36

3.2. IIR Module

filter, Equation 3.19 can be expanded like the following.

y[n] = x[n] + y[n− 1]

= x[n] + x[n− 1] + y[n− 2]

= x[n] + x[n− 1] + x[n− 2] + y[n− 3]

· · ·

=

n∑i=0

x[i] (3.20)

This leads to the expression of an accumulator, where the output of the filter is the sum of all

past inputs.

A PI filter is a variant of the PID controller without the D component. The PI filter is a

single order system because it contains a pole at DC and a zero at a finite frequency. The PI

filter can be implemented in a first-order IIR filter in the following way.

y[n] = x[n] + b1x[n− 1] + y[n− 1], − 1 < b1 < 0 (3.21)

The PI filter resembles the pure integrator, with the exception of a non-zero b1. A negative b1

coefficient places a zero at a finite frequency and it effectively reduces the effect of the integrator

at high frequencies.

Another example, the LP filter, is a filter that attenuates high frequency components in a

signal. The following is a LP filter in its IIR form.

y[n] = b0x[n]− a1y[n− 1] (b0 = 1, − 1 < a1 < 0) (3.22)

Here, we can see a similarity between this expression and an averaging technique in signal

processing called the “weighted sum”. By converting the recursive relationship into a direct

relationship between the input and the output of the filter, Equation 3.22 can be expanded like

37

3.2. IIR Module

the following,

y[n] = x[n] + αy[n− 1] (α = −a1 ∈ (0, 1) )

= x[n] + α(x[n− 1] + αy[n− 2]

)= x[n] + αx[n− 1] + α2

(x[n− 2] + αy[n− 3]

)· · ·

=

n∑i=0

αix[n− i] (3.23)

Here, the components in the sum are exponentially weighted based the amount of time elapsed

since that sample was taken.

The final example, the HP pass filter, can also be considered a DC block with finite gain

at high frequencies. A HP filter has a zero at DC and a pole at a finite frequency. It has the

following IIR relationship.

y[n] = b0x[n]− b1x[n− 1]− a1y[n− 1] (b0 = 1, b1 = −1, − 1 < a1 < 0)

= x[n]− x[n− 1]− a1y[n− 1] (− 1 < a1 < 0) (3.24)

The DC blocking behaviour of the IIR form of an HP filter can be observed from the coefficients

b0 = 1, b1 = −1, where the sum of a static input weighted with the coefficients b0 and b1 is 0.

The additional requirement of −1 < a1 < 0 is equivalent to adding a LP filter, which limits the

gain at high frequency.

3.2.3 Implementation Details

Fractional Resolution Representation

In this work, the IIR filter is implemented in the form of Fixed Point (FP) arithmetic due to

the forbidding high cost of floating point arithmetic in FPGAs used in this project. All the IIR

coefficients are implemented as FP numbers with the fractional resolution of R bits. The FP

38

3.2. IIR Module

number satisfy the following relationships.

bn =Bn2R

, R=fractional width (3.25)

an = −An2R

(3.26)

Here the IIR coefficients in capital letter are the FP numbers, and the IIR coefficients in lower

letters are defined Section 3.2.1. The programming interface between the the FPGA servo and

the PC also adopt the FP format. It is important to note the negative sign in Equation 3.26

when programming the IIR coefficients. This negative sign is the result of reducing negation

oprations in the IIR implementation in the FPGA. Programming the An coefficients with the

wrong sign will result in poles being placed on the right-hand-side of the s-domain (oscillatory)

rather than the left-hand-side of the s-domain (stable).

Since the implementation of arithmetic operation in FPGAs requires explicit declaration

of all underlying operations (as opposed to designing within a selection of arithmetic opera-

tions that have been previously defined in an MCU), some design pitfalls exist in the FPGA

implementation of an IIR filter. One such mistake is illustrated in Figure 3.3. Here, the IIR

coefficients are 16-bit in width and the width of all operands are explicitly annotated like it

would be in an Hardware Description Language (HDL) description of an IIR filter. At a first

glance, the IIR filter appears to implement 10 fractional bits in all the coefficients correctly.

This can be confirmed by tracing the gain through each data path in the IIR filter. What goes

hardly noticed in this IIR filter is the loss of computation precision. We can identify this issue

by setting B0 = 1, B1 = 0 and A1 = 210 = 1024, which should configure the IIR as a pure

integrator with a very small gain. When the input is set to a small value, 1 for example, the

output of a pure integrator should produce a shallow ramp, but the implementation shown in

Figure 3.3 produces a sustained 0 at the output.

The correct implementation, as shown in Figure 3.4 is similar to the previous implemen-

tation, but many of the internally stored values in the correct implementation are wider in

width. The filter does not have the computation issue described above due to the additional

computation precision.

39

3.2. IIR Module

ΣB0

B1

210

÷

A1

14 14

30

32 2230

Figure 3.3: An incorrect implementation of a first order IIR filter with FP coefficients (B0, B1

and A1) with 10-bit fractional resolution. The FPGA implementation is made up of simpleoperations like multiplication (×), addition (

∑), division (÷) by the power of 2 implemented

as a shift operation, saturation logic ( ) and clock delays ( ). the width of internal path isnoted in grey next to the path. The placement of the ÷210 operation has a large effect on theeffectiveness of the implementation. The difference between the incorrect implementation andthe correct implementation shown in Figure 3.4 is highlighted here in red.

Σ

B0

Σ210

B1

210

÷210

÷

A1

14 30 24 14

40

31 41 42 32

Figure 3.4: A correct implementation of a first-order IIR filter with FP coefficients (B0, B1 andA1) with 10-bit fractional resolution. The placement of ×210 and ÷210 has a large effect on thewidth of the internally stored values and subsequently the correctness of the IIR implementation.The FPGA implementation is made up of simple operations like multiplication (×), addition(∑

), division (÷) by the power of 2 implemented as a shift operation, saturation logic ( ) andclock delays ( ).

40

3.2. IIR Module

IIR Implementation for Different FPGA Servos

It is worthwhile to summarize the variety of IIR filters commissioned in this work. In broad

categories, as listed in Table 3.1, two IIR filters are commissioned, one for the DE3 FPGA

exclusively and the other one for the DE2 FPGA but the latter is not platform dependent. Table

3.1 also summarizes other differences between the two implementations. One such difference is

that the DE3 version implements 32-bit coefficients while the DE2 version implements 16-bit

coefficients. We note that the DE2 version is designed to have adjustable coefficient width upon

synthesis of the HDL.

Table 3.1: A summary of filters implemented in various FPGA platform in this work. Theformat Qx.y means that the FP representation of the coefficient has x integer bits and yfractional bits. In the case of the Q3.28 format, a total of 32 bits are needed to represent 1 signbit, 3 integer bits and 28 fractional bits. In the case of the Q5.10 format, a total of 16 bits areneeded.

Platform Portability Coefficient Format Complexity (Single)

IIR DE3 No Q3.28 3

IIR DE2 Yes Q5.10 3

The flexibility of the DE2 implementation means that little effort is needed to adopt this

implementation onto a different FPGA like the DE1-SOC, or to change the coefficient width

with from 16-bit to 32-bit. This portability, combined with compatibility of the daughter-card

with DE1-SOC (described in Chapter 2) means that the DE2 servo design can be ported to

DE1-SOC and most other development education platform by Altera.

Integral Anti-Windup

In control systems, integral anti-windup is often implemented to limit the maximum contribu-

tion the integral term has to the total control gain. The purpose is to prevent the controller

from over compensating as the closed-loop system recovers from an out-of-lock state. In the

FPGA servo, integral anti-windup is implemented as a saturator block at the output of the

filter, as shown in Figure 3.4 with the symbol of , that clamps the IIR output to the DAC

range. We note that this particular implementation of integral anti-windup has a problem with

the high order of integration as discussed in Section 3.2.8, but is nevertheless chosen due to its

negligible computation delay and modest resource footprint.

41

3.2. IIR Module

Less Than Unity Servo Gain

Adapting an existing IIR filter, as it is shown in Figure 3.4 to implement a gain of 2a, with

a < 0 calls for modification of the filter. Changing the input coefficient values to implement

a lower gain is not advisable because the coefficients are coupled to the frequency resolution

(refer to Section 3.2.5 for the relationship between the coefficients and the frequency resolution

of poles and zeros). Alternatively, implementing the lower gain can be done by dividing the

output of the IIR filter; however, this must be done with care because an incorrect placement of

the division can reduce the output range of the IIR filter. A reasonable way to implement logic

gain of 1/2 is illustrated in Figure 3.5. In the case of a gain that is less than unity, the internally

stored past IIR output needs to be expanded to have more fractional bits to compensate for

the attenuation at the output of the IIR filter.

Σ

B0

Σ210

B1

210

÷211

÷

A1

14 30 25 14

41

31 41 42 32

Figure 3.5: Implementation of a 1st order IIR with a built-in gain of 1/2. The coefficients areFP with 10-bit fractional resolution. The difference between the gain of 1/2 implementationand the unity gain implementation is highlight in red. The division of 2 is placed at the outputof the filter but the width of the internally stored values are increased to compensate for thepotential loss of the output range.

This particular filter implementation is used in the study of the optimal distribution of gain

in a closed-loop system in Section 4.1.5. The gain distribution is investigated because of its

effect on noise, and the results of this study are presented in Chapter 4. Our findings show that

increasing the input gain and reducing the gain through the FPGA logic can improve the noise

suppression capability of the closed-loop system. However, the IIR filter with 16-bit coefficients

is found to have a limited frequency resolution for the placement of poles and zeros.

How Higher Order Filters are Implemented

Transfer functions with a higher number of poles and zeros are implemented by adding depth

to each IIR or by cascading them as illustrated in Figure 3.6. An IIR filter of high-order can

42

3.2. IIR Module

implement a maximum number of zeros or poles that is equal to the depth of the IIR filter. A

few high-order IIR filter when cascaded implement a transfer function in the z-domain like the

following.

CFPGA(z) =(b0 + b1z

−1 + ...+ bn−1z−(n−1) + bnz

−n

1 + a1z−1 + ...+ an−1z−(n−1) + anz−n)(b′0 + b′1z

−1 + ...

1 + a′1z−1 + ...

)... (3.27)

z-1Σ

z-1

z-1

z-1

z-1

z-1

b0

...

...

b1

bn

bn-1

-a1

-an-1

-an

z-1Σ

z-1b0'

b1' -a1'...

Figure 3.6: Two methods for expanding the order of IIR, depth-wise (left) and length-wise incascaded form (right)

Both methods of implementing multiple poles and zeros have some disadvantages. When

using a single high-order IIR filter to implement multiple poles and zeros, the frequency resolu-

tion for pole or zero placement diminishes as more poles of a half of or zeros are implemented in

the same IIR filter. In the case of the cascaded configuration the disadvantage is a larger delay.

When implementing complex filters such as the PII with lag-lead filter used in Chapter 4, both

techniques are used. For the PII filter with lag-lead, the 6 poles and 6 zeros in the transfer

function are divided up into two third-order IIR filters with 32-bit coefficients in a cascaded

configuration. The poles and zeros are distributed in such a way that both IIR configurations

require similar amount of computation precision.

3.2.4 Verification and Simulation

Verification at the basic level is essential for correctly designing a moderately complex system.

The importance of verification at the HDL level was often overlooked in this FPGA servo

project and this often leads to detours. Three levels of verification were implemented by the

end of the project. The simulation includes testing of individual data paths of an IIR filter, the

43

3.2. IIR Module

open-loop simulation of IIR filters and the closed-loop simulation of IIR filters.

As the simplest verification method illustrated here, the data path verification of an IIR filter

is sufficient to confirm the correctness of an IIR implementation. The open-loop and closed-

loop simulation serves more as way to strengthen our understanding of the IIR filter. More

specifically, the result of an open-loop simulation resembles the transfer function measurement

of the FPGA servo made by a network analyzer (as shown in Section 3.2.5). Similarly, the

result of a closed-loop simulation result allows us to predict the closed-loop performance of the

FPGA servo (which is evaluated in Chapter 4).

Issues encountered in implementing the FPGA servo are investigated with the verification

and simulation tools described in this section. An example of an issue encountered is the loss

of computation precision due to the incorrect handling of the Least Significant Bit (LSB)s as

illustrated in Figure 3.4 in Section 3.2.3. Another issue is the saturation of signals at the input

or output of an IIR filter, similar to the saturation of the error signal at the ADC described

in Section 4.4. Finally, a set of closed-loop simulations are useful to investigate the maximum

level of white noise that a closed-loop IIR filter can suppress, a study that is much more time-

consuming if done with the FPGA servo hardware.

All the HDL simulations are made using the Altera Edition of Modelsim provided in the

Version 13.1 of the Quartus II design suite. The compatibility between the simulation tool and

the Cyclone II FPGA is not affected by the removal of Cyclone II from the list of supported

devices in Quartus 13.1. The HDL simulation is checked against a separate implementation of

an IIR filter in C++. The rest of the tasks, including signal processing, analysis and plotting

of simulation results are made in MATLAB.

IIR Data Path Verification

The verification of all data paths in an IIR filter insures the correctness of the IIR filter. The

test values, as listed in Table 3.2, cover the most commonly made mistakes in implementing an

IIR filter in an HDL. The tests are designed such that if any of the test conditions were to fail,

the tester should be able to quickly isolate the problem to a few lines of code.

The correct gain and delay in an IIR filter insures that the filter implements the correct trans-

fer function. An HDL implementation of an IIR filter is particularly susceptible to unintended

44

3.2. IIR Module

Table 3.2: Test values for the IIR filter used in the DE2 servo, where FP representation ofthe the IIR coefficients, B0, B1, B2, B3, A1, A2 and A3, all have 10 bits (the relationshipbetween the FP numbers and the IIR coefficients can by found in Equation 3.25 and 3.26). Theimplementation details of a first order IIR filter can be found in Figure 3.4. The input widthand the output width of the IIR filter are both 14-bit.

Test Data In B0 B1 B2 B3 A1 A2 A3 Data Out

Gain, 100 1024 0 0 0 0 0 0 100Signed 0 2048 0 0 0 0 0 200

and 0 0 3072 0 0 0 0 300Delay 0 0 0 4096 0 0 0 400

1024 0 0 0 1024 0 0 100, 200, 300, ...1024 0 0 0 0 1024 0 100 x 2 cycle,

200 x 2 cycles,300 x 2 cycles, ...

1024 0 0 0 0 0 1024 100 x 3 cycle,200 x 3 cycles,300 x 3 cycles, ...

Bound 4096 16384 0 0 0 0 0 0 8192-16384 0 0 0 0 0 0 -8191

LSB 1 1024 -1023 0 0 1024 0 0 0 x 1024 cycles,1 x 1024 cycles, ...

Low-pass

0↓

10016 0 0 0 1008 0 0 Reaching 76 in 64

cycles, approach-ing the steadystate of 100

latches which can modify the relationship between the IIR coefficients and the frequencies of

poles and zeros that an IIR filter implements. The gain and delay in an IIR filter can be tested

by monitoring the IIR output while activating one IIR coefficient at a time. The forward path

coefficients, B0, B1, B2 and B3, are assigned different values and the output is expected to be

updated with the gain and the corresponding delay of 1, 2 or3 clock cycles. The feedback path

coefficients, A1, A2 and A3 are tested by configuring the IIR filter as an integrator, by setting

B0 to 2R (R is the fractional resolution of the coefficient in bit) and one of A1, A2 or A3 to a

positive value. The outputs of these integrators are expected to be ramps that update at an

interval of 1, 2 or 3 clock cycles that correspond to the data path tested.

Testing the IIR filter around bound condition verifies the saturation and truncation logic

located at the output of the IIR filter, and this prevents overflow or under-utilization of the

IIR output. Whenever the bound condition fails the IIR filter can still implement the correct

45

3.2. IIR Module

transfer function for a sufficiently small input, but a larger input triggers overflow and causes

instability. In the tests for bound conditions, the IIR input is sufficiently large to cause the

output to clip. The output is expected to clip at the maximum or minimum of the IIR output.

Any other clipping behaviours need to be investigated.

Careful LSB handling is important for reaching a low noise floor when the IIR filter is used

in a closed-loop system. Unwanted LSB truncation can manifest either as insensitivity to small

fluctuation at the IIR input or inability to accurately address the frequency of a pole or a zero.

Both scenarios can be tested by configuring the IIR as an integrator with the lowest frequency

zero that the system can implement and setting the IIR input to 1. If the IIR filter produces a

very slow ramp at the output then the LSBs are likely handled correctly. Otherwise, a sustained

0 at the IIR output indicates that the LSBs are handled incorrectly.

Open-Loop Simulation

The open-loop simulation of the IIR is a set of tests where the HDL implementation of IIR filters

are given an input waveform generated from MATLAB, as opposed to the static test values

described in the previous section. The most useful test waveform is the sinusoidal waveform

which can be used to measure the transfer function of the HDL implementation of a IIR filter

when the period of the sinusoidal wave is varied. The open-loop simulation of the HDL is

compared against an C++ implementation of an IIR filter. As the C++ implementation uses

double float operands, any mistakes frequently made in HDL with fixed point mathematics in

sign extension, numerical saturation, numerical rounding can also be detected

Closed-Loop Simulation

The closed-loop simulation of IIR filters is very helpful for a better understanding of the IIR

filter. The simulation is implemented by configuring an IIR filter in a closed loop in the HDL

testbench and allowing a disturbance to be injected into the loop with a waveform generated

from MATLAB. Figure 3.7 shows the similarity between the open-loop and closed-loop simu-

lation of an IIR filter as they can be configured from the same simulation resources.

The test waveform used in the closed-loop simulation is typically a white noise source rather

than the sinusoidal disturbance used for the open-loop simulation. The use of white noise has

46

3.2. IIR Module

IIR IIR IIR IIR +

export to MATLAB

import from MATLAB

a) b)

import from MATLABexport to

MATLABexport to MATLAB

Figure 3.7: Simulation scheme of IIR in a) open-loop and b) closed-loop. Both simulation areimplemented in HDL and in C++ to 1) verify the implementation of the IIR in FPGA and 2)to provide better understand of IIR filters

the advantage of probing a range of frequencies rather than a single one. The simulation can

optionally export signals at various points of the loop. When the signal is analyzed with FFT,

result is equivalent to taking the transfer function of the IIR filter when it is configured in

closed-loop.

The method of extracting the transfer function from an IIR filter with the FFT and a white

noise input is computationally intensive. This is because the resolution of transfer function is

limited by the bandwidth of the white noise. This means that to obtain the transfer function of

the simulated system at low frequency (with high resolution) the IIR filter needs to be simulated

against a long duration of white noise. In quantitative terms, probing the frequency response of

the IIR at 100Hz requires the IIR to be simulated over 10 ms worth of white noise waveform of

the same duration. That is 200,000 frames of data if the IIR logic is clocked at 50 MHz. Both

the HDL simulation in Modelsim and the C++ implementation can process a similar amount

of data in under 15 minutes, although such a simulation in MATLAB would be less practical.

To demonstrate the usefulness of the closed-loop simulation, Figure 3.8 shows the effect

of loss of computation precision. In this simulation, two cascaded IIR filters are configured

in closed-loop and the noise spectrum at the input of the first IIR filter is computed. It is

important to note that the amplitude of white noise is evaluated in spectral density with the

quantization step at the input of the IIR filter used as the unit. In this simulation, a white

noise disturbance with spectral density of 140 /√

Hz is injected into the loop at the output

of the cascaded filters. As shown in Figure 3.7, the IIR implementation with LSB error has

limited ability to suppress noise at low frequency. In comparison, the IIR performance without

47

3.2. IIR Module

the LSB error reaches far below the quantization level of the IIR input, giving a maximum

noise suppression of 104 times. It is important to note that a noise suppression of 104 times

is equivalent to 80 dB, a level of suppression that is never achieved with the FPGA hardware

(refer to Chapter 4). We speculate that other factors, such as input noise floor, limits the

performance of the real FPGA servo.

102 103 104 105 106 107

Frequency, Hz

10-1

100

101

102

103

104 Noise Suppression Capability of IIR Filters

IIR Implementation (Correct)IIR Implementation (LSB Error)

Figure 3.8: The closed-loop simulation with white noise as disturbance. This data shows thespectrum at the input of the closed-loop for two versions of IIR filter: the version of the IIRwith the error in LSB handling (in red) and the correct version (in blue).

Another set of simulations demonstrates the versatility of the closed-loop simulation. As

shown in Figure 3.9, this set of simulations reveals the effect of a limited IIR input and output

range as the amplitude of disturbance increases. This set of simulations is implemented in C++

to emulate a single IIR filter with 14-bit wide input and output, configured in closed-loop. The

level of noise injected into the loop is varied. It is important to note that amplitude of white

noise is evaluated in spectral density with the quantization step at the input of the IIR filter

used as the unit. For white noise with spectral density of 140 /√

Hz the peak-to-peak amplitude

of the error signal becomes larger than the input range of the IIR module (−8191 ∼ 8192 for

a input width of 14-bit). This clipping causes the closed-loop system rapidly breaks down and

amplifies noise rather than suppressing it. This behaviour is similar to the amplification of noise

observed in Section 4.1.3 when the gain in the FPGA servo is over-tuned. However, when the

48

3.2. IIR Module

input and output range of the IIR filter is extended, the amplification effect lessens. This allows

us to conclude that the amplification of noise observed in Section 4.1.3 and this simulation is

due to clipping at either the IIR input or the IIR output.

102 103 104 105 106 107

Frequency, Hz

101

102

103

104

Noise Suppression over a Range of Noise Amplitude

Amp=100Amp=109Amp=118Amp=130Amp=141Amp=154Amp=167Amp=183Amp=200Amp=500Amp=1000

Figure 3.9: The effect of noise amplitude on noise suppression. This shows simulation of differentlevel of noise injected until the servo break out of lock.

3.2.5 Characterization: Pole and Zero Resolution

In analog servos, the frequencies of poles and zeros are determined by the set of RC constants

implemented in the feedback circuit of op-amps. The RC corner frequencies are often carefully

selected to implement poles or zeros with even spacing in logorithmic scale at frequencies such

as 10 Hz, 30 Hz, 100 Hz and etc [33]. The mechanism of enabling the poles or zeros in analog

servos is through mechanical switches. In comparison, the FPGA servo can be configured with

different frequencies of poles and zeros by simply updating the parameters of the IIR filter

inside the FPGA servo. The added flexibility of the FPGA servo is nevertheless constraint

by the frequency resolution of poles and zeros that the IIR filter can implement. This section

explores the origin of these limitations in a simple first-order IIR filter.

49

3.2. IIR Module

Derivation of Frequency Resolution

Through experimenting with an IIR filter, we found that frequencies at which the poles and

zeros can be placed in an IIR filter is quantized with a resolution set by the clock speed of the IIR

filter (fclk) and the fractional width of the coefficients (R), like in the following proportionality

relationship.

∆f ∝ fclk2R

(3.28)

This means that the frequency resolution of the IIR filter scales linearly with the clock frequency

and increases exponentially as the fractional width of the coefficients increases. This intuitive

scaling relationship can be derived from the mapping relationship between the s-domain and

the z-domain as shown in Equation 3.11. The scaling factor in Equation 3.28 can be found by

following the derivation provided in the following text.

In this derivation, ωp0 and ωz0 are used to represent radial frequency of a pole and a zero

in the s-domain, and z0 and p0 are used to represent the z-domain equivalent of the pole and

the zero. According to the mapping relationship between the z-domain and the s-domain as

the following.

sT = ln z, T = 1/fclk (3.29)

Here, ωp0 and p0 has the following relationship.

ωp0T = ln (p0), T = 1/fclk (3.30)

Here T is the sampling time and is the inverse of clock frequency fclk of the IIR filter.

It is important to note that the value of the pole in radial frequency is different from its value

in ordinary frequency by a factor of 2π. The radial frequency is the quantity that s-domain

poles or zeros are evaluated in, and the ordinary frequency is the quantity that is typically

referred to when describing the periodicity of a waveform in the time domain. Here, fp0 is used

to represent the pole in ordinary frequency (in Hz), and it is related to ωp0 by the following

50

3.2. IIR Module

relationship.

ωp0 = 2πfp0 (3.31)

This means that the ordinary frequency of a pole is related to its z-domain equivalent by the

following relationship.

fp0 =fclk2π

ln (p0) (3.32)

Here, the term ln (p0) can be evaluated by taking the linear approximate of ln as p0 approach

1 from below. This approximation is equivalent to implementing a pole or a zero with frequency

much lower than the clock frequency of the IIR filter (z → 1− is equivalent to s→ 0−). In the

typical usage of a PID controller, the corner frequency of a pole or a zero is lower than 1 MHz

while the IIR filter is clock between 50 MHz and 75 MHz in this work. This suggests that it is

valid to approximate p0 and z0 as approaching 1 from below.

To reflect the hardware implementation in the FPGA, the z-domain pole p0 is written in

terms of the FP number like the following.

p0 =A1

2R(3.33)

Here A1 is an FP number with R fractional bits (refer to Section 3.2.3 for definition of the IIR

coefficients). Using this relationship, the frequency resolution of fp0 can be expanded like the

following.

∆fp0 =fclk2π

ln (A1

2R)− fclk

2πln (

A1 −∆A1

2R) (3.34)

Here, the smallest change that is allowed in A1 is ∆A1 = 1. By expanding the ln around 1, the

frequency resolution can be found to be the following,

∆fp0 =fclk2π

(A1

2R− A1 −∆A1

2R

), ∆A1 = 1

=fclk

2π · 2R(3.35)

This concludes that the scaling factor in Equation 3.28 is 2π. This is confirmed by checking

51

3.2. IIR Module

the transfer function of various IIR filters in MATLAB. When fclk is to 50 MHz, the frequency

resolution of a single pole or zero that implemented by a first order IIR filter is about 7.1

kHz when the coefficients has 10-bit fractional resolution (16-bit coefficients). Details on the

measurement of frequency resolution can be found in the next section. When coefficients with

28-bit fractional resolution (32-bit coefficients) are used, the frequency resolution of a pole or

a zero can be as low as ∆f = 48 mHz.

The same scaling factor does not necessarily hold true for the frequency resolution of a zero

in a first order IIR filter. This is because the z-domain implemented in the FPGA has the

following relationship,

z0 =B1

B0(3.36)

as indicated by the definition of the IIR coefficients in Section 3.2.3. When the B0 coefficient

is fixed at B0 = 2R (the FP equivalent of b0 = 1), the frequency resolution of the zero has the

same relationship as the frequency resolution of a pole as shown by the following relationship,

∆fp0 =fclk

2π · 2R, B0 = 2R (3.37)

However, when B0 is not fixed at 2R, the frequency resolution of the zero is < fclk/2π · 2R for

B0 > 2R and > fclk/2π · 2R for B0 < 2R.

In a more general case, an IIR filter of higher order can implement multiple poles and zeros.

It is possible to show that the resolution of the pole placement in a multi-order IIR filter,

depends on the value of all the other poles implemented in the same IIR filter, by factoring

and reducing Equation 3.27 in Section 3.2.3. In summary, it is important to keep in mind that

the resolution of a pole in an IIR filter that implement multiple poles is always worse than if a

single pole is implemented (for further reading, please see [34, p.383]).

When working with IIR filter of higher order, it is important to note that small adjust to

poles and zeros in z-domain can lead to dramatic change in the transfer function. In some

cases, the phase response of the transfer function can be modified by as much as 180 degree,

which can cause instability in a closed-loop system. While IIR filter with high computation

precision can implement a more complex transfer function without introducing instability, for

52

3.2. IIR Module

any IIR filter with finite fractional resolution, this problem can occur if the transfer function

becomes too complex. As a solution to this issue, this work develops a MATLAB routine (refer

to Appendix D) that compares the s-domain transfer function and the closest transfer function

that the hardware can implement in both amplitude and phase. Ultimately, it is up to the user

to make sure that the phase response of the s-domain transfer function is not compromised

when converted to a hardware implementation.

Measurement of Frequency Resolution

The frequency resolution of poles and zeros in an IIR filter can be characterized as a series of

transfer function with small variation in the IIR coefficients. A network analyzer like the SR780

can be used to take the transfer function. The network analyzer generates a chirp signal and

when it is used as the input to the FPGA servo, the cross correlation (computed by the SR780)

between the output of the FPGA servo and the chirp signal gives the transfer function.

A typical result of this measurement is shown in Figure 3.10. Here, the IIR filter is configured

as a PI filter with a fixed corner frequency and is tested against chirp signals of different

amplitudes. In all of the measurements, the transfer function agrees with the ideal transfer

function of a PI (in the dotted line) at intermediate frequencies, between 10 kHz to 1 MHz

(only the regions between 10 kHz and 100 kHz is shown). At low frequencies, the amplitude

response of the measured transfer function saturates, while the phase response does something

completely unrecognizable. The non-ideal behaviour of the PI filter at low frequencies is not

visible in its z-domain transfer function where the input and the output signals are unlimited in

amplitude. As it can be observed in Figure 3.10, the transfer function measurement approaches

the ideal PI transfer function, as the input amplitude is lowered and the IIR output saturates

around 200 mV regardless of the input amplitude. This suggests that the non-ideal behaviour

is rather caused by saturation at the output of either the IIR filter or the FPGA servo. This

saturation voltage may differ in other testing scenarios if any DC component is present in the

chirp signal or if the gain and the offset circuit is part of the measurement.

Figure 3.11 shows the lowest 3 non-zero zeros implementable by a first order IIR with

coefficients with 10 fractional bits. The coefficients are programmed as B0 = 1024 and A1 =

1024 for all three filter, and B1 = −1021, B1 = −1022 and B1 = −1023 respectively for each

53

3.2. IIR Module

0

10

20

30

40

50

Mag

nitu

de, d

B

Measurement of PI Filter Transfer Functions Implemented in the FPGA servo

fPI

=25 kHz, Vpk

=20 mV

fPI

=25 kHz, Vpk

=60 mV

fPI

=25 kHz, Vpk

=100 mV

fPI

=25 kHz, ideal

102 103 104 105

Frequency, Hz

90

135

180P

hase

, deg

ree

Figure 3.10: Transfer function measurement (with SR780) of a PI filter with chirp input ofdifferent amplitude. The measured transfer function approach the ideal shape as the chirp signalbecomes smaller in amplitude. This suggests that the non-ideal behaviour of the implementedPI transfer function is due to clipping at the output of the IIR filter or the FPGA servo.

filter. The corner frequencies of these PI filters are, 22 kHz, 14 kHz and 7.1 kHz, indicating

a frequency resolution of roughly 7.1 kHz. When compared against an IIR filter with high

fracitonal resolution, a higher resolution of zero can be found.

An alternative method for measuring the frequency resolution of a single pole or zero is to

set the IIR filter to the lowest pole or zero that is allowed by the IIR filter and use a function

generator to scan over a small frequency range until the 3 dB (corner) frequency is found. This

method do not verify the shape of the transfer function everywhere else in the frequency range,

but is an extremely fast sanity check for a first order IIR filter, and it should be used with care

on a higher order IIR filter.

3.2.6 Characterization: Resource Allocation

The computation footprint of IIR filters is an important consideration in selecting the right

FPGA in an FPGA servo design. Before investigating this issue, we would like to identify the

computation resources in an FPGA. The simplest type of configurable logic unit in an FPGA

is the LE (by Altera convention) or Look-up Table (LUT) (by Xilinx convention). Although

54

3.2. IIR Module

-5

0

5

10

15

20

25

Mag

nitu

de, d

B

Frequency Resolution of a Zero in a PI filter, Clock Frequency = 50 MHz

B0=1024, B

1=-1023

B0=1024, B

1=-1022

B0=1024, B

1=-1021

3 dB

102 103 104 105

Frequency, Hz

90

135

180P

hase

, deg

ree

Figure 3.11: Transfer function measurement that demonstrates the frequency resolution of azero in a PI filter, where coefficients has 10 bit fractional resolution. The coefficients are setto B0 = 1024, A1 = 1024 and B1 = −1021, B1 = −1022 and B1 = −1023 for each filter. Thecorner frequency of the PI filters can be found as the 3 dB frequency (intersection with thedashed line) and are respectively 22 kHz, 14 kHz and 7.1 kHz.

LEs can be configured to form any kind of logical devices, arithmetic operations are best

implemented with the FPGAs DSP resources. The DSP based computation resources in the

two FPGAs used in this thesis, the high-performance Stratix III in DE3 and the economic

Cyclone II in DE2, are different in complexity, as illustrated by the comparison in Figure 3.12.

CLRN

D Q

ENA

Data A

Data B

aclrclock

ena

signa (1)signb (1)

CLRN

D Q

ENA

CLRN

D Q

ENAData Out

Embedded Multiplier Block

OutputRegisterInput

Register

++

144 44InputData

Inpu

t Reg

iste

r B

ank

Pip

elin

e R

egis

ter

Ban

k

Add

er/

Acc

umul

ator

Out

put R

egis

ter

Ban

k

Half-DSP Block

Result

Figure 3.12: Comparison between DE2 (left) and DE3 (right) computation resources

The DSP resources in an Cyclone II FPGA are simple multipliers with optional input and output

latches as illustrated in Figure 3.12 (left). In comparison, the DSP resources in an Stratix III

55

3.2. IIR Module

FPGA are DSP engines which contain multipliers followed by two stages of accumulators,

with the first accumulator responsible for summing the output of multipliers and the second

accumulator responsible for summing of output several DSP engines, as illustrated in Figure

3.12 (right). It is important to note that the HDL synthesizer shipped in Quartus 13.1 does not

provide full support to all necessary features of the DSP engines in the Stratix III FPGA, which

necessitates declaration of the DSP explicitly. Although using specific accumulator features in

the DSPs helps to lower the computation delay in the IIR filter, reference to the DSP features

reduces the portability of this HDL implementation. Thus, specific references to DSP structures

are avoided unless necessary.

In order to accurately assess the computation footprint of IIR filters in FPGAs, we use

18-bit by 18-bit multipliers as the unit of the assessment. Among the IIR filters implemented

in this work (Table 3.1), the most suitable IIR implementaion for this study is the filter used

in the DE2 servo because it can be easily configured to implement a variety of coefficient width

and various IIR depth. This study also assumes that the accumulators absent in the Cyclone II

FPGA are to be constructed out of LEs. Table 3.3 shows that the number of 18×18 multipliers

needed to implement IIR filters of various coefficient widths and depths.

Table 3.3: A summary of the computation footprint of various IIR filters with different depthand coefficient widths, quantified by the number of 18 × 18 multipliers.

16 bit coeff., with 10 bit 32 bit coeff., with 20-28fractional resolution bit fractional resolution(18×18 multipliers) (18×18 multipliers)

1st order IIR 4 82nd order IIR 7 133rd order IIR 10 18

With the computation footprint of IIR filters in Table 3.3 and the computation resources

in FPGAs in Table 3.4, it is possible to devise a strategy on distributing DSP resources in an

FPGA servo. For example, the IIR filter needed to implement the PII + lag-lead control is

in the form of 2 third-order IIR filters in cascaded configuration both with 32-bit coefficients.

The computation footprint of this IIR filter is 36 multipliers per channel, an impossibility for

the DE2 FPGA (with 35 multipliers in total), but is manageable for both the DE3 FPGA (384

multipliers) and the DE1-SOC FPGA (174 multipliers).

56

3.2. IIR Module

Table 3.4: Comparison of computation resources in various FPGA platforms

DE3 DE2 DE1-SOC

18×18 Multiplier 384 35 174

Since the DE2 FPGA is limited in computation resources, a reasonable way of distributing

the DSP resources is to implement in each channel 2 first-order IIR filters in a cascaded config-

uration. One of the IIR filters can be configured with 16-bit coefficients and other with 32-bit

coefficients to allow implementation of PII with one high frequency zero and one low frequency

zero. Many variations exist, but they all have to work within the resources available in the

DE2 FPGA. The ultimate solution is to port existing DE2 implementation to the DE1-SOC

to allow a more complex filter.

3.2.7 Comments on Computation Delay

The computation delay through the IIR logic can be combined with the delay through the analog

frontend and the ADC/DAC described in Chapter 2 to compute the total latency through the

FPGA servo (typically around 200 ns in total). This computation delay is not absolute as

a lower computation delay can often be achieved by additional computation resources and

additional development time. In an effort to minimize the computational delay, the IIR filter

commissioned in this project is optimized to have a delay of 1 cycle at either the maximum

frequency allowed for the ADC and the DAC or at twice of this frequency. For example, a

single DE2 IIR filter with 16-bit coefficients has 1 cycle of delay at fclk = 130 MHz while the

ADC and the DAC are clocked at 65 MHz. The fclk for the DE3 32-bit coefficients IIR is lower

and various versions of the design are clocked with a single cycle of delay at either 50 MHz or

75 MHz although more optimization would allow an additional increase in the clock frequency.

As the result of this optimization, the computation delay is similar or less than the ADC/DAC

delay, even when up to 3 IIR filters are cascaded to realize a more complex filter.

The main tool used in reducing the IIR computation delay is Altera’s TimeQuest timing

analyser. The timing analyzer helps by identifying the limiting factor in computation delay and

providing clues to reduce the total delay. Another look at the IIR implementation illustrated

in Figure 3.4 in Section 3.2.3 should reveal that the forward paths (the signal paths between

57

3.2. IIR Module

the IIR input and the IIR output) and the feedback paths (the signal paths between the past

IIR output and the current IIR output) has different computation complexity. The feedback

paths have a larger computation load because the scaling factors for the feedback paths, A1, for

example, need to multiple against internally stored values that are wider. This is why it is often

the feedback path that has trouble satisfying the timing constraint. As a concrete example, the

total timing budget for one IIR filter in the DE2 implementation is 7.7 ns. This is assuming

the IIR filter is clocked at 130 MHz. Each feedback path (An) is composed of two 18-bit by

18-bit multiplications that takes 3.5 ns (specification is obtained from [35, 5-21]), while working

in parallel. An additional summation step must follow the two 18-bit by 18-bit multiplication

operation, and this summation step is not present in the case of the forward paths (Bn).

A few optimization techniques were found to be helpful. In one case, the FPGA synthesis

planner is allowed to place redundant buffers for a few internally stored values which allow

the synthesis planner more freedom in placing the slowest signal paths, and eventually leads to

reduction in delay. In another instance, the design of three cascaded IIRs are allowed 4 total

clock delays, with the additional clock cycle designated to allow the signals to travel from the

IIR output to the FPGA pins. Having an additional delay allows the maximum frequency of

this block (derived from the same master clock as that derived for the ADC and DAC driver)

to be higher than if the IIR filters were designed to have 3 clock delay (each IIR filter takes

up one clock delay). This allowed the servo logic to be clocked at twice of the clock frequency

for the ADC and the DAC rather than at the same frequency, so as a result the total delay

is reduced by 1/3. Admittedly, these examples of reducing the computation delay may not be

feasible in all optimization scenarios. Many optimization strategies are discussed in text on

reducing delays in FPGA design [36].

3.2.8 Comments on PII

This section comments on some observations made during the use of a PII filter. Some of these

observations, regarding the offset at the output of the PII filter specifically, is inherent to the

PII filter and should be present regardless of the underlying implementation (whether is digital

or analog). The observations regarding the strange saturation behaviour of the PII is specific to

the implementation of the IIR filter by this work and is not present in an analog implementation

58

3.2. IIR Module

or likely IIR filters with a different saturation logic.

PII Offset

The IIR filter produces an offset on its output when configured as an integrator. This offset

can be observed at the output of a single PI filter as illustrated in Figure 3.13 . Similarly, when

two PI filters are cascaded together to form an PII filter, a ramp appears on its output as it is

also evident in Figure 3.13. The offset and the ramp at the output of the IIR filters may seem

counter intuitive as the input sinusoid contains no offset. However, this behaviour is expected

from the integral of a sinusoid over a finite interval. The first order integration of a sine wave

has a DC offset dependent on phase of the input. The second order integration subsequently

integrates this offset and produces a ramp with a slope that is dependent on the phase of the

input sine wave. The simulation shown in Figure 3.13 produces this behaviour after it was first

discovered with the FPGA servo hardware. The details of the simulation method are discussed

in Section 3.2.4.

1000 2000 3000 4000 5000 6000 7000 8000 9000 10000

Clock

0

1000

2000

3000

4000

5000

6000

7000

8000

Dig

ital C

ode

Open-Loop Simulation of a PI Filter and a PII Filter in Cascade Form

IIR InputPI OutputPII Output

Figure 3.13: The open-loop simulation of the PI filter and the PII filter in cascaded form,showing the offset at the output of the PI filter and the ramp at the output of the PII filterin cascade. As it can be observed in this figure, the input to the filter is a sine wave with nooffset.

The ramp at the output of the PII causes the IIR output to quickly “rail to either the min-

59

3.2. IIR Module

imum or the maximum of the IIR output. This behaviour complicates the open-loop measure-

ment of the transfer function of the PII. In contrast to the inconvenient open-loop behaviour,

when the PII is used in closed-loop this ramp is suppressed by the servo logic and does not

affect the closed-loop performance of the servo.

An Unusual Saturation Behaviour of the PII Filter

The IIR filter commissioned by this work (as illustrated in Figure 3.4 in Section 3.2.3) has an

edge case where instability exists. The instability occurs when a single IIR filter implements

a PII filter in the form of a second-order IIR filter. The instability occurs when the output

of the IIR filter saturates but the filter fails to hold the output in saturation as illustrated in

Figure 3.14 starting roughly at 6.6 · 104 clock in the simulation. The spectral measurement of

the output the filter may appear normal if the instability does not frequently occur. However,

this is a serious problem in a closed-loop system because when the plant drifts further away

than the range of the actuator the servo would fail to hold the actuator at its limit and result in

losing the lock. As this instability does not occur when a single IIR filter implements more than

one non-zero pole/zero (as opposed to the PII containing 2 poles at s = 0), this work resorts

to avoiding the instability by limiting each IIR to implement a single order of integration and

add IIR in cascade if needed.

To examine the cause of this instability, the exact instability scenario is emulated in sim-

ulation, which then provides the values of internal registers at the moment when instability

occurs, as shown in the inset of Figure 3.14. The simulation reveals that the problem occurs

at the moment when the saturation logic is activated. Activating the simple saturation logic is

equivalent to introducing an impulse at the IIR output, with a sufficient amplitude to prevent

the IIR output from overflowing. The record of this impulse, remains in the IIR filter and

manifests itself as a ramp at the IIR output over time.

A better saturation logic is to modify the internal states of the IIR filter in a coherent

manner to avoid introducing this impulse. One way is to scale all the internal states by the

same amount that the IIR output is changed by. This is equivalent to modifying internal states

of the IIR filter as if all past inputs were smaller in amplitude. We were able to simulate this

implementation in C++ and to confirm that this saturation logic fixes the unusual saturation

60

3.2. IIR Module

0 1 2 3 4 5 6 7 8 9 10

Clock 104

-8000

-6000

-4000

-2000

0

2000

4000

6000

8000

Dig

ital C

ode

DFI Instability When Implementing PII

IIR Input, x[n]IIR Output, y[n]IIR Output, y[n-1]IIR Output, y[n-2]

Saturation Logic Acitivated

Figure 3.14: The open-loop simulation of a second-order IIR filter configured as a PII filter. ThePII in this configuration fails to saturate at its boundary, as opposed to its expected behaviourin Figure 3.13 with a PII filter in cascaded form. Instabilities occur at the clock frame 6.6 · 104

(shown in the inset), 8.0 · 104, 8.8 · 104 and 9.5 · 104.

behaviour for a PII filter or a PI3 filter when implemented in a single IIR filter.

3.2.9 More on Filter Design

IIR and FIR are two broad classes of digital filters that can be designed with many different

strategies. Two such strategies of designing an IIR filter are described in Section 3.2.1 including

the use of an exact s-domain to z-domain transformation and the use of a bilinear approximation.

This section describes two other methods of designing filter, and it also comments on whether

these alternatives are suitable for use in a closed-loop system.

Higher Order of Approximation for an Integrator

In Section 3.2.1, the controller is designed in the s-domain, transformed into the z-domain and

then converted into the time domain to produce the IIR coefficients. Another method, less

commonly used, is to design the controller directly in the time domain. This method is based

on transforming the differential equation that describes the relationship between the filter input

and the filter output into a difference equation that can be directly implemented with an IIR

61

3.2. IIR Module

or an FIR filter. For example, a pure integrator controller can be described by the following

expression where x(t) is the input and y(t) is the output.

y(t) =

∫ t0

0x(t)dt (3.38)

This continuous-time relationship can be converted into a discrete-time relationship using var-

ious numerical integration methods including the rectangular integration rule, the trapezoidal

integration rule, or other rules (see, for example, ch.6 of ref [37]). The continuous-time expres-

sion evaluated to the lowest order using the rectangular integration rule yields the following

difference relationship,

y[n] = Tx[n] + y[n− 1] (3.39)

where T is the sampling period of the discrete-time system. Similarly, the next higher order

approximation using the trapezoidal integration rule results in the following equation.

y[n] = T(x[n] + x[n− 1]

2

)+ y[n− 1] (3.40)

It is worth noting that this method yields the same result as the s-domain equivalent of the

differential equation followed by a transformation into the z-domain using the bilinear approx-

imation (refer to Section 3.2.1).

Like the rectangular integration rule, the trapezoidal integration rule has a residual error

when used to integrate smooth functions. The residual error can be reduced with a second order

approximation of integration, called the Simpson’s Integration rule. By following this rule, the

differential relationship in Equation 3.38 can be transformed into the following relationship.

y[n] = T(x[n] + 4x[n− 1] + x[n− 2]

3

)+ 0 · y[n− 1] + y[n− 2] (3.41)

In preliminary tests of the FPGA servo, this Simpsons Integration rule relationship was com-

bined with a zero around 70 kHz to form a PI filter and was used to form closed-loop lock with

the FPGA servo hardware. The servo system was able to lock with this PI filter but exhibited

no obvious advantage over the trapezoidal integration rule. Rather, compared to the PI filter

62

3.2. IIR Module

that follows the trapezoidal integration rule, a PI filter that follows the Simpson’s integration

rule increases the loop delay by one clock cycle and takes up more computation resources.

To conclude, this study is meant to illustrate that transforming a continuous-time rela-

tionship into a discrete-time relationship by converting the integral or differential equation

(Equation 3.38) into difference equations (Equation 3.39, 3.40 and 3.41) is a valid method of

producing IIR coefficients for use in the servo logic. This study also shows that a closed-loop

control system is rather forgiving with integration error and that reducing the integration error

does not seem to result in a significantly better closed-loop performance. The later observation

is reminiscent of the observation made in Section 3.2.8 where the PII offset error does not have

a detrimental effect on the closed-loop control performance.

IIR vs FIR in Implementing a Phase Compensator

To reduce the impact of the loop resonance in a closed-loop system, the use of a lag-lead filter

is investigated in detail in Section 4.2.6. Before arriving at the decision to use the lag-lead

filter, the work also considered other types of digital filters to form a bandstop filter to be used

along with a PII filter to cancel the loop resonances. Two other types of bandpass filters are

considered. They are an elliptic bandstop filter that has an equivalent form as an IIR filter and

an FIR bandpass filter designed via the windowing methods. To keep the comparison fair, all

the bandstop filters are designed with a centre frequency of 0.1 fclk where the fclk is the clock

frequency of the filter. Their frequency domain response (transfer function) is shown in Figure

3.15 along side with the lag-lead filter, which is designed via the bilinear transformation.

One filter candidate is a second order elliptic bandstop filter with a target stop-band between

0.05fclk − 0.2fclk. The filter is computationally equivalent to a fourth order IIR filter. One

unacceptable feature of the elliptic filter is the sign change at each node of the filter, as shown

in Figure 3.15 at approximately 0.07fclk and 0.14fclk. This means that the filter has different

signs in frequencies between 0.07fclk − 0.14fclk than all other frequencies, making it impossible

to avoid positive feedback for all frequency. This positive feedback is undesired for closed-loop

systems as it often leads to instability.

The other candidate is a 30th order FIR bandstop filter with a target stop band between

0.05fclk − 0.2fclk. Although the computation complexity of FIR filter is not directly compa-

63

3.2. IIR Module

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1-20

-10

0

10

Mag

nitu

de (

dB)

IIR vs FIR

IIR-BilinearIIR-EllipticFIR

0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1

Normalized Frequency (x rad/sample)

-100

0

100

Pha

se (

degr

ee)

Figure 3.15: Comparison of three different digital filters all implementing a notch filter withcenter frequency at 0.1fclk. Only the bandstop filter designed with the bilinear method (lag-lead) is suitable for used in closed-loop, because the elliptic bandstop filter changes sign at 0.7fclk and 0.14 fclk and the FIR bandstop filter has excessive delay.

rable with an IIR filter, the comparison can be made by assessing the amount of computation

resources used by the two filters. In this way, a 30th order FIR filter in this study is found to

use a similar number of 18-bit by 18-bit multipliers as a 9th order IIR filter. Besides the large

computation footprint, the FIR bandstop filter also has a large delay that scales with the order

the of the filter (the order is 30 in this case). Despite these disadvantages, the FIR filter can,

nevertheless, be used in a closed-loop controller and should be considered if a better alternative

is not available.

As the remaining candidate, the IIR filter designed via the bilinear method is composed of

two poles, at 1 MHz and 8 MHz and two zeros, at 2 MHz and 4 MHz and converted to z-domain

with a clock frequency of fclk = 50 MHz. Although the IIR filter obtained via the bilinear

method has a wide attenuation band and attenuates much less within the band, as shown

in Figure 3.15, it has a stable phase response and uses a reasonable amount of computation

resources as only a second order IIR filter. As a result of this comparison, the lag-lead filter

designed with the bilinear method was chosen, and it is used as the compensator to reduce loop

resonances. A detailed discussion of its closed loop performance is provided in Section 4.2.6.

64

3.3. Arbitrary Waveform Generator

3.3 Arbitrary Waveform Generator

Waveform generation is a ubiquitous and versatile tool in an AMO laboratory. The need for

waveform generation ranges from dithering laser frequencies to modulating laser intensities.

It is convenient feature for a laser servo to combine the function of stabilizing the laser with

waveform generation and this can be easily implemented in an FPGA servo. Additionally, the

waveform generation capability of an AWG can be used to implement new features, such as lock-

in detection and system identification. This section describes the design of an AWG produced

by this work, how the AWG can be program, its residual error, and other characteristics of the

module.

3.3.1 Implementation

With flexibility and speed as the main design requirement, the waveform generator is imple-

mented as a fourth order polynomial with programmable coefficients as illustrated in Figure

3.16. The timescale of the polynomial is controlled by a ramp generator (left module). The

shape of the waveform can be controlled by the coefficients to the fourth order polynomial

(right). All the ramp parameters and the polynomial coefficients can be controlled from a PC

via USB. A soft-core MCU in the FPGA receives the parameters through the serial link and

then transfers the parameters to the AWG. The address where the parameters can be accessed

is provided in Appendix C.

max

min

incprescaler( )

clk

clk

rst

trig

rampy=a0+a1x+a2x

2+a3x3+a4x

4 out

(31:16)

Figure 3.16: A block diagram of the arbitrary waveform generator, implemented as a counterfollowed by a 4th order polynomial. The counter produces a 32-bit triangular waveform and canbe controlled through internal registers: “max”, “min”, “inc” and “prescaler”. The triangularwave at the output of the first module has a range between “max” and “min” control and aslope of fclk ·(inc/prescaler). The polynomial coefficients are implemented as 16-bit FP numberswith 10 fractional bits. Signal responsible for external trigger are “rst” and “trig”.

Synchronous control of the AWG is accomplished with an external trigger signal. This

allows the waveform generator to operate in synchronization with the rest of the experiment.

65


3.3.2 Coefficients, Residual Error and Verification

A simple configuration of the AWG is an triangular wave generator, where the coefficients are

programmed as a1 = 1 and an = 0. The slope and the amplitude of the ramp is controlled by the

counter parameters, like “ramp min”, “ramp max”, “increment” and “prescaler”. Configuration

of an arbitrary waveforms is accomplished by adjusting the AWG coefficients A0, A1, A2, A3

and A4. They are the FP representation of the coefficients of a fourth polynomial and are

defined like the following.

An = an · 2R, R=fraction resolution=10 (3.42)

The coefficients can be found by a least square fit to fourth order polynomial. The sample

coefficients for implementing sinusoidal or Gaussian waveform are listed in Table 3.5. Because

the underlying implementation in the AWG is in FP arithmetic, the coefficients here are also

in the format of FP number with 10-bit fraction resolution.

Table 3.5: The best fit parameters to implement a sine or a Gaussian waveform. The AWGis implemented as 4th order fixed point polynomial. The parameters related to the ramp(“min”, “max” and “increment”) are 32-bit FP numbers with 16-bit fractional resolution. Theparameters for the polynomial, A0, A1, A2, A3 and A4, are 16-bit FP numbers with 10-bitfractional resolution

Ramp Ramp Pre-Min Max Increment scaler A0 A1 A2 A3 A4

Gaussian 0 0x800000 0x10000 1 13 899 −1522 1825 −372

Sine 0 0x4000000 0x10000 1 4096 1000 −27415 18277 0

A small but significant residual error remains when fitting the target waveform to a polyno-

mial, as it is shown in Figure 3.17 for both the sine wave and the Gaussian wave. When a fourth

order polynomial is used, the residual error in fitting to a sine or a Gaussian waveform is about

2% of the total amplitude of the waveform. Although increasing the order of the polynomial

decreases the residual error, the cost of computation resources increases rapidly as the benefit

of a smaller residual error diminishes.

Another potential issue is that the residual error is not smooth at the boundary of the

polynomial. This can be observed at the 0th, 500th, 1000th clock frame in Figure 3.17. This is

because the least square method is used for fitting the waveform to a polynomial. If a fitting

66


0

0.5

1

Trig

Arbritrary Waveform Generator, Signal I/O

0

500

Ram

p

0

0.5

1G

auss

ian

-0.02

0

0.02

Erro

r

-500 0 500 1000 1500 2000 2500Clock

0

1

2

Sine

-0.02

0

0.02

Erro

r(Fractional)

(Fractional)

Figure 3.17: The sine and Gaussian waveform output of the AWG, with their respective residualerror. The AWG has two trigger mode, a single trigger modes (in black) and a continuous-triggermode (in grey).

method is based on the Laguerre polynomials with smooth boundary conditions, the AWG

output would not exhibit this behaviour.

The AWG implemented in this work has a verification scheme, where the HDL description

of the AWG is compared against another description of the same algorithm programmed in

MATLAB. The MATLAB description of the AWG anticipates the computation precision of the

HDL implementation and no discrepancy is expected from the two sets of implementation. The

verification scheme is in the spirit of modular testing already described in previous sections and

it is meant to produce self-documenting and reusable code.

3.3.3 Alternative Designs

An AWG with an underlying polynomial implementation has the advantage of needing very little

bandwidth to program since the waveform is generated within the FPGA. Another approach is

to use the FPGA as a memory device. This implies generating the waveform on a PC and then

uploading it into the FPGA. This work explored this approach and comments are provided

below on what was found.

The very first iteration of the waveform generator simply stored the waveform in the on-chip

67

3.4. Proposal on Feature Expansion

memory bits in an FPGA in the form of Read Only Memory (ROM) and used a counter to

step through the data (The syntax of doing this in Verilog can be found at this reference [38,

p.295]). This design is incredibly easy to make, but the waveform is read only. Changing the

waveform requires access to the FPGA design program and this creates a barrier to update the

waveform for other experimenter in the lab.

Another possible implementation of an AWG is to store the waveform in random access

memory of the FPGA and to program it from a PC through a softcore MCU. This immediately

turns out to be a bad idea on the DE2 FPGA platform, due the lack of a fast communication

option between the FPGA and the PC. It is important to keep in mind that the AWG consumes

14-bit data at 50 MHz. The constraint of slow communication interface between PC and the

FPGA platform is lifted on newer FPGA platforms and should allow the implementation of a

memory-based AWG.

3.3.4 Future Improvements

In general, implementing an AWG in the form of polynomial function has the advantage of

being quick to re-configure. However, as the complexity of the waveform increases additional

computation complexity is needed. Implementing a polynomial function with higher complexity

is exponentially more work as the complexity increases. In the case when truly arbitrary wave-

form with lots of discontinuities is needed, the memory-based AWG implementation described

in Section 3.3.3, may become more favourable.

3.4 Proposal on Feature Expansion

The FPGA servo designed by this work has the potential to become a versatile, control toolbox

with wide adoption in AMO experiments. So far, this work has explored the implementation of

two of these tools, the IIR filter and the AWG. More features can be added to the FPGA servo

over time, and this section is meant to discuss potential implementations for some of these new

features, including lock-in detection, auto-lock detection and plant detection. A few of these

features have already been demonstrated in published work by NIST [14], and while this can

serve as reference design it may not be easily transferable to an Altera platform.

68


3.4.1 Lock-in Detection

The lock-in technique is a detection technique for weak signals that is widely used in AMO

experiments. Some example applications are the PDH technique [39] and the use of lock-in

detection in saturated absorption spectroscopy [33]. The theory underlying the operation of

lock-in amplifiers is discussed in various texts [40]. In essence, a lock-in amplifier is a modulation

and demodulation technique that is based on the orthogonality principles of sine waves. The

outcome of this technique is a very sharp notch filter at the modulation/demodulation frequency

and this helps to recover signal from a high level of background noise. The implementation of

a lock-in amplifier is illustrated in Figure 3.18. In this design, both the in-phase and the 90

degree out-of-phase component is recovered from the lock-in input. Some comments on this

type of digital lock-in implementation can be found at a white paper by Zurich tech [41]. Some

lock-in implementation does not include the 90 degree out-of-phase component, but we suspect

that those types of implementation are suitable for modulation frequency that are low enough

that the signal latency through the plant is not sufficient to cause a significant phase shift.

IIRADC DAC

sin

cos

Demodulation (Lock-in)

Servo

Modulation

x

y

Figure 3.18: An implementation proposal of lock-in amplifier in the FPGA servo. The servologic is divided in to demodulation, servo and modulation (what is not shown here is the rest ofthe servo and the laser configured in closed-loop. Both in-phase component (x) and 90 degreeout-of-phase component (y) are recovered from the input signal and they must be combinedas complex numbers (rather than as simple addition of the amplitudes) to generate the errorsignal.

The lock-in detection logic can be implemented in the FPGA servo and be used in conjunc-

tion with the servo logic without the need for additional electronics. Some of the basic building

blocks of a lock-in an amplifier are already implemented in this work. The sine and cosine

waveform can be handled by the AWG described in Section 3.3, or by the alternative design of

69


the AWG where the waveform is preprogrammed in ROM. The period of the sine and cosine

can be controlled with clock prescalers to the AWG module. In addition, the LP filter that

follows the multiplier can be implemented in the form of IIR. The remaining pieces are simple

arithmetic and pose no obstacle to implementing lock-in detection.

3.4.2 Auto-Lock Logic

The auto-lock logic, sometimes referred to as the lock-recovery logic, is the mechanism to

automatically lock a plant to a pre-programmed setpoint. The use of an auto-lock mechanism

in an experiment reduces the manual work need to lock lasers and is very beneficial in an

complex AMO experiment. The typical locking method is to manually adjust an offset to

the laser controller until the frequency of a free-running laser is within detectable range of a

frequency discriminator. This manual adjustment can be replaced by ramping the slow-DAC in

the FPGA servo slowly until an error signal is detected. Once the error signal is detected, the

FPGA servo can engage the lock by setting the IIR coefficients. The trick to this implementation

is to keep the auto-lock logic in the MCU that is built-in to the FPGA. The auto-lock routine

is a sequential process and is more intuitive to be implemented in C/C++.

3.4.3 Plant Detection

Plant detection, or sometimes referred to as system identification, is a set of control techniques,

widely used in identifying the optimal control parameters in applications such as motor servos.

Some system identification techniques measure the transfer function of a plant in an open-

loop configuration. In some implementations, a chirped sine wave is used as the control input

of the plant and a cross-correlation or an FFT is used to identify the transfer function.

Another set of techniques configures the plant in closed-loop when identifying the optimal

control parameters. The second type of detection techniques is sometimes the preferred method

when locking the frequency of a laser or a cavity, because it is often the case that the laser or

cavity to be locked is not passively stable enough to allow a thorough open-loop investigation.

Despite the widespread use in other applications, the technique of plant detection in a closed-

loop configuration is not common practice in AMO experiments. The addition of closed-loop

plant detection would therefore be a valuable tool in an AMO researcher’s toolbox.

70

Chapter 4

Servo Performance and Intensity

Stabilization

The hardware design and the firmware design of the FPGA servo is discussed in previous

chapters. In both designs, the noise level and the delay of the servo are optimized for a better

closed-loop performance. This chapter focuses on the resulting closed-loop performance of the

FPGA servo with an emphasis on noise suppression.

For users only previously exposed to analog servos, the closed-loop performance of a digital

servo is not obvious. The signal quantization introduced by the ADC and DAC can be especially

worrisome. For example, the quantization level of the ADC used in the DE2 system is in theory

around 60 uV, with 14-bit resolution and an input range of 1 V peak-to-peak. This level of

correction isn’t acceptable for most applications, but in practice the computation precision

allows the servo to correct to level much lower than the quantization step of the ADC or the

DAC. Precision below the quantization step is the result of oversampling and signal averaging

and this has been reported in [14], [18].

In the following section, we describe various techniques that are useful in maximizing the

level of noise suppression in a closed-loop system. The closed-loop performance is investigated

with two setups, one with the FPGA servo forming a closed-loop system onto itself, referred

to as the “self-lock configuration” and the other with the FPGA servo installed in an intensity

stabilizing setup. The self-lock investigation focuses on exploring the limit of the FPGA servo

performance while the intensity stabilization setup focuses on demonstrating the additional

improvement that an FPGA servo can offer when compared to an analog servo.

71

4.1. Self Lock Benchmark

4.1 Self Lock Benchmark

The self-lock test is a convenient method for determining the performance limits of a servo.

When used in control applications, the self lock performance of the servo can be combined with

the noise floor and the bandwidth of the detector and the actuator to predict the closed-loop

performances in a specific application.

4.1.1 Locking Performance

Before using the FPGA servo in any application, it is necessary for the user to confirm that the

servo performs as expected. The self-lock test, illustrated in Figure 4.1, provides a convenient

benchmark. In the self-lock test shown in Figure 4.1, the FPGA servo is configured as a PII

controller with negative feedback and is configured with two corner frequencies at 200 kHz.

It is important to set the corner frequencies high to reveal the input noise of the servo for a

large range of frequencies but not too high to worsen the loop resonance. Here, the PI corner

frequencies (200 kHz) are set to be roughly a decade below the loop bandwidth (2-2.5 MHz)

of the servo. The typical input noise level of the servo and the bandwidth of the servo can be

observed from the data.

+ +

Servo

PI

Figure 4.1: The self-lock configuration is a closed-loop feedback system formed by the FPGAservo and no other detectors or actuators. This is a convenient method for evaluating theperformance of a servo.

The spectrum can be examined in two frequency ranges, for frequencies less than 200 kHz

where noise suppression is active, and for frequencies larger than 200 kHz where the noise

suppression is not effective. In the frequency range less than 200 kHz, the spectrum is limited

by the input noise of the servo, shown in the self-lock data in Figure 4.2 to be around 11 nV/√

Hz

for the DE3 prototype and around 25 nV/√

Hz for the DE2 prototype. In the high frequency

range, the frequency of the lowest resonance reveals the total delay of the servo, with the

72


following relationship.

fbandwidth =1

2Tlatency(4.1)

It can be observed from the data, that these two servo prototypes has a loop delay of 277 ns

and 227 ns respectively. Additionally, a small resonance can be observed at 200 kHz and it is

the closed-loop behaviour of two zeros place at the same frequency. This effect can be avoided

if the two zeros of the PII filter is spaced a decade apart.

101 102 103 104 105 106

Frequency (Hz)

-155

-150

-145

-140

-135

-130

-125

dBV

pp/r

t(H

z)

Noise spectral denisty, Self Lock

DE2 Prototype (PII), 200kHz, 200kHzDE3 Prototype (PII), 200kHz, 200kHz

Figure 4.2: The self lock data of the DE2 servo and the DE3 prototype servo. The minimumnoise floors of the two servos are -152 dBV/

√Hz and -159 dBV/

√Hz. They are equivalent

to 25 nV/√

Hz and 11 nV/√

Hz respectively. The self-lock spectrum is optimized according totechniques discussed in sections 4.1.3 - 4.1.6. Additionally, the origin of the spikes in frequenciesbetween 60 Hz and 40 kHz more visible on the DE2 spectrum is covered in Section 2.4.5.

We note that even without a spectrum analyser (eg SR780 and RSA3303A), it is possible

to check the performance of a servo in closed-loop. The delay of the servo can be investigated

by increasing the loop gain to purposely introduce an oscillation at the loop resonance. The

frequency of the oscillation follows the same relationship shown in Equation 4.1. With careful

planning, the noise floor of the servo can be investigated with an oscilloscope and analysed

73


either with a built-in FFT function on the scope or downloaded to a computer and analysed

off line. It is important to note the noise floor of the oscilloscope in this case, and it is possible

that only high resolution oscilloscopes with deep memory buffers are suitable for this task.

If the performance of the servo deviates from normal, then each circuit components can be

investigated further with information in the hardware and firmware chapter.

4.1.2 Noise Suppression

Before discussing the practical side of noise suppression, we will first discuss a theoretical model

for noise in a closed-loop control system. Figure 4.3 shows a schematic of the FPGA servo

configured in closed-loop, with the variable gain amplifiers modelled by frequency independent

gain factors G1 and G2 and with the offset circuit omitted. It is important to note that although

not shown in the diagram, other factors of amplification are present in the loop. Examples

include the logic gain, any fixed amplification or attenuation in the servo and amplification in

the actuator or the detector. These factors are not included in this model as they only clutter

the argument on noise suppression that is presented here. In a more general sense, G1 can be

regarded as the total gain between the input of the closed-loop system and the servo logic, and

G2 can be regarded as the total gain between the servo logic and the output of the closed-loop

system.

+-

+ + +ss+wPIG1 G2

N0 N1 N2 N3

PI=IN OUT

Figure 4.3: The model used for analysing the noise suppression in a closed-loop servo systembased on an FPGA servo. For a simpler analysis on noise suppression regarding gain distribu-tion, the non tunable gain in the circuit.

Noise sources N0, N1, N2 and N3 model noise introduced at different locations in the loop.

The output of the loop (including the contribution from each noise) has the following transfer

74


function.

OUT = ING1G2PI

1 +G1G2PI

+N0G1G2PI

1 +G1G2PI

+N1G2PI

1 +G1G2PI

+N2G2

1 +G1G2PI

+N31

1 +G1G2PI

(4.2)

The denominator for any of the terms in the transfer function remains the same regardless

of the location of the noise source, but the numerator of each term in the transfer function is

the forward path between the location of the noise and the output of the closed-loop system.

The transfer efficiency of the noise to the closed-loop output in two limits is summarized in

Table 4.1. Understanding the behaviour in the two limits helps with the interpretation of the

data and with identifying the location of the noise sources.

Table 4.1: The expected output noise from sources in the loop in two limits assuming G1G2 =0.5 and all other components in the loop have unity gain.

OUT=

ω ωPI ω ωPI

N0N0

3N1

G1

N1G2

1 +G1G2

0 ·N2N2G2

1 +G1G2

0 ·N3N3

3

The suppression of noise at frequencies ω >> ωPI is not complete regardless of where the

noise is injected into the loop. This is consistent with our empirical experience of a servo

having a limited bandwidth. In contrast, the noise level at frequencies ω << ωPI depends on

the location of the noise. Any noise introduced after the servo logic, whether it is N2 or N3,

is completely suppressed regardless of the loop gain. On the other hand, noise injected at the

input of the servo (N0), is written directly onto the output of the closed-loop system. This

75


means that the noise at the first stage of the servo is the most influential on the overall servo

performance. The noise N1 (injected after the variable input gain) has a transfer efficiency onto

the output of the closed-loop system that depends on the distribution of the gain inside the

loop. In particular, increasing the input gain G1 while keeping the product of G1G2 constant

decreases the transfer efficiency of N1 onto the output, at no cost to the other noise sources.

This means that increasing G1 while keeping G1G2 constant beneficial to the noise performance

of the closed-loop system, when N1 is substantial.

Equipped with these conclusions, we are able to continue the investigation in an informed

fashion. In the studies that follow, the effect of loop gain, corner frequency and gain distribution

on noise suppression is investigated.

4.1.3 Loop Gain

Based on empirical tuning experience, we know that there is an optimal loop gain for suppressing

noise. Figure 4.4 illustrates the behaviour of the noise spectrum when the loop gain is varied.

We observe an optimal loop gain of 0.5 (equivalent to G1G2 = 1.2 due to other factors for gain

in the loop) because when the gain is lowered the width of the suppression band shrinks, but

when gain is increased the height of the resonance due to loop delay increases. The loop delay

resonance is not visible in this plot as it is above 1 MHz. Nevertheless when the height of the

loop delay resonance increases, the peak-to-peak amplitude of the error signal also increases

until it exceeds the peak-to-peak range of the ADC. When the error signal exceeds the ADC

input range, the servo loop adds noise to the quantity being controlled rather than suppressing

it. As seen in Figure 4.4, the range of gain where the closed-loop controller switches from noise

suppression (at G1G2 = 1.2) to noise amplification (at G1G2 = 1.76) is small.

4.1.4 Corner Frequency

Similar to the effect of increasing the gain, increasing the corner frequency of the PI filter

widens the suppression band, as shown in Figure 4.5. The upper bound of the corner frequency

of the PI filter is limited by the bandwidth of the closed-loop. Because a PI filter introduces

a 90 degree phase delay in the output for frequencies ω << ωPI , when corner frequency is

too close to the bandwidth of the closed-loop, the delay introduced by the PI filter interacts

76


101 102 103 104 105

Frequency [Hz]

-140

-130

-120

-110

-100

-90

-80Noise Spectral Denisty, Scan Loop Gain, DE2 Prototype

G1=8, G

2=0.060

G1=8, G

2=0.085

G1=8, G

2=0.100

G1=8, G

2=0.150

G1=8, G

2=0.220

Figure 4.4: The effect of loop gain on noise suppression. As loop gain increases the width of thesuppression band also increases. However, once the amplitude of the loop delay resonance (atfrequencies above 1 MHz) exceed the input range of the ADC, the closed-loop system amplifiesrather suppresses noise.

with the bandwidth of the loop and exacerbates the loop delay resonance. A worse loop delay

resonance can cause the closed-loop system to amplify noise when the amplitude of the error

signal exceeds the ADC input as it is already seen in the case of an excessive loop gain in

Section 4.1.3. To avoid this issue, it is often safe to first set the corner frequency at a tenth of

the loop bandwidth and to then make fine adjustment to the corner frequency.

4.1.5 Gain Distribution

Input Gain vs Output Gain

Section 4.1.2 makes the argument that the gain distribution has an effect on the noise suppres-

sion through the evaluation of the transfer function of a closed-loop control system, and this

section presents data on this effect. Figure 4.6 shows a higher gain at the input of the servo (G1)

while keeping the total loop-gain constant improves the noise floor of the closed-loop system.

77


101 102 103 104 105

Frequency [Hz]

-140

-130

-120

-110

-100

-90

Noise Spectral Denisty, Scan Corner Frequency, DE2 Prototype

PII, 70kHz, 7kHzPII, 140kHz, 14kHz

Figure 4.5: The effect of corner frequency on noise suppression. As the corner frequencies ofthe PII filter increase the width of the suppression band also increases. The limitation of thisoptimization technique is covered in the text.

78


This behaviour indicates that the performance of the servo is limited by a noise source after the

variable gain amplifier (refer to Section 2.3.3 and Section 2.4.5 for details on the noise floor of

the FPGA servo hardware). Unfortunately, G1 cannot be increased indefinitely. As the input

gain G1 increases, the amplified error signal eventually becomes larger than the input range of

the ADC and causes the servo to lose lock. This gain distribution effect on the servo noise floor

is also present for an analog servo as well, but the FPGA servo needs special consideration due

to the limited the input range of an ADC compared to that of a standard opamp.

101 102 103 104 105

Frequency [Hz]

-140

-130

-120

-110

-100

-90

-80

Noise Spectral Denisty, Scan Gain Distribution, DE2 Prototype

G1=1, G

2=1.2

G1=2, G

2=0.6

G1=4, G

2=0.3

G1=8, G

2=0.15

Figure 4.6: The effect of G1 and G2 on noise suppression. When loop gain is kept constant, ahigher G1 leads to an improvement in noise suppression in frequencies where noise suppressionis limited by N1 (the ADC) in the noise model.

FPGA Gain vs Output Gain

Similar to the limitation of ADC range, the DAC is also limited and it needs sufficient amplifi-

cation to correct the noise in the system. As seen before, trading off output gain for input gain

improves noise performance; however, the actuation range of the closed-loop system is reduced

in the process and this in turn reduces the maximum amplitude that the system can correct

79


for. This scenario can be avoided by decreasing the gain through the FPGA logic rather than

at the variable gain stage following the DAC. Reducing the gain through the FPGA logic is

simpler with 32-bit IIR coefficients as the pole-zero resolution is high and a reduction of the

pole-zero resolution is unlikely to affect the ability of the system to lock. On the other hand,

reducing the gain through the FPGA is not as straightforward with 16-bit IIR coefficients as

the pole-zero resolution placement is already 7 kHz (details of this implementation is discussed

in Section 3.2.3). Figure 4.7 shows a scenario where the lock was able to suppress a higher level

of error when the FPGA gain is traded off for output gain.

101 102 103 104 105

Frequency [Hz]

-135

-130

-125

-120

-115

-110

-105

-100

-95

-90

-85Noise Spectral Denisty, Decrease Logic Gain, DE2 Prototype

max noise = 0.2Vpp, G1=4, G

L=1, G

2=0.3

max noise = 0.4Vpp, G1=4, G

L=0.5, G

2=0.6

Figure 4.7: The effect of G2 and logic gain on noise suppression. When loop gain and G1 arekept constant, decreasing gain through the servo logic in the FPGA and increasing G2 (thegain between the DAC and the servo output) increases the maximum amplitude of noise thatthe closed-loop system can correct.

4.1.6 The Optimal Strategy

Based on the study, we can conclude that the optimal tuning strategy is to choose the total loop

gain and the poles and the zeros suitable for the laser system and then redistribute the gain

within the servo for the optimal noise performance. (We follow this practice in the later stages

80

4.2. Intensity Lock

of this project.) The tuning example discussed is for a PI filter but all the same principles apply

for a different transfer function. Thus, compared to an analog servo, the FPGA servo has an

additional step of choosing the gain distribution. Here, the optimal distribution can be obtained

by first deciding on the output amplification needed to give the actuator a sufficient range and

then maximizing input amplification without letting the amplified error signal saturates the

ADC. The gain through the FPGA can then be used as a free parameter to keep loop-gain

constant.

The best experimental result for suppressing white noise with a 30 MHz bandwidth, as

shown already in Figure 4.7 is in excess of 40 dB. The suppression of single tone noise within

the suppression band can be much better and is estimated to be as high as 160 dB. This is

under the assumption that sufficient gain follows the DAC to amplify the correction to 10V

and the input gain is at least 8 to obtain a input noise floor of 100 nV/√

Hz. The difference

in the ability of a servo to suppress white noise and single-tone perturbation can illustrate the

constraints of a digital servo. In the case of white noise, a large band of the noise can not be

suppressed so the residual error is large which in turn limits the input gain. The single tone

perturbation is another extreme where the perturbation can be completely suppressed and little

residual noise is left to limit the input gain so the maximum perturbation that the servo can

suppress is set by the DAC range and the amplification that follows. A realistic application

will likely involve a noise spectrum somewhere between the two extremes, and either the ADC

range or the amplification after the DAC can be the limiting factor for the noise performance.

4.2 Intensity Lock

In this section, the FPGA servo system is applied to an intensity stabilization application. This

is a different application from the use of an FPGA to provide PDH based frequency control of

a laser previously demonstrated in various published works [9, 14]. The intensity stabilization

builds upon the FPGA servo discussed in previous sections, with the addition of intensity

modulation and measurement hardware. This section first covers the design of the hardware

and then describes some optimization techniques used to improved the closed-loop performance

of the intensity stabilization system.

81

4.2. Intensity Lock

This study also focuses on demonstrating the performance of the FPGA servo in comparison

to and beyond that of a high-performance analog servo. The ease for such improvement on the

same piece of hardware is all thanks to the ease of reprogramming the FPGA and its ability to

emulate complex transfer functions. Three servos, the Vescent D2-125, the DE2 servo prototype

and the DE3 servo prototype are used to make the baseline comparison. The DE2 prototype

is equipped with a 16-bit IIR and the DE3 prototype is equipped with a 32-bit IIR (refer to

Chapter 3 for details on IIR implementation). Two aspects of the servo performance can be

observed from the study. First, the two servos have similar noise floors at the highest gain

setting, both are in the 10 nV/√

Hz range. Secondly, the bandwidth of the closed-loop system

is dominated by the intensity control hardware (i.e. the plant) with a delay of 400 ns, making

the bandwidth difference of the analog servo (at 10 MHz) and that of the FPGA servo (2.5

MHz) less consequential.

4.2.1 Motivation

The shot-to-shot variation between experimental cycles in a scientific investigation often directly

affects the quality of the result. The laser intensity is a factor that can affect a cold-atom

experiment in many stages, including changing the the population of the initial atomic sample,

changing the AC Stark shift relevant for spectroscopy and changing the exposure intensity of

atom cloud during absorption imaging [42]. The dependence of cold-atom experiments on this

quality makes active stabilization of intensity a viable route in making the experiments robust.

The hardware developed under the umbrella of intensity stabilization has another use and

that is intensity modulation. Wide bandwidth modulation of intensity also has use in cold

atom experiments. Example applications include dynamic formation of dipole trap [43] and

transformation of the internal quantum state population [44].

4.2.2 A Note About Noise Units

In previous sections, the electronic noise level of the servo and the associated electronics is

evaluated in nV/√

Hz. In this section, the intensity stability of the laser is evaluated in

82

4.2. Intensity Lock

Relative Intensity Noise (RIN), with the following relationship.

RIN =

⟨∆P (t)2

⟩P 2

0

(4.3)

Here, P is the laser power and the square of which (intensity) is proportional to the detected

electrical power, PE , at a photodetector [45]. This gives rise to the expression for RIN as the

following.

RIN =∆PEPE0

=(VAC)2

(VDC)2(4.4)

Here, the direct observables VAC and VDC can be obtained from an Electrical Spectrum Analyzer

(ESA) and an multimeter respectively.

Here, the RIN is an evaluation of the closed-loop intensity stabilization system rather than

the just the servo alone. This means that the conversion from servo noise floor to RIN of the

laser highly depends on the noise floor of the detector and the amount of light being detected.

The implementation detail of this intensity stabilization system is covered in the following

section.

4.2.3 Implementation

Intensity stabilization is achieved with an AOM driven by a Radio Frequency (RF) source with

a variable power and a Si biased amplified photodetector. The AOM allows manipulation of

laser intensity by splitting the beam with a variable diffraction efficiency controlled by the RF

power sent to the AOM. The latency of the AOM depends on the proximity of the laser beam

with respect to the piezo element that creates the moving diffraction pattern in the crystal

and is typically in the 200-400 ns range. The Si detectors used are the Thorlabs DET10A

photodetector and the Hamamatsu S5971 Si photodiode biased with well regulated 5 V. The

DET10A and the S5971 detectors respectively have the Noise-Equivalent Power (NEP) of 1.2×

10−13 W/√

Hz and 7.4× 10−15 W/√

Hz and bandwidth of 350 MHz (calculated from the rise-

time of 1ns) and 100 MHz.

For a more thorough study, additional intensity noise is injected into the system via a second

AOM whose RF power is modulated by a VGA driven by a DS345 function generator that is

83

4.2. Intensity Lock

configured to generate white noise with bandwidth of 30 MHz. The system that artificially

injects intensity noise resembles a laser with an inherent noise of the same level. It may be

counter-intuitive at first, but the latency through the noise injection AOM and the location

where the noise is injected (before or after the correction AOM) does not affect the noise

suppressing capability of the system.

AO

M 1

ServoA

OM

2

Noise

RF 1 VAtt 1 RF 2 VAtt 2 PD 1 PD 2

Figure 4.8: The opto-electrical system used to study intensity stabilization. The intensitystabilization consists of a RF source (RF1), a variable attenuator (VAtt1), an AOM (AOM1),a photo-detector (PD1) and an analog or an FPGA servo. To study the performance of theintensity stabilization system on various level and type of intensity noise, a noise modulationsystem is constructed from a RF source (RF2), a variable attenuator (VAtt2), an AOM (AOM2)and a noise generator. Finally, the out-of-loop detection of intensity noise of the system isaccomplished via a second photo-detector (PD2).

Actuator

The AOM is a diffraction device with a diffraction grating dynamically formed inside an acousto-

optical material by a compression wave. The compression wave is generated by a piezo mounted

at one end of the crystal and travels at the speed of sound. The piezo is often driven from an

RF source through an Inductor-Capacitor (LC) resonator. At different RF power levels, the

compression wave forms diffraction grating of different contrast in the crystal.

The RF power is controlled using a fast analog switch based on the MAAVSS0006, which

is only available as a single IC. For this work we designed a PCB with coaxial connectors as

the interface to the IC. The core schematic of the design is shown in Figure 4.9 with additional

84

4.2. Intensity Lock

details in Appendix B.

Figure 4.10 shows the relationship between the control voltage and the transmission effi-

ciency. This analog RF switch can only accept a rather low input power (10 dBm), so it is often

the first component in the RF amplification chain. A few observations can be made from the

data in Figure 4.10. For example, the leakage when the switch is off, typically in the -60 dB to

-80 dB range, suggests the need for a mechanical shutter when the light level must be fully off.

In addition, we observe variation between devices, suggesting that calibration maybe needed for

each device. Finally, we note that the transition between on and off is not linear but appears to

be roughly linear in dB in the transition region. This means that the closed-loop system using

this intensity modulator may not maintain a constant gain for all set points and open-loop use

of this modulator may need special consideration on the nonlinearity of the modulator.

In this design of an analog RF switch, speed is a major consideration. The variable atten-

uator is chosen for the fast rise and fall time specified to be 10 ns in the datasheet [46]. Since

the variable attenuator is to be used as part of an intensity modulator, its transfer function is

evaluated. The transfer function shown in Figure 4.10 shows the performance of the analog RF

switch together with an AOM. In this particular case, the transfer function has modulation

bandwidth of 3 MHz, and a latency of about 400 ns observed from the phase response plot. In

the case of the latency, the time it takes the compression wave to travel to the laser beam is

the dominant source of delay with every 1 mm of distance between the laser beam to the piezo

driver costing about 230 ns (calculated from the speed of sound in Tellurium Dioxide (TeO2)

[47]). The latency time causes the closed-loop bandwidth of an intensity stabilization scheme

with AOM to be limited to about 1 MHz, although the modulation (open-loop) bandwidth is

much higher. The modulation bandwidth of 3 MHz shown in this transfer function data is

likely the result of the finite beam size coupled with the speed of sound in the crystal. We note

that these data were taken with an OP37 opamp in the which was subsequently replaced with

AD829 with a faster response. The AD829 was observed to have a bandwidth of 90 MHz. It

would be interesting to see if the modulation bandwidth increases from this change.

With use in closed-loop, some optimization is done to reduce the total loop latency. Besides

placing the focus of the laser beam close to the piezo driver, the BNC cable lengths are minimized

and this led to a small reduction in delay.

85

4.2. Intensity Lock

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A

Date: 2016-10-25 Sheet ofFile: C:\Users\..\VAtt_diagram.SchDoc Drawn By:

R3

1k

R2

1k

R510k

GND

15V

-15V GND GNDRFIN1

GND 2

RFOUT 3

GND4

VC5MAAVSS0006

100pFC13

GND7pF

C15

R1

4k

0.1uFC17

GND

2

36

5COMP

AD829JR

RF IN RF OUT

VCTRL

PIC1301

PIC1302COC13

PIC1501PIC1502

COC15PIC1701

PIC1702COC17

PIR101PIR102

COR1PIR201PIR202

COR2

PIR301 PIR302

COR3

PIR50CCW

PIR50CWPIR50W

COR5

PIU201

PIU202

PIU203

PIU204

PIU205

COU2PIU?02

PIU?03

PIU?05

PIU?06

COU?

PORF IN PORF OUT

POVCTRL

Figure 4.9: Diagram of the variable attenuator circuit with the AD829 configured in currentcompensation mode. A snapshot of the layout and additional details can be found in AppendixB.

0 0.2 0.4 0.6 0.8 1 1.2 1.4 1.6 1.8 2

Control Voltage, V

-90

-80

-70

-60

-50

-40

-30

-20

-10

0

RF

Tra

nsm

issi

on, d

B

Transmission vs Control Voltage

VR1

VR2

VR3

VR4

VR5

VR6

VR7

Figure 4.10: Control voltage versus transmission through the variable attenuator. It is impor-tant to note the variation in the response to input voltage and in maximum RF suppression.

86

4.2. Intensity Lock

-15

-10

-5

0

Mag

nitu

de, d

B

AOM-Based Intensity Actuator, Transfer Function

102 103 104 105 106

Frequency, Hz

-360

-270

-180

-90

0P

hase

, deg

ree

Figure 4.11: Transfer function of the variable attenuator + AOM + PD system. The loopdelay is about 400 ns. As the delay is dominated by the distance between the laser beamand the ultrasonic source in the AOM, this delay is modified at various point of the intensitystabilization study due to small positional changes but is kept to a range of 200-400 ns. Themodulation bandwidth is in excess of 3 MHz. This opens up the use of this system in highspeed intensity modulation.

Detector

As the interpretation of the closed-loop transfer function in Section 4.1.2 shows, the noise floor

of the closed-loop system, especially at low frequencies is highly dependent on the noise level

of the first stage. This means that the noise level of the detector sets the lower bound on

the closed-loop performance. The intensity stability achieved by this work is the result of

optimizations made to reduce the noise level of the detector as much as possible.

The major contributor of noises at the detector is the electronic/photon shot noise, the

thermal noise of the charge carriers, the op-amp flicker noise often referred to as the 1/f or pink

noise, and the easily over-looked power supply noise that often couples into electronic circuits.

The shot noise expressed for electricity

⟨i2⟩

= 2eI∆f (4.5)

where e is elementary charge and ∆f is bandwidth, is hard to work around without increasing

87

4.2. Intensity Lock

the intensity of indecent light onto a photo-detector, as the shot-noise is the by-product of the

particle-like property of both the electronics and photons and is proportional to square root

of the number of particles. Once the intensity is fixed, the impedance that is driven by the

photodetector (modelled as a variable current source) and the gain after the photodetector are

both free design parameters that affect the SNR of the detector. An excellent source on design

principles can be found here [48]. In the work conducted here, the noise floor of the detector

is much lower than the noise floor of the servo, with detector noise floor at the 1 nV/√

Hz

level (assuming 1 mA average photocurrent and 50 Ω impedance). This suggest that additional

gain at or after the detector can improve the overall performance, by a factor of 100 until the

photon/electronic shot noise becomes the limiting factor.

Another technique for identifying noise sources is to apply the characteristic shape of the

noise spectrum of various noise type. This is a useful technique when the only direct observable

is the spectrum of the noise from an ESA. For example, both shot noise and thermal noise are

constant in frequencies[49]. The op-amp flicker noise or the 1/f has a slope of -20 dB/decade

at low frequency [50, p.84]. Noise with any other characteristic shapes whether is it is in the

form of spikes or a broad spectrum are likely a result of poor practice in the form of improper

ground, noisy power supply or inadequate shielding of signals.

In the implementation scheme shown in Figure 4.8, intensity is monitored by two photode-

tectors with only one detector in the feedback loop of the system. This technique is often

referred to as out-of-loop detection, and it is helpful for detecting whether the noise floor of the

detector is higher than the servo. When adding the out-of-loop detection, we focus the laser

beam onto both detectors and keep the path difference minimal. The in-loop spectrum looks

identical to the out-of-loop spectrum, but to eliminate differences at low frequencies, we found

it necessary to reduce the air circulation near the detectors.

4.2.4 PII Comparison

In comparing the performance of the FPGA servo against analog servos, we use a well-reputed

commercial analog servo by Vescent as a benchmark (D2-125). For this comparison, the FPGA

servo needed to work within the constraints set by the analog servo. The D2-125 model by

Vescent, implements a Proportional double-Integral and Derivative (PIID) with configurable

88

4.2. Intensity Lock

corner frequencies.

In the interest of fairness in comparing the three servos, the total loop gain of each closed-

loop system is kept the same after we determined the optimal loop gain. The corner frequencies

of the servos are chosen according to the loop delay of each system. In the case of the Vescent

servo, with the higher servo bandwidth of 10 MHz, a higher corner frequency at 100 kHz is

possible without worsening the oscillation at the loop delay resonance. In the FPGA servo,

with a lower servo bandwidth of 2.5 MHz, a corner frequency of 70 kHz is chosen due to the

higher loop latency. As it can be observed in Figure 4.12, the width of the suppression band is

not substantially different between the systems formed by different servos, since the latency of

the AOM is the limiting factor to the closed-loop performance.

10 1 10 2 10 3 10 4 10 5 10 6

Frequency (Hz)

-130

-120

-110

-100

-90

-80

Rel

ativ

e In

tens

ity N

oise

(dB

c/H

z)

Noise spectral denisty, Baseline Comparison PII

DE2 (PII), 70kHz, 7kHzDE3 (PII), 70kHz, 7kHzVescent (PII), 100kHz, 10kHz

Figure 4.12: Alternative baseline comparison of DE2, DE3 and Vescent servo for the intensitystabilization study. All servos realize a PII transfer function to match Vescent. The gain andcorner frequencies of all servos are tuned to optimize the noise suppression. The origin of thespikes in frequencies between 60 Hz and 40 kHz visible on the DE2 spectrum is covered inSection 2.4.5.

To complete the controller’s transfer function, the corner frequency for the second integrator

is chosen to be a decade below the corner frequency of the first PI. This was done because

89

4.2. Intensity Lock

when two zeros are too close in frequency, the closed-loop system pushes the zeros away from

the real axis in the s-domain (this can be observed in a root locus diagram) and this can result

in oscillation. The contribution of the derivative component is not studied here and and thus

was not enabled.

The spectrum shows that the FPGA and the Vescent servo have similar noise floors of

roughly 10 nV/√

Hz at 1 kHz. With the exception of the small difference in the frequencies of

the loop resonances, the noise spectrum capability of the two types of servo is nearly identical.

This is not surprising as similar transfer function are implemented in the servos.

4.2.5 PI3 Improvement

As a natural extension of the PII servo, a PI3 (3 integrator in cascade) was attempted on the

intensity stabilization system. This is accomplished by cascading three IIR filters in the FPGA

servo, all configured as integrators. The difference between the PII filter and the PI3, shown in

Figure 4.13 is that it widens the suppression band without adding oscillation at the loop delay

resonance. This is an example of a filter that cannot be easily implemented in an analog servo

without additional hardware.

4.2.6 PII + Lag-Lead Improvement

The lag-lead filter is another example of a filter that can not be easily implemented in an analog

servo. Unlike the PI3 filter, which can still be constructed by chaining multiple existing analog

servos, the lag-lead filter is impractical to implement as an analog circuit due to its large number

of tunable poles and zeros.

The lag-lead filter is effectively a notch filter composed of two poles and two zeros. Similar

to the lead-lag filter (a bandpass filter), the lag-lead filter can be introduced into a transfer

function to modify the transfer function locally, as illustrated by their transfer functions shown

in Figure 4.14. The lag-lead filter can be used to suppress loop resonance when implemented

with a center frequency that is the same as the frequency of the loop resonance. Because the

lag-lead filter reduces the gain locally at the loop resonance, the amplitude of the loop oscillation

is reduced. Another benefit of a notch filter (the lag-lead filter) at loop resonance is to allow

the loop gain to be increased and thus results in a wider suppression band for noise. Both

90

4.2. Intensity Lock

10 1 10 2 10 3 10 4 10 5 10 6

Frequency (Hz)

-110

-105

-100

-95

-90

-85

-80

-75

Rel

ativ

e In

tens

ity N

oise

(dB

c/H

z)

Noise spectral denisty, PI3

DE3 (PII), 70kHz, 70kHzDE3 (PI3), 70kHz, 70kHz, 70kHz

Figure 4.13: Demonstration of the DE3’s ability to implement an additional integrator andits effect on noise suppression. The corner frequency of 70 kHz is used for all 3 poles. Thesuppression slope changes from 40 dB/decade to 60 dB/decade as expected.

effects are illustrated in Figure 4.14, where the DE3 prototype servo with 32-bit IIR coefficient

implements a PII + lag-lead filter with total latency of about 200 ns.

The lag-lead filter and the PI3 are merely examples of advanced servo transfer function that

an FPGA servo can implement without costing hardware development time or servo perfor-

mance. This also means that the use of FPGA servo can lower the barrier for exploring the use

of advanced servo transfer function for the use in laser control. Despite of the added flexibility

in implementing servo transfer functions, it is still important to keep in mind at additional

servo gain is only beneficial at frequencies where the noise floor of the servo is not a limiting

factor. That is to say that noise suppression is still fundamentally limited by the input noise

of the servo.

91

4.2. Intensity Lock

1

2

3

4

Am

p (d

B)

Lead-lag Transfer Function

105 106 107 108

Frequency (kHz)

-15

-10

-5

0

5

10

15P

hase

(de

gree

)

-4

-3

-2

-1

Am

p (d

B)

Lag-lead Transfer Function

105 106 107 108

Frequency (kHz)

-15

-10

-5

0

5

10

15

Pha

se (

degr

ee)

Figure 4.14: The transfer function of the lead-lag and the lag-lead filer with center frequencyat 1 MHz and a bandwidth of 1.5 MHz. The lead-lag filter is composed of zeros at 250 kHz and4 MHz and poles at 500 kHz and 2 MHz. The lag-lead filter is composed of zeros at 500 kHzand 2 MHz and poles are 250 kHz and 4 MHz.

10 1 10 2 10 3 10 4 10 5 10 6

Frequency (Hz)

-115

-110

-105

-100

-95

-90

-85

-80

-75

Rel

ativ

e In

tens

ity N

oise

(dB

c/H

z)

Noise spectral denisty, PII+Lag-lead

DE3 (PII), 70kHz, 7kHzDE3 (PII+LL), 70kHz, 7kHzDE3 (PII+LL+Gain), 70kHz, 7kHz

Figure 4.15: Demonstration of the DE3’s ability to implement lag-lead filter at center frequencyof 700 kHz. The lag-lead filter has two effects 1) suppression of loop resonance of the servosystem 2) allowing increase in gain and thus widening of the noise suppression band

92

4.3. Conclusion

4.3 Conclusion

The most intriguing conclusion drawn from the study covered in this chapter is the similar in

performance of the analog servo and the FPGA servos when configured in closed-loop (Section

4.2.4). Specifically, when the analog servo and the FPGA servo are configured with similar

transfer functions, both as PII filters, the closed-loop performance does not show substantial

differences in either noise suppression or the frequencies of the loop resonance. The similarity

in loop resonance is a result of the plant being a substantial source of delay in the closed-loop

system and the similarity in noise floor is a result of carefully design circuits with detailed

consideration in noise reduction already covered in Chapter 2.

The work by this chapter demonstrates the versatility of an FPGA servo and its ability to

form advanced transfer functions. The implementation of advanced transfer function an FPGA

servo is suggested by a few published work as a potential benefit this new technology [14], but

this work is the first to demonstrate the use of advanced transfer functions in the form of PI3

and PII+lag-lead in an FPGA servo (Section 4.2.5 - 4.2.6). We are able to show the benefit

of these advanced transfer functions in widening the noise suppression band beyond what was

demonstrated with PII, which is considered a benchmark in this study.

Another contribution covered in this chapter is the summary of the tuning techniques needed

to work with an FPGA and how the techniques differ from working with an analog servo (Section

4.1). The study shows that tuning parameters like loop gain and frequencies of the poles and

zeros affect the closed-loop transfer function of the FPGA servo similarly to its effect on the

anlog servo. In comparison to the analog servo, the FPGA servo has a stronger dependence on

gain distribution as the system is limited by the noise floor at the ADC and the output range

of the DAC. The work summarize a strategy for the optimal gain distribution when using an

FPGA servo (Section 4.1.6), where the user must be careful to avoid the signals from exceeding

the range of the ADC or the DAC at any time.

93

Chapter 5

Case Study: Evaporation in a Dipole

Trap

Previous chapters describe the design of a high-performance FPGA servo and the evaluation

of its performance in closed-loop. As a natural extension to the work described so far, we look

into using the FPGA-based system to improve existing experiments. In this case study, we

investigate in the relationship between the active stabilization of the laser intensity and the

evaporation efficiency in a dipole trap. This case study demonstrates the use of an FPGA

servo in the intensity stabilization of lasers and shows that its use is not limited to frequency or

phase stabilization (as demonstrated in various published work [8], [14]). This chapter starts by

motivating the importance of laser intensity in a dipole trap and eventually reach the conclusion

of whether active intensity stabilization is a suitable solution to improving evaporation efficiency.

5.1 Motivation and Background

Optical-only traps with wavelength far detuned from the cooling transitions of Alkali atoms

have long been used to trap and cool neutral atoms to study the dynamics of atomic clouds

at temperatures under the micro Kelvin level [51]. At the Quantum Degenerate Gas (QDG)

laboratory, an dipole trap is used to perform a second cooling stage to create ultra-cold Li or

Li+Rb atomic mixtures, and it is preceded by loading and cooling of neutral Li and/or Rb

atoms in a Magneto-Optical Trap (MOT) [52], [53]. The dipole trap is generated by focusing

the output of a 1090 nm, 100 W fiber laser onto the atoms, and it is responsible for evaporatively

cooling the atom cloud further and confining the cloud for scientific investigation. The final

stage of each experiment is the absorption imaging of the atomic cloud with a small amount of

on resonance light, which captures the atom number and the physical distribution of the atoms

94

5.2. Dipole Trap and Trap Frequency

and provides clues as to what happened during the experiment.

The purpose of this investigation of evaporative cooling of Li in a dipole trap is to improve

the evaporation efficiency since this will increase the number of atoms available for the ex-

periments. A higher atom population has many benefits. Examples include a higher quality

absorption image due to a higher signal to noise and a better evaporation efficiency of an atomic

mixture (Li and Rb for example) where Li acts as the sympathetic coolant [54]. Prior to this

study, the atoms undergo a transfer from a D2 MOT to a high power dipole trap formed by

a 100 W multimode fiber laser (SPI SP-100C-0013), and then another transfer to a low power

dipole trap formed by a 20 W single mode fiber laser (IPG YLR-20-1064-LP-SF). The transfer

is necessary because the 100 W SPI laser lacks the intensity stability to cool the Li cloud below

temperatures of 1 uK, and the 20 W IPG laser is not powerful enough to allow a direct transfer

to it from the D2 MOT. This study investigates the stability issues in the 100 W SPI laser and

aims to minimize the atom losses due to transfer between the two dipole traps.

5.2 Dipole Trap and Trap Frequency

Improving the evaporation efficiency starts with a basic understanding of dipole traps. Although

detailed reviews of dipole traps can be found in various published work [55], this thesis provides

a condensed overview that covers the basic concepts needed for investigating issues related

to evaporation efficiency. One concept is the approximation of the profile of a dipole trap

as a harmonic potential, which has constant spacing between adjacent energy levels. This

approximation is good for atoms with very low energy as they only explore the bottom of

the Gaussian shaped potential which is very nearly harmonic. Here the energy spacing is

characterized by the harmonic trap frequency, and the atoms are most sensitive to perturbations

at this frequency.

The trapping potential produced by a focused laser beam is proportional to the intensity.

The profile of a focused Gaussian beam is illustrated in Figure 5.1 (left) and it has the following

expression.

I = I0e− 2x2

w(z)2 (5.1)

95

5.2. Dipole Trap and Trap Frequency

Here I0 is the peak intensity, z is the position on the propagating axis of the laser and x is the

position on an axis perpendicular to the propagation axis of the laser. The parameter w(z) is

the width of the Gaussian profile as a function of z position with the following expression.

w(z) = w0

√1 +

(z

zR

)2

(5.2)

The interaction between the light field and neutral atoms depends on the wave length of the

light field and the atomic transitions available in the atoms. Fine structures aside, the single

valence electron in an 6Li atom can make transition between the ground state 1s22s1 and the

excited state 1s22p1 with light at 671 nm. Both the SPI laser and IPG laser with respective

central wavelengths of 1091 nm and 1065 nm are far-red-detuned from the transition and form

attractive potentials for the atoms.

The attractive energy potential has the profile of the following

U ∝ I ∼ U0e− 2x2

w(z)2 , w(z) = w0

√1 +

(z

zR

)2

(5.3)

When only considering radial motion at the beam waist, this expression can be converted into

the following by applying Taylor expansion.

U ∼ U0(1− 2x2

w20

+4x4

w40

) (5.4)

After dropping the higher order terms in the Taylor expansion, the energy potential can be

approximated as a harmonic potential with the following expression,

U = U02x2

w20

(5.5)

which is harmonic and therefore has evenly spaced energy levels. This approximation is illus-

trated in Figure 5.1 (middle). This means that trapped atoms can be excited by a perturbation

(acting on their positional degree of freedom) at this frequency and move up the ladder of

energies leading to heating of the ensemble and eventually loss of particles from the trap. The

96

5.3. Loss Mechanisms

spacing between energy level has the following expression,

∆U = h

√4U0

mw0(5.6)

which can be characterized by the following

ωr =

√4U0

mw0(5.7)

referred to as the trap frequency. Here, the subscript “r” refers to the radial axis of the laser.

The same second order approximation can be applied to the propagating axis, z, with the

following expression,

ωa =

√4U0

mzR(5.8)

where the characteristic length scale, rather than the width of the beam waist, is the Rayleigh

length. The ensemble temperature is sensitive to perturbations at or near these frequencies. In

our experiments, we also use a crossed beam geometry, as illustrated in Figure 5.1 where the

trap frequencies are determined by the combined potential of the two beams.

x

zx

ωr

ωa x'

z'

Figure 5.1: Side view of a focused Gaussian beam (left), the Gaussian-shaped potential, in thecross section (middle) often approximated as a harmonic potential in the deep trap limit andthe top view of crossed focused beam (right).

5.3 Loss Mechanisms

A commonly used cooling technique in an optical dipole trap is so-called forced evaporative

cooling where the potential of the trap is lowered slowly by decreasing the beam intensity

forcing the hottest atoms to escape and leaving behind a cooler sample after the ensemble has

97

5.3. Loss Mechanisms

re-thermalized. In this process, not all atoms that started in the dipole trap remain. As shown

by OHara et al [56], [57], when the re-thermalization timescale is very rapid, the evaporation is

efficient and the ensemble temperature closely tracks the trap depth. In this case, the ratio of

the trap depth to the temperature U/kT = η is typically of the order η = 10 and the number

of atoms in the trap follows the following scaling law.

N

Ni=( UUi

)3/[2(η−3)]=( UUi

)0.22(5.9)

Here, Ui and U are the depth of the initial and the final trap potential and the Ni and N are

respectively the initial and final population. A detailed discussion of the efficiency of the force

evaporative cooling is provided by the work of OHara at el [56] [57].

With the knowledge of the achievable efficiency of a force evaporation routine, it was sur-

prising to see the evaporation efficiency of 6Li in the 100 W SPI laser drastically deviate from

the scaling law in trap less than 10 W in power. Some detective work went into debugging this

problem. The investigation is based on an understanding of various loss mechanisms that can

lead to a loss of atoms in a dipole trap.

5.3.1 Background Scattering

Trap loss can be caused by collisions with residual particles in the vacuum. It is somewhat

surprising that collisions with these room temperature particles can sometimes be soft enough

to leave the trapped particles in the trap but with a higher kinetic energy. Both loss and

heating of the ensemble reduce the efficiency of evaporation. However, in our case, we observed

efficient evaporation in the 20 W IPG laser. To completely rule out background collisions as the

problem, we measured the loss rates in both dipole traps at different laser powers to confirm

that the poor SPI evaporation was not the result of a poor vacuum in our experiment.

5.3.2 Loss Due to Resonant Scattering

With background scattering eliminated as a possible cause, the next possible cause evaluated

was the loss of atom due to spectral components close to Li6 D2 line in the SPI. Off resonant

scattering was ruled out since the evaporation in the IPG laser at similar powers was better

98

5.4. Study

and its operation wavelength is actually closer to the D2 line at 671nm. The SPI laser was

found to have no significant spectral power near 671 nm on an optical spectrum analyzer Ando

Q6315. These observations lower the likelihood of resonant scattering as a possible cause. These

observations lower the likelihood of optical pumping as a possible cause.

5.3.3 Parametric Heating

With the first two candidates deemed unlikely causes, the final candidate is the stability of

the laser itself. The work by Savard at el categorized stability of a dipole trap into two types,

the pointing stability which affects the physical location of the trap and the intensity stability

which affects the depth of the trap and the trap frequencies [58]. Both types of instability,

when oscillating on similar time scales as the trap frequency, are able to excite trapped atoms

to higher energies leading to ensemble heating and, eventually, to trap loss. In our experiment,

the pointing stability of the SPI is carefully handled with the use of a CNC-machined fiber-

mounts from solid stainless steel, weighted mechanical posts and stable commercial mirror

mounts. This leaves the intensity noise of the SPI laser the only remaining and a highly likely

cause of the evaporation issue.

5.4 Study

As a starting point for this study, we note that it was shown by Savard et al [58] that the

heating rate of a trapped atomic ensemble is related to the intensity noise of the trap laser by

the following expression.

Γε = π2υ2trapSε(2υtrap) (5.10)

Here Γε is the e-folding time of temperature in the trap due to intensity noise in the laser. It

is related to the value of the trap frequency and the one-sided power spectrum of the relative

intensity noise at twice of the trap frequency. This relationship allows us to make the connection

between intensity noise of the laser (in RIN) and heating rate.

99

5.4. Study

5.4.1 Heating Rate of Existing Trap

The heating rate of the trapped ensemble can be characterized by measuring the temperature

after various hold times. The ensemble temperature is measured using a Time-of-Flight (TOF)

method, where the atom cloud is allowed to expand in free space for some time, and the cloud

size after expansion (i.e. the speed of the expansion) provides a measure of the average kinetic

energy at the beginning of the expansion and in turn the average temperature [42]. The heating

rate measurement is therefore a series of TOF measurements after the atom cloud is held in the

dipole trap for different times. The heating rate measurement is therefore more time-consuming

than a loss rate measurement, but the heating rate measurement gives more insight into the

evolution of the ensemble over time.

As shown in Figure 5.2, the temperature of a 6Li cloud is shown for different hold times

in the SPI laser trap at 10 W, corresponding to the power where the evaporation efficiency

was observed to be poor. The data is consistent with an exponential increase in the cloud

temperature with an e-folding time of 1.9 s. With the knowledge of the e-folding time, and the

relationship between the laser intensity noise and heating rate in Equation 5.10, it is possible

to infer the level of intensity noise that would be responsible for the heating rate. Figure 5.2

shows a measurement of the intensity noise of the SPI laser at a similar output power, and

the noise level is consistent with an e-folding time of 1.9 s. The intensity noise of the laser at

similar power can be seen in Figure 5.2, to be in similar level as what would be responsible for

a e-folding time of 1.9 s. The trap frequency is estimated to be 5 kHz in the axial direction and

1 kHz in the radial direction.

While this agreement is evidence that the problem is related to the intensity noise, we need

to confirm that reducing the intensity noise of the SPI actually leads to a lower heating and

loss rates.

5.4.2 The Effect of Intensity Stabilization

In order to check if a reduction in the intensity noise reduces the atom loss during evaporation

due to heating, we used the active intensity stabilization system presented in Chapter 4 to

reduce the intensity noise. This involved using an AOM together with the FPGA servo. The

100

5.4. Study

0 0.5 1 1.5

time (s)

100

120

140

160

180

200

220

240

260

280

tem

pera

ture

(uK

)

Heating Rate in SPI at cross trap (10W set power)

temperature at 10W (TOF)exponential fit

Figure 5.2: heating rate of the atom cloud when SPI held at 10W. The heating rate correspondto a e-folding time of 1.9 s. this is also a screenshot not a proper plot

analog signal previously used to control the SPI power output was used as the setpoint for the

FPGA servo.

The effect of the active stabilization on the intensity noise can be seen in Figure 5.3. The

active intensity stabilization has a finite bandwidth, but it is able to suppress the intensity

noise at the trap frequency to a much lower level. To investigate how the evaporation efficiency

changes as a result, a forced evaporation routine was developed to compare the evaporation

with and without active stabilization. The evaporation efficiency both with and without active

stabilization was independently optimized by choosing the durations of a set of piecewise linear

ramps that optimized each linear stage in which the laser power dropped by a factor of 2.

This crude optimization method was employed to perform a quick check to determine if active

stabilization had any effect on the evaporation efficiency.

The evaporation efficiency of the free-running SPI laser and the SPI laser with noise sup-

pression is shown in Figure 5.4. The predicted number versus final power (given in Eqn. 5.9) for

an efficient evaporation (η = 10) is included in this plot for reference. The active stabilization

is observed to provide a slight improvement in atom numbers down to 12 W, but the efficiency

drops sharply compared to the unstabilized case for powers below 10 W. This drop was not

further investigated but may have been due to an instability in the servo at lower setpoints or

101

5.4. Study

10 1 10 2 10 3 10 4 10 5

Frequency (Hz)

-5.5

-5

-4.5

-4

-3.5

-3

-2.5

-2

-1.5

-1

-0.5

Rel

ativ

e In

tens

ity N

oise

, log

10

SPI RIN at 5W and TOF at 10W

passive noiseactiveHeating, temperature e folding time = 10 sHeating, temperature e folding time = 1 sHeating, temperature e folding time = 0.1 sTOF measurement at 10 W (radial)TOF measurement at 10 W (axial)

Figure 5.3: Side by side comparison of RIN level responsible for measured heating rate andRIN of laser. The constant heating rate line show 20 dB/decade slope. It appears that activeintensity stabilization should reduce heating rate.

due to noise features near to the trap frequency below 10 W not being evident in Figure 5.3

since this was an in-loop rather than an out-of-loop measurement

We are not able to show whether active intensity stabilization with AOM is is sufficient

at improvement evaporation efficiency. because the study opt for a simpler method to reduce

intensity noise once the method is revealed. We speculate that the effect of active intensity sta-

bilization is not necessarily thoroughly monitored during the experiment as the noise spectrum

of the laser is taken at a single power with an in-loop measurement rather than an out-of-loop

measurement at multipler power setting.

5.4.3 Passive Stability

In investigating the intensity stability of the 100 W SPI laser, we found that the passive stability

of the SPI laser is better at high power setpoints. With the use of the SR780 VNA and the

DET10A photodetector, the intensity noise measurement of the SPI laser is taken at various

power settings between 1 W and 100 W. The results are shown in Figure 5.5 and reveal that

this laser exhibits a relatively low RIN at high power setpoints and a much higher RIN at low

powers. The data revealed a much more simple remedy to fix the evaporation efficiency. The

102

5.4. Study

10 0 10 1 10 2

SPI Set Power, (W)

10 -1

10 0

Nor

mal

ized

Ato

m N

umbe

r

Forced Evaporation in Dipole Trap with Intensity Stabilization

2 = 10With IntensityStabilizationWithout IntensityStabilization

Figure 5.4: Evaporation efficiency of the sample without (yellow) and with (red) intensitystabilization. It is possible to see a small improvement in efficiency for end trap power of 50,25 and 12 W, but the evaporation still cannot reach the desired trap depth.

solution was to operate the laser at a high intensity setpoint and to turn the power down using

an external AOM. This behavior also provides a rather clear explanation as to the drastic

performance difference between our two dipole trap lasers. By driving forced evaporation

through lowering the power setpoint of the SPI laser, the RIN and ensemble heating would

increase counteracting the cooling of the sample and leading to a rather inefficient evaporation.

103

5.5. Future Work

101 102 103 104 105

Frequency (Hz)

-6

-5

-4

-3

-2

-1

RIN

Noise spectral denisty

SPI Power = 1WSPI Power = 3WSPI Power = 12WSPI Power = 25WSPI Power = 50WSPI Power = 100WT e-folding time = 0.1 sT e-folding time = 1 sT e-folding time = 10 s

Figure 5.5: passive stability of fiber laser at various power settings in RIN.

5.4.4 Improved Evaporation

With a better knowledge of the RIN of the SPI laser, we were able to depreciate the use of

the power setting on the SPI and instead use an AOM and a Direct Digital Synthesizer (DDS)

with variable RF output to modify the depth of the trap. Indeed, the equipment was already

in place due to the previous work on active intensity stabilization. As shown in Figure 5.6,

this method produced a highly efficient evaporation in the SPI down to very low trap depths.

This one change yielded a factor of 4 improvement in atom number and eliminated the need to

transfer the atoms to the IPG for the final evaporation stages.

5.5 Future Work

Since the primary objective of this particular study was to improve the total atom number

at the lowest temperatures by improving the evaporation in the SPI and avoiding the need

to transfer between the two dipole traps, the study ended once this objective was fulfilled.

While some evidence was obtained that active intensity stabilization improved the evaporation,

further investigation was unnecessary.

Although the observed improvement in evaporation was only marginal, this study does not

104

5.5. Future Work

Figure 5.6: The atom number versus final power in the evaporation ramp using the SPI at nearits maximum power setup (where the passive stability of the laser is relatively good) and anAOM to control the power delivered to the atoms showed a highly efficient evaporation (η =10). The atom number shows an apparent drop when the ensemble is imaged at zero magneticfield since Feshbach molecules are forming at powers below 1 W and are not imaged at lowmagnetic fields. The images taken at high magnetic field show that the ensemble is still presentand still evaporating very efficiently down to powers below 100 mW.

undermine the usefulness of active stabilization. One likely use of the IPG laser that was freed

up from the new evaporation routine is in lattice-forming. As it was shown in the work by Blatt

et al, active intensity stabilization can improve the lifetime in a lattice trap where the passive

stability of the laser, at 106 level in RIN, was improved to the 107 level with the use of an

AOM-based noise-eater [59]. It should be noted that the active intensity stabilization discussed

in the work have to undergo a redesign, particularly in the detection and front end section, to

achieve a similar noise floor as the one presented in the work by Blatt el at.

105

Chapter 6

Conclusion

In the quest to understand the theoretical and practical limitations of digital servos realized by

FPGAs, this work involved the design and construction of FPGA servos based on two different

FPGA development platforms (Chapter 2): the DE2 and the DE3 by Altera. Both servos

are shown to be capable of reaching loop delay of less than 200 ns (including conversion and

computation delay) and are competitive against the published open-source design by NIST with

a total delay of 320 ns [14] and the Digilock product by Toptica with a total delay of 200 ns

[17]. The design based on the DE2 platform is consolidated onto a single daughtercard that

is compatible with most of the development platforms provided by Altera, such as the DE3

through an adapter and the new FPGA platforms that have built-in HPS processors like the

DE1-SOC.

On the firmware side, this work included servo logic designs in the form of the IIR filter

and other useful instrumentation tools like the AWG (Chapter 3). This work also explored

the practical aspects of developing high speed signal processing modules in an FPGA with an

emphasis on the verification of the each part of the implementation. Contributions are made

to the development of digital servos by optimizing each IIR filter to a single clock delay with

a master clock speed of 50-75 MHz. This feature reduces the computation delay through the

FPGA servo and reduces the overall latency through the FPGA servo. In addition, this work

explores an interesting and important limitation of discrete-time filters that is highly relevant

to the present discussion. We explore the discrete frequency resolution of poles and zeros

implemented by an IIR filter, and an expression is derived for the frequency resolution in a first

order IIR filter.

This work also reports on a side-by-side comparison between an FPGA servo and a high-

speed analog servo in closed-loop in both a self-lock configuration and an intensity stabilization

106

Chapter 6. Conclusion

configuration (Chapter 4). In the comparisons, it is clear that the noise floor and the bandwidth

of the servos play an important role in the closed-loop performance of the system. In our design

of the FPGA servos, the overall noise floor of the servo has a best case scenario of 10 nV/√

Hz

at 1 kHz, when the input gain (gain between the servo input and ADC) is set to the maximum.

This performance is similar to that of the analog servo. However, it is important to note that

the noise floor of a FPGA servo is limited by the ADC at 177 nV/√

Hz which means that a

large gain is needed between the servo input and the ADC. Also, the distribution of gain in

the FPGA servo loop has to be carefully tuned to produce the 10 nV/√

Hz noise performance.

The analog servo and the FPGA servo are also different in signal latency. Broadly speaking,

a high-speed analog servo is faster than the FPGA servo designed in this work by >4 times.

In this work, we benchmarked a fast commercial analog servo with closed-loop bandwidth of

of 10 MHz. In comparison, the FPGA servos produced by this thesis operate with closed-loop

bandwidth of 2-2.5 MHz. In the present design, the signal conversion from the analog to the

digital domain and back again to the analog domain from the digital domain is substantial.

The conversion delay is 80-120 ns and accounts for 40-60% of the total delay in the FPGA

servo. The computation delay takes up a smaller fraction as a result of the speed optimization

in designing the IIR logic, with the cascade of two third order IIR filters costing between 23

ns (DE2 servo) and 40 ns (DE3 servo). This account for 13 - 20% of the total delay. The

delay in the analog signal conditioning stage in this design is only 30 ns (15% of the total)

and other propagation delay, such as the time it takes for the digital signals to travel from the

ADC to the FPGA and then back to the DAC), makes up for the rest. We note that the total

delay through an analog servo should be similar in magnitude to the delay through the analog

front-end of this FPGA servo with the use of similar op-amp technology. The delay in signal

conversion and, to a lesser extent, the computational delay are the culprits in the additional

delay in an FPGA servo. The longer total delay of the FPGA servo limits its use to closed-loop

system with a target closed loop bandwidth of <1 MHz. However, even with this constraint,

the FPGA servo is still able to satisfy a large number of closed-loop applications.

This work also explores the use of a digital servo design and the quantization error that

results. Some published works has already argued for and demonstrated that the quantization

error of the ADC and the DAC does not degrade the performance of an FPGA servo [14],

107

Chapter 6. Conclusion

[18]. The work done in thesis agree with these findings and found the noise level of the ADC

in nV/√

Hz almost more important. In this work, we observed two other quantization effects.

The first is the quantization of the z-domain due the finite computation precision that the IIR

can be implemented in (Section 3.2.5). The second is the effect of computation precision on

the noise floor of the overall servo system. To the best of our knowledge, these effects have not

been explicitly investigated previously.

One application of an FPGA servo explored in this work is the intensity stabilization of

a laser for atom trapping. In particular, we examined the evaporation efficiency of atoms

from an optical dipole trap with and without intensity stabilization (Chapter 5). The work

found preliminary evidence suggesting that intensity stabilization improved the evaporation

efficiency; however, because a different solution was found further work to quantify this effect

was not performed. In particular, this study found that the passive intensity stability of the

laser is sufficient when the laser operates at a high power setting and thus forced evaporation

was performed using an external AOM to modify the beam intensity. The study does not

undermine the usefulness of active intensity stabilization in scenaios where the passive stability

of the laser is not sufficient [60]; nor does it undermine the usefulness of FPGA servos in AMO

experiments as demonstrated in many published works the use in active stabilization of laser

frequency and phase [5], [8], [14].

The development of fast FPGA servo hardware and logic are only the the first steps towards

wide spread use of digital servos in closed-loop laser control applications. This work argues that

a well-designed FPGA servo is comparable with a high-performance analog servo as long as the

target closed-loop bandwidth of the laser system is less than 1 MHz. Although the performance

of the FPGA servo is convincing, it still takes effort to optimize the servo in different laser

systems that may require more tuning techniques and even different servo transfer functions.

So far, the closed-loop control application that have been demonstrated to work with FPGA

servo are intensity stabilization (this work), frequency stabilization (NIST) [14]. Existing open-

source FPGA servo designs, like in the one published by NIST can be very helpful in accelerating

the wide-spread use of FPGA servos.

108

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114

Appendix A

The Servo Daughter Card

The servo daughter card is designed to be compatible with the GPIO header used in many Altera

development boards, like the DE2 etc. When attached to a compatible FPGA development

board, the servo daughter card produces a dual channel FPGA servo, with built-in analog

frontend. The design rationale and the performance of the FPGA servo is described in detail in

the hardware chapter in Chapter 2. This section covers the rest of technical details including

schematics, circuit layout, bill of material and a few mistakes on the board that needs to be

worked around and be eliminated in future revisions.

A.1 Power Supply

Operation of the servo daughter requires additional power supply besides the power supply on

the FPGA development board. A quiet ±13 ∼ 15V voltage is needed to power the analog

frontend and the current consumption depends on whether the signal conversion section, the

ADC and the DAC, is powered through the GPIO header on the FPGA development board or

through the power supply input on the servo daughter card. The ADC and DAC on the servo

daughter card consumes up to 600 mA of current, whereas the rest of the daughter card circuit

consumed up to 200 mA. When the ADC and the DAC is powered through the power supply

input on the daughter card via a chain of linear regulators, the high current consumption of

the ADC and the DAC cause the linear regulators to operate too close to their thermal limit so

this mode of operation is not recommended without additional thermal relief around the linear

regulators. Powering the ADC and DAC via the 3.3 V supply on the GPIO header is more

convenient, but can not guarantee noise performance.

115

A.2. Pending Design Changes

A.2 Pending Design Changes

The next few pages provides the schematics, the layout and the bill of material for the servo

daughter card and what is shown here is the very first iteration of the PCB design. All major

parts of the design works as intended, but a few quirks exist at the schematics level and needs

to be worked around in the assembly process. The first is the polarity of the LDAC signal on

the slow DAC IC, DAC8734. The pull up resistor R504(A/B) on the LDAC signal should be

modified into a pull down with a near by ground pad on the PCB to enable latching the DAC

output by default. The second is a missing input signal to the DACMODE pin on the fast DAC

IC, AD8967. This can be fixed with a solder bridge between the DACMODE pin (48) to the

adjacent A3V3 pin (47) which selects the independent access mode of the two DAC channel

within the IC. The third mistake is the missing resistive divider between the slow DAC output

and some of the offset input of the analog frontend. The missing divider need to be inserted in

place of the resistor R309(A/B), likely in the form of a ”dead-bug”

The above problems, including the thermal limitation around the linear regulators are to

be fixed in future revisions, but there is one other quirk of this design that is to stay. A careful

comparison between the ADA card provided by Altera and the daughter servo card designed

in this work should reveal that the pin mapping on the GPIO header of the two daughter card

are not the same. Because the pin mapping of the fast DAC is different between the two board,

change of pin mapping is needed to port FPGA design for one daughter card to the other. To

match the servo daughter card to the ADA card means significant redesign of the PCB layout

and offer little benefit, this quirk of the design is to stay.

A.3 Design Files

The following page shows the schematics, layout and bill of material of the servo daughter card.

The design is meant to be self-documenting, with a hierarchical schematics structure and device

annotation that are meant to inform the schematics sub-page that the device is from.

116

1

1

2

2

3

3

4

4

D D

C C

B B

A A

1

Altium LimitedL3, 12a Rodborough RdFrenchs ForestNSWAustralia 20868

12016-06-07 5:40:02 PMC:\Users\Public\Documents\qdg_projects_repo\trunk\PRJ_servo_daughter_card\top.SchDoc

Title

Size: Number:Date:File:

Revision:Sheet ofTime:

Letter

U_PowerPower.SchDoc

VIN_A+VIN_A-

VIN_B+VIN_B-

VREF

ADC_CLKAADC_CLKB

ADC_OTRAADC_OTRB

ADC_DA[0..13]ADC_DB[0..13]

ADCADC.SchDoc

DAC_DA[0..13]DAC_DB[0..13]

DAC_WRTA

DAC_CLKA

DAC_WRTB

DAC_CLKB VOUT1

VOUT2

DACDAC.SchDoc

GAIN_INPUT VIN_A+VIN_A-

OFFSET_INPUTMANUAL_OFFSETEXTERNAL_OFFSET

VIN1

SERVO_IN

VOCM

IAF1Input_AF.SchDoc

GAIN_INPUTVOUT1OFFSET_INPUT

SERVO_OUT

OAF1Output_AF.SchDoc

VSLOW[1..4]SL_CSSL_SCLKSL_SDI

SL_SDO

SL_LDAC

REF1Slow_DAC_w_REF.SchDoc

ADC_OTRAADC_OTRB DAC_WRTB

DAC_WRTA

ADC_CLKAADC_CLKB

DAC_CLKADAC_CLKB

MS_SCLKMS_SDO

MS_LDACMS_SDISLAVE1_CSSLAVE2_CS

DAC_DA[0..13]DAC_DB[0..13]

ADC_DA[0..13]ADC_DB[0..13]

InterfaceInterface.SchDoc

GAIN_INPUT VIN_A+VIN_A-

OFFSET_INPUTMANUAL_OFFSETEXTERNAL_OFFSET

VIN1

SERVO_IN

VOCM

IAF2Input_AF.SchDoc

GAIN_INPUTVOUT1OFFSET_INPUT

SERVO_OUT

OAF2Output_AF.SchDoc

VSLOW[1..4]SL_CSSL_SCLKSL_SDI

SL_SDO

SL_LDAC

REF2Slow_DAC_w_REF.SchDoc

VA1

VA2

VA3

VA4

VB1

VB2

VB3

VB4

VA[1..4]

VB[1..4]

MANUAL_OFFSET

IMO1Input_Manual_Offset.SchDoc

MANUAL_OFFSET

IMO2Input_Manual_Offset.SchDoc

5

1

2 3 4

J2

COAX-F

5

1

2 3 4

J6

COAX-F

J4A

BNC_DUAL

J4B

BNC_DUAL

AGNDAGND

AGNDAGND

VOUT1

VOUT2

VOUT1

SERVO_OUT1SERVO_OUT2

SERVO_OUT1

5

1

2 3 4

J1

COAX-F

5

1

2 3 4

J5

COAX-F

J3A

BNC_DUAL

J3B

BNC_DUAL

AGNDAGND

AGND

VOUT2

SERVO_OUT2

AGND

VEXT1

VEXT2

VIN1

VIN2

J9A

BNC_DUAL

J9B

BNC_DUAL

5

1

2 3 4

J7

COAX-F

5

1

2 3 4

J11

COAX-F

5

1

2 3 4

J13

COAX-F

AGNDAGND

AGNDAGND

AGND

SERVO_IN1

VIN1

VEXT1

SERVO_IN1

SERVO_IN2

J10A

BNC_DUAL

J10B

BNC_DUAL

5

1

2 3 4

J8

COAX-F

5

1

2 3 4

J12

COAX-F

5

1

2 3 4

J14

COAX-F

AGNDAGND

AGNDAGND

AGND

SERVO_IN2

VIN2

VEXT2

VOCMADC_VREF

U_VOCM_generateVOCM_generate.SchDoc

PIJ101

PIJ102 PIJ103 PIJ104 PIJ105

COJ1

PIJ201


COJ2

PIJ301

PIJ302

COJ3A

PIJ302PIJ303

PIJ304

COJ3B

PIJ401

PIJ402

COJ4A

PIJ402PIJ403

PIJ404

COJ4B

PIJ501


COJ5

PIJ601


COJ6

PIJ701


COJ7

PIJ801


COJ8

PIJ901

PIJ902

COJ9A

PIJ902PIJ903

PIJ904

COJ9B

PIJ1001

PIJ1002

COJ10A

PIJ1002PIJ1003

PIJ1004

COJ10B

PIJ1101

PIJ1102 PIJ1103 PIJ1104 PIJ1105

COJ11

PIJ1201

PIJ1202 PIJ1203 PIJ1204 PIJ1205

COJ12

PIJ1301

PIJ1302 PIJ1303 PIJ1304 PIJ1305

COJ13

PIJ1401

PIJ1402 PIJ1403 PIJ1404 PIJ1405

COJ14

PIJ102 PIJ103 PIJ104 PIJ105 PIJ202 PIJ203 PIJ204 PIJ205PIJ302PIJ304 PIJ402PIJ404

PIJ502 PIJ503 PIJ504 PIJ505 PIJ602 PIJ603 PIJ604 PIJ605

PIJ702 PIJ703 PIJ704 PIJ705 PIJ802 PIJ803 PIJ804 PIJ805PIJ902

PIJ904

PIJ1002

PIJ1004PIJ1102 PIJ1103 PIJ1104 PIJ1105 PIJ1202 PIJ1203 PIJ1204 PIJ1205

PIJ1302 PIJ1303 PIJ1304 PIJ1305 PIJ1402 PIJ1403 PIJ1404 PIJ1405

PIJ302 PIJ402

PIJ701PIJ901

NLSERVO0IN1

PIJ801PIJ1001

NLSERVO0IN2

PIJ401 PIJ601

NLSERVO0OUT1

PIJ301 PIJ501

NLSERVO0OUT2

PIJ1301

NLVEXT1

PIJ1401

NLVEXT2

PIJ903 PIJ1101

NLVIN1

PIJ1003 PIJ1201

NLVIN2

PIJ201PIJ403

NLVOUT1

PIJ101PIJ303

NLVOUT2

NLVA010040

NLVA1

NLVA010040

NLVA2

NLVA010040

NLVA3

NLVA010040

NLVA4

NLVB010040

NLVB1

NLVB010040

NLVB2

NLVB010040

NLVB3

NLVB010040

NLVB4

117

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D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\DAC.SchDoc Drawn By:

DAC_DA0DAC_DA1DAC_DA2

DAC_DA[0..13] DAC_DA[0..13]

DAC_DA3DAC_DA4DAC_DA5DAC_DA6DAC_DA7DAC_DA8

DAC_DA10DAC_DA11DAC_DA12DAC_DA13

DAC_DA9

DAC_DB[0..13] DAC_DB[0..13]

DAC_DB0DAC_DB1DAC_DB2DAC_DB3DAC_DB4DAC_DB5DAC_DB6DAC_DB7DAC_DB8

DAC_DB10DAC_DB11DAC_DB12DAC_DB13

DAC_DB9

DAC_WRTADAC_WRTA

DAC_CLKADAC_CLKA

DAC_MODEDAC_SLEEP

GAINCTRL

FSADJ2FSADJ1

100

R102100

150

R104150

100

R103100

150

R105150

DNP

R100DNP

2K

R1062K

DNP

R101DNP

0

R1070

2K

R1082K

2K

R1092K

0.1uF

C1080.1uF

IOUTA1IOUTB1

IOUTA2IOUTB2

DB0-P1 (LSB)1

DB1-P12

DB2-P13

DB3-P14

DB4-P15

DB5-P16

DB6-P17

DB7-P18

DB8-P19

DB9-P110

DB10-P111

DB11-P112

DB12-P113

DB13-P1 (MSB)14D

CO

M1

15D

VD

D1

16

WRT1/IOWRT17

CLK1/IQCLK18

CLK2/IQRESET19

WRT2/IQSET20

DC

OM

221

DV

DD

222

DB0-P2 (LSB)23

DB1-P224

DB2-P225

DB3-P226

DB4-P227

DB5-P228

DB6-P229

DB7-P230

DB8-P231

DB9-P232

DB10-P233

DB11-P234

DB12-P235

DB13-P2 (MSB)36

SLEEP37

AC

OM

38

IOUTA2 39

IOUTB2 40

FSADJ241

GAINCTRL42 REFIO 43

FSADJ144

IOUTB1 45IOUTA1 46

AVD

D47

MODE48

U100AD9767

DAC_WRTB

DAC_CLKB

DAC_WRTB

DAC_CLKB

FSADJ2FSADJ1GAINCTRLDAC_SLEEP

DAC_CLKADAC_CLKB

+A3.3V +A3.3V

AGND AGND AGND AGNDDGND DGND

+D3.3V +D3.3V

+A3.3V+D3.3V

AGND DGND

AGND

25R110

50R111

25R112

50R113

AGND AGND

AGND AGNDAGND

+A3.3V

DGND

+D3.3V

10uFC100

0.1uFC104

10uFC101

1uFC102

1uFC103

0.1uFC105

0.01uFC106

0.01uFC107

1uFC109

1uFC110

1uFC111

0.01ufC112

0.01uFC113

0.01uFC114

VOUT1

VOUT2

PIC10001

PIC10002COC100

PIC10101

PIC10102COC101

PIC10201

PIC10202COC102

PIC10301

PIC10302COC103

PIC10401

PIC10402COC104

PIC10501

PIC10502COC105

PIC10601

PIC10602COC106

PIC10701

PIC10702COC107

PIC10801

PIC10802COC108

PIC10901

PIC10902COC109

PIC11001

PIC11002COC110

PIC11101

PIC11102COC111

PIC11201

PIC11202COC112

PIC11301

PIC11302COC113

PIC11401

PIC11402COC114

PIR10001

PIR10002COR100

PIR10101

PIR10102COR101

PIR10201

PIR10202COR102

PIR10301

PIR10302COR103

PIR10401

PIR10402COR104

PIR10501

PIR10502COR105

PIR10601

PIR10602COR106

PIR10701

PIR10702COR107

PIR10801

PIR10802COR108

PIR10901

PIR10902COR109

PIR11001

PIR11002COR110

PIR11101

PIR11102COR111

PIR11201

PIR11202COR112

PIR11301

PIR11302COR113

PIU10001

PIU10002

PIU10003

PIU10004

PIU10005

PIU10006

PIU10007

PIU10008

PIU10009

PIU100010

PIU100011

PIU100012

PIU100013

PIU100014

PIU100015

PIU100016

PIU100017

PIU100018

PIU100019

PIU100020

PIU100021

PIU100022

PIU100023

PIU100024

PIU100025

PIU100026

PIU100027

PIU100028

PIU100029

PIU100030

PIU100031

PIU100032

PIU100033

PIU100034

PIU100035

PIU100036

PIU100037

PIU100038

PIU100039

PIU100040

PIU100041

PIU100042 PIU100043

PIU100044

PIU100045

PIU100046

PIU100047

PIU100048

COU100

PIC10002 PIC10102 PIC10202 PIC10302 PIC10402 PIC10502 PIC10602 PIC10702

PIR10002 PIR10102PIU100047

PIC10902 PIC11002 PIC11102 PIC11202 PIC11302 PIC11402

PIR10202 PIR10302PIU100016 PIU100022


PIC10801

PIR10601 PIR10701 PIR10801 PIR10901

PIR11001 PIR11101

PIR11201 PIR11301

PIU100038

PIR10201

PIR10402

PIU100018

NLDAC0CLKA

PODAC0CLKA

PIR10301

PIR10502

PIU100019

NLDAC0CLKB

PODAC0CLKB

PIU100048NLDAC0MODE

PIR10001

PIR10602

PIU100037

NLDAC0SLEEP

PIU100017NLDAC0WRTA

PODAC0WRTAPIU100020

NLDAC0WRTBPODAC0WRTB


PIR10401 PIR10501

PIU100015PIU100021

PIR10802

PIU100044

NLFSADJ1

PIR10902

PIU100041

NLFSADJ2

PIR10101

PIR10702

PIU100042

NLGAINCTRL

PIR11102

PIU100046NLIOUTA1

POVOUT1

PIR11302

PIU100039NLIOUTA2

POVOUT2

PIR11002PIU100045

NLIOUTB1

PIR11202PIU100040

NLIOUTB2

PIC10802PIU100043

PIU10001

NLDAC0DA0000130

NLDAC0DA0

PODAC0DA0000130

PIU10002

NLDAC0DA0000130

NLDAC0DA1

PODAC0DA0000130

PIU10003

NLDAC0DA0000130

NLDAC0DA2

PODAC0DA0000130

PIU10004

NLDAC0DA0000130

NLDAC0DA3

PODAC0DA0000130

PIU10005

NLDAC0DA0000130

NLDAC0DA4

PODAC0DA0000130

PIU10006

NLDAC0DA0000130

NLDAC0DA5

PODAC0DA0000130

PIU10007

NLDAC0DA0000130

NLDAC0DA6

PODAC0DA0000130

PIU10008

NLDAC0DA0000130

NLDAC0DA7

PODAC0DA0000130

PIU10009

NLDAC0DA0000130

NLDAC0DA8

PODAC0DA0000130

PIU100010

NLDAC0DA0000130

NLDAC0DA9

PODAC0DA0000130

PIU100011

NLDAC0DA0000130

NLDAC0DA10

PODAC0DA0000130

PIU100012

NLDAC0DA0000130

NLDAC0DA11

PODAC0DA0000130

PIU100013

NLDAC0DA0000130

NLDAC0DA12

PODAC0DA0000130

PIU100014

NLDAC0DA0000130

NLDAC0DA13

PODAC0DA0000130

PIU100023

NLDAC0DB0000130

NLDAC0DB0

PODAC0DB0000130

PIU100024

NLDAC0DB0000130

NLDAC0DB1

PODAC0DB0000130

PIU100025

NLDAC0DB0000130

NLDAC0DB2

PODAC0DB0000130

PIU100026

NLDAC0DB0000130

NLDAC0DB3

PODAC0DB0000130

PIU100027

NLDAC0DB0000130

NLDAC0DB4

PODAC0DB0000130

PIU100028

NLDAC0DB0000130

NLDAC0DB5

PODAC0DB0000130

PIU100029

NLDAC0DB0000130

NLDAC0DB6

PODAC0DB0000130

PIU100030

NLDAC0DB0000130

NLDAC0DB7

PODAC0DB0000130

PIU100031

NLDAC0DB0000130

NLDAC0DB8

PODAC0DB0000130

PIU100032

NLDAC0DB0000130

NLDAC0DB9

PODAC0DB0000130

PIU100033

NLDAC0DB0000130

NLDAC0DB10

PODAC0DB0000130

PIU100034

NLDAC0DB0000130

NLDAC0DB11

PODAC0DB0000130

PIU100035

NLDAC0DB0000130

NLDAC0DB12

PODAC0DB0000130

PIU100036

NLDAC0DB0000130

NLDAC0DB13

PODAC0DB0000130

PODAC0CLKAPODAC0CLKB

PODAC0DA0PODAC0DA1PODAC0DA2PODAC0DA3PODAC0DA4PODAC0DA5PODAC0DA6PODAC0DA7PODAC0DA8PODAC0DA9PODAC0DA10PODAC0DA11PODAC0DA12PODAC0DA13PODAC0DA0000130

PODAC0DB0PODAC0DB1PODAC0DB2PODAC0DB3PODAC0DB4PODAC0DB5PODAC0DB6PODAC0DB7PODAC0DB8PODAC0DB9PODAC0DB10PODAC0DB11PODAC0DB12PODAC0DB13PODAC0DB0000130

PODAC0WRTAPODAC0WRTB

POVOUT1

POVOUT2

118

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\ADC.SchDoc Drawn By:

AG

ND

1

VIN+_A2

VIN-_A3

AG

ND

4AV

DD

5

REFT_A6

REFB_A7

VREF8

SENSE9

REFB_B10 REFT_B11

AVD

D12

AG

ND

13

VIN-B14 VIN+_B15

AG

ND

16

AVD

D17

CLK_B 18

DCS 19

DFS 20

PDWN_B 21

OEB_B 22

D0_B (LSB) 23

D1_B 24

D2_B 25

D3_B 26

D4_B 27

DR

GN

D28

DRV

DD

29

D5_B 30

D6_B 31

D7_B 32

D8_B 33

D9_B 34

D10_B 35

D11_B 36

D12_B 37

D13_B (MSB) 38

OTR_B 39

DR

GN

D40

DRV

DD

41

D0_A (LSB) 42

D1_A 43

D2_A 44

D3_A 45

D4_A 46

D5_A 47

D6_A 48

D7_A 49

D8_A 50

D9_A 51

DRV

DD

52D

RG

ND

53

D10_A 54

D11_A 55

D12_A 56

D13_A (MSB) 57

OTR_A 58

OEB_A 59

PDWN_A 60

MUX_SELECT 61

SHARED_REF 62

CLK_A 63

AVD

D64

U200AD9248

AGND DGND

ADC_DA0ADC_DA1ADC_DA2ADC_DA3ADC_DA4ADC_DA5ADC_DA6ADC_DA7ADC_DA8ADC_DA9ADC_DA10ADC_DA11ADC_DA12ADC_DA13

ADC_OTRAADC_OEAADC_CLKAADC_POWERON

MUX_SELECTSHARED_REFDCSDFS

ADC_OTRBADC_OEBADC_CLKBADC_POWERON

ADC_DB0ADC_DB1ADC_DB2ADC_DB3ADC_DB4ADC_DB5ADC_DB6ADC_DB7ADC_DB8ADC_DB9ADC_DB10ADC_DB11ADC_DB12ADC_DB13

0.1uFC219

10uFC218

AGND

AGND

0.1uF

C214

0.1uF

C217 10uFC215

0.1uFC216

0.1uF

C220

0.1uF

C223 10uFC221

0.1uFC222

REFB_BREFT_BVIN_B-VIN_B+

REFB_AREFT_A

VIN_A+VIN_A-

AGND

AGND

+A3.3V +D3.3V

100R200

150R204

100R201

150R205

ADC_CLKAADC_CLKB

DGND DGND

+D3.3V +D3.3V

1KR208

DNPR216

1KR209

DNPR217

ADC_OEAADC_OEB

AGND AGND

+A3.3V +A3.3V

DNPR210

1KR218

DNPR211

1KR219

DFSADC_POWERON

AGND AGND

+A3.3V +A3.3V

DNPR202

1KR206

DNPR203

1KR207

DCSSHARED_REF

DGND DGND

+D3.3V +D3.3V

VIN_A+VIN_A-

VIN_B+VIN_B-

AGND

+A3.3V

DGND

+D3.3V

10uFC200

0.1uFC204

10uFC201

1uFC202

1uFC203

0.1uFC205

0.01uFC206

0.01uFC207

1uFC208

1uFC209

1uFC210

0.01uFC211

0.01uFC212

0.01uFC213

ADC_CLKAADC_CLKB

ADC_OTRA

ADC_OTRB

ADC_DA[0..13]

ADC_DB[0..13]

ADC_DA[0..13]

ADC_DB[0..13]

VREF

PIC20001

PIC20002COC200

PIC20101

PIC20102COC201

PIC20201

PIC20202COC202

PIC20301

PIC20302COC203

PIC20401

PIC20402COC204

PIC20501

PIC20502COC205

PIC20601

PIC20602COC206

PIC20701

PIC20702COC207

PIC20801

PIC20802COC208

PIC20901

PIC20902COC209

PIC21001

PIC21002COC210

PIC21101

PIC21102COC211

PIC21201

PIC21202COC212

PIC21301

PIC21302COC213

PIC21401PIC21402

COC214

PIC21501

PIC21502COC215

PIC21601

PIC21602COC216

PIC21701PIC21702

COC217

PIC21801

PIC21802COC218

PIC21901

PIC21902COC219

PIC22001PIC22002

COC220

PIC22101

PIC22102COC221

PIC22201

PIC22202COC222

PIC22301PIC22302

COC223

PIR20001

PIR20002COR200

PIR20101

PIR20102COR201

PIR20201

PIR20202COR202

PIR20301

PIR20302COR203

PIR20401

PIR20402COR204

PIR20501

PIR20502COR205

PIR20601

PIR20602COR206

PIR20701

PIR20702COR207

PIR20801

PIR20802COR208

PIR20901

PIR20902COR209

PIR21001

PIR21002COR210

PIR21101

PIR21102COR211

PIR21601

PIR21602COR216

PIR21701

PIR21702COR217

PIR21801

PIR21802COR218

PIR21901

PIR21902COR219

PIU20001

PIU20002

PIU20003

PIU20004

PIU20005

PIU20006

PIU20007

PIU20008

PIU20009

PIU200010

PIU200011

PIU200012

PIU200013

PIU200014

PIU200015

PIU200016

PIU200017

PIU200018

PIU200019

PIU200020

PIU200021

PIU200022

PIU200023

PIU200024

PIU200025

PIU200026

PIU200027

PIU200028

PIU200029

PIU200030

PIU200031

PIU200032

PIU200033

PIU200034

PIU200035

PIU200036

PIU200037

PIU200038

PIU200039

PIU200040

PIU200041PIU200042

PIU200043

PIU200044

PIU200045

PIU200046

PIU200047

PIU200048

PIU200049

PIU200050

PIU200051

PIU200052

PIU200053

PIU200054

PIU200055

PIU200056

PIU200057

PIU200058

PIU200059

PIU200060

PIU200061

PIU200062

PIU200063

PIU200064 COU200


PIR20802 PIR20902 PIR21002 PIR21102

PIU20005 PIU200012 PIU200017PIU200064


PIR20002 PIR20102 PIR20202 PIR20302

PIU200029PIU200041PIU200052

PIR20001

PIR20402

PIU200063NLADC0CLKA

POADC0CLKA

PIR20101

PIR20502

PIU200018NLADC0CLKB

POADC0CLKB

PIR20801

PIR21602

PIU200059NLADC0OEA

PIR20901

PIR21702

PIU200022NLADC0OEB

PIU200058NLADC0OTRA POADC0OTRA

PIU200039NLADC0OTRB POADC0OTRB

PIR21101

PIR21902

PIU200021

PIU200060NLADC0POWERON


PIC21402

PIC21702

PIC21801 PIC21901

PIC22002

PIC22302

PIR21601 PIR21701 PIR21801 PIR21901

PIU20001PIU20004

PIU20009

PIU200013PIU200016

PIR20201

PIR20602

PIU200019NLDCS

PIR21001

PIR21802

PIU200020NLDFS


PIR20401 PIR20501 PIR20601 PIR20701

PIU200028PIU200040PIU200053

PIU200061NLMUX0SELECT

PIC21802 PIC21902PIU20008

POVREF

PIC21502 PIC21602PIC21701

PIU20007NLREFB0A

PIC22102 PIC22202PIC22301

PIU200010NLREFB0B

PIC21401

PIC21501 PIC21601PIU20006

NLREFT0A

PIC22001

PIC22101 PIC22201PIU200011

NLREFT0B

PIR20301

PIR20702

PIU200062NLSHARED0REF

PIU20002NLVIN0A0POVIN0A0

PIU20003NLVIN0A0POVIN0A0

PIU200015NLVIN0B0POVIN0B0

PIU200014NLVIN0B0

POVIN0B0

PIU200042

NLADC0DA0000130

NLADC0DA0

POADC0DA0000130

PIU200043

NLADC0DA0000130

NLADC0DA1

POADC0DA0000130

PIU200044

NLADC0DA0000130

NLADC0DA2

POADC0DA0000130

PIU200045

NLADC0DA0000130

NLADC0DA3

POADC0DA0000130

PIU200046

NLADC0DA0000130

NLADC0DA4

POADC0DA0000130

PIU200047

NLADC0DA0000130

NLADC0DA5

POADC0DA0000130

PIU200048

NLADC0DA0000130

NLADC0DA6

POADC0DA0000130

PIU200049

NLADC0DA0000130

NLADC0DA7

POADC0DA0000130

PIU200050

NLADC0DA0000130

NLADC0DA8

POADC0DA0000130

PIU200051

NLADC0DA0000130

NLADC0DA9

POADC0DA0000130

PIU200054

NLADC0DA0000130

NLADC0DA10

POADC0DA0000130

PIU200055

NLADC0DA0000130

NLADC0DA11

POADC0DA0000130

PIU200056

NLADC0DA0000130

NLADC0DA12

POADC0DA0000130

PIU200057

NLADC0DA0000130

NLADC0DA13

POADC0DA0000130

PIU200023

NLADC0DB0000130

NLADC0DB0

POADC0DB0000130

PIU200024

NLADC0DB0000130

NLADC0DB1

POADC0DB0000130

PIU200025

NLADC0DB0000130

NLADC0DB2

POADC0DB0000130

PIU200026

NLADC0DB0000130

NLADC0DB3

POADC0DB0000130

PIU200027

NLADC0DB0000130

NLADC0DB4

POADC0DB0000130

PIU200030

NLADC0DB0000130

NLADC0DB5

POADC0DB0000130

PIU200031

NLADC0DB0000130

NLADC0DB6

POADC0DB0000130

PIU200032

NLADC0DB0000130

NLADC0DB7

POADC0DB0000130

PIU200033

NLADC0DB0000130

NLADC0DB8

POADC0DB0000130

PIU200034

NLADC0DB0000130

NLADC0DB9

POADC0DB0000130

PIU200035

NLADC0DB0000130

NLADC0DB10

POADC0DB0000130

PIU200036

NLADC0DB0000130

NLADC0DB11

POADC0DB0000130

PIU200037

NLADC0DB0000130

NLADC0DB12

POADC0DB0000130

PIU200038

NLADC0DB0000130

NLADC0DB13

POADC0DB0000130

POADC0CLKAPOADC0CLKB

POADC0DA0POADC0DA1POADC0DA2POADC0DA3POADC0DA4POADC0DA5POADC0DA6POADC0DA7POADC0DA8POADC0DA9POADC0DA10POADC0DA11POADC0DA12POADC0DA13POADC0DA0000130

POADC0DB0POADC0DB1POADC0DB2POADC0DB3POADC0DB4POADC0DB5POADC0DB6POADC0DB7POADC0DB8POADC0DB9POADC0DB10POADC0DB11POADC0DB12POADC0DB13POADC0DB0000130

POADC0OTRA

POADC0OTRB

POVIN0A0

POVIN0B0

POVREF

119

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\Input_AF.SchDoc Drawn By:

2

3

1

74

6

5

8

U300AD829JR

12

3

4

5

6

7

8

GND

IN

U302AD603AR

-IN1

VOCM2VS+

3

+OUT 4

-OUT 5

VS-

6

/PD 7

+IN8

U301AD8137

270

R305

270

R313

56pC302

56pC304

1uFC315

1uFC313

10nFC314

10nFC316

1uFC323

1uFC321

10nFC322

10nFC324

+12V

-12V

+5V

-5V

+5V

-5V

+5V

-5V

AGND

AGND

AGND

GAIN_INPUT

GAIN_CTRL

18k

R321

1KR324

1uFC325

AGND

GAIN_CTRL

0

R307

DNPR312

AGND

0

R302

0

R308

499R311

1K1

R303

1K1

R314

25pFC303

25pFC305

AGND

AGND

470

R304

470

R315

1K1R316

1K1R301

9p1C301

9p1C308

1K

R306

1K

R300

3pF

C300

HACK2

R30950R310

AGND

VIN_A+

VIN_A-AGND 3pFC306

25pFC307

AGND

NULL1

NULL2

DNPR317

DNPR319

NULL2

NULL1

-12V

R318DNP

INPUT_AF_OUT

1uFC311

10nFC312

1uFC319

10nFC320

+12V

-12V

AGND

OFFSET_INPUT

DNP

R320

DNPR322

MANUAL_OFFSET

SERVO_IN

VIN1EXTERNAL_OFFSET

VOCM

PIC30001 PIC30002

COC300

PIC30101

PIC30102COC301

PIC30201

PIC30202COC302

PIC30301

PIC30302COC303

PIC30401

PIC30402COC304

PIC30501

PIC30502COC305

PIC30601

PIC30602COC306

PIC30701

PIC30702COC307

PIC30801

PIC30802COC308

PIC31101

PIC31102COC311

PIC31201

PIC31202COC312

PIC31301

PIC31302COC313

PIC31401

PIC31402COC314

PIC31501

PIC31502COC315

PIC31601

PIC31602COC316

PIC31901

PIC31902COC319

PIC32001

PIC32002COC320

PIC32101

PIC32102COC321

PIC32201

PIC32202COC322

PIC32301

PIC32302COC323

PIC32401

PIC32402COC324

PIC32501

PIC32502COC325

PIR30001 PIR30002COR300 PIR30101

PIR30102

COR301

PIR30201 PIR30202COR302

PIR30301PIR30302COR303


PIR30501 PIR30502COR305

PIR30601 PIR30602COR306

PIR30701 PIR30702COR307

PIR30801 PIR30802COR308

PIR30901 PIR30902COR309

PIR31001

PIR31002COR310

PIR31101

PIR31102COR311

PIR31201

PIR31202COR312




PIR31601

PIR31602

COR316

PIR31701

PIR31702COR317

PIR3180CCW

PIR3180CWPIR3180W

COR318

PIR31901

PIR31902COR319

PIR32001 PIR32002COR320

PIR32101 PIR32102COR321

PIR32201 PIR32202COR322

PIR32401

PIR32402COR324

PIU30001

PIU30002

PIU30003

PIU30004PIU30005

PIU30006

PIU30007PIU30008

COU300

PIU30101

PIU30102

PIU30103

PIU30104

PIU30105

PIU30106

PIU30107

PIU30108

COU301

PIU30201

PIU30202

PIU30203

PIU30204

PIU30205

PIU30206

PIU30207

PIU30208 COU302

PIC31302 PIC31402 PIC31502 PIC31602

PIU30103PIU30208

PIC31102 PIC31202

PIU30007

PIC32101 PIC32201 PIC32301 PIC32401

PIU30106PIU30206

PIC31901 PIC32001

PIR31701PIR3180W

PIR31902

PIU30004

PIC30201PIC30301

PIC30402PIC30502

PIC30701



PIC32501

PIR31001

PIR31101PIR31201PIR31402

PIR32401

PIU30003

PIU30202

PIU30204

PIC32502

PIR32102

PIR32402

PIU30201NLGAIN0CTRL

PIR30302

PIR30802

PIR31102

NLINPUT0AF0OUT

POVIN1

PIC30001

PIC30601

PIR30001

PIR30602

PIR30902

PIR32002

PIR32202

PIU30002

PIC30002

PIR30002

PIR30701PIU30006

PIC30101

PIR30401

PIU30108

PIC30102PIR30101

PIR30501

PIU30105

PIC30202

PIR30502 POVIN0A0

PIC30302

PIR30102

PIR30301 PIR30402

PIC30401PIR31301 POVIN0A0

PIC30501

PIR31401 PIR31502

PIR31601

PIC30602 PIC30702

PIU30005

PIC30801

PIR31302

PIR31602

PIU30104

PIC30802

PIR31501

PIU30101

PIR30201

PIU30205

PIR30202

PIR30801PIU30207

PIR30601

PIR31002

POSERVO0IN

PIR30702

PIR31202

PIU30203

PIR30901

POOFFSET0INPUT

PIR32001POEXTERNAL0OFFSET

PIR32101POGAIN0INPUT

PIR32201POMANUAL0OFFSET

PIU30102POVOCM

PIU30107

PIR3180CCW

PIR31901

PIU30008

NLNULL1

PIR31702

PIR3180CW

PIU30001

NLNULL2

POEXTERNAL0OFFSET

POGAIN0INPUT

POMANUAL0OFFSET

POOFFSET0INPUT

POSERVO0IN

POVIN1

POVIN0A0

POVOCM

120

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\Output_AF.SchDoc Drawn By:

12

3

4

56

7

8

GND

IN

U401AD603AR

2

3

1

74

6

5

8

U400AD829JR

GAIN_INPUT18k

R408

1KR412

1uFC407

AGND

GAIN_CTRL

+12V

1uFC403

10nFC404

AGND

-12V

1uFC409

10nFC410

+5V

1uFC405

10nFC406

AGND

-5V

1uFC411

10nFC412

AGND

GAIN_CTRL 0

R402

499R405

1K

R403

1K

R406

1K

R400

+12V

-12V

3pF

C400

AGND

0

R401+5V

-5V

0

R404VOUT1

OFFSET_INPUT1K5

R409

401R413

1uFC408

AGND

OFFSET_CTRL

OFFSET_CTRL

AGND3pFC401

25pFC402

AGND

NULL1

NULL2

DNPR410

DNPR414

NULL2

NULL1

-12V

R411DNP

DNPR407

AGND

2

3

1

74

6

5

8

U402DNP

+24V

+24V

1uFC415

10nFC416

AGND

-5V

1uFC417

10nFC418

-5V1KR417

1KR418

100pFC414

AGND

100pFC413

AGND

NULL3NULL4

DNPR419

DNPR421

NULL4

NULL3

-5V

R420DNP

0

R416

0

R415

SERVO_OUT

PIC40001 PIC40002

COC400

PIC40101

PIC40102COC401

PIC40201

PIC40202COC402

PIC40301

PIC40302COC403

PIC40401

PIC40402COC404

PIC40501

PIC40502COC405

PIC40601

PIC40602COC406

PIC40701

PIC40702COC407

PIC40801

PIC40802COC408

PIC40901

PIC40902COC409

PIC41001

PIC41002COC410

PIC41101

PIC41102COC411

PIC41201

PIC41202COC412

PIC41301

PIC41302COC413

PIC41401

PIC41402COC414

PIC41501

PIC41502COC415

PIC41601

PIC41602COC416

PIC41701

PIC41702COC417

PIC41801

PIC41802COC418

PIR40001 PIR40002COR400

PIR40101 PIR40102COR401

PIR40201 PIR40202

COR402


PIR40401 PIR40402COR404

PIR40501

PIR40502COR405

PIR40601 PIR40602COR406

PIR40701

PIR40702COR407

PIR40801 PIR40802COR408

PIR40901 PIR40902COR409

PIR41001

PIR41002COR410

PIR4110CCW

PIR4110CWPIR4110W

COR411

PIR41201

PIR41202COR412

PIR41301

PIR41302COR413

PIR41401

PIR41402COR414

PIR41501 PIR41502COR415

PIR41601 PIR41602COR416

PIR41701

PIR41702COR417

PIR41801

PIR41802COR418

PIR41901

PIR41902COR419

PIR4200CCW

PIR4200CWPIR4200W

COR420

PIR42101

PIR42102COR421

PIU40001

PIU40002

PIU40003

PIU40004PIU40005

PIU40006

PIU40007PIU40008

COU400

PIU40101

PIU40102

PIU40103

PIU40104

PIU40105

PIU40106

PIU40107

PIU40108 COU401

PIU40201

PIU40202

PIU40203

PIU40204PIU40205

PIU40206

PIU40207PIU40208

COU402

PIC40502 PIC40602

PIU40108

PIC40302 PIC40402

PIU40007

PIC41502 PIC41602

PIU40207

PIC41101 PIC41201 PIC41701 PIC41801

PIR41901PIR4200W

PIR42102

PIU40106 PIU40204

PIC40901 PIC41001

PIR41001PIR4110W

PIR41402

PIU40004PIC40201

PIC40301 PIC40401 PIC40501 PIC40601

PIC40701 PIC40801PIC40902 PIC41002 PIC41102 PIC41202

PIC41301

PIC41501 PIC41601

PIC41702 PIC41802

PIR40501

PIR40701

PIR41201 PIR41301

PIR41801

PIU40003

PIU40102

PIU40104

PIC40702

PIR40802

PIR41202

PIU40101

NLGAIN0CTRL

PIC40001

PIC40101

PIR40001

PIR40301

PIR40602

PIU40002

PIC40002

PIR40002

PIR40401PIU40006

PIC40102 PIC40202

PIU40005

PIC41302PIU40205

PIC41401PIR41701

PIR41802

PIU40203

PIC41402

PIR41502

PIR41601

PIR41702

PIU40206

PIR40101

PIU40105

PIR40102

PIR40201PIU40107 PIR40202 PIR40302

PIR40502PIR40402

PIR41501

PIU40202

PIR40702

PIU40103POVOUT1

PIR40801POGAIN0INPUT PIR40901POOFFSET0INPUT

PIR41602 POSERVO0OUT

PIR4110CCW

PIR41401

PIU40008

NLNULL1

PIR41002

PIR4110CW

PIU40001NLNULL2

PIR4200CCW

PIR42101

PIU40208NLNULL3

PIR41902

PIR4200CW

PIU40201NLNULL4

PIC40802

PIR40601

PIR40902

PIR41302

NLOFFSET0CTRLPOGAIN0INPUT POOFFSET0INPUT

POSERVO0OUT

POVOUT1

121

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\Slow_DAC_w_REF.SchDoc Drawn By:

CS2

SCLK3

SDI4

SDO5

LDAC6

RST7

GPI

O-0

8G

PIO

-19

UNI/BIP-A10

DG

ND

11IO

VD

D13

DV

DD

14

VOUT-0 15

RFB2-0 16RFB1-0 17

SGND-0 18

SGND-1 20

RFB1-1 21

RFB2-1 22

VOUT-1 23

AVD

D26

AVD

D35

AG

ND

27

AVSS

28

AVSS

33

REF

GN

D-A

29R

EF-A

30R

EF-B

31

REF

GN

G-B

32

VMON 34

VOUT-3 38

RFB2-3 39RFB1-3 40

SGND-3 41

SGND-2 43

RFB1-2 44

RFB2-2 45

VOUT-2 46

AIN47

UNI/BIP-B48

NC1 NC12 NC19 NC24 NC25 NC36 NC37 NC42

U501DAC8734

0.1uFC505

10uFC503

1uFC504

0.01uFC506

0.1uFC515

10uFC513

1uFC514

0.01uFC516

+12V

-12V

AGND

+12V -12V

AGND

AGND

VSLOW1

VSLOW2

VSLOW3

VSLOW4

VSLOW[1..4]VSLOW[1..4]

1K

R503AGNDCS

SCLKSDISDOLDAC

AIN

POLARITY_APOLARITY_B

RST

CS

SCLK

SDI

SDO

RSTPOLARITY_APOLARITY_B

DNPR507

1KR513

DNPR508

1KR514

+D3.3V +D3.3V

DGND DGND

0

R510

0

R511

0

R512

0

R506

LDAC0

R516

1KR509

DNPR515

+D3.3V

DGND

1K

R502

HACK1

R504

+D3.3V

+D3.3V

SL_CS

SL_SCLK

SL_SDI

SL_SDO

SL_LDAC

DGND

+D3.3V +D5V

AGND1K

R505

AGND

AGND

NC

VIN2

TEMP3

GND4 TRIM/NR 5VOUT 6

NCNC

U500

REF5050

+12V

AGND

AGND

10uFC501 0

R501

10uFC502

AGND

0

R500

47uFC500

AGND

REF

REF

REF

DGND

+D3.3V

1uFC507

0.01uFC508

DGND

+D5V

1uFC509

0.01uFC510

AGND

+12V

1uFC511

0.01uFC512

PIC50001

PIC50002COC500

PIC50101

PIC50102COC501

PIC50201

PIC50202COC502

PIC50301

PIC50302COC503

PIC50401

PIC50402COC504

PIC50501

PIC50502COC505

PIC50601

PIC50602COC506

PIC50701

PIC50702COC507

PIC50801

PIC50802COC508

PIC50901

PIC50902COC509

PIC51001

PIC51002COC510

PIC51101

PIC51102COC511

PIC51201

PIC51202COC512

PIC51301

PIC51302COC513

PIC51401

PIC51402COC514

PIC51501

PIC51502COC515

PIC51601

PIC51602COC516

PIR50001 PIR50002COR500

PIR50101

PIR50102COR501


PIR50301 PIR50302COR503



PIR50601 PIR50602COR506

PIR50701

PIR50702COR507

PIR50801

PIR50802COR508

PIR50901

PIR50902COR509

PIR51001 PIR51002COR510

PIR51101 PIR51102COR511

PIR51201 PIR51202COR512

PIR51301

PIR51302COR513

PIR51401

PIR51402COR514

PIR51501

PIR51502COR515

PIR51601 PIR51602COR516

PIU50001

PIU50002

PIU50003

PIU50004

PIU50005

PIU50006

PIU50007PIU50008

COU500

PIU50101

PIU50102

PIU50103

PIU50104

PIU50105

PIU50106

PIU50107

PIU50108PIU50109

PIU501010

PIU501011

PIU501012

PIU501013 PIU501014

PIU501015

PIU501016

PIU501017

PIU501018

PIU501019

PIU501020

PIU501021

PIU501022

PIU501023

PIU501024

PIU501025

PIU501026

PIU501027

PIU501028 PIU501029PIU501030

PIU501031 PIU501032

PIU501033

PIU501034

PIU501035

PIU501036

PIU501037

PIU501038

PIU501039

PIU501040

PIU501041

PIU501042

PIU501043

PIU501044

PIU501045

PIU501046

PIU501047

PIU501048

COU501


PIU50002

PIU501026 PIU501035

PIC50702 PIC50802

PIR50202

PIR50402

PIR50702 PIR50802 PIR50902

PIU501013

PIC50902 PIC51002

PIU501014

PIC51301 PIC51401 PIC51501 PIC51601

PIU501028 PIU501033 PIC50001PIC50101

PIC50201


PIC51302 PIC51402 PIC51502 PIC51602

PIR50302

PIR50502

PIU50004

PIU501018

PIU501020

PIU501027

PIU501029

PIU501032

PIU501041

PIU501043

PIR50501 PIU501047NLAIN

PIR50201

PIR50601

PIU50102

NLC\S\

PIC50701 PIC50801 PIC50901 PIC51001

PIR51301 PIR51401 PIR51501

PIU501011

PIR50401

PIR51601

PIU50106

NLL\D\A\C\

PIC50102PIU50005

PIC50202

PIR50101

PIR50001

PIR50102PIU50006

PIR50301PIU501034

PIR50602 POSL0CS

PIR51002 POSL0SCLK

PIR51102 POSL0SDI

PIR51202 POSL0SDO

PIR51602 POSL0LDAC

PIU50001

PIU50003

PIU50007PIU50008

PIU50101

PIU50108PIU50109

PIU501012

PIU501016

PIU501019

PIU501022

PIU501024

PIU501025

PIU501036

PIU501037

PIU501039

PIU501042

PIU501045

PIR50801

PIR51402

PIU501010

NLPOLARITY0APIR50701

PIR51302

PIU501048

NLPOLARITY0B

PIR50901

PIR51502

PIU50107

NLR\S\T\

PIC50002PIR50002

PIU501030

PIU501031

NLREF

PIR51001

PIU50103

NLSCLK

PIR51101

PIU50104

NLSDI

PIR51201

PIU50105

NLSDO

PIU501015

PIU501017

NLVSLOW010040

NLVSLOW1

POVSLOW010040

PIU501021

PIU501023

NLVSLOW010040

NLVSLOW2

POVSLOW010040

PIU501044

PIU501046

NLVSLOW010040

NLVSLOW3

POVSLOW010040

PIU501038

PIU501040

NLVSLOW010040

NLVSLOW4

POVSLOW010040

POSL0CS

POSL0LDAC

POSL0SCLK

POSL0SDI

POSL0SDO

POVSLOW1POVSLOW2POVSLOW3POVSLOW4POVSLOW010040

122

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\Interface.SchDoc Drawn By:



DAC_DB11DAC_DB10

DAC_DB5DAC_DB4DAC_DB1DAC_DB0DAC_WRTB

DAC_DA13DAC_DA12DAC_DA9DAC_DA8DAC_DA5

DAC_DA4DAC_DA1DAC_DA0DAC_WRTADAC_DB13DAC_DB12DAC_DB9DAC_DB8

DAC_DB7DAC_DB6DAC_DB3DAC_DB2

ADC_OTRAADC_OTRBADC_DB2ADC_DB3ADC_DB6

ADC_DB7ADC_DB10ADC_DB11

ADC_DA2ADC_DA3ADC_DA6


ADC_DB0ADC_DB1ADC_DB4ADC_DB5ADC_DB8

ADC_DB9ADC_DB12ADC_DB13ADC_DA0ADC_DA1ADC_DA4ADC_DA5ADC_DA8


ADC_OTRAADC_OTRB

DAC_WRTB

DAC_WRTA

ADC_CLKAADC_CLKB

DAC_CLKADAC_CLKB

ADC_CLKAADC_CLKB

DAC_CLKADAC_CLKB

MS_SCLKMS_SDO

MS_LDACMS_SDI

SLAVE1_CSSLAVE2_CS

DGND

DGND

DAC_DA[0..13]DAC_DA[0..13]

DAC_DB[0..13]DAC_DB[0..13]

ADC_DA[0..13]

ADC_DB[0..13]

ADC_DA[0..13]

ADC_DB[0..13]

MS_SCLKMS_SDO

SLAVE2_CSSLAVE1_CS

MS_LDACMS_SDI

Interface to DE2

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

J600

GPIO

1 23 45 67 89 1011 1213 1415 1617 1819 2021 2223 2425 2627 2829 3031 3233 3435 3637 3839 40

J602

GPIO

iADC_CHA ADC_OTRAADC_CLKA

ADC_DA[0..13]iADC_CHAiADC_CHA

iADC_CHBiADC_CHBiADC_CHB

iDAC_CHA

iDAC_CHB

iDAC_CHAiDAC_CHA

iDAC_CHBiDAC_CHB

ADC_CLKBADC_OTRB

DAC_DA[0..13]

DAC_CLKADAC_WRTA

DAC_CLKBDAC_WRTB

ADC_DB[0..13]

DAC_DB[0..13]

PIJ60001 PIJ60002

PIJ60003 PIJ60004

PIJ60005 PIJ60006

PIJ60007 PIJ60008

PIJ60009 PIJ600010

PIJ600011 PIJ600012

PIJ600013 PIJ600014

PIJ600015 PIJ600016

PIJ600017 PIJ600018

PIJ600019 PIJ600020

PIJ600021 PIJ600022

PIJ600023 PIJ600024

PIJ600025 PIJ600026

PIJ600027 PIJ600028

PIJ600029 PIJ600030

PIJ600031 PIJ600032

PIJ600033 PIJ600034

PIJ600035 PIJ600036

PIJ600037 PIJ600038

PIJ600039 PIJ600040

COJ600

PIJ60201 PIJ60202

PIJ60203 PIJ60204

PIJ60205 PIJ60206

PIJ60207 PIJ60208

PIJ60209 PIJ602010

PIJ602011 PIJ602012

PIJ602013 PIJ602014

PIJ602015 PIJ602016

PIJ602017 PIJ602018

PIJ602019 PIJ602020

PIJ602021 PIJ602022

PIJ602023 PIJ602024

PIJ602025 PIJ602026

PIJ602027 PIJ602028

PIJ602029 PIJ602030

PIJ602031 PIJ602032

PIJ602033 PIJ602034

PIJ602035 PIJ602036

PIJ602037 PIJ602038

PIJ602039 PIJ602040

COJ602

PIJ600019

NLADC0CLKA

POADC0CLKAPIJ600021

NLADC0CLKB

POADC0CLKB

PIJ60001

NLADC0OTRA

POADC0OTRAPIJ60003NLADC0OTRB POADC0OTRB

PIJ602019

NLDAC0CLKA

PODAC0CLKAPIJ602021

NLDAC0CLKB

PODAC0CLKBPIJ602020

NLDAC0WRTA

PODAC0WRTA

PIJ602039

NLDAC0WRTB

PODAC0WRTB

PIJ600012

PIJ600030

PIJ602012

PIJ602030

PIJ600038NLMS0LDACPOMS0LDACPIJ600037

NLMS0SCLKPOMS0SCLKPIJ600040

NLMS0SDIPOMS0SDIPIJ600039

NLMS0SDOPOMS0SDO

PIJ600011

PIJ600029

PIJ602011

PIJ602023

PIJ602029

PIJ602040

PIJ60201NLSLAVE10CS

POSLAVE10CSPIJ60203

NLSLAVE20CSPOSLAVE20CS

PIJ600020

NLADC0DA0000130

NLADC0DA0

POADC0DA0000130

PIJ600022

NLADC0DA0000130

NLADC0DA1

POADC0DA0000130

PIJ600023

NLADC0DA0000130

NLADC0DA2

POADC0DA0000130

PIJ600025

NLADC0DA0000130

NLADC0DA3

POADC0DA0000130

PIJ600024

NLADC0DA0000130

NLADC0DA4

POADC0DA0000130

PIJ600026

NLADC0DA0000130

NLADC0DA5

POADC0DA0000130

PIJ600027

NLADC0DA0000130

NLADC0DA6

POADC0DA0000130

PIJ600031

NLADC0DA0000130

NLADC0DA7

POADC0DA0000130

PIJ600028

NLADC0DA0000130

NLADC0DA8

POADC0DA0000130

PIJ600032

NLADC0DA0000130

NLADC0DA9

POADC0DA0000130

PIJ600033

NLADC0DA0000130

NLADC0DA10

POADC0DA0000130

PIJ600035

NLADC0DA0000130

NLADC0DA11

POADC0DA0000130

PIJ600034

NLADC0DA0000130

NLADC0DA12

POADC0DA0000130

PIJ600036

NLADC0DA0000130

NLADC0DA13

POADC0DA0000130

PIJ60002

NLADC0DB0000130

NLADC0DB0

POADC0DB0000130

PIJ60004

NLADC0DB0000130

NLADC0DB1

POADC0DB0000130

PIJ60005NLADC0DB0000130

NLADC0DB2

POADC0DB0000130

PIJ60007NLADC0DB0000130 NLADC0DB3

POADC0DB0000130

PIJ60006NLADC0DB0000130

NLADC0DB4

POADC0DB0000130

PIJ60008NLADC0DB0000130 NLADC0DB5

POADC0DB0000130

PIJ60009

NLADC0DB0000130NLADC0DB6

POADC0DB0000130

PIJ600013

NLADC0DB0000130

NLADC0DB7

POADC0DB0000130

PIJ600010

NLADC0DB0000130NLADC0DB8

POADC0DB0000130

PIJ600014

NLADC0DB0000130

NLADC0DB9

POADC0DB0000130

PIJ600015

NLADC0DB0000130

NLADC0DB10

POADC0DB0000130

PIJ600017

NLADC0DB0000130

NLADC0DB11

POADC0DB0000130

PIJ600016

NLADC0DB0000130

NLADC0DB12

POADC0DB0000130

PIJ600018

NLADC0DB0000130

NLADC0DB13

POADC0DB0000130

PIJ602018

NLDAC0DA0000130

NLDAC0DA0

PODAC0DA0000130

PIJ602016

NLDAC0DA0000130

NLDAC0DA1

PODAC0DA0000130

PIJ602017

NLDAC0DA0000130

NLDAC0DA2

PODAC0DA0000130

PIJ602015

NLDAC0DA0000130

NLDAC0DA3

PODAC0DA0000130

PIJ602014

NLDAC0DA0000130

NLDAC0DA4

PODAC0DA0000130

PIJ602010

NLDAC0DA0000130

NLDAC0DA5

PODAC0DA0000130

PIJ602013

NLDAC0DA0000130

NLDAC0DA6

PODAC0DA0000130

PIJ60209

NLDAC0DA0000130

NLDAC0DA7

PODAC0DA0000130

PIJ60208

NLDAC0DA0000130

NLDAC0DA8

PODAC0DA0000130

PIJ60206

NLDAC0DA0000130

NLDAC0DA9

PODAC0DA0000130

PIJ60207

NLDAC0DA0000130

NLDAC0DA10

PODAC0DA0000130

PIJ60205

NLDAC0DA0000130

NLDAC0DA11

PODAC0DA0000130

PIJ60204

NLDAC0DA0000130

NLDAC0DA12

PODAC0DA0000130

PIJ60202

NLDAC0DA0000130

NLDAC0DA13

PODAC0DA0000130

PIJ602037

NLDAC0DB0000130

NLDAC0DB0

PODAC0DB0000130

PIJ602035

NLDAC0DB0000130

NLDAC0DB1

PODAC0DB0000130

PIJ602038

NLDAC0DB0000130

NLDAC0DB2

PODAC0DB0000130

PIJ602036

NLDAC0DB0000130

NLDAC0DB3

PODAC0DB0000130

PIJ602033

NLDAC0DB0000130

NLDAC0DB4

PODAC0DB0000130

PIJ602031

NLDAC0DB0000130

NLDAC0DB5

PODAC0DB0000130

PIJ602034

NLDAC0DB0000130

NLDAC0DB6

PODAC0DB0000130

PIJ602032

NLDAC0DB0000130

NLDAC0DB7

PODAC0DB0000130

PIJ602028

NLDAC0DB0000130

NLDAC0DB8

PODAC0DB0000130

PIJ602026

NLDAC0DB0000130

NLDAC0DB9

PODAC0DB0000130

PIJ602027

NLDAC0DB0000130

NLDAC0DB10

PODAC0DB0000130

PIJ602025

NLDAC0DB0000130

NLDAC0DB11

PODAC0DB0000130

PIJ602024

NLDAC0DB0000130

NLDAC0DB12

PODAC0DB0000130

PIJ602022

NLDAC0DB0000130

NLDAC0DB13

PODAC0DB0000130

POADC0CLKAPOADC0CLKB

POADC0DA0POADC0DA1POADC0DA2POADC0DA3POADC0DA4POADC0DA5POADC0DA6POADC0DA7POADC0DA8POADC0DA9POADC0DA10POADC0DA11POADC0DA12POADC0DA13POADC0DA0000130

POADC0DB0POADC0DB1POADC0DB2POADC0DB3POADC0DB4POADC0DB5POADC0DB6POADC0DB7POADC0DB8POADC0DB9POADC0DB10POADC0DB11POADC0DB12POADC0DB13POADC0DB0000130

POADC0OTRAPOADC0OTRB

PODAC0CLKAPODAC0CLKB

PODAC0DA0PODAC0DA1PODAC0DA2PODAC0DA3PODAC0DA4PODAC0DA5PODAC0DA6PODAC0DA7PODAC0DA8PODAC0DA9PODAC0DA10PODAC0DA11PODAC0DA12PODAC0DA13PODAC0DA0000130

PODAC0DB0PODAC0DB1PODAC0DB2PODAC0DB3PODAC0DB4PODAC0DB5PODAC0DB6PODAC0DB7PODAC0DB8PODAC0DB9PODAC0DB10PODAC0DB11PODAC0DB12PODAC0DB13PODAC0DB0000130

PODAC0WRTA

PODAC0WRTB

POMS0LDACPOMS0SCLKPOMS0SDIPOMS0SDO

POSLAVE10CSPOSLAVE20CS

123

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\Power.SchDoc Drawn By:

AGND

/SHDN1

GND2

IN3

ADJ 4

OUT 5

TAB/IN6

U701

LT3015

/SHDN1

IN2

GND3

OUT 4

ADJ 5

TAB/GND6

U700

LT1963

VIN+

VIN-

12V

10uFC706

1uFC709

0.01uFC710

10uFC711

1uFC712

0.1uFC713

0.1uFC714

0.01uFC715

10KR700

1K2R701

10uFC727

1uFC730

0.01uFC731 10uF

C7221uFC723

0.1uFC724

0.1uFC725

0.01uFC726

12.1KR702

100KR703

HACK3

L701

HACK3

L704

10uFC708

10uFC707

10uFC728

10uFC729

AGND

AGND

AGNDAGND

AGND

+12V

-12V

AGND

/SHDN1

GND2

IN3

ADJ 4

OUT 5

TAB/IN6

U705

LT3015

/SHDN1

IN2

GND3

OUT 4

ADJ 5

TAB/GND6

U703

LT1963

12V

10uFC739

10uFC740

0.1uFC741

10uFC742

1uFC743

0.1uFC744

0.1uFC745

0.01uFC746

3K3R705

1KR707

10uFC759

10uFC760

0.1uFC761 10uF

C7541uFC755

0.1uFC756

0.1uFC757

0.01uFC758

10KR708

33KR710

AGND

AGND

AGNDAGND

AGND

+5V

-5V

+12V

-12V

/SHDN1

IN2

GND3

OUT 4

ADJ 5

TAB/GND6

U702

LT1963

10uFC732

0.1uFC733

10uFC734

1uFC735

0.1uFC736

0.1uFC737

0.01uFC738

2KR704

1KR706

AGND

AGND

+12V

AGND

+A3.3V

AGND

+A3.3V

HACK3

L700

10uFC703

10uFC700

HACK3

L7020.1uFC701

0.01uFC702

0.1uFC704

0.01uFC705

DGND

+D3.3V

/SHDN1

IN2

GND3

OUT 4

ADJ 5

TAB/GND6

U704

LT1963

10uFC747

0.1uFC748

10uFC749

1uFC750

0.1uFC751

0.1uFC752

0.01uFC753

3K3R709

1KR711

AGND

AGND

+12V

AGND

+A5V

AGND

+A5V

HACK3

L703

10uFC719

10uFC716

0.1uFC717

0.01uFC718

0.1uFC720

0.01uFC721

DGND

+D5V

VIN_FILTERED+

VIN_FILTERED-

12

J701

Header 2

123

J700

Header 3

VIN+

VIN-AGND AGND

+24V

PIC70001

PIC70002COC700

PIC70101

PIC70102COC701

PIC70201

PIC70202COC702

PIC70301

PIC70302COC703

PIC70401

PIC70402COC704

PIC70501

PIC70502COC705

PIC70601

PIC70602COC706

PIC70701

PIC70702COC707

PIC70801

PIC70802COC708

PIC70901

PIC70902COC709

PIC71001

PIC71002COC710

PIC71101

PIC71102COC711

PIC71201

PIC71202COC712

PIC71301

PIC71302COC713

PIC71401

PIC71402COC714

PIC71501

PIC71502COC715

PIC71601

PIC71602COC716

PIC71701

PIC71702COC717

PIC71801

PIC71802COC718

PIC71901

PIC71902COC719

PIC72001

PIC72002COC720

PIC72101

PIC72102COC721

PIC72201

PIC72202COC722

PIC72301

PIC72302COC723

PIC72401

PIC72402COC724

PIC72501

PIC72502COC725

PIC72601

PIC72602COC726PIC72701

PIC72702COC727

PIC72801

PIC72802COC728

PIC72901

PIC72902COC729

PIC73001

PIC73002COC730

PIC73101

PIC73102COC731

PIC73201

PIC73202COC732

PIC73301

PIC73302COC733

PIC73401

PIC73402COC734

PIC73501

PIC73502COC735

PIC73601

PIC73602COC736

PIC73701

PIC73702COC737

PIC73801

PIC73802COC738

PIC73901

PIC73902COC739

PIC74001

PIC74002COC740

PIC74101

PIC74102COC741

PIC74201

PIC74202COC742

PIC74301

PIC74302COC743

PIC74401

PIC74402COC744

PIC74501

PIC74502COC745

PIC74601

PIC74602COC746

PIC74701

PIC74702COC747

PIC74801

PIC74802COC748

PIC74901

PIC74902COC749

PIC75001

PIC75002COC750

PIC75101

PIC75102COC751

PIC75201

PIC75202COC752

PIC75301

PIC75302COC753

PIC75401

PIC75402COC754

PIC75501

PIC75502COC755

PIC75601

PIC75602COC756

PIC75701

PIC75702COC757

PIC75801

PIC75802COC758PIC75901

PIC75902COC759

PIC76001

PIC76002COC760

PIC76101

PIC76102COC761

PIJ70001

PIJ70002

PIJ70003

COJ700

PIJ70101

PIJ70102

COJ701

PIL70001 PIL70002

COL700

PIL70101 PIL70102

COL701

PIL70201 PIL70202

COL702

PIL70301 PIL70302

COL703

PIL70401 PIL70402

COL704

PIR70001

PIR70002COR700

PIR70101

PIR70102COR701

PIR70201

PIR70202COR702

PIR70301

PIR70302COR703

PIR70401

PIR70402COR704

PIR70501

PIR70502COR705

PIR70601

PIR70602COR706

PIR70701

PIR70702COR707

PIR70801

PIR70802COR708

PIR70901

PIR70902COR709

PIR71001

PIR71002COR710

PIR71101

PIR71102COR711

PIU70001

PIU70002

PIU70003

PIU70004

PIU70005

PIU70006

COU700

PIU70101

PIU70102

PIU70103

PIU70104

PIU70105

PIU70106

COU701

PIU70201

PIU70202

PIU70203

PIU70204

PIU70205

PIU70206

COU702

PIU70301

PIU70302

PIU70303

PIU70304

PIU70305

PIU70306

COU703

PIU70401

PIU70402

PIU70403

PIU70404

PIU70405

PIU70406

COU704

PIU70501

PIU70502

PIU70503

PIU70504

PIU70505

PIU70506

COU705

PIC74202 PIC74302 PIC74402 PIC74502 PIC74602PIR70502PIU70304

PIC71102 PIC71202 PIC71302 PIC71402 PIC71502

PIC73202 PIC73302

PIC73901 PIC74002 PIC74102

PIC74702 PIC74802

PIR70002PIU70004

PIU70201

PIU70202

PIU70301

PIU70302

PIU70401

PIU70402

PIJ70101

PIC70002 PIC70102 PIC70202


PIL70001

PIR70402PIU70204

PIC71602 PIC71702 PIC71802


PIL70301

PIR70902PIU70404

PIC70302 PIC70402 PIC70502PIL70002

PIC71902 PIC72002 PIC72102PIL70302

PIC75401 PIC75501 PIC75601 PIC75701 PIC75801PIR71001PIU70505


PIC75902 PIC76001 PIC76101

PIR70301PIU70105

PIU70501

PIU70503

PIU70506

PIC70001 PIC70101 PIC70201

PIC70602PIC70701 PIC70801 PIC70901 PIC71001 PIC71101 PIC71201 PIC71301 PIC71401 PIC71501

PIC71601 PIC71701 PIC71801PIC72202 PIC72302 PIC72402 PIC72502 PIC72602

PIC72701PIC72802 PIC72902 PIC73002 PIC73102

PIC73201 PIC73301 PIC73401 PIC73501 PIC73601 PIC73701 PIC73801


PIC74701 PIC74801 PIC74901 PIC75001 PIC75101 PIC75201 PIC75301

PIC75402 PIC75502 PIC75602 PIC75702 PIC75802PIC75901 PIC76002 PIC76102

PIJ70002 PIJ70102

PIL70201

PIR70101 PIR70202

PIR70601

PIR70701 PIR70802

PIR71101

PIU70003

PIU70006

PIU70102

PIU70203

PIU70206

PIU70303

PIU70306

PIU70403

PIU70406PIU70502

PIC70301 PIC70401 PIC70501

PIC71901 PIC72001 PIC72101

PIL70202

PIR70001

PIR70102

PIU70005

PIR70201

PIR70302

PIU70104

PIR70401

PIR70602

PIU70205

PIR70501

PIR70702

PIU70305

PIR70801

PIR71002

PIU70504

PIR70901

PIR71102

PIU70405

PIC70702

PIJ70001

PIL70101

PIC72801

PIJ70003

PIL70401

PIC70601PIC70802 PIC70902 PIC71002PIL70102

PIU70001

PIU70002NLVIN0FILTERED0

PIC72702PIC72901 PIC73001 PIC73101

PIL70402

PIU70101

PIU70103

PIU70106NLVIN0FILTERED0

124

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\Input_Manual_Offset.SchDoc Drawn By:

NC

VIN2

TEMP3


NCNC

U801

REF5050

+12V

AGND

AGND

100pFC806 1K

R804

100pFC809

AGND

3

26

74

U800OPA735 or AD829

+12V

-12VAGND

1K

R800

R803Value

AGND

100pFC808

AGND

1K

R801

MANUAL_OFFSET1K

R802

1KR805

100pFC807

AGND

100pFC802

100pFC800

100pFC801

100pFC803

100pFC804

100pFC805

+12V

-12V

AGND

PIC80001

PIC80002COC800

PIC80101

PIC80102COC801

PIC80201

PIC80202COC802

PIC80301

PIC80302COC803

PIC80401

PIC80402COC804

PIC80501

PIC80502COC805

PIC80601

PIC80602COC806

PIC80701

PIC80702COC807

PIC80801

PIC80802COC808

PIC80901

PIC80902COC809

PIR80001 PIR80002COR800

PIR80101 PIR80102COR801

PIR80201 PIR80202COR802

PIR8030CCW

PIR8030CWPIR8030W

COR803

PIR80401

PIR80402COR804

PIR80501

PIR80502COR805

PIU80002

PIU80003

PIU80004

PIU80006

PIU80007 COU800

PIU80101

PIU80102

PIU80103

PIU80104

PIU80105

PIU80106

PIU80107PIU80108

COU801

PIC80002 PIC80102 PIC80202 PIC80302

PIU80007PIU80102

PIC80401 PIC80501

PIU80004

PIC80001 PIC80101 PIC80201 PIC80301

PIC80402 PIC80502

PIC80601PIC80701

PIC80801PIC80901

PIR8030CCW

PIR80501

PIU80003PIU80104 PIC80602PIU80105

PIC80702

PIR80202

PIR80502

POMANUAL0OFFSET

PIC80802

PIR80101

PIR8030W

PIC80902

PIR80401

PIR80001

PIR80102 PIU80002

PIR80002

PIR80201PIU80006PIR8030CWPIR80402PIU80106

PIU80101

PIU80103

PIU80107PIU80108

POMANUAL0OFFSET

125

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A4

Date: 2016-06-07 Sheet ofFile: C:\Users\..\VOCM_generate.SchDoc Drawn By:

NC

VIN2

TEMP3


NCNC

U901

REF5050

+12V

AGND

AGND

10uFC901 0

R902

10uFC902

AGND

6K8

R900

10uFC900

AGND

2

3

1

74

6

5

8 U900AD829JR

3K3R903

AGND

+12V

-12V

VOCM0

R901

DNP

R904ADC_VREF

1uFC903

0.1uFC904

1uFC905

0.1uFC906

+12V

-12V

AGND

1uFC907

0.1uFC908

+12V

AGND

PIC90001

PIC90002COC900

PIC90101

PIC90102COC901

PIC90201

PIC90202COC902

PIC90301

PIC90302COC903

PIC90401

PIC90402COC904

PIC90501

PIC90502COC905

PIC90601

PIC90602COC906

PIC90701

PIC90702COC907

PIC90801

PIC90802COC908

PIR90001 PIR90002COR900

PIR90101 PIR90102COR901

PIR90201

PIR90202COR902

PIR90301

PIR90302COR903

PIR90401 PIR90402COR904

PIU90001

PIU90002

PIU90003

PIU90004PIU90005

PIU90006

PIU90007PIU90008COU900

PIU90101

PIU90102

PIU90103

PIU90104

PIU90105

PIU90106

PIU90107PIU90108

COU901

PIC90302 PIC90402

PIC90702 PIC90802

PIU90007PIU90102

PIC90501 PIC90601

PIU90004PIC90001PIC90101

PIC90201

PIC90301 PIC90401

PIC90502 PIC90602PIC90701 PIC90801

PIR90301

PIU90104 PIC90002PIR90002

PIR90302 PIU90003PIC90102PIU90105

PIC90202

PIR90201

PIR90001

PIR90202PIU90106

PIR90101

PIU90002

PIU90006 PIR90102

PIR90402

POVOCM

PIR90401POADC0VREF

PIU90001

PIU90005

PIU90008

PIU90101

PIU90103

PIU90107PIU90108

POADC0VREF

POVOCM

126

PAC10002 PAC10001COC100

PAC10102 PAC10101COC101

PAC10202 PAC10201COC102

PAC10302 PAC10301COC103

PAC10402PAC10401COC104




PAC10802 PAC10801COC108

PAC10902 PAC10901COC109PAC11002 PAC11001COC110

PAC11102 PAC11101COC111







PAC20302 PAC20301COC203

PAC20402 PAC20401COC204

PAC20502 PAC20501COC205

PAC20602 PAC20601COC206

PAC20702 PAC20701COC207




PAC21102 PAC21101COC211

PAC21202 PAC21201COC212

PAC21302 PAC21301COC213




PAC21702PAC21701COC217PAC21802PAC21801

COC218

PAC21902 PAC21901COC219





PAC300A02 PAC300A01COC300A

PAC300B02 PAC300B01COC300B







PAC304A02PAC304A01COC304A

PAC304B02PAC304B01COC304B











































































































PAC70002

PAC70001COC700

PAC70102

PAC70101COC701

PAC70202

PAC70201COC702

PAC70302

PAC70301COC703

PAC70402

PAC70401COC704

PAC70502

PAC70501COC705

PAC70601

PAC70602

COC706

PAC70702

PAC70701COC707

PAC70802

PAC70801

COC708PAC70902

PAC70901COC709

PAC71002

PAC71001COC710

PAC71102

PAC71101

COC711PAC71202

PAC71201COC712

PAC71302

PAC71301

COC713PAC71402

PAC71401

COC714PAC71502

PAC71501COC715

PAC71602

PAC71601COC716

PAC71702

PAC71701COC717

PAC71802

PAC71801COC718

PAC71902

PAC71901COC719

PAC72002

PAC72001COC720

PAC72102

PAC72101COC721

PAC72202

PAC72201COC722

PAC72302

PAC72301

COC723

PAC72402

PAC72401COC724

PAC72502

PAC72501COC725

PAC72602

PAC72601

COC726

PAC72701

PAC72702

COC727

PAC72802

PAC72801

COC728PAC72902

PAC72901COC729

PAC73002

PAC73001

COC730PAC73102

PAC73101

COC731

PAC73202

PAC73201

COC732PAC73302

PAC73301COC733

PAC73402

PAC73401COC734

PAC73502

PAC73501

COC735PAC73602

PAC73601COC736

PAC73702

PAC73701COC737

PAC73802

PAC73801

COC738

PAC73901

PAC73902COC739

PAC74002

PAC74001

COC740PAC74102

PAC74101

COC741

PAC74202

PAC74201COC742

PAC74302

PAC74301

COC743PAC74402

PAC74401COC744

PAC74502

PAC74501

COC745PAC74602

PAC74601COC746

PAC74702

PAC74701

COC747PAC74802

PAC74801COC748

PAC74902

PAC74901

COC749PAC75002

PAC75001COC750

PAC75102

PAC75101

COC751PAC75202

PAC75201COC752

PAC75302

PAC75301

COC753

PAC75402

PAC75401

COC754PAC75502

PAC75501COC755

PAC75602

PAC75601

COC756PAC75702

PAC75701COC757

PAC75802

PAC75801

COC758

PAC75901

PAC75902

COC759

PAC76002

PAC76001COC760

PAC76102

PAC76101

COC761




























PAC90701 PAC90702COC907

PAC90801 PAC90802COC908

PAJ101PAJ103

PAJ104PAJ105

PAJ102

COJ1

PAJ201PAJ203

PAJ204PAJ205

PAJ202

COJ2

PAJ304

PAJ302

PAJ301PAJ303

COJ3

PAJ404

PAJ402

PAJ401PAJ403

COJ4

PAJ501PAJ503

PAJ504PAJ505

PAJ502

COJ5

PAJ601PAJ603

PAJ604PAJ605

PAJ602

COJ6

PAJ701

PAJ703

PAJ704PAJ705

PAJ702

COJ7

PAJ801PAJ803

PAJ804PAJ805

PAJ802

COJ8

PAJ904

PAJ902

PAJ901PAJ903

COJ9

PAJ1004

PAJ1002

PAJ1001PAJ1003

COJ10

PAJ1101PAJ1103

PAJ1104PAJ1105

PAJ1102

COJ11

PAJ1201PAJ1203

PAJ1204PAJ1205

PAJ1202

COJ12

PAJ1301PAJ1303

PAJ1304PAJ1305

PAJ1302

COJ13

PAJ1401PAJ1403

PAJ1404PAJ1405

PAJ1402

COJ14

PAJ600040PAJ600039

PAJ600038PAJ600037

PAJ600036PAJ600035

PAJ600034PAJ600033

PAJ600032PAJ600031

PAJ600030PAJ600029

PAJ600028PAJ600027

PAJ600026PAJ600025

PAJ600024PAJ600023

PAJ600022PAJ600021

PAJ600020PAJ600019

PAJ600018PAJ600017

PAJ600016PAJ600015

PAJ600014PAJ600013

PAJ600012PAJ600011

PAJ600010PAJ60009

PAJ60008PAJ60007

PAJ60006PAJ60005

PAJ60004PAJ60003

PAJ60002PAJ60001

COJ600

PAJ602040PAJ602039

PAJ602038PAJ602037

PAJ602036PAJ602035

PAJ602034PAJ602033

PAJ602032PAJ602031

PAJ602030PAJ602029

PAJ602028PAJ602027

PAJ602026PAJ602025

PAJ602024PAJ602023

PAJ602022PAJ602021

PAJ602020PAJ602019

PAJ602018PAJ602017

PAJ602016PAJ602015

PAJ602014PAJ602013

PAJ602012PAJ602011

PAJ602010PAJ60209

PAJ60208PAJ60207

PAJ60206PAJ60205

PAJ60204PAJ60203

PAJ60202PAJ60201

COJ602

PAJ70001

PAJ70002

PAJ70003

COJ700

PAJ70102

PAJ70101COJ701

PAL70001

PAL70002COL700

PAL70101PAL70102COL701

PAL70201

PAL70202COL702

PAL70301

PAL70302COL703 PAL70401PAL70402

COL704

PAR10002PAR10001COR100


PAR10202 PAR10201COR102

PAR10302 PAR10301COR103



PAR10602 PAR10601COR106

PAR10702 PAR10701COR107

PAR10802 PAR10801COR108

PAR10902 PAR10901COR109

PAR11002 PAR11001COR110PAR11102 PAR11101COR111

PAR11202 PAR11201COR112

PAR11302 PAR11301COR113

PAR20002 PAR20001COR200


PAR20302 PAR20301COR203

PAR20402 PAR20401COR204


PAR20702 PAR20701COR207

PAR20802 PAR20801COR208

PAR20902 PAR20901COR209

PAR21002 PAR21001COR210

PAR21102 PAR21101COR211

PAR21602 PAR21601COR216

PAR21702 PAR21701COR217

PAR21802 PAR21801COR218

PAR21902 PAR21901COR219

PAR300A02 PAR300A01COR300A

PAR300B02 PAR300B01COR300B

PAR301A02PAR301A01COR301A

PAR301B02PAR301B01COR301B

































PAR318A0CCW

PAR318A0W

PAR318A0CWCOR318A

PAR318B0CCW

PAR318B0W

PAR318B0CWCOR318B

































PAR411A0CW

PAR411A0W

PAR411A0CCWCOR411A

PAR411B0CCW

PAR411B0W

PAR411B0CWCOR411B

















PAR420A0CW

PAR420A0W

PAR420A0CCWCOR420A

PAR420B0CCW

PAR420B0W

PAR420B0CWCOR420B





































PAR70002

PAR70001COR700

PAR70102

PAR70101

COR701

PAR70202

PAR70201COR702

PAR70302

PAR70301

COR703

PAR70402

PAR70401

COR704

PAR70502

PAR70501

COR705

PAR70602

PAR70601COR706

PAR70702

PAR70701COR707

PAR70802

PAR70801

COR708

PAR70902

PAR70901COR709

PAR71002

PAR71001COR710

PAR71102

PAR71101

COR711







PAR803A0CW

PAR803A0W

PAR803A0CCWCOR803A

PAR803B0CW

PAR803B0W

PAR803B0CCWCOR803B






PAR90101 PAR90102COR901

PAR90201 PAR90202COR902



PAU10001PAU10002PAU10003PAU10004PAU10005PAU10006PAU10007PAU10008PAU10009PAU100010PAU100011PAU100012PAU100013PAU100014PAU100015PAU100016PAU100017PAU100018PAU100019PAU100020PAU100021PAU100022PAU100023PAU100024

PAU100025PAU100026PAU100027PAU100028PAU100029PAU100030PAU100031PAU100032PAU100033PAU100034PAU100035PAU100036PAU100037PAU100038PAU100039PAU100040PAU100041PAU100042PAU100043PAU100044PAU100045PAU100046PAU100047PAU100048

COU100

PAU200016PAU200015PAU200014

PAU200013PAU200012

PAU200011PAU200010PAU20009

PAU20008PAU20007PAU20006PAU20005PAU20004PAU20003PAU20002

PAU20001

PAU200032PAU200031PAU200030PAU200029PAU200028PAU200027PAU200026PAU200025PAU200024PAU200023PAU200022PAU200021PAU200020PAU200019PAU200018PAU200017



COU200

PAU300A01PAU300A02PAU300A03PAU300A04


COU300A

PAU300B01PAU300B02PAU300B03PAU300B04


COU300B



COU301A



COU301B



COU302A



COU302B



COU400A



COU400B



COU401A


PAU401B08PAU401B07PAU401B06PAU401B05COU401B



COU402A



COU402B

PAU500A01

PAU500A02

PAU500A03PAU500A04

PAU500A08

PAU500A07

PAU500A06PAU500A05COU500A

PAU500B01

PAU500B02

PAU500B03

PAU500B04

PAU500B08

PAU500B07

PAU500B06

PAU500B05COU500B

PAU501A01PAU501A02PAU501A03PAU501A04PAU501A05PAU501A06PAU501A07PAU501A08PAU501A09PAU501A010PAU501A011PAU501A012

PAU501A013PAU501A014PAU501A015PAU501A016PAU501A017PAU501A018PAU501A019PAU501A020PAU501A021PAU501A022PAU501A023PAU501A024PAU501A025PAU501A026PAU501A027PAU501A028PAU501A029PAU501A030PAU501A031PAU501A032PAU501A033PAU501A034PAU501A035PAU501A036

PAU501A037PAU501A038PAU501A039PAU501A040PAU501A041PAU501A042PAU501A043PAU501A044PAU501A045PAU501A046PAU501A047PAU501A048COU501A

PAU501B01

PAU501B02PAU501B03

PAU501B04PAU501B05PAU501B06PAU501B07PAU501B08PAU501B09PAU501B010PAU501B011PAU501B012

PAU501B013PAU501B014PAU501B015PAU501B016PAU501B017PAU501B018PAU501B019PAU501B020PAU501B021PAU501B022PAU501B023PAU501B024PAU501B025PAU501B026PAU501B027PAU501B028PAU501B029PAU501B030PAU501B031PAU501B032PAU501B033PAU501B034PAU501B035PAU501B036

PAU501B037PAU501B038PAU501B039PAU501B040PAU501B041PAU501B042PAU501B043PAU501B044PAU501B045PAU501B046PAU501B047PAU501B048COU501B

PAU70001

PAU70002PAU70003

PAU70004

PAU70005PAU70006

COU700

PAU70101PAU70102

PAU70103

PAU70104

PAU70105PAU70106

COU701

PAU70201PAU70202

PAU70203

PAU70204PAU70205PAU70206

COU702

PAU70301

PAU70302

PAU70303PAU70304PAU70305PAU70306

COU703

PAU70401

PAU70402

PAU70403PAU70404

PAU70405PAU70406

COU704

PAU70501

PAU70502PAU70503PAU70504

PAU70505PAU70506COU705



COU800A



COU800B



COU801A



COU801B

PAU90005 PAU90006 PAU90007 PAU90008

PAU90004 PAU90003 PAU90002 PAU90001COU900

PAU90105 PAU90106 PAU90107 PAU90108

PAU90104 PAU90103 PAU90102 PAU90101COU901

PAC313A02PAC313B02PAC314A02PAC314B02PAC315A02PAC315B02PAC316A02PAC316B02PAC405A02PAC405B02PAC406A02PAC406B02PAC74202PAC74302PAC74402PAC74502PAC74602PAR70502

PAU301A03PAU301B03

PAU302A08PAU302B08PAU401A08PAU401B08

PAU70304

PAC311A02PAC311B02PAC312A02PAC312B02PAC403A02PAC403B02PAC404A02PAC404B02PAC503A02PAC503B02PAC504A02PAC504B02PAC505A02PAC505B02PAC506A02PAC506B02PAC511A02PAC511B02PAC512A02PAC512B02PAC71102PAC71202PAC71302PAC71402PAC71502PAC73202PAC73302

PAC73901

PAC74002PAC74102PAC74702PAC74802PAC800A02PAC800B02PAC801A02PAC801B02PAC802A02PAC802B02PAC803A02PAC803B02PAC90302PAC90402PAC90702PAC90802PAR70002PAU300A07PAU300B07PAU400A07PAU400B07

PAU500A02PAU500B02

PAU501A026

PAU501A035

PAU501B026

PAU501B035

PAU70004

PAU70201PAU70202PAU70301PAU70302PAU70401PAU70402

PAU800A07PAU800B07

PAU801A02PAU801B02

PAU90007

PAU90102

PAC415A02PAC415B02PAC416A02PAC416B02

PAJ70101

PAU402A07PAU402B07PAC10002PAC10102PAC10202PAC10302PAC10402PAC10502PAC10602PAC10702PAC20002PAC20102PAC20202PAC20302PAC20402PAC20502PAC20602PAC20702PAC70002PAC70102PAC70202PAC73402PAC73502PAC73602PAC73702PAC73802

PAL70001

PAR10002PAR10102PAR20802PAR20902PAR21002PAR21102PAR70402

PAU100047

PAU20005

PAU200012

PAU200017

PAU200064

PAU70204

PAC71602PAC71702PAC71802PAC74902PAC75002PAC75102PAC75202PAC75302

PAL70301

PAR70902

PAU70404

PAC10902PAC11002PAC11102PAC11202PAC11302PAC11402PAC20802PAC20902PAC21002PAC21102PAC21202PAC21302PAC507A02PAC507B02PAC508A02PAC508B02PAC70302PAC70402PAC70502

PAL70002

PAR10202PAR10302PAR20002PAR20102PAR20202PAR20302PAR502A02PAR502B02PAR504A02PAR504B02PAR507A02PAR507B02PAR508A02PAR508B02PAR509A02PAR509B02

PAU100016 PAU100022

PAU200029

PAU200041

PAU200052

PAU501A013PAU501B013

PAC509A02PAC509B02PAC510A02PAC510B02PAC71902PAC72002PAC72102

PAL70302


PAC321A01PAC321B01PAC322A01PAC322B01PAC323A01PAC323B01PAC324A01PAC324B01PAC411A01PAC411B01PAC412A01PAC412B01PAC417A01PAC417B01PAC418A01PAC418B01PAC75401PAC75501PAC75601PAC75701PAC75801PAR419A01PAR419B01PAR420A0WPAR420B0W

PAR421A02PAR421B02PAR71001

PAU301A06PAU301B06


PAU402A04PAU402B04

PAU70505

PAC319A01PAC319B01PAC320A01PAC320B01PAC409A01PAC409B01PAC410A01PAC410B01PAC513A01PAC513B01PAC514A01PAC514B01PAC515A01PAC515B01PAC516A01PAC516B01PAC72201PAC72301PAC72401PAC72501PAC72601

PAC75902

PAC76001PAC76101PAC804A01PAC804B01PAC805A01PAC805B01PAC90501PAC90601PAR317A01PAR317B01PAR318A0WPAR318B0W

PAR319A02PAR319B02PAR410A01PAR410B01PAR411A0WPAR411B0W



PAU501A028

PAU501A033

PAU501B028

PAU501B033

PAU70105

PAU70501

PAU70503 PAU70506

PAU800A04PAU800B04PAU90004

PAJ600019

PAR20001 PAR20402

PAU200063

PAJ600021

PAR20101 PAR20502

PAU200018

PAJ600020

PAU200042

PAJ600022

PAU200043

PAJ600023

PAU200044

PAJ600025

PAU200045

PAJ600024

PAU200046

PAJ600026

PAU200047

PAJ600027

PAU200048

PAJ600031

PAU200049

PAJ600028

PAU200050

PAJ600032

PAU200051

PAJ600033

PAU200054

PAJ600035

PAU200055

PAJ600034

PAU200056

PAJ600036

PAU200057

PAJ60002

PAU200023

PAJ60004

PAU200024PAJ60005

PAU200025PAJ60007 PAU200026PAJ60006

PAU200027PAJ60008 PAU200030

PAJ60009

PAU200031

PAJ600013

PAU200032

PAJ600010

PAU200033

PAJ600014

PAU200034

PAJ600015

PAU200035

PAJ600017

PAU200036

PAJ600016

PAU200037

PAJ600018

PAU200038

PAR20801 PAR21602

PAU200059

PAR20901 PAR21702

PAU200022

PAJ60001

PAU200058

PAJ60003

PAU200039

PAR21101 PAR21902

PAU200021

PAU200060

PAC10001PAC10101PAC10201PAC10301PAC10401PAC10501PAC10601PAC10701PAC10801PAC20001PAC20101PAC20201PAC20301PAC20401PAC20501PAC20601PAC20701 PAC21402PAC21702PAC21801PAC21901 PAC22002PAC22302PAC302A01PAC302B01PAC303A01PAC303B01 PAC304A02PAC304B02PAC305A02PAC305B02PAC307A01PAC307B01PAC311A01PAC311B01PAC312A01PAC312B01PAC313A01PAC313B01PAC314A01PAC314B01PAC315A01PAC315B01PAC316A01PAC316B01 PAC319A02PAC319B02PAC320A02PAC320B02PAC321A02PAC321B02PAC322A02PAC322B02PAC323A02PAC323B02PAC324A02PAC324B02PAC325A01PAC325B01PAC402A01PAC402B01PAC403A01PAC403B01PAC404A01PAC404B01PAC405A01PAC405B01PAC406A01PAC406B01PAC407A01PAC407B01PAC408A01PAC408B01 PAC409A02PAC409B02PAC410A02PAC410B02PAC411A02PAC411B02PAC412A02PAC412B02PAC413A01PAC413B01PAC415A01PAC415B01PAC416A01PAC416B01 PAC417A02PAC417B02PAC418A02PAC418B02PAC500A01PAC500B01PAC501A01PAC501B01PAC502A01PAC502B01PAC503A01PAC503B01PAC504A01PAC504B01PAC505A01PAC505B01PAC506A01PAC506B01PAC511A01PAC511B01PAC512A01PAC512B01 PAC513A02PAC513B02PAC514A02PAC514B02PAC515A02PAC515B02PAC516A02PAC516B02PAC70001PAC70101PAC70201

PAC70602

PAC70701PAC70801PAC70901PAC71001PAC71101PAC71201PAC71301PAC71401PAC71501PAC71601PAC71701PAC71801 PAC72202PAC72302PAC72402PAC72502PAC72602

PAC72701

PAC72802PAC72902PAC73002PAC73102PAC73201PAC73301PAC73401PAC73501PAC73601PAC73701PAC73801

PAC73902

PAC74001PAC74101PAC74201PAC74301PAC74401PAC74501PAC74601PAC74701PAC74801PAC74901PAC75001PAC75101PAC75201PAC75301 PAC75402PAC75502PAC75602PAC75702PAC75802

PAC75901

PAC76002PAC76102PAC800A01PAC800B01PAC801A01PAC801B01PAC802A01PAC802B01PAC803A01PAC803B01 PAC804A02PAC804B02PAC805A02PAC805B02PAC806A01PAC806B01PAC807A01PAC807B01PAC808A01PAC808B01PAC809A01PAC809B01PAC90001PAC90101PAC90201PAC90301PAC90401 PAC90502PAC90602PAC90701PAC90801

PAJ102 PAJ103

PAJ104PAJ105

PAJ202 PAJ203

PAJ204PAJ205

PAJ302PAJ304

PAJ402PAJ404

PAJ502 PAJ503

PAJ504PAJ505

PAJ602 PAJ603

PAJ604PAJ605

PAJ702 PAJ703

PAJ704PAJ705

PAJ802 PAJ803

PAJ804PAJ805

PAJ902PAJ904

PAJ1002PAJ1004

PAJ1102 PAJ1103

PAJ1104PAJ1105

PAJ1202 PAJ1203

PAJ1204PAJ1205

PAJ1302 PAJ1303

PAJ1304PAJ1305

PAJ1402 PAJ1403

PAJ1404PAJ1405

PAJ70002

PAJ70102

PAL70201

PAR10601PAR10701PAR10801PAR10901PAR11001PAR11101PAR11201PAR11301PAR21601PAR21701PAR21801PAR21901PAR310A01PAR310B01PAR311A01PAR311B01PAR312A01PAR312B01 PAR314A02PAR314B02PAR324A01PAR324B01PAR405A01PAR405B01PAR407A01PAR407B01PAR412A01PAR412B01PAR413A01PAR413B01PAR418A01PAR418B01 PAR503A02PAR503B02PAR505A02PAR505B02PAR70101 PAR70202PAR70601PAR70701 PAR70802PAR71101

PAR803A0CCWPAR803B0CCW


PAU100038

PAU20001

PAU20004

PAU20009

PAU200013

PAU200016

PAU300A03PAU300B03 PAU302A02PAU302A04 PAU302B02PAU302B04 PAU400A03PAU400B03 PAU401A02PAU401A04 PAU401B02PAU401B04

PAU500A04PAU500B04

PAU501A018 PAU501A020

PAU501A027

PAU501A029

PAU501A032

PAU501A041PAU501A043

PAU501B018 PAU501B020

PAU501B027

PAU501B029

PAU501B032

PAU501B041PAU501B043

PAU70003 PAU70006PAU70102

PAU70203 PAU70206PAU70303 PAU70306PAU70403 PAU70406PAU70502

PAU800A03PAU800B03PAU801A04PAU801B04PAU90104

PAR505A01

PAU501A047

PAR505B01

PAU501B047

PAR502A01PAR506A01

PAU501A02

PAR502B01PAR506B01

PAU501B02

PAJ602019

PAR10201 PAR10402

PAU100018

PAJ602021

PAR10301 PAR10502

PAU100019

PAJ602018

PAU10001

PAJ602016

PAU10002

PAJ602017

PAU10003

PAJ602015

PAU10004

PAJ602014

PAU10005

PAJ602010

PAU10006

PAJ602013

PAU10007

PAJ60209

PAU10008

PAJ60208

PAU10009

PAJ60206

PAU100010

PAJ60207

PAU100011

PAJ60205

PAU100012

PAJ60204

PAU100013

PAJ60202

PAU100014

PAJ602037

PAU100023

PAJ602035

PAU100024

PAJ602038

PAU100025

PAJ602036

PAU100026

PAJ602033

PAU100027

PAJ602031

PAU100028

PAJ602034

PAU100029

PAJ602032

PAU100030

PAJ602028

PAU100031

PAJ602026

PAU100032

PAJ602027

PAU100033

PAJ602025

PAU100034

PAJ602024

PAU100035

PAJ602022

PAU100036

PAU100048

PAR10001 PAR10602

PAU100037

PAJ602020

PAU100017

PAJ602039

PAU100020

PAR20201 PAR20602

PAU200019

PAR21001 PAR21802

PAU200020

PAC10901PAC11001PAC11101PAC11201PAC11301PAC11401PAC20801PAC20901PAC21001PAC21101PAC21201PAC21301PAC507A01PAC507B01PAC508A01PAC508B01PAC509A01PAC509B01PAC510A01PAC510B01PAC70301PAC70401PAC70501PAC71901PAC72001PAC72101

PAJ600012

PAJ600030

PAJ602012

PAJ602030

PAL70202

PAR10401PAR10501PAR20401PAR20501PAR20601PAR20701PAR513A01PAR513B01PAR514A01PAR514B01PAR515A01PAR515B01

PAU100015 PAU100021

PAU200028

PAU200040

PAU200053


PAR10802

PAU100044

PAR10902

PAU100041

PAC325A02PAR321A02PAR324A02

PAU302A01

PAC325B02PAR321B02PAR324B02

PAU302B01


PAU401A01


PAU401B01

PAR10101 PAR10702

PAU100042

PAJ903

PAJ1101

PAR303A02PAR308A02PAR311A02

PAJ1003

PAJ1201

PAR303B02PAR308B02PAR311B02

PAJ201

PAJ403

PAR11102PAR407A02

PAU100046

PAU401A03

PAJ101

PAJ303

PAR11302PAR407B02

PAU100039

PAU401B03

PAR11002

PAU100045

PAR11202

PAU100040

PAR504A01PAR516A01

PAU501A06

PAR504B01PAR516B01

PAU501B06

PAJ600038

PAR516A02PAR516B02

PAJ600037

PAR510A02PAR510B02

PAJ600040

PAR512B02

PAJ600039

PAR511A02

PAU200061

PAC10802

PAU100043

PAC21802PAC21902PAR90401

PAU20008

PAC300A01PAC306A01PAR300A01 PAR306A02PAR309A02PAR320A02PAR322A02

PAU300A02

PAC300A02PAR300A02PAR307A01PAU300A06

PAC300B01PAC306B01PAR300B01 PAR306B02PAR309B02PAR320B02PAR322B02

PAU300B02

PAC300B02PAR300B02PAR307B01PAU300B06

PAC301A01PAR304A01

PAU301A08


PAU301A05

PAC301B01PAR304B01

PAU301B08


PAU301B05

PAC303A02PAR301A02PAR303A01 PAR304A02PAC303B02PAR301B02PAR303B01 PAR304B02PAC305A01PAR314A01 PAR315A02PAR316A01PAC305B01PAR314B01 PAR315B02PAR316B01 PAC306A02PAC307A02PAU300A05

PAC306B02PAC307B02PAU300B05

PAC308A01 PAR313A02PAR316A02

PAU301A04

PAC308A02PAR315A01

PAU301A01

PAC308B01 PAR313B02PAR316B02

PAU301B04

PAC308B02PAR315B01

PAU301B01

PAC400A01PAC401A01PAR400A01PAR403A01 PAR406A02

PAU400A02

PAC400A02PAR400A02PAR404A01PAU400A06

PAC400B01PAC401B01PAR400B01PAR403B01 PAR406B02

PAU400B02

PAC400B02PAR400B02PAR404B01PAU400B06

PAC401A02PAC402A02PAU400A05

PAC401B02PAC402B02PAU400B05

PAC413A02PAU402A05

PAC413B02PAU402B05

PAC414A01PAR417A01 PAR418A02

PAU402A03

PAC414A02PAR415A02PAR416A01 PAR417A02PAU402A06

PAC414B01PAR417B01 PAR418B02

PAU402B03

PAC414B02PAR415B02PAR416B01 PAR417B02PAU402B06

PAC501A02

PAU500A05

PAC501B02

PAU500B05

PAC502A02PAR501A01 PAC502B02PAR501B01 PAC806A02

PAU801A05

PAC806B02

PAU801B05

PAC807A02PAR322A01 PAR802A02PAR805A02PAC807B02PAR322B01 PAR802B02PAR805B02PAC808A02PAR801A01

PAR803A0W

PAC808B02PAR801B01

PAR803B0W

PAC809A02PAR804A01 PAC809B02PAR804B01 PAC90002PAR90002PAR90302

PAU90003

PAC90102

PAU90105

PAC90202PAR90201PAR302A01PAU302A05

PAR302A02PAR308A01PAU302A07

PAR302B01PAU302B05

PAR302B02PAR308B01PAU302B07

PAR307A02PAR312A02

PAU302A03

PAR307B02PAR312B02

PAU302B03

PAR401A01PAU401A05

PAR401A02PAR402A01PAU401A07

PAR401B01PAU401B05

PAR401B02PAR402B01PAU401B07

PAR402A02PAR403A02PAR405A02PAR402B02PAR403B02PAR405B02PAR404A02PAR415A01

PAU402A02

PAR404B02PAR415B01

PAU402B02

PAR500A01 PAR501A02

PAU500A06

PAR500B01 PAR501B02

PAU500B06

PAR503A01

PAU501A034

PAR503B01

PAU501B034

PAR511B02PAR512A02PAR70001 PAR70102

PAU70005

PAR70201 PAR70302

PAU70104

PAR70401 PAR70602

PAU70205

PAR70501 PAR70702

PAU70305

PAR70801 PAR71002

PAU70504

PAR70901 PAR71102

PAU70405

PAR800A01 PAR801A02

PAU800A02

PAR800A02PAR802A01

PAU800A06

PAR800B01 PAR801B02

PAU800B02

PAR800B02PAR802B01

PAU800B06 PAR803A0CW

PAR804A02

PAU801A06 PAR803B0CW

PAR804B02

PAU801B06

PAR90001 PAR90202

PAU90106

PAR90101

PAU90002

PAU90006

PAR90102PAR90402

PAU301A02PAU301B02

PAR318A0CCW

PAR319A01PAU300A08

PAR318B0CCW

PAR319B01PAU300B08

PAR411A0CCW

PAR414A01PAU400A08

PAR411B0CCW

PAR414B01PAU400B08

PAR317A02

PAR318A0CWPAU300A01

PAR317B02

PAR318B0CWPAU300B01

PAR410A02

PAR411A0CWPAU400A01

PAR410B02

PAR411B0CWPAU400B01 PAR420A0CCW

PAR421A01PAU402A08

PAR420B0CCW

PAR421B01PAU402B08

PAR419A02

PAR420A0CWPAU402A01

PAR419B02

PAR420B0CWPAU402B01

PAC408A02PAR406A01 PAR409A02PAR413A02PAC408B02PAR406B01 PAR409B02PAR413B02PAR508A01 PAR514A02

PAU501A010

PAR508B01 PAR514B02

PAU501B010

PAR507A01 PAR513A02

PAU501A048

PAR507B01 PAR513B02

PAU501B048

PAR509A01 PAR515A02

PAU501A07

PAR509B01 PAR515B02

PAU501B07

PAC500A02PAR500A02


PAC500B02PAR500B02


PAC21502PAC21602PAC21701

PAU20007

PAC22102PAC22202PAC22301

PAU200010

PAC21401PAC21501PAC21601

PAU20006

PAC22001PAC22101PAC22201

PAU200011

PAR510A01

PAU501A03

PAR510B01

PAU501B03

PAR511A01

PAU501A04

PAR511B01

PAU501B04

PAR512A01

PAU501A05

PAR512B01

PAU501B05

PAJ701

PAJ901

PAR306A01 PAR310A02

PAJ801

PAJ1001

PAR306B01 PAR310B02

PAJ401

PAJ601

PAR416A02

PAJ301

PAJ501

PAR416B02PAR20301 PAR20702

PAU200062

PAJ60201

PAR506B02

PAJ60203

PAR506A02PAR408A01

PAU501A015 PAU501A017

PAR409A01

PAU501A021 PAU501A023

PAR408B01


PAR409B01


PAR321A01

PAU501B015 PAU501B017

PAR309A01

PAU501B021 PAU501B023

PAR321B01


PAR309B01


PAJ1301

PAR320A01

PAJ1401

PAR320B01 PAC70702

PAJ70001

PAL70101

PAC72801

PAJ70003

PAL70401

PAC302A02PAR305A02

PAU20002

PAC304A01PAR313A01

PAU20003

PAC302B02PAR305B02

PAU200015

PAC304B01PAR313B01

PAU200014

PAC70601

PAC70802PAC70902PAC71002

PAL70102PAU70001PAU70002

PAC72702

PAC72901PAC73001PAC73101

PAL70402PAU70101

PAU70103 PAU70106127

A.3. Design Files

Table A.1: The bill of material of the servo daughter card

Designator Values Digikey Number Quantity

C100, C101, C200, C201,

C215, C218, C221, C500A,

C500B, C501A, C501B,

C502A, C502B, C503A,

C503B, C513A, C513B,

C700, C703, C707, C708,

C711, C716, C719, C722,

C728, C729, C732, C734,

C740, C742, C747, C749,

C754, C760, C900, C901,

C902

10uF 311-1459-1-ND 38

Continued on next page

128

A.3. Design Files

Table A.1 – continued from previous page


C102, C103, C109, C110,

C111, C202, C203, C208,

C209, C210, C311A, C311B,

C313A, C313B, C315A,

C315B, C319A, C319B,

C321A, C321B, C323A,

C323B, C325A, C325B,

C403A, C403B, C405A,

C405B, C407A, C407B,

C408A, C408B, C409A,

C409B, C411A, C411B,

C415A, C415B, C417A,

C417B, C504A, C504B,

C507A, C507B, C509A,

C509B, C511A, C511B,

C514A, C514B, C709, C712,

C723, C730, C735, C743,

C750, C755

1 uF 399-1284-1-ND 58


129

A.3. Design Files



C104, C105, C108, C204,

C205, C214, C216, C217,

C219, C220, C222, C223,

C505A, C505B, C515A,

C515B, C701, C704, C713,

C714, C717, C720, C724,

C725, C733, C736, C737,

C741, C744, C745, C748,

C751, C752, C756, C757,

C761, C904, C906, C908

0.1 uF 1276-1003-1-ND 39

C106, C107, C112, C113,

C114, C206, C207, C211,

C212, C213, C506A, C506B,

C508A, C508B, C510A,

C510B, C512A, C512B,

C516A, C516B, C702, C705,

C710, C715, C718, C721,

C726, C731, C738, C746,

C753, C758

0.01uF 311-1136-1-ND 32

C300A, C300B, C306A,

C306B, C400A, C400B,

C401A, C401B

3 pF 399-1107-1-ND 8

C301A, C301B, C308A,

C308B

9.1 pF 311-1098-1-ND 4

C302A, C302B, C304A,

C304B

56 pF 1276-1833-1-ND 4


130

A.3. Design Files



C303A, C303B, C305A,

C305B, C307A, C307B,

C402A, C402B

25 pF 1276-2621-1-ND 8

C312A, C312B, C314A,

C314B, C316A, C316B,

C320A, C320B, C322A,

C322B, C324A, C324B,

C404A, C404B, C406A,

C406B, C410A, C410B,

C412A, C412B, C416A,

C416B, C418A, C418B

10 nF 311-1136-1-ND 24

C413A, C413B, C414A,

C414B, C800A, C800B,

C801A, C801B, C802A,

C802B, C803A, C803B,

C804A, C804B, C805A,

C805B, C806A, C806B,

C807A, C807B, C808A,

C808B, C809A, C809B

100 pF 399-1122-1-ND 30

C706, C727, C739, C759 10 uF PCE3914CT-ND 4

J3, J4, J9, J10 BNC DUAL ACX1655-ND 4

J600, J602 GPIO OR1153-ND 2

R102, R103, R200, R201 100 Ω 311-100CRCT-ND 4

R104, R105, R204, R205 150 Ω 311-150CRCT-ND 4

R106, R108, R109, R704 2 kΩ 311-2.00KCRCT-ND 4


131

A.3. Design Files



R107, R302A, R302B,

R307A, R307B, R308A,

R308B, R401A, R401B,

R402A, R402B, R404A,

R404B, R415A, R415B,

R416A, R416B, R500A,

R500B, R501A, R501B,

R506A, R506B, R510A,

R510B, R511A, R511B,

R512A, R512B, R516A,

R516B, R901, R902

0 311-0.0ARCT-ND 33 Ω

R110, R112 25 Ω 311-24.9CRCT-ND 2

R111, R113, R310A, R310B 50 Ω P49.9CCT-ND 4


132

A.3. Design Files



R206, R207, R208, R209,

R218, R219, R300A, R300B,

R306A, R306B, R324A,

R324B, R400A, R400B,

R403A, R403B, R406A,

R406B, R412A, R412B,

R417A, R417B, R418A,

R418B, R502A, R502B,

R503A, R503B, R504A,

R504B, R505A, R505B,

R509A, R509B, R513A,

R513B, R514A, R514B,

R706, R707, R711, R800A,

R800B, R801A, R801B,

R802A, R802B, R804A,

R804B, R805A, R805B

1k Ω 311-1.00KCRCT-ND 50

R301A, R301B, R303A,

R303B, R314A, R314B,

R316A, R316B

1.1 kΩ 311-1.10KCRCT-ND 8 Ω

R304A, R304B, R315A,

R315B

470 Ω 311-470CRCT-ND 4

R305A, R305B, R313A,

R313B

270 Ω 311-270CRCT-ND 4

R311A, R311B, R405A,

R405B

499 Ω 311-499CRCT-ND 4


133

A.3. Design Files



R321A, R321B, R408A,

R408B

18 kΩ 311-18.0KCRCT-ND 4

R409A, R409B 1.5 kΩ 311-1.50KCRCT-ND 2

R413A, R413B 401 Ω 311-402CRCT-ND 2

R700, R708 10 kΩ 311-10.0KCRCT-ND 2

R701 1.2 kΩ 311-1.20KCRCT-ND 1

R702 12.1 kΩ 311-12.1KCRCT-ND 1

R703 100 kΩ 311-100KCRCT-ND 1

R705, R709, R903 3.3 kΩ 311-3.30KCRCT-ND 3

R900 6.8 kΩ 311-6.8KARCT-ND 1

R710 33 kΩ 311-33.0KCRCT-ND 1

U300A, U300B, U400A,

U400B, U800A, U800B, U900

AD829JR AD829JRZ-ND 7

U301A, U301B AD8137 AD8137YRZ-REEL7CT-ND 2

U302A, U302B, U401A,

U401B

AD603AR AD603ARZ-REEL7CT-ND 4

U500A, U500B, U801A,

U801B, U901

REF5050 296-22211-5-ND 5

U700, U702, U703, U704 LT1963 LT1963AEQ#TRPBFCT-ND 4

U701, U705 LT3015 LT3015EQ#PBF-ND 2

U100 AD9767 1

U200 AD9248 1

U501A, U501B DAC8734 2

J1, J2, J5, J6, J7, J8, J11,

J12, J13, J14

COAX-F 10

J700 Header 3 1


134

A.3. Design Files



J701 Header 2 1

135

Appendix B

The Variable Attenuator

The variable RF attenuator used for intensity control in Chapter 4 and Chapter 5 is constructed

for general use in the lab. The characteristics of this variable attenuator such as the speed of

the variable attenuator and the relationship between input voltage and RF transmission is

covered in Section 4.2.3. This section covers the finer technical details, such as special assembly

instructions and pending design changes.

B.1 Design Details and Pending Changes

The variable attenuator is designed around the MAAVSS0006 IC. Because the IC is not avail-

able commercially in a package that is convenient to use, a PCB and enclosure is designed to

host the IC. This allows the variable attenuator to have a BNC interface. In this design, two

variable attenuating channels are designed into each package and they are mean to be used in

cascade mode to achieve modulation range of 60-70 dB. The device need a quiet ±13 − 15 V

power supply, supplied through a 5-pin mini-XLR connector. The pin-out of this connector is

compatible with the standard power supply standard in the QDG lab.

The design document presented here is the second PCB version of the variable attenuator

design. It fixed various problem in the original PCB design although some problem still remains.

One mistakes at the schematics level needs to be corrected in future revision and it is

the compensation scheme of the AD829. The compensation capacitor, C15 and C16 in their

respective channels are incorrectly attached to the Pin 8 of the AD829, rather, it should be

attached to Pin 5. The mistake is patched by soldering C15 and C16 between Pin 5 of the

respective op-amp and a nearby via on the ground plane, but it should be fixed as the patch

add additional processing step to the design. While fixing this mistake, it is also a good chance

to try out the current compensation scheme, as the work found the current compensation scheme

136

B.2. Calibration

to be typically faster than the voltage compensation scheme. Section 4.2.3 shows evidence that

the circuit around AD829 is the bottleneck in speed so such a change has the potential to

improve modulation speed. The change is very simple and should not disturb the layout else

where on the PCB.

B.2 Calibration

Each variable attenuator has a different relationship between its input control voltage and the

RF transmission. This can be observed in Figure 4.10 and we did not look into the cause of

this variable. Thus, each variable attenuator needs to be calibrated. It may help to use the

potentiometer R5 and R10 to add an offset to the input voltage so that the variable attenuator

transition from “on” to “off” between 0 to 0.5 V.

B.3 Assembly

In the second version of the design (design files are included in later part of this section), all

the connectors are soldered to the PCB and can be fastened to the removable panel on the

enclosure for extra security. The panels can be machined from a flat sheet of metal in a water

jet machine. Once the PCB is soldered and calibrated, the assembly is complete by sliding the

PCB into the existing card guide in the commercial enclosure and attaching the panels. The

easiest way to do this is to compress the enclosure on a vise to prevent the PCB from sticking

to card guide.

B.4 Design Files

The design documents presented here, the schematics, PCB layout, the bill of material and the

panel design is sufficient to reproduce the variable attenuator design.

137

1

1

2

2

3

3

4

4

D D

C C

B B

A A

Title

Number RevisionSize

A

Date: 2016-06-07 Sheet ofFile: C:\Users\..\VariableAttenuatorBoard.SchDocDrawn By:

2

36

47

1

8

5

U1Op Amp

R3

1k

R2

1k

R510k

GND

15V

-15V

15V

-15V

GND GND

P2

BNC

P1

BNC

P3

BNC

GND

GND

GND

RFIN1

GND 2

RFOUT 3

GND4

VC5

MAAVSS0006

U2

0.1uF

C8

0.1uF

C12

15V

GND

-15V

0.1uF

C4

0.1uF

C10

15V

GND

-15V

2

36

47

1

8

5

U3Op Amp

1K

R8

Res31K

R7

Res3

R1010k

GND

15V

-15V

15V

-15V

GND GND

P5

BNC

P4

BNC

P6

BNC

GND

GND

GND

RFIN1

GND 2

RFOUT 3

GND4VC5

MAAVSS0006

U4

15V

-15V

GND

100pF

C13Cap Semi

GND

100pF

C14Cap Semi

GND

+15V1+5V2

GND5

-5V3

-15V4

P7

QDG Power Conn

7pF

C15Cap Semi

GND

7pF

C16Cap Semi

GND

R1

4k

R6

4k

0.1uF

C17Cap Semi

0.1uF

C18Cap Semi

GND

GND

10uH

L1

Inductor

10uH

L2

Inductor

0.1uF

C1

0.1uF

C2

GND

GND

10uF

C9

10uF

C3

10uF

C7

10uF

C11

PIC101

PIC102COC1

PIC201

PIC202COC2

PIC301

PIC302COC3

PIC401

PIC402COC4

PIC701

PIC702COC7

PIC801

PIC802COC8

PIC901

PIC902COC9

PIC1001

PIC1002COC10

PIC1101

PIC1102COC11

PIC1201

PIC1202COC12

PIC1301

PIC1302COC13

PIC1401

PIC1402COC14

PIC1501

PIC1502COC15

PIC1601

PIC1602COC16

PIC1701

PIC1702COC17

PIC1801

PIC1802COC18

PIL101 PIL102

COL1

PIL201 PIL202

COL2

PIP101

PIP102

COP1

PIP201

PIP202

COP2

PIP301

PIP302

COP3

PIP401

PIP402

COP4

PIP501

PIP502

COP5

PIP601

PIP602

COP6

PIP701

PIP702

PIP703

PIP704

PIP705

COP7

PIR101PIR102

COR1

PIR201PIR202

COR2

PIR301 PIR302

COR3

PIR50CCWPIR50CW

PIR50W

COR5

PIR601PIR602

COR6

PIR701PIR702

COR7

PIR801 PIR802

COR8

PIR100CCWPIR100CW

PIR100W

COR10

PIU101

PIU102

PIU103

PIU104PIU105

PIU106

PIU107PIU108

COU1

PIU201

PIU202

PIU203

PIU204

PIU205

COU2

PIU301

PIU302

PIU303

PIU304PIU305

PIU306

PIU307PIU308

COU3

PIU401

PIU402

PIU403

PIU404

PIU405

COU4

PIC901 PIC1001 PIC1101 PIC1201

PIL201

PIR50CCW

PIR100CCW

PIU104

PIU304

PIC302 PIC402 PIC702 PIC802PIL101

PIR50CW

PIR100CW

PIU107

PIU307

PIC102

PIC201



PIC1301

PIC1401

PIC1501

PIC1601

PIC1701

PIC1801

PIP102

PIP202

PIP302

PIP402

PIP502

PIP602

PIP705

PIU103

PIU202PIU204

PIU303

PIU402PIU404

PIC101PIL102

PIP701

PIC202PIL202 PIP704

PIC1302

PIR101

PIU106 PIU205

PIC1402

PIR601

PIU306 PIU405

PIC1502

PIU108

PIC1602

PIU308

PIC1702

PIR301

PIR50W

PIC1802

PIR801

PIR100W

PIP101

PIU203

PIP201 PIR202

PIP301

PIU201

PIP401

PIU403

PIP501 PIR702

PIP601

PIU401

PIP702

PIP703

PIR102

PIR201

PIR302

PIU102

PIR602

PIR701

PIR802

PIU302

PIU101

PIU105

PIU301

PIU305

138

PAC101PAC102

COC1

PAC201PAC202

COC2

PAC302PAC301

COC3

PAC402PAC401

COC4

PAC702PAC701

COC7

PAC802PAC801

COC8

PAC902

PAC901

COC9

PAC1002

PAC1001

COC10

PAC1102PAC1101

COC11

PAC1202PAC1201

COC12PAC1302PAC1301

COC13

PAC1402PAC1401

COC14

PAC1501PAC1502

COC15PAC1601PAC1602

COC16

PAC1701

PAC1702

COC17

PAC1801PAC1802

COC18

PAL101 PAL102

COL1

PAL201PAL202

COL2

PAP101 PAP102

COP1

PAP201PAP202

COP2

PAP301 PAP302

COP3

PAP401 PAP402

COP4

PAP501PAP502

COP5

PAP601 PAP602

COP6

PAP705PAP704

PAP703 PAP702

PAP701

PAP70NC

COP7

PAR101PAR102

COR1PAR202PAR201

COR2

PAR302PAR301

COR3

PAR50CWPAR50W

PAR50CCW

COR5PAR601PAR602

COR6PAR702PAR701

COR7

PAR802PAR801

COR8

PAR100CWPAR100W

PAR100CCW

COR10PAU101PAU102

PAU103

PAU104

PAU108PAU107

PAU106

PAU105

COU1

PAU205 PAU204

PAU203PAU202PAU201

COU2

PAU301PAU302

PAU303

PAU304

PAU308PAU307

PAU306

PAU305

COU3

PAU405 PAU404

PAU403PAU402PAU401

COU4PAC901PAC1001 PAC1101PAC1201

PAL201

PAR50CCW PAR100CCWPAU104 PAU304

PAC302

PAC402

PAC702

PAC802

PAL101

PAR50CW PAR100CWPAU107 PAU307

PAC102 PAC201

PAC301

PAC401

PAC701

PAC801

PAC902PAC1002 PAC1102PAC1202PAC1301 PAC1401

PAC1501PAC1601PAC1701PAC1801

PAP102

PAP202

PAP302 PAP402

PAP502

PAP602

PAP705

PAU103

PAU202

PAU204

PAU303

PAU402

PAU404

PAC101PAL102

PAP701

PAC202PAL202

PAP704

PAC1302

PAR101

PAU106

PAU205 PAC1402

PAR601

PAU306

PAU405

PAC1502

PAU108

PAC1602

PAU308

PAC1702

PAR301

PAR50W

PAC1802

PAR801

PAR100W

PAP101

PAU203

PAP201

PAR202

PAP301

PAU201

PAP401

PAU403

PAP501

PAR702

PAP601

PAU401

PAR102

PAR201PAR302

PAU102

PAR602

PAR701

PAR802

PAU302

139

B.4. Design Files

Table B.1: The bill of material of the variable attenuator unit.

Electrical

Designator Values Manufacturer Part Number Quantity

U2, U4 Variable attenuator MAAVSS0006TR-3000 2U1, U3 AD829 AD829JRZ 2R2, R3, R7, R8 1k RC0805FR-071KL 4R1, R6 4.02k RC0402FR-074K02L 2R5, R10 10k SM-42TW103 2P1, P2, P3, P4,P5, P6

BNC 1-1337543-0 6

P7 Mini-XLR TRAPC5MX 1C13, C14 100pF C0805C101J5GACTU 2C15, C16 7pF CL21C070CBANNNC 2C3, C9, C7, C11 10uF GRM21BR61C106KE15K 4C1, C2, C4, C10,C8, C12, C17,C18

10uF CL21B104KBCNNNC 8

L1, L2 100uH LBR2012T100K 2

Mechanical

Enclosure - EX-4500 1

140

Appendix C

Register Address of FPGA

Peripheral

The SOC design FPGA servo is composed of an MCU embedded in the FPGA and a few

specialized modules for data processing. The MCU specializes in communication tasks such

as processing the commands between the PC and the servo and the coordination between the

modules. The specialized modules handle high-speed signal processing tasks that require the

flexibility of the FPGA to implement different logical structures.

When generating an SOC, each module instantiated in the SOC are given a unique address.

These addresses are used by the MCU to access the modules and each parameter in a specialized

module can be accessed at a fixed offset from the base address. The offset addresses of these

paremeters are listed in Table C.1 - C.5. In an SOC that contains multiple IIR filters, each

filter is given a unique base address.

The advantage of this design scheme is flexibility and portability. Each specialized module

can be designed and tested as a unit. To expand an FPGA servo design from a single IIR filter

per channel to 3 IIR filter configured in cascade, the work only involves editing the configuration

of the SOC to instantiate more IIR filters and editing the command interface in the MCU to

make sure that the PC can control the newly added IIR modules.

It is important to note that although the Serial Peripheral Interface (SPI) module used to

control the slow DAC is a very general structure generated from Altera toolbox, the design in

MCU needs to take into account the command structure of the slow DAC (each command to

the slow DAC is 3 Byte long). Because two ICs are connected in the daisy-chain fashion, in

order to talk the second IC in the chain, the MCU must issue 3 bytes carrying the command

intended for the second IC and the immediately issue another 3 Bytes (could be just a No

141

Appendix C. Register Address of FPGA Peripheral

Operation (NOP) command) in order to prompt the first IC in the chain to relay the first 3

bytes to the second IC.

Table C.1: The address at which the IIR coefficients can be accessed in the general purposeIIR filter tested on the DE2 FPGA. The coefficients are signed.

Register Address Register Function Format

0 B 0 Q5.101 B 1 Q5.102 B 2 (If used) Q5.103 B 3 (If used) Q5.104 A 1 Q5.105 A 2 (If used) Q5.106 A 3 (If used) Q5.10

Table C.2: The address at which the IIR coefficients can be accessed in the IIR filter designedfor the DE3 FPGA.


0 B 0 Q3.281 B 1 Q3.282 B 2 (If used) Q3.283 B 3 (If used) Q3.284 A 1 Q3.285 A 2 (If used) Q3.286 A 3 (If used) Q3.28

Table C.3: The register address of the FIR filter.


0 B 0 Q5.101 B 1 Q5.102 B 2 (If used) Q5.103 B 3 (If used) Q5.104 B 4 (If used) Q5.105 B 5 (If used) Q5.106 B 6 (If used) Q5.10

142

Appendix C. Register Address of FPGA Peripheral

Table C.4: The register address for the SPI module that is used to control the slow DACs in theFPGA servo based on the DE2 and the custom-made servo daughtercard. In the daughtercard,two ICs are connected in a daisy chain fashion. To communicate to the second IC in the chain,data has to be sent out in multiples of 3 bytes. The SPI module is generated from Altera’stoolbox.


0 CPU Read U81 CPU Write U82 SPI Status 1-bit3 SPI Control 1-bit4 - -5 Slave Select 1-bit6 End of Packet 1-bit

Table C.5: The register address of the AWG module

Register Address Register Name Format

0 Ramp Inc U321 Ramp Max U322 Ramp Min U323 Ramp Prescaler U164 A 0 Q5.105 A 1 Q5.106 A 2 Q5.107 A 3 Q5.108 A 4 Q5.10

143

Appendix D

PC-Side Software

The PC-side software is responsible for generating the IIR coefficients, AWG coefficients and

providing a Graphical User Interface (GUI) for the FPGA servo user. The majority of the PC-

side software including the GUI is developed in MATLAB. However, the design can be ported

into a different environment as the commands to the FPGA is well defined and non-proprietary.

D.1 Command Format

The command interface of the FPGA exposed control to modules in the SOC as setting that

can be accessed at unique addresses. The address to the setting is defined in the code that

run in the MCU where the commands are interpreted. The setting from different module are

typically assigned a unique offset. To access the setting the keywords “set”, “get” and “print”

are used, with the format like “keyword address (value)”. For example, a dual channel FPGA

servo with a single IIR filter maybe need a command “set 0 1024” and “set 16 1024” to set the

B0 of the IIR filter for the first servo channel and the second servo channel respectively.

D.2 IIR Coefficients and Screening of Transfer Functions

Because the IIR filter has limited resolution, the PC-side software find the nearest transfer

function that the FPGA servo can implement and compares it to the transfer function that the

user requested. The software leaves it up to the user to make sure that the transfer function

implemented by the hardware does not cause instability in the loop.

For the PC-side software to make this comparison correctly a few parameters need to be

recorded correctly in PC-side software. The important parameters are the clock speed of the IIR

logic (not to be confused with clock speed of the ADC or the DAC which can be different), the

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D.2. IIR Coefficients and Screening of Transfer Functions

resolution of the IIR coefficients that is implemented in the FPGA servo (the common formats

are Q5.10 and Q3.28) and how the IIR filters are cascade. The PC side program also needs to

know the format of the commands and the address that each coefficient can be accessed at (this

is not be confused with the location where these coefficients are stored in the MCU’s memory

space).

Currently, there is no way of knowing the exact configuration of IIR filters that is pro-

grammed in the FPGA without accessing the source code that describes the FPGA circuitry.

This can be a source of confusion when FPGA servos with different IIR configurations are

present. We currently combat this problem with the use of unique system ID which is a periph-

eral generated by the Altera toolbox which receives a unique timestamp every time the SOC

is regenerated. The system ID peripheral is also given a device ID to differentiate IIR filter

designed for different FPGAs.

This method still requires access to the source code to make sure that the program on the

PC and inside the MCU in the FPGA are compatible with the FPGA design. If the developer

make sure to only release one servo design for general use then only one PC side program

needs to be released and no compatibility issue would surface. In the case where multiple servo

designs are needed, a comprehensive way of fixing this is to add special command in the MCU

to allow the FPGA servo to inform any potential PC host its underlying IIR filter structure.

The PC side program are then required to query this information from the FPGA servo and

adapt its tuning interface accordingly.

To illustrate the importance of this screening process, an example output of the tuning

interface is shown in Figure D.1. Here the tuning interface is “hard-coded” to interface with

an FPGA servo where the underlying FPGA logic is a single third order IIR filter. The output

based two IIR filters are overlay to illustrate the effect of computation precision in IIR filter.

It can be observed in Figure D.1 that the IIR filter with 32-bit coefficients can implement the

shape of a PID control although it has trouble addressing the high frequency pole precisely.

In comparison, the IIR filter with 16-bit coefficients fails to implement the integrator (at low

frequency) and the resulting transfer function is unusable in closed-loop.

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D.3. Slow DAC Calibration Table

Figure D.1: Example output of the PC software. In this case, the user input are zeros at -70kHz and -1 MHz and poles at 0 and -10 MHz and the underlying servo logic is implemented asa single IIR filter. The input forms an PID controller, but IIR filter with different coefficientresolution emulate the transfer function with different accuracy. The resulting transfer functionfrom the IIR filter with 16-bit coefficient (Q5.10) fails to implement the integrator.

D.3 Slow DAC Calibration Table

The slow DAC calibration table is needed for the variable gain circuits in the FPGA servo

because often in a servo loop the gain has to be adjusted for optimal performance. The VGA

used in this FPGA servo is linear-in-dB. Instead of approximating the gain as a exponential

function, this work approximate the gain with a calibration table with value in the slow DAC

and gain. Any intermediate gain is interpolated linearly from the closest two entries in the

calibration table.

Each offset circuit is calibrated with a free parameter that represents the linear relationship

between the slow DAC value and the offset voltage.

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