the sudbury neutrino observatory electronics chain

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IEEE TRANSACTIONSON NUCLEAR SCIENCE, VOL. 42, NO. 4, AUGUST 1995 925 The Sudbury Neutrino Observatory Electronics Chain D.F. Cowen, T. Ekenberg, J.R. Klein, F.M. Newcomer, R. Van Berg, R.G. Van de Water, P. Wittich The University of Pennsylvania, Dept. of Physics A. Biman: R.L. Stevenson Queen’s University, Dept. of Physics May 18, 1995 A bst ra ct The Sudbury Neutrino Observatory (SNO) is a second generation real time solar neutrino water Cherenkov de- tector using 1,000 Tonnes of D20 viewed by almost 10,000 Photomultiplier tubes 20cm in diameter. The electronics chain is required to provide deadtimeless sub-nanosecond tinie and charge measurement for Photomultiplier pulses in the range of 1 - 1000 photo electrons. While the solar neutrino event rate is very low, the electronics chain must handle background rates in excess of 1 kHz and burst rates in excess of 1 MHz. The electronics chain is implemented using three full cus- torn integrated circuits and commercial ADCs, memory, and logic. The DAQ interface is VME compatible. We will briefly describe the SNO detector and then con- centrate on the design of the electronic system including novel features of the DAQ and trigger paths. I. INTRODUCTION The Sudbury Neutrino Observatory (SNO) [l] is a second generation, underground, real time, solar neutrino, water Cherenkov detector. The detector will also be sensitive to atmospheric and supernova generated neutrinos. The SNO det,ector is located in a large cavity excavated at the 6800 foot level in the INCO, Ltd., Creighton mine near Sudbury, Ontario. The target for the solar neutrinos is 1,000 tonnes of DzO contained in a twelve meter diameter acrylic vessel surrounded by a light water shield of minimum diameter twenty two meters. A spherical geodesic shell of diameter seventeen meters surrounds the D20 and supports almost 10,000 20 cm photomultiplier tubes (PMT), each with a light collecting reflector. The electronics chain, shown in Figure 1 , provides deadtimeless sub-nanosecond time and charge measurement for PMT pulses in the range of 1 - 1000 photo electrons. The electronics chain must handle background radioactivity rates in excess of 1 kHz and po- tential astrophysical burst rates in excess of l MHz. The cavity for the detector is complete, the geodesic pho- tornultiplier support structure is presently being installed, *Presently, Queen’s University7Electrical Eiigiiieeriiig and prototype electronics are being tested. The detector is scheduled to begin filling with water at the end of 1995 and data taking will commence in the beginning of 1996. A. Physics Motivation The SNO experiment is designed to study the fundamental properties of neutrinos, in particular the mass and mixing parameters. This is to be accomplished by measuring the flux of electron type neutrinos, v,, which are produced in the sun, and by comparing it to the flux of all flavors of neutrino detected on earth in an appropriate energy inter- val. Observation of neutrino flavor transformation through this comparison is unambiguous evidence that at least one neutrino flavor has non-zero mass. Non-zero neutrino mass is evidence for physics beyond the Standard Model of fun- damental particle interactions. Non-zero neutrino mass might also have cosmological implications, and coiilcl ac- count for the presence of “hot” dark matter implied in some cosmological models by the observations of the cos- mic microwave background radiation anisotropy, angular correlations of galaxies, correlations of galaxy clusters, and other cosmological data. The 1,000 tonnes of D20 is utilized as a target to allow detection of neutrinos through the reactions where v, refers to any flavor of interacting neutrino. The elastic scattering of neutrinos from electrons (1) is highly directional, and establishes the sun as the source of the detected neutrinos. The absorption of v, on deuterons (2) produces an electron with an energy highly correlated with that of the neutrino. This reaction is sensitive to the en- ergy spectrum of v, and deviations from the parent spec- trum. The disintegration of the deuteron by neutrinos (3) is independent of neutrino flavor and has a threshold of 2.2 MeV. Measurement of tthe rate of this reaction determines the total flux of 8B neutrinos, even if their flavor has been transformed. This makes the interpretation of the results

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IEEE TRANSACTIONS ON NUCLEAR SCIENCE, VOL. 42, NO. 4, AUGUST 1995 925

The Sudbury Neutrino Observatory Electronics Chain

D.F. Cowen, T. Ekenberg, J.R. Klein, F.M. Newcomer, R. Van Berg, R.G. Van de Water, P. Wittich

The University of Pennsylvania, Dept. of Physics A. Biman: R.L. Stevenson

Queen’s University, Dept. of Physics

May 18, 1995

A bst ra ct The Sudbury Neutrino Observatory (SNO) is a second

generation real time solar neutrino water Cherenkov de- tector using 1,000 Tonnes of D 2 0 viewed by almost 10,000 Photomultiplier tubes 20cm in diameter. The electronics chain is required to provide deadtimeless sub-nanosecond tinie and charge measurement for Photomultiplier pulses in the range of 1 - 1000 photo electrons. While the solar neutrino event rate is very low, the electronics chain must handle background rates in excess of 1 kHz and burst rates in excess of 1 MHz.

The electronics chain is implemented using three full cus- torn integrated circuits and commercial ADCs, memory, and logic. The DAQ interface is VME compatible.

We will briefly describe the SNO detector and then con- centrate on the design of the electronic system including novel features of the DAQ and trigger paths.

I. INTRODUCTION The Sudbury Neutrino Observatory (SNO) [l] is a second generation, underground, real time, solar neutrino, water Cherenkov detector. The detector will also be sensitive to atmospheric and supernova generated neutrinos. The SNO det,ector is located in a large cavity excavated at the 6800 foot level in the INCO, Ltd., Creighton mine near Sudbury, Ontario. The target for the solar neutrinos is 1,000 tonnes of DzO contained in a twelve meter diameter acrylic vessel surrounded by a light water shield of minimum diameter twenty two meters. A spherical geodesic shell of diameter seventeen meters surrounds the D 2 0 and supports almost 10,000 20 cm photomultiplier tubes (PMT), each with a light collecting reflector. The electronics chain, shown in Figure 1 , provides deadtimeless sub-nanosecond time and charge measurement for PMT pulses in the range of 1 - 1000 photo electrons. The electronics chain must handle background radioactivity rates in excess of 1 kHz and po- tential astrophysical burst rates in excess of l MHz.

The cavity for the detector is complete, the geodesic pho- tornultiplier support structure is presently being installed,

*Presently, Queen’s University7 Electrical Eiigiiieeriiig

and prototype electronics are being tested. The detector is scheduled to begin filling with water at the end of 1995 and data taking will commence in the beginning of 1996.

A . Physics Motivation The SNO experiment is designed to study the fundamental properties of neutrinos, in particular the mass and mixing parameters. This is to be accomplished by measuring the flux of electron type neutrinos, v,, which are produced in the sun, and by comparing it to the flux of all flavors of neutrino detected on earth in an appropriate energy inter- val. Observation of neutrino flavor transformation through this comparison is unambiguous evidence that at least one neutrino flavor has non-zero mass. Non-zero neutrino mass is evidence for physics beyond the Standard Model of fun- damental particle interactions. Non-zero neutrino mass might also have cosmological implications, and coiilcl ac- count for the presence of “hot” dark matter implied in some cosmological models by the observations of the cos- mic microwave background radiation anisotropy, angular correlations of galaxies, correlations of galaxy clusters, and other cosmological data.

The 1,000 tonnes of D 2 0 is utilized as a target to allow detection of neutrinos through the reactions

where v, refers to any flavor of interacting neutrino. The elastic scattering of neutrinos from electrons (1) is highly directional, and establishes the sun as the source of the detected neutrinos. The absorption of v, on deuterons (2) produces an electron with an energy highly correlated with that of the neutrino. This reaction is sensitive to the en- ergy spectrum of v, and deviations from the parent spec- trum. The disintegration of the deuteron by neutrinos ( 3 ) is independent of neutrino flavor and has a threshold of 2.2 MeV. Measurement of tthe rate of this reaction determines the total flux of 8B neutrinos, even if their flavor has been transformed. This makes the interpretation of the results

926

PMT Cables

- : l /

16 per Crate

\E ranslator Card 0

/w DAQ Control

Low Voltage Power

Trigger Cables

Global Trigger c-

via SNO I

Central Timing Test Time Counters

Calibration Timer GPS Link

Event Tagging

Figure 1: Block diagram of the SNO electronics system. The crate level electronics on the left side of the figure are repeated 20 times, and connect to the central system on the right of the figure.

of the experiment independent of theoretical calculations, unlike all other solar neutrino experiments.

The electrons from reactions (1) or (2) and gammas from (3) produce Cherenkov light which is then detected by the PhiTs. These events are low occupancy as they typically involve 50 hit PMTs or about 0.2% of the 9500 total. Re- construction of the event vertex and particle direction is made from timing of the hits. The total energy of the inter- action is proportional to the number of detected photons. Radioactive background events are concentrated at very low energies (<< 1% occupancy), while occasional higher energy cosmic ray muons or atmospheric and super nova neutrinos will involve much larger (I-50%) occupancies.

B. Electronics Overview

The conceptual design of the SNO signal processing elec- tronics (shown in Figure 1) is quite similar to the elec- tronics constructed for the Kaniiokande I1 solar neutrino experiment [a], but the SNO design uses modern custom integrated circuit technology to provide cost reduction and increased reliability to compensate for the order of mag- nitude increase in the number of photomultiplier tubes. This new front end circuitry will improve the performance of the SNO detector relative to Kamiokande I1 by factors of 4 in dynamic range, 2 in time resolution, 20 in power dissipation, 4 in area, and 2 in cost per channel. Most of this improvement is obtained by moving discrete and small scale integration analog components into three full custom,

application specific, integrated circuits:

0 A wide dynamic range integrator.

0 A fast, sensitive, discriminator and timing circuit.

0 An analog / digital pipelined memory.

Further cost reduction and improved functionality is ob- tained by using high volume, large scale integration, com- mercial components for the remainder of the circuitry.

The signal processing electronics is arranged into twenty identical VME-like crates, each processing signals from 512 photomultipiers. All of the analog processing, except for the actual analog to digital conversion, is contained in the three integrated circuits listed above. The integrator and discriminator chips were implemented in a fast comple- mentary bipolar process while the pipelined analog digi- tal memory is fabricated in a 1.2pm CMOS process. The design provides a self triggered, essentially deadtimeless, measurement of time (< 1 ns) and charge (< 0.1 to > 1000 photoelectrons) with a burst capability above 1 MHz and a sustained low energy event rate better than 1 kHz. One front end board processes 32 channels, digitizes the signals, and stores the digital results in a 4 MB memory (designed to buffer bursts such as would be expected from a nearby supernova). Sixteen front end boards are housed in each crate. A trigger formation board and a commer- cial VME single board computer (SBC) are also required in each crate. The PMT signal and high voltage are carried on a single cable (105 feet of 75R RG59-like waterproof

927

coaxial cable). There are 512 such cables connected in the rear of each crate. Programmable test, calibration, and di- agnostic facilities are implemented throughout the crate.

Each of the 20 signal processing crates is connected via ethernet to a central data acquisition system. The system trigger is provided by a fast central trigger processor which receives timing information from a GPS system and trigger primitive data from each crate. The trigger primitives are transmitted via dedicated cables to the central trigger logic which returns a global trigger signal for each interesting event.

In the sections below we separately describe the design and implementation of the signal, data, and trigger flows in some detail and then summarize the planned overall characteristics of the electronic system for the SNO detec- tor. We also include measurements of the performance of the prototype integrated circuits operating in a relatively realistic environment.

11. SIGNAL FLOW The analog pulse from each PMT travels over the coaxial line to the High Voltage Card and then into the Front End Card and the three custom integrated circuits. At this stage the system operates as 10,000 independent, asyn- chronous, data driven, pipelines. The outputs of these pipelines are treated synchronously and this process is de- scribed later in the section on Data Flow.

A. High Voltage Card One commercial bulk high voltage power supply provides D(: power for the 16 High Voltage Cards (HVCs) in one crate. A PMT base draws 140pA at design voltage, so each crate of 512 PMTs requires about 70 mA at 2,OOOV. Each HVC takes the bulk high voltage and provides cur- rent to 32 PMTs through individual isolating, filtering, and trimming networks. The HVC plugs into the rear of the signal processing crate and connects directly to the Front End Card in the front of the crate. The HVC also pro- vides disconnects for individual 750 cables, HV blocking capacitors for the PMT signal, overvoltage and breakdown protection for the integrated circuits, limited readback of thr PMT current, and a programmable calibration pulse source for each channel. The PMT signal is transmitted through a connector to the Front End Card (FEC) where it is properly terminated, split and attenuated.

B. Bipolar Chip Set On the FEC, the signal current is delivered to a four chan- nel discriminator chip (,CNOD) where any leading edge is observed by a fast differentiator while the current is split into two branches (approximately in the ratio 1:16) and fed into two separate channels of an eight channel charge integrator (SNOINT) . The discriminator (SNOD) and in-

PMT Output - Discriminator (Internal Signal)

1 RESET I SAMPLE1

Global Trigger

I I I I I I I I I I I I I I I I

0 25 50 75 100 125 150 175 200 ns

Figure 2: Single channel timing cycle. With no GT present, a channel resets automatically at the end of a timing cycle (- 200 ns).

tegrator (SNOINT) chips were fabricated as full custom designs in AT&T's CBICU-2 [3] process'.

The SNOINT chip, which uses high quality external capacitors for the actual integration, has dual integrator channels in order to increase the effective dynamic range to more than 14 bits. A multiple pole shaper network provides an internal analog delay of 14 ns with a current integration time of approximately 44 ns. This delay pro- vides time for the associated discriminator chip SNOD to release the reset clamp on the external capacitor.

Each channel of the SNOD chip has an independent dis- criminator and gate generators to provide the timing func- tions necessary for the SNOINT chip. The RESET signal which controls the integrator reset switch is also used to initiate a time measurement cycle and to provide system trigger primitives. Leading edge signal detection is pro- vided by a four stage comparator circuit with balanced AC and DC; hysteresis and programmable threshold. S N O D also provides a SAMPLE signal to control the separate recording of charge from instantaneous and reflected pho- tons.

The outputs of the high and low gain integrator sections (QHi and QLo) and the low level differential control sig- nals from the discriminator (RESET and SAMPLE) are delivered to a CMOS analog memory. The analog mem- ory then acquires voltage samples of the QHi and QLo integrals at the leading and trailing edges of SAMPLE. The leading edge of SAMPLE, at about 30ns, latches data for Short Sample (the direct light from the event) and the trailing edge, at 200ns, latches Long Sampk (re- flected light). In order to limit the complexity and area of the memory chip, only three of the four possible charge samples are actually recorded, as shown in Table 1 The ac-

'These chips are described in more detail in the accompanying pa- per: A Wide Dynamic Range Integrator-Discriminator-Timer Chip Se1 for P M T Applications.

928

4 MB DRAM

Not Used Total Reflected Light

BUS VME 7 INTERFACE

Table 1: Signal name and intended use of the three charge measurements.

tual choice of which three are recorded is a programmable feature of the memory chip.

C. CMOS Chip

The CMOS member of the SNO chip set provides analog memory, a Time to Amplitude Converter (TAC), chan- nel and trigger logic for the SNO detector. The produc- tion version of this chip (QUSN6) ’. provides a 16 deep, three Q (charge) and one T (time) analog memory with associated channel and trigger logic. This mixed analog / digital device is designed using full custom analog blocks coinbined with auto placed and routed standard cells and is fabricated in the Northern Telecom CMOS4S [4] process.

As shown in Figure 2, the timing sequence and TAC in QUSN6 are initiated on the leading edge of RESET. The TAC for any tube is stopped by a centrally gener- ated Global Trigger (GT) signal. The charge integral mea- surement voltages (low and high gain) from S N O I N T are sampled on the leading and trailing edges of the signal SAMPLE. If a GT signal arrives from the central trig- ger system before an internal time-out is reached, the four analog voltages (TAC, high gain long sample, low gain long sample and low gain short sample) are stored in one of the 16 analog memory banks and an associated digital mem- ory (a dual port RAM cell) records the sequence number of thn GT (to allow event building), the memory location (to allow second order corrections of the data) and any asso- ciated condition flags. If a GT signal does not arrive from the central trigger system before the internal time-out is reached, the channel resets itself and is ready to accept another PMT input signal. Thus the only deadtime is the per P M T deadtime of one GT timing cycle (set to about 200 ns to allow for light reflection across the SNO detector volume).

In addition to this basic FIFO like data path, the Q llSN6 chip includes a trigger generation function, some basic utility functions, and extensive self test capability.

Separate internal counters are used to scale RESET to ker:p independent track of PMT noise rates and count error conditions (such as FIFO full). All counters and latc,hes art? accessible for testing via an external scan path and a variety of programmable adjustments (such as fine varia- tions of the TAC slope) are built in.

2Tliis chip is described in more detail in the acconipanyillg pa- per: An Analog Memory, Time to Amplitude Converter, and Trigger Logic Chip fo r P M T Applications

DATA SEQUENCER GT !

AVAIL.

Digital Memory

,- Figure 3: On board data flow from the PMT inputs to the VME interface.

111. DATA FLOW While the write process into the analog memory is da ta drzven by a timely coincidence of a PMT pulse and a GT pulse, the readout sequence from the analog memory is an entirely separate process controlled by a pair of hand- shake lines - data available and chip select. This allows QUSN6 to operate without an external clock, thus reduc- ing the potential digital to analog cross talk.

A. Analog to Digital Conversion As shown in Figure 3, an output signal indicating new data available initiates an external readout sequencer (responsi- ble for all 32 individual chips on a single front end board). The sequencer is a clocked, synchronous state machine im- plemented in a standard FPGA. At the sequencer’s con- venience, a QUSN6 chip with DataAvailable held high is selected and the pending memory location presents four individually buffered analog voltages to the four on-board 12 bit 211,s ADCs. After the ADCk have sampled the ana- log voltages, the sequencer issues four read strobes tu the QUSN6. The first three strobes read three bytes of digital information; the 16 bit GT sequence number (or Trigger ID), four bits of cell address, and four flag bits. The fourth read strobe clears the memory location.

B. Bufler Memory

At the end of the sequencer’s cycle, a three word, 12 byte, fixed format data structure (Table 2) is loaded into the on- board memory. The memory is implemented as standard SIMM DRAM under the control of a commercial dual port controller. The sequencer operates one port of the con- troller as a FIFO while the second port is accessed via the VME bus interface. Each three word descriptor is complete in the sense that the measured time and charge and‘ the geographic (channel number) and temporal (GT sequence number) location or address are fully specified.

Note that since the ADCs take two microseconds to con- vert and a GT cycle is only 250 ns, i t is possible to build up several events in the analog memory before a conver- sion is requested and, because the sequencer reads out the

929

1

2

Flag Crate+Channel Trigger Identifier

Err QLoLong Flag QHiLong

Cell TAC Flag QHiShort

2 5 1 9 8 1 1 8

4 I 12 4 I 12

Table 2: Three word data structure (hit descriptor) for a single PMT hit.

SBC RAM DAQ SBC

Tape

QrJSN6 chips in round robin order, it is possible that hit descriptors will be loaded into memory out of temporal seL quence. This melange of data is sorted out in the central DAQ event builder where additional header information from the Timing and Trigger systems is added to the hit descriptors.

20 VME Backplanes - 0.4 GB)s Single Ethernet - 0.3 MB/s

Single Drive - 0.6 MB/s

C;. Backplane and VME Interface

Each crate has a VME single board computer (SBC) act- ing as crate master. This computer polls front end boards to read out data from buffer memories as it becomes avail- able. The SBC examines the write pointer for each board and compares the value to its internal list of last used read pointers - initiating a read of data from the board if the write pointer has advanced past the last read. Thus the memory in the SBC acts as one more level of derandomiz- ing buffer, the third after the 16 cell analog memory and tht. 4MB (1.3 x IO6 hit descriptors) buffer memory. The front end card is configured as a D32, A32, longword only, VME slave.

While the SNO backplane is, logically, a VME device, thrt physical backplane used to connect the front end and trigger cards uses metric FutureBus style connectors. In order to to reduce the susceptibility of the front end to in- terference and crosstalk from digital signals, the signals are transmitted as low level, controlled transition time, GTL and differential ECL signals. VME defined signals not re- quired for the D32, A32 slave protocols are not included on the backplane. SNO specific timing and triggering sig- nals such as GT, CNHit, and TestTime are included as part of the backplane. Connection from the SNO specific backplane to a small (4 slot) commercial VME backplane holding the crate SBC is via a translator board which han- dles the signal and logic conversion tasks.

D. Event Building

Full events are built at the central DAQ crate which is connected to the front end crate SBCk via a standard eth- ernet link. The link runs only between the DAQ SBC; and the 20 front end crate SBCs and so can operate using a restricted and somewhat more efficient subset of the stan- dard TCP/IP protocols. After events are built from the spatially and temporally disconnected fragments collected from across the DAQ network, they are stored on tape for

QUSN6 I 9,500 PMTs x 4MHz I 460 GB/s I I ’

FEC RAM I 300 FECs x 0.5 MHz I 1.8 GB/s I

later analysis. A small percentage of events will be exam- ined on line for monitoring purposes.

It should be noted that this data driven, self sparsi- fying architecture has inherently relatively modest band- width requirements but that the SNO electronics system is specifically designed to place bandwidth limits only in the natural positions after each level of buffering in the event building chain. The multiple sample analog memo- ries at the very front end allow a new PMT hit from each of 9,500 PMTs to be taken each trigger cycle (or - 250 ns). The 2ps ADCs feed into the 1.3 MHit board memory, the crate data goes over VME into the SBC memory, and the crate SBCs transmit data via ethernet into the cen- tral DAQ SBC and on to tape. The effective bandwidth at each step is indicated in Table 3. The most stringent bandwidth limitations, imposed by Ethernet and the tape drive, are not immutable parts of the design and the rates quoted could be easily increased if necessary.

IV. TRIGGERING The basic physics trigger for SNO is the generation of Cherenkov light by an electron or gamma ray. Each MeV of deposited energy results in about ten simultaneous pho- toelectrons detected by the PMT array. Thus the most powerful hardware trigger for detection of solar neutrinos is a simple count of the number of PMTs that have fired in the recent past. Because the PMT array is 17 meters in diameter, different photons from an interaction in the D20 could differ in travel time to the PMTs by as much as 66 ns. For this reason we have set a nominal trigger resolving time of about 100 ns to allow all direct photons from a Cherenkov event to be counted toward a possible trigger. The actual counting of hits is done via a chain of analog summations.

A. NHit Summations The leading edge of RESET is used in QUSN6 to initate a pair of independently programmable (digitally set width and delay) current pulses. The longer pulse (nominally 100ns) is sent to the first stage of a 10,000 input analog sum. This first stage ( C P M T = ~ 32NHi t ) is implemented using a high speed operational amplifier located on the front end card as shown in Figure 4. The output of the front end card sum is transmitted over the backplane to

930

Phir 1 B _I i - - - - l A

I/ PMT(N) o u t p u t - p r o m p t ~ g ~

1 SNOD(N) out to Trigger - - n GT

150 ns Cable Round Trlp + 20 ns Delay

PMT(N+I) Oulput . reflected light - * 05 ns Retlectlon Time

F-1 Phir 32 >fB*,

1 OOns - On Front End Card

Board14 ' A Board15 N Board 16 + c c Y

On Trigger Card

Figure 4: Trigger formation a t the crate level. The 20 ns trigger is implemented in an identical fashion.

thr crate trigger card where the next level of analog sum (Ccard=1..16NHit) is performed. The final level of sum- ming is done on the outputs of the 20 crate trigger cards. The output of this global sum circuit is then compared against a programmable threshold to look for occurrences of simultaneous PMT hits above this preset number. Any suin above the threshold will generate a Global Trigger (GT). SNO will typically look in the range of 10 to 40 si- multaneous firings (- 1-4 MeV). The second current pulse generated by QUSNti is nominally much narrower (about 20 ns) and will be used in an identical summing tree to generate a separate trigger for calibration and background studies where one wishes to limit the fiducial volume con- tributing to the trigger.

While the trigger is constructed as a linear sum of pulses from nearly 10,000 PMTs, the dynamic range required of the sum circuitry is very much less than 10,OOO:l as the SNO trigger will ordinarily he set, to fire a t about 30 to 40 PMT hits and certainly well below 100 PMTs (10 MeV of deposited energy). Thus, the actual full scale range requirement, is on the order of any 100 - 200 PMTs in the system and the implementation of the casc.aded analog sum system is much simpler.

R . Trigger Generation Normal triggers are initiated by the sum of NHit, described above, but provision is made for additional triggers for calibration and diagnostic purposes. For instance laser pulsers, test pulse generators, and the limited volume 20 ns trigger are also available. All of these trigger initiators feed into an OR in the central trigger system. The output of this OR is synchronized with the local high precision clock (50MHz). This synchronized signal latches the state of the inputs to the OR (identifying the relevant initiator) and the synchronized pulse is sent out to the front end crates as Global Trigger (GT). This sync,hronizat,ion process en- sures that all times are measured relative to a stable clock edge. Each GT also increments a 24 bit counter in the c.eiitra1 trigger logic (as well as the 16 bit counter in each of the QlJSNti chips) and the value of this count is used as the Trigger ID number to uniquely ident,ify individual evtmts. A resynchronization pulse (not shown in Figure 6), is issued every 216th GTs to check that all QUSNG Trig-

0 ns 50 100" 150'ns 200no 250ns

Figure 5: Trigger cycle diagram in the time frame of a Front End Card. A single prompt PMT hit a t time 0 travels to the central trigger system and helps to produce a GT which is received back at the FEC: at, time 175 ns. This initiates data acquisition for both the prompt hit ( P M T N ) and the reflected light late hit ( P M T N + I ) .

ger I D counters agree. Errors are reported by individual QlJSNti error flags and repeat errors would lead to chip replacement. As all GTs are identical from the point of view of the front end, there are no trigger biases intro- duced during calibrations or testing. As the GT reaches eac.h QIISNG any and all hits in the prior -200 ns period are latched and assigned a common Trigger ID number.

The actual width of a trigger cycle is programmablf, and is set to correspond to the longest possible path for re- flected light in the SNO tank plus adequate early and late buffer periods. The trigger cycle must also allow sufficient time for electrical signals to propagate from each crate to the central trigger and then return. The light transit time across the diameter of the 17 m PMT sphere is about 85 ns in water and the crates are placed such that about 20 m of cable (150 ns round trip for PI = 0.81c) is required from the front end crate to the central timing system. Thus trigger cycles on the order of 200 to 250 ns, as shown in Figure 5. are the correct length. With the GT timing shown in the figure and the internal time out in QUSNG set to 200 ns, an event would include data from PMTs firing up tlo 25 ns before and 175 ns after the initiating event,. The cen- tral trigger logic stores trigger initiator requests received just before the end of an ongoing trigger cycle and will is- sue a delayed GT exact,ly one cycle after the previous GT in order to efficiently collect all interesting data. In cases where continuous sampling of the detector is interesting, it. is possible t,o continue to issue GT pulses and read out all PMT hits up to the bandwidth limits of the event building system (see Section I I I D) .

C:. Time K r e p i n g

Two separate oscillators are used to keep a record of ab- solute and relative time. A commercial GPS system pro- vides a 10 MHz signal as well as precision time markers at requested [Jniversal Times. This system is nominally accurate to order 100 ns and will allow correlation of SNO data with that of other astronomical detectors. Since the GPS receiver must be on the surface and all the other elec- tronics is below ground, communication delays due to the

931

128 BITS

Trigger I ID

Lid R I O REO.

To From End

TestTimo

Figure 6: Counters and registers of the timing system. This four word (44 + 44 + 24 + 16 bits) time descriptor provides time of day and flag information for all of the three word PMT descriptor records having the same Trig- ger ID number. The 128 bits of time and identification information are built into the event header by the DAQ computer.

4 km long fiber optics must be continuously monitored. This is done by using a separate pair of fibers in the same bundle and measuring total round trip propagation time. As shown in Figure 6, a high stability quartz oscillator operating at 50MHz offers a higher precision short time standard and is used for all normal event reconstruction.

The data from the two long period (about 20 days of GPS oscillator and 4 days of quartz oscillator) counters plus the latched Trigger ID register and latched trigger initiator and flag bits is collected by the DAQ computer and used to identify the time of day of the event fragments bearing that Trigger ID number. This information plus other useful data is formed into a header for the event.

The programmable preset register allows the generation of an electronic timing pulse at a set time relative to the next GT pulse. This TestTinie pulse is distributed to all front end crates where it can be used (with appropri- ate mask bits) to enable pedestals, time ramps, or charge injection at the very front end of the signal chain.

V. PERFORMANCE Extensive measurements have been made of the prototype integrated circuits as single devices, as a coupled chip set, and on full functionality (but only eight channel) prototype boards running with the prototype DAQ software. The performance of the prototype bipolar chips is extremely close to that predicted in the pre-fabrication simulations. The first full-functionality CMOS prototype demonstrated the, required level of analog performance, but had three separate digital faults which have been corrected in the latest QUSN6 version. While rnany additional tests will be run, the charge linearity, obtained from the first board lexel tests, shown in Figure 7 and Figure 8 fully satisfies our design goals. The linearity and precision of the time mvasurement shown in Figure 9 are also significantly bet- ter than the minimum requirements of SNO. It is impor-

1 0 6

104

1 0 2

Slope= -1 0.24 +/- 0.06 (counts/pC)

8 1 0 1 2 1 4 0 2 4 6 Input Charge in units of pC ( l p C = 0.625pe)

Figure 7: Tincorrected ADC counts vs. pulser input charge in pC for QHiShort. For time slewing corrections the re- gion of greatest interest is from a fraction to a few pho- toelectrons. This data was taken using the full sequencer, 2ps ADC, buffer memory, VME readout chain. The verti- cal extent of the error bars reflects the measurement error, the horizontal extent is a feature of the plotting program.

tant to note that while these plots are all taken on a single board (eight channels per prototype board) with pulser rather than PMT inputs, in other respects the data is rep- resentative of final system performance. On the prototype board as in the final system there are multiple, indepen- dent, high speed queues each employing simultaneous read and write operations and, in addition, there are multiple asynchronous digital tasks being performed in the back- ground of the analog acquisition cycle.

Since the original submission of this manuscript, we have completed a number of single and multiple board tests us- ing both pulsers and sample SNO photomultiplier tubes3 and have verified stable and reliable operation of the chip set and system. We have operated multiple PMTs at thresholds less than 0.1 photoelectrons rms and demon- strated pedestal widths better than 0.1 pe for the high gain charge channel and about 125 ps rms for the time measurement. All three custom integrated circuits have been submitted for final production.

VI. SUMMARY A data driven, deadtimeless, pipelined, high dynamic range, electronics system has been designed for the Sud- bury Neutrino Observatory. This system integrates signal processing, triggering, and data collection in a coherent fashion. We are finishing prototype tests as of this writing and have begun the production of chips. Final board de- sign is nearing completion and production boards should be taking preliminary data from the detector this Fall. The efficiency of this system in terms of cost, power, and bulk is much improved because of the full custom integrated

3Hanmiainatsu R1408 20cm tubes, Hammamatsu Photonics Cor- porat i on, Hanmiamat su City, Japan.

932

References I - Slope= -1.141 +/ 0.003 (CountslpC)

0 100 200 300 400 Input Charge in units of pC ( l p C = 0.625pe)

Figure 8: Uncorrected ADC counts vs. pulser input charge in pC for QLoShort. The input attenuator is non-linear for the smallest signals on this range and the upper end of the range is limited by a protection diode which is refer- enced to ground in the prototype design.

' 1 2 0 303

2 8 0

7 0

6 0

Slope= ~3 .210 +/- 0.005 (counts/nsec)

- 1 I I I 100 1 5 0 200 2 5 0

Global Trigger Delay (nsec)

Figure 9: IJncorrected ADC count,s for TAC vs. the delay time from the charge input to GT. Data below 100 ns is not plotted because of one of the design faults in QU,'5"5, mentioned above, prevents correct analog dorage of times shorter than about 100ns.

circuits that make up the majority of the signal chain

VII. ACKNOWLEDGEMENTS

Wv would like to thank J . Wilkersori and R. Ahmad of the (Jniversity of Washington and F. McCiirt of Los Alamos Nat,ional Laboratory for the data acquisition code used to make the board level measurements described here. Jim Cook and Ron Pearce a t Penn and Alvin Bell a t Queen's made the prototype systems possible and Marc Jacobsen a t Penn made the wafer and chip level circuit measure- ments necessary to get beyond the single channel stage. Wc are also very much indebted to AT&T and Northern Telecom for invaluable technical advice as well as the very tangible and generous direct contributions made by both corporations to the design and fabrication of the integrated circuits.

[l] Sudbury Neutrino Observatory Proposal, G .T . Ewan et al., SNO-87-12, October, 1987.

[2] Real-tirne, Directional Measurement of 8B Solar Neu- trinos in the Kamiokande I1 Detector, K.S. Hirata et al. (Kamiokande Collaboration), Physical Review D44, 2241-60 (1991).

[B] AT&T Microelectronics, Allentown, Pennsylvania

[4] Northern Telecom, Ottawa, Ontario, Canada.