the timepix3 chip - indico€¦ · tdcpix (na62) ibm 130n 2012 300 45*40 toa and tot 48 0-suppresed...

The Timepix3 chip

C.Brezinaa, Y.Fua, M.De Gasparib, V.Gromovc, X.Llopartb*, T.Poikelab, F.Zapponc and A.Krutha

On behalf of the Medipix3 collaboration

a Bonn university b CERN c NIKHEF

Ou

tlin

e • Introduction

– Timepix3 Motivation – Pixel operation

• Measurements

– Timepix3 Readout System – PC and iTOT mode:

• Single Pixel gain and ENC • Full chip ENC • Equalization

– TOA and TOT: • TOT linearity • Timewalk • TOT linearity

– Results summary – Wafer Probing – Timepix3 TPC [Preliminary]

• Conclusions

ESE Seminar – X.Llopart 25th February 2014 2

Hybrid Pixel Detectors Operation Modes

• In a hybrid pixel detector the energy threshold is used to eliminate noise or low energy events → Noise-free system

• Nature of measurements after discriminator:

– Particle Counting (PC)

• Count of number of events in a fix time (Shutter)

– Time-Over-Threshold (TOT)

• TOT charge per event

• iTOT integral of the charge over a fix time (Shutter)

– Time of Arrival (TOA)

• Measure of the arrival time (Time stamping)

– Binary (Bi)

• 1 bit per event tagged with Bx

ESE Seminar – X.Llopart

Threshold

TOT

TOA

25th February 2014 3

4 25th February 2014 ESE Seminar – X.Llopart

Chip Name Technology Year Pixel Size

[um] Pixel Array

Pixel Operation Bits/Pixel Data Type

Start readout

Acquisition Type

Trigger Readout

Output data port

Medipix2 IBM 250n 2005 55 256*256 PC 14 Full frame External Non-

continuous No

1-LVDS @ 180 Mbps

EIGER UMC 250nm 2010 75 256*256 PC 4, 8 or 12 Full frame External Continuous No 32-bit CMOS DDR

@ 200 Mbps

Medipix3RX IBM 130n 2012 55 256*256 PC 1,6,12 or 24 Full frame External Continuous No 1,2,4 or 8-LVDS

@ 250 Mbps

Timepix IBM 250n 2006 55 256*256 PC, TOT or TOA 14 Full frame External Non-

continuous No

32-bit CMOS @ 100 Mbps

SmallPix IBM 130n 2014 ? 35-40 384*384 512*512

TOA and TOT PC and iTOT

24-32 0-compressed External Continuous No 1,2,4 or 8-LVDS

@ 250 Mbps

ClicPix_demo TSMC 65nm 2012 25 64*64 TOT and TOA 9 0-compressed External Non-

Continuous No

1 or 2-LVDS @ 640 Mbps

Alice1LHCb IBM 250n 2001 50*425 256*32 TOA and Binary 2 FIFO of 8 bit BCO 0-compressed External Continuous Yes 32-GTL

@ 40 Mbps

PSI46 (CMS) IBM 250n 2005 100*150 52*80 Analog ? 0-suppresed External Continuous Yes 6-8 bit analog

@ 40 MHz

FEI3 (ATLAS) IBM 250n 2006 50 *400 160*18 TOA and TOT

8-bit TOA + address

EOC event Buffering

0-suppresed External Continuous Yes 1-LVDS

@ 40 Mbps

FEI4 (ATLAS) IBM 130n 2011 50*250 336*80 TOA and TOT ? 0-suppresed External Continuous Yes 1-LVDS

@ 320 Mbps

TDCpix (NA62) IBM 130n 2012 300 45*40 TOA and TOT 48 0-suppresed Data

driven Continuous No

4 CML @ 3.2 Gbps

ToPIX (PANDA) IBM 130n 2012 100 116*110 TOA and TOT 48 0-suppresed Data

driven Continuous No

1-LVDS @ 312.4 Mbps

Timepix3 IBM 130n 2013 55 256*256 PC and iTOT TOA and TOT

TOA 44 0-suppresed

Data driven

Continuous No 1 to 8-SLVDS DDR

@ 640 Mbps

VeloPix IBM 130n 2014? 55 256*256 PC

TOA and TOT 30 0-suppresed

Data driven

Continuous No 4 CML

@ 5.2 Gbps

Dosepix IBM 130n 2010 220 16*16 TOT 256 Full frame External Semi-

Continuous No

1-CMOS @ 10 Mbps

Hybrid pixel ASICs classification (from 2012 seminar)

Imaging

HEP Low Rate

HEP Triggered

HEP Trigger-less

Dosimetry

Timepix (2006) • IBM 250nm 6-metals

• Operation modes:

– Particle arrival time (TOA)

– Charge information (iTOT)

– Event counting (PC)

• Frame based readout


CSA

DiscTHR

14 bits

Shift

Register

Input

Ctest

Testbit

Test Input

Mask

4 bits thr Adj

Mux

Mux

Clk_Read

Previous Pixel

Next Pixel

Conf

8-bits PCR Polarity

Ref_Clk

Timepix

Synchronization

Logic

Ref_Clkb

P0

P1

Shutter

OvControl

Clk_Read

Shutter_int

Analog Digital

Timepix Pixel Schematic Timepix picture

16

.12

mm

14.111 mm

55 µm


Timepix chip architecture

IO

Logic

LVDS

In

LVDS

Out32-bit CMOS Output

256-bit Fast Shift Register

358

4-b

it P

ixel

Co

lum

n-0

358

4-b

it P

ixel

Co

lum

n-0

Bandgap + 13 DACs

16120

m

14111 m

358

4-b

it P

ixel

Co

lum

n-1

358

4-b

it P

ixel

Co

lum

n-1

358

4-b

it P

ixel

Co

lum

n-2

55

358

4-b

it P

ixel

Co

lum

n-2

55

14080

m (

pix

el a

rray

)

Main Specs:

• 256x256 55µm square pixels

• Analog Power → 440mW

• Bits stored in pixel → 14

• Serial readout (@100Mbps) → 9.17 ms

• Parallel readout (@100Mbps) → 287 µs

• Full custom design

• > 36M Transistors


Timepix

• The Timepix (2006) has proven to be a versatile chip with a large range of applications: – X-ray radiography, X-ray polarimetry, low energy electron microscopy – Radiation and beam monitors, dosimetry – 3D gas detectors, neutrons, fission products – Gas detector, Compton camera, gamma polarization camera, fast

neutron camera, ion/MIP telescope, nuclear fission, astrophysics – Imaging in neutron activation analysis, gamma polarization imaging

based on Compton effect – Neutrino physics – Main Linear Collider application: pixelated TPC readout

• > 350 original paper citations



L. Pinsky

Timepix3 motivation • Main driving requirements:

1. Simultaneous TIME (TOA) and CHARGE (TOT) information per pixel 2. Minimize dead time → Event-by-event readout and 0-supressed 3. Monotonic TOT in both detection polarities 4. Improve time measurements resolution

• Experience gained in the design of the Medipix3 chip (2009): – Technology (130nm CMOS) – Building blocks recycled (CERN’s HD Standard Cell library, DACs, …)

• Designed by CERN, Nikhef and Bonn University with the support of the Medipix3 Collaboration


CERN 130nm HD Library

• Physical specs: – “Mainly” Low power transistors – Row Height is fixed to 2.4 µm – Well Tap library

• Maximum frequency < ~700 MHz (@1.5V) • Encounter Library Characterizer (ELC) used:

– Full Synopsis library: • lib, ecsm, ecsm_si and ccs • delays, static and dynamic power • Corners:

– 1.2V : -55C FF, 25C TT and 125C SS – 1.5V : -55C FF, 25C TT and 125C SS

– Verilog library – LEF files – HTML documentation

• ~50 cells are available in the library

• Used in Medipix3RX

6 µm

4.8

µm

Minimum DFF available in default CERN Standard

Cell 130nm library

5.6 µm

2.4

µm

Minimum DFF In the custom made High

density 130nm library x2 smaller !!!

1.8

µm

3.8 µm

Minimum DFF available in a commercial Standard

Cell 65nm library x4 smaller !!!


CERN 130nm HD Special cells (I)

• Cells with “non-standard” functional behaviour can be integrated

2.4

µm

3.6 µm

VOTERI_B_XL (VeloPix)

NOR5_A_XL (Medipix3RX)

2.8 µm


9.6

µm

18 µm

CERN 130nm HD Special cells (II)

• Cells with non-standard row height are also possible to integrate: – Row height multiple (2.4 µm)

– Pitch length multiple (0.4 µm)

4.8

µm

14.8 µm

640MHz VCO (Timepix3)

CLK_Q_RVT_XL (Timepix3)


Timepix vs Timepix3 Timepix (2006) Timepix3 (2013)

Pixel arrangement 256 x 256

Pixel size 55 x 55 µm²

Technology 250nm CMOS - 6Metals 130nm CMOS - 8Metals

Acquisition modes 1) Charge (iTOT) 2) Time (TOA) 3) Event counting (PC)

1) Time (TOA) AND Charge (TOT) 2) Time (TOA) 3) Event counting (PC) AND integral charge (iTOT)

Readout Type 1) Full-Frame 1) Data driven (DD) 2) Frame (FB)

Zero suppressed readout NO YES

Dead time per pixel > 300µs readout time of one frame

> 475ns Pulse measurement time + packet transfer time

Minimum timing resolution 10ns 1.562ns

On-chip Power pulsing (PP) NO YES

Minimum detectable charge ~750e- >500e-

Output bandwidth 1 LVDS ≤200Mbps 32 CMOS ≤3.2Gbps

1 to 8 SLVS @640Mbps DDR ≤5.2Gbps


~600x

6.4x

1.5x


1.6x

Swiss technology comparison

25th February 2014 ESE Seminar – X.Llopart 14

Timepix (2006) Timepix3 (2013)

Trigger-less frame based and zero-supressed readout

• Maximum frame rate (all pixels hit): 1300 fps @5.12Gbps

Acquisition time

Address[16-bit] 0xA Data[28-bits]

Data Packet (48 bits)

48bit 48bit 48bit 48bit 48bit

End of Command (48 bits)

Shutter

Qin

DataOut

ChipID [32b] 0x71 0xA0


Maximum frame rate [fps] Frame Based Readout

1

10

100

1000

10000

1 2 3 4 5 6 7 8

[fp

s]

number of active links [8b10b ON]

40Mbps

80Mbps

160Mbps

320Mbps

640Mbps

Worst case: all pixels readout 48bit/pixel and 8b10b → 3.932 Mbits/frame (x2.5 Mpix3)

~1300 fps


Trigger-less event-by-event data driven and zero-supressed readout

• Achievable count rate: – uniformly distributed events → ~40 Mhits/s/cm2 @5.12Gbps

• Full matrix readout: ~800 µs @5.12Gbps

Acquisition time

Address[16-bit] 0xB Data[28-bits]

Data Packet (48 bits)

48bit 48bit 48bit 48bit 48bit 48bit

End of Command (48 bits)

Shutter

Qin

DataOut

ChipID [32b] 0x71 0xB0


Maximum Event Readout Data Driven Readout

0

10

20

30

40

50

60

70

80

90

1 2 3 4 5 6 7 8

MH

itsP

rocc

ess

ed

/s

number of active links @640Mbps and 8b10b ON

20MHz40MHz60MHz80MHz>86MHz

Sys Clock

85.3 Mhits/s


Tpeak < 25ns

Pixel Operation in TOA & TOT [DD]

TOT (10 bits) =4

Preamp Out

Disc Out

Clk (40MHz)

FTOA (4 bits)=7 VCO Clk (640MHz)

TOT Clk (40MHz)

TOA (14-bit) 16383 X TOA (14 bits)=16383

16384 0 2 3 4 16383 16382 1

Pixel Readout Starts (475ns→ 19 clock cycles)

Global TOA (14-bit)


Tpeak < 25ns

Pixel Operation in TOA only [DD]

Preamp Out

Disc Out

Clk (40MHz)

FTOA (4 bits)=7 VCO Clk (640MHz)

TOA (14-bit) 16383 X TOA (14 bits)=16383

16384 0 2 3 4 16383 16382 1

Pixel Readout Starts (475ns→ 19 clock cycles)

Global TOA (14-bit)


Pixel Operation in PC and iTOT [FB]


Preamp Out

Clk (40MHz)

Shutter

Pixel readout can start in

Data Driven or Frame based

Disc Out

3 0 PC (14 bits)=3 1 2 PC (10-bit)

5 0 iTOT (14 bits)=5 1 2 3 4 iTOT (14-bit)


Timepix3 Pixel Schematic


Global threshold (LSB= ~10e-)

Front-end (Analog)

Leakage Current compensation

Preamp

Input pad

1 pixel

VCO @640MHz

Super pixel (Digital)

Control voltage

Common for 8 pixels

640MHz

TpA TpB

TestBit MaskBit

Front-end (Digital)

Counters &

Latches

clock (40MHz)

Time stamp

14

-bits

Synchronizer &

Clock gating

OP Mode

4-bit Local Threshold

~50mV/ke-

TOA (14-bit) FTOA (4-bit) TOT (10-bit) TOA & TOT

TOA (14-bit) FTOA (4-bit) TOA

iTOT (14-bit) PC (10-bit) PC & iTOT 3fF

3fF

Deserializer [1x31]

Super pixel FIFO

[2x31]

Data out to EOC

37

-bit

s

clock (40MHz)

Token arbitration

31

-bit

s

han

dsh

ake


T. Poikela

Timepix3 Pixel Operation

• 4 Look-up-tables (LUT) needed to decode pixel data: – 14-bit gray counter – 14-bit LFSR – 10-bit LFSR – 4-bit LFSR


Acquisition Modes Superpixel VCO

Measurement type On-pixel counter depth Valid Data bits

Time (TOA) AND Charge (TOT)

ON TOA TOT

Fast ToA

14-bit (gray counter) 10-bit (LFSR with overflow) 4-bit (binary counter with overflow)

28

OFF TOA TOT

Event Counter

14-bit (gray counter) 10-bit (LFSR with overflow) 4-bit (LFSR with overflow)

Time (TOA) ON

TOA Fast ToA

14-bit (gray counter) 4-bit (binary counter with overflow)

18 OFF

TOA Event Counter

14-bit (gray counter) 4-bit (LFSR with overflow)

Event counting (PC) AND integral charge (iTOT)

ON iTOT

Event counter 14-bit (LFSR) 10-bit (LFSR with overflow)

28 OFF

iTOT Event counter Event Counter

14-bit (LFSR) 10-bit (LFSR with overflow) 4-bit (LFSR with overflow)

Asynchronous column data transfer

• 2-phase handshake protocol using single rail coding

• Globally-asynchronous locally-synchronous column readout protocol (GALS)


CORNER

SS 1.4V 125C

[MHits]

TT 1.5V 25C

[MHits]

FF 1.6V -55C

[MHits]

SP 0 only 0.45 0.45 0.45

SP 63 only 0.41 0.45 0.465

All SPs 1.36 1.5 1.6

Full Matrix

174 192 205

T. Poikela

Pixel Matrix Clock distribution

• Nominal clock frequency is 40MHz (up to 80MHz)

• Synchronous clock distribution in the pixel matrix required for TOA time stamping:

– Simulated bottom to top skew is (1.05ns, 1.45ns and 2ns) in (FF, TT and SS) corners

• Minimize peak digital current consumption: – Configurable double-column pixel matrix clock phase shift:

– In pixel clock is gated if pixel is not hit


Number of phases # Columns with same clk phase

phase delay Peak current

clk distribution only

1 128 25ns 1.075 A

2 64 12.5ns 537.6 mA

4 32 6.25ns 268.8 mA

8 16 3.125ns 134.4 mA

16 8 1.5625ns 67.2 mA

Tim

epix

3 F

loo

rpla

n

ESE Seminar – X.Llopart 25th February 2014

Reset DACOutExtDAC

BandGapGlobal DACs

EoC

[0]

PLLx 2,4,8 and 16

Output Block

PP

ul[0

]

DataInEnableInT0_SyncShutter

EnablePowerPulsingExtTPulse

SLVS_TERM

DataOut[7:0]ClkOutData

ClkIn40PLLOut

Clk

Ou

t4

0,8

0,1

60

or

32

0

Pix

el M

atri

x

E-Fuses32 bits

VDDA/GNDA

VDDPLL/GNDPLL

Sup

erPixel[0

]

Sup

erPixel[0

]

Sup

erPixel[6

3]

Sup

erPixel[6

3]

Sup

erPixel[0

]Su

perP

ixel[63

]

Bus Controller48 bit bus

VDDA33

VDD/GND

Pixel MatrixData controller

Clk

40

Per

iph

ery

Buffered Bias Voltage

OscBias640

Slo

w C

on

tro

l&

Co

mm

and

D

eco

der

Analog Periphery Control Logic

IOP

ads

Res

et

EoC

[1]

PP

ul[1

]

PP

ul[2

]

OscB[2]

EoC

[12

6]

EoC

[12

7]

PP

ul[1

27

]

OscB[63]

PP

ul[1

28

]

OscB[0]

14100 µm

14

08

0 µ

m1

26

0 µ

m8

70

µm

26

1 BandGap 18 Global DACs

EoC

[0]

PLL 8x Serializer 8b10b DDR

E-Fuses 32 bits C

lk4

0

Buffered bias voltages

VCO bias 640MHz

Slow Control &

Command Decoder

Analog Periphery Control Logic

EoC

[1]

EoC

[2]

VCO Buffer[2]

EoC

[12

6]

EoC

[12

7]

VCO Buffer[63] VCO Buffer [0]

14080 µm

12

60

µm

Bus Controller

Timepix3 Active Periphery

Data output DDR 8b10b encoding (1 to 8 links) Up to 8x640 Mbps (5.12 Gbps)

Periphery bus (3.84Gbps)

64 VCO control voltage buffers

128 End of Column logic


Timepix3 IO


Timepix3 Differential I/O

Name Type VID(mV) VICM (V) VOD (mV) VOCM (V)

Min Max Min Max Min Max Min Max

DataIn I SLVS/LVDS 80 1500 0.1 1.3 - - - -

EnableIn I SLVS/LVDS 80 1500 0.1 1.3 - - - -

Reset I SLVS/LVDS 80 1500 0.1 1.3 - - - -

T0_Sync I SLVS/LVDS 80 1500 0.1 1.3 - - - -

Shutter I SLVS/LVDS 80 1500 0.1 1.3 - - - -

EnablePowerPulsing I SLVS/LVDS 80 1500 0.1 1.3 - - - -

ExtTPulse I SLVS/LVDS 80 1500 0.1 1.3 - - - -

ClkIn40 I SLVS/LVDS 80 1500 0.1 1.3 - - - -

ClkInRefPLL I SLVS/LVDS 80 1500 0.1 1.3 - - - -

PLLOut O SLVS - - - - 70 380 0.19 0.25

DataOut[7:0] O SLVS - - - - 70 380 0.19 0.25

ClkOut O SLVS - - - - 70 380 0.19 0.25

Timepix3 CMOS I/O

Name Type VIL(V) VIH (V)

Min Max Min Max SLVS_TERM I CMOS -0.2 0.5 1 1.6

Timepix3 Analog I/O

Name Type VI(V) VO (V)

Min Max Min Max DACOut O Analog - - GNDA VDDA (1.5)

ExtDAC I Analog -0.2 1.6 - -


Periphery Command List


Periphery Operation Header [8 bits] Header DataIN [16 bits] DataOut [40 bits]

AnalogPeriphery

SenseDACsel ExtDACsel SetDAC_Code ReadDAC_code

I I I

IO

0x00 0x01 0x02 0x03

{DAC Code}[4:0] {DAC Code}[4:0]

{DAC Value}[13:5] {DAC Code}[4:0] {DAC Code} [4:0]

{DAC Value}[13:5] {DAC Code}[4:0]

EFuse_Burn EFuse_Read EfuseRead_BurnConfig

I I O

0x08 0x09 0x0A

{FuseProgramConfig}[10:0]}

{8’b0} [39:32]{ChipID}[31:0] {FuseProgramConfig}[20:0]}

TP_Period TP_PulseNumber TPConfig_Read TP_internalfinished

I I O O

0x0C 0x0D 0x0E 0x0F

{TPphase} [11:8]{ TPperiod }[7:0] {TPnumber }[15:0]

{TPphase, TPperiod, TPnumber}[27:0] 8’b{0000_1111}{ChipID}[31:0]

OutputBlockConfig OutBlockConfig OutBlockConfig_Read_en

I O

0x10 0x11

{OutputBlockConfig}[12:0] {27’b0} [39:13] {OutputBlockConfig}[12:0]

PLLConfig PLLConfig PLLConfig_Read_en

I O

0x20 0x21

{PLLConfig}[7:0] {32’b0} [39:8] {PLLConfig}[7:0]

GeneralConfig

GeneralConfig GeneralConfig_Read_en SLVSConfig SLVSConfig_Read_en PowerPulsingPattern PowerPulsingConfig_Read_en PowerPulsingON_finished

I O I O I O O

0x30 0x31 0x34 0x35 0x3C 0x3D 0x3E

{GeneralConfig}[11:0]

{SLVSConfig}[4:0]

{PowerPulsingPattern}[7:0]

28’b0} [39:12] {GeneralConfig}[11:0]

{35’b0} [39:6] {SLVSConfig}[4:0]

{32’b0} [39:8] {PowerPulsingPattern}[7:0]

8’b{0011_1111}{ChipID}[31:0]

Timer

ResetTimer SetTimer_15_0 SetTimer _31_16 SetTimer _47_32 RequestTimeLow RequestTimeHigh TimeRisingShutterLow TimeRisingShutterHigh TimeFallingShutterLow TimeFallingShutterHigh T0_Sync_Commnad

I I I I O O O O O O O

0x40 0x41 0x42 0x43 0x44 0x45 0x46 0x47 0x48 0x49 0x4A

{SetTimer[15:0]}[15:0]

{SetTimer[31:16]} [15:0] {SetTimer[47:32]} [15:0]

{8’b0} [39:32]{Timer[31:0]}[31:0] {24’b0} [39:16]{Timer[47:32]}[15:0]

{8’b0} [39:32]{TimerShutterR[31:0]}[31:0] {24’b0} [39:16]{TimerShutterR[47:32]}[15:0]

{8’b0} [39:32]{TimerShutterL[31:0]}[31:0] {24’b0} [39:16]{TimerShutterL[47:32]}[15:0]

ControlOperation

Acknlowledge EndOfCommand OtherChipCommand WrongCommand

O O O O

0x70 0x71 0x72 0x73

{H1,H2,H3} [39:32] { ChipID} [31:0] {H1,H2,H3} [39:32] {ChipID} [31:0]

{8’b0} [39:32] { ChipID} [31:0] {H1,H2,H3} [39:32] {ChipID} [31:0]


Power pulsing strategy in Timepix3

• Analog power-pulsing:

– Preamp (3µA), DiscS1 (2µA) and DiscS2 (2µA) are the ~98% of the analog power consumption in the pixel matrix (460mA)

– One Periphery multiplexer for the 3 biasing lines in each double column selects between the Power-ON or Power-OFF states

– Power-ON (8-bits) and Power-OFF (4-bits) values are programmed in 2 periphery DACs for each power pulsed bias line

– Power pulsing multiplexer is selected by a sequential column to column signal with independent adjustable turn-on and turn off times

• System clock gating:

– Clock gating is applied at the end of the analog power-off sequence

– This feature can be disabled


Power pulsing time diagram


OFF (<25mW)

64 bits

PowerPulsingSettings DataIn

EnablePowerPulsing

Power Pulsing ON Finished

ChipID 0h3F3F DataOut

ClockDividerPP_ON[2:0] = 000 NumberOfSimultaneousColumnsPP_ON[5:3] = 100 ClockDividerPP_OFF[8:6] = 010 NumberOfSimultaneousColumnsPP_ON[11:9] = 101 EnablePowerPulsingInDigitalDomain = 1

ON (~750mW) AnalogPower

ON OFF

0.8 µs @ 40 MHz

6.4 µs @ 40 MHz

ON

ON Clock (internal)

Ramp-down Ramp-up

0.8 µs ≤ Ramp-up/down ≤ 2.56 ms @40MHz

Dat

a o

utp

ut

pac

ket

typ

es


Pixel Matrix Configuration

Acquisition (VCO OFF)

Address[43:28]{1010 or 1011}[47:44] TOA[27:14] TOT[13:4]ToA and ToT mode

Only ToA

Event Count and iToT

FTOA[3:0]

Address[43:28] TOA[27:14] dummy[13:4] FTOA[3:0]

Address[43:28] iTOT[27:14] EventCounter[13:4] dummy[3:0]

dummy[27:20]

Address[43:28] TOA[27:14] TOT[13:4] HitCounter[3:0]

Address[43:28] TOA[27:14] dummy[13:4]

Address[43:28] iTOT[27:14] EventCounter[13:4]

HitCounter[3:0]

HitCounter[3:0]

Acquisition (VCO ON)

{1010 or 1011}[47:44]

{1010 or 1011}[47:44]

{1010 or 1011}[47:44]ToA and ToT mode

Only ToA

Event Count and iToT

{1010 or 1011}[47:44]

{1010 or 1011}[47:44]

Address[43:28] PCR[19:14] dummy[13:0]{1001}[47:44]Pixel Configuration

dummy[9:2]Address[43:37] CTPR[1:0]{1101}[47:44]CTPR Configuration

Periphery Configuration

DataOutPeriphery [39:0]{H2,H3}[46:40]Periphery Command

Control Commands

ChipID[31:0]{0111_0000}[47:40]Acknowledge cmd {H1,H2,H3}[39:32]

ChipID[31:0]{0111_0001}[47:40]End of cmd {H1,H2,H3}[39:32]

ChipID[31:0]{0111_0010}[47:40]Other Chip cmd {0000_0000}[39:32]

EoC[27:10]Dummy[36:28]

{0}[47]

@ data readout

dummy[43:0]Stop Matrix Readout

or Reset Sequential{1111 or 1110}[47:44]

ChipID[31:0]{0111_0011}[47:40]Wrong cmd {H1,H2,H3}[39:32]


00.10.20.30.40.50.60.70.80.9

11.11.21.31.41.51.61.71.81.9

22.12.2

0.1 1 10 100 1000 10000 100000

Po

wer

[W

]

Chip Hit Rate [Mhits/s]

Hit Processing

Idle

Periphery

Digital

Analog

Total

Power Consumption Data Driven [VDD=1.5V and VDDA=1.5V]


<1.5 W @80MHit/s

00.10.20.30.40.50.60.70.80.9

11.11.21.31.41.51.61.71.81.9

22.12.2

0.1 1 10 100 1000 10000 100000

Po

wer

[W

]

Chip Hit Rate [Mhits/s]

Hit ProcessingIdlePeripheryDigitalAnalogTotal

Power Consumption PC Frame-based [VDD=1.5V and VDDA=1.5V]


Data Driven limit ~100 KHz/pixel

14100 µm

16

21

0 µ

m

Sen

siti

ve A

rea

(14

08

0 µ

m)

Active Periphery (1260 µm)

Pad extenders (870 µm)

Timepix3 Layout


Double column: 2x256pixels 64 super pixels

55 µm

55

µm

Super Pixel (SP): • 2x4 pixels • 110x220 μm2

Full Pixel Matrix: 256x256 pixels 128 double columns 8192 VCOs (640MHz) 177 Mtransistors

Active Periphery

Pad Extenders: Removed if TSV

Analog Front-End: • 13x55 μm2 • <25% pixel area

VCO (FTOA): • 9.6x20 μm2 • < 0.8% SP area

IO Pad on digital area: • Careful shielding • Pad is ½ of Timepix


Medipix chip family


0.01

0.1

1

10

0 100 200 300 400 500 600 700

Tra

nsis

tor

den

sit

y p

er

pix

el

[trt

s/µ

m2]

CMOS process [nm]

Medipix1 (1998)

Medipix2 (1998)

Timepix (2006)

Timepix3 (2013)

Medipix3RX (2011)

Clicpix (2013)


MEASUREMENTS


Timepix3 readout → SPIDR (Nikhef)

• Speedy PIxel Detector Readout (SPIDR):

– Readout system for Medipix3 and Timepix3 (single upto quads)

– 1 x 10Gbps Ethernet link IO

• First chips available since beginning of September 2013

• All measurements reported use data readout @640Mbps/link


Timepix3 Chip

VC707 Evaluation Board

10 Gbit Ethernet

Virtex 7 FPGA


Timepix3 CERN PCBs


Timepix3 CERN chip board

Timepix3 Probe card

Timepix3 translator FMC/VHDCI

J. Alozy

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

1.1

1.2

1.3

1.4

1.5

0 64 128 192 256 320 384 448 512

[V]

DAC Code [LSB]

IB_PRE_ON

VPRE_NCAS

IB_IKRUM

VFBK

IB_DIS1_ON

IB_DIS2_ON

IB_PIXDAC

IB_TPBIN

IB_TPBOUT

VTP_COA

IB_CP_PLL

VTHR_FIN

VTP_FINE

IB_PRE_OFF

VTHR_COA

IB_DIS1_OFF

IB_DIS2_OFF

PLL_VCNTRL

Timepix3 DACs


VTHR (~10e- LSB) Range: 5.11 ke-

TestPulse (~50e- LSB) Range : > 18ke-


Pixel Data readout

• Data readout in Data Driven and Frame Based readout works as predicted in post-layout digital simulations

Frame based Full column readout


0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

0 50 100 150 200 250

Eve

nt

rate

(M

Hit

s)

Event number

TT1.5V25C

SS1.4V125C

FF1.6V-55C

0.7

0.9

1.1

1.3

1.5

1.7

1.9

2.1

0 50 100 150 200 250

Eve

nt

rate

(M

Hit

s)

Event number

TT1.5V25CSS1.4V125CFF1.6V-55CMeasured

250 Test Pulses in 1 pixel [Threshold scan in PC & iTOT mode, 1 pixel]


0

100

200

300

400

500

-25 0 25 50 75 100 125 150 175 200 225 250

Co

uu

nts

Threshold DAC [LSB]

Noise Floor

TP=988e-

TP=1542e-

TP=2004e-

ENC ~5.7 LSBrms = ~60 e-

y = 10.4 e-/LSBR² = 0.999

0

500

1000

1500

2000

2500

-25 0 25 50 75 100 125 150 175 200 225 250

Co

uu

nts

Threshold DAC [LSB]

Assuming: Ctest=3fF → Tpulse=20e-/mV


250 Test Pulses in 256 pixels [Threshold scan in PC & iTOT mode, pixel matrix equalized]


0

125

250

375

500

0 250 500 750 1000 1250 1500 1750 2000 2250 2500

Co

un

ts

[e-]

Noise Floor

TP=988e-

TP=1542e-

TP=2004e-

y = 1.0014xR² = 0.9999

0

500

1000

1500

2000

2500

0

20

40

60

80

100

0 250 500 750 1000 1250 1500 1750 2000 2250 2500[e-]

~3.9% rms pixel-to-pixel gain variation


Pixel ENC [Threshold scan over noise floor in PC & iTOT mode, 3 random pixels]


0

100

200

300

400

500

600

700

800

900

-500 -400 -300 -200 -100 0 100 200 300 400 500

Co

un

ts

Threshold [e-]

ENC = 56.2e-rms

ENC = 59.8e-rms

ENC = 56.7e-rms


0

2000

4000

6000

8000

10000

0 10 20 30 40 50 60 70 80 90 100C

ou

nts

ENC [e-]

Full Matrix ENC [Threshold scan over noise floor in PC & iTOT mode]


µ = 59.9e-

σ = 2.85e-

9 pixels not responding

15 pixels ENC > 80e-

1 256

256

1

X (column number)

Y

0 25 50 75 100

• ENC matches predictions from simulations


0

1000

2000

3000

4000

5000

6000

7000

8000

9000

-1500 -1250 -1000 -750 -500 -250 0 250 500 750 1000 1250 1500

Co

un

ts

[e-]

Pixel-to-pixel Threshold Equalization [Threshold scan over noise floor in PC & iTOT mode]


1 256

256

1

X (column number)

Y

-1500 -750 0 750 1500

µ0 = -762e-

σ0 = 195e-

1 256

256

1

X (column number)

Y

-1500 -750 0 750 1500

µF = 762e-

σF = 197e-

1 256

256

1

X (column number)

Y

-1500 -750 0 750 1500

µeq = 0e-

σeq = 35e-

Pixel DAC = 0x0 Pixel DAC = 0xF


Full chip minimum threshold [Equalized pixel matrix, 16 pixels masked]


1

2

4

8

16

32

64

128

256

512

1024

2048

4096

8192

16384

32768

65536

0 100 200 300 400 500 600 700 800 900 1000

Nu

mb

er

of

acti

ve p

ixe

ls

Threshold [e-]

TOA and TOT in Data Driven Readout mode

PC and iTOT in Sequential Readout mode

TOA and TOT (VCO ON) ~500e-

ENC of ~77e-rms PC and iTOT ~400e-

ENC of ~60e-rms

~100e-


1 256

256

1

X (column number)

Y

947 951.5 956 960.5 965

Corrected TOA measurement

FTOA Uniformity (1.562 ns/bin) [ Full matrix TOA & TOT mode, 1 single Test Pulse]


1 256

256

1

X (column number)

Y

947 951.5 956 960.5 965

Horizontal spread: 16-clock phase distribution (16 bins)

Vertical spread: ~3ns Test pulse propagation delay (3 bins)

RAW TOA measurement → data 18 bins

[FTOA LSB]


0

5000

10000

15000

20000

25000

30000

35000

40000

45000

50000

-10 -5 0 5 10

pix

el n

um

ber

VCO bin [LSB]

σ=~0.55 LSBrms

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0

10

20

30

40

50

60

70

80

0 2.5 5 7.5 10 12.5 15 17.5 20

[µs]

tim

e [n

s]

[ke-]

TOA

TOT

TOT (Linear fit)

Timewalk and TOT linearity [Qin scan in TOA & TOT mode, pixel (0,0), threshold at 500e-, 64 events averaged]


TOT slope ~75ns/ke-

Electrical Test Pulse: • ~18 ke- maximum Test Pulse • Resolution ~50e-/step

Threshold at ~500e-


Timewalk and TOT linearity [Qin scan in TOA & TOT mode, pixel (0,0), threshold at 500e-, 64 events averaged]


0

10

20

30

40

50

60

70

80

0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5

tim

e [

ns]

[ke-]

TOA (TOT>0)

TOA (TOT>7)

Threshold at ~500e-

Timewalk < 10ns @Threshold + 1ke-


TOT spread [Qin scan in TOA & TOT mode, diagonal pixels, threshold at 500e-]


0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

0 2.5 5 7.5 10 12.5 15 17.5 20

[µs]

[e-]

Threshold at ~500e-

TOT spread ~6.5%rms


Summary of measurements


Timepix (2006) Timepix3 (2013)

ENC (without sensor) 100e-rms 59.9e-rms ± 2.85e-rms

Threshold distribution 250e-rms ~195e-rms

Threshold distribution equalized 35e-rms < 35e-rms

Minimum Threshold (without sensor) >650e- >400e- (PC & iTOT) >500e- (TOA & TOT)

Pixel analog power consumption 6.5µW @ 2.2V < 12µW @ 1.5V < 0.5µW if power pulsing ON

Measured Timewalk <50ns @ 1ke- over threshold <10ns @ 1ke- over threshold

TOT spread ~5%rms ~6.5%rms

An absolute calibration using a radiation source is needed in order to confirm the values presented


Timepix3 Wafer Probing

1. Burning e-fuses → Produces a unique ChipID 2. Power consumption (analog, digital) 3. Control voltages (Bandgap, PTAT, PLL control, …) 4. Register values after reset 5. DACs scan 6. Matrix configuration write & read 7. S-curves with analog test pulses (Event counting mode) →

gain spread 8. Noise scan (Event counting mode) → baseline & noise

spread 9. TOA & TOT measurement with digital test pulses → TOT

counter, TOA gray counter, fine TOA counter & VCO


S. Kulis

Power Consumption after Reset


Digital Power Consumption [W] Analog Power Consumption [W]

S. Kulis

Wafer Probing Yield [W1]


Category A (52%): less than 30 bad pixels

(randomly distributed across the whole matrix)

Category B (8%): one dead column (more than 8

bad pixels in one column), or one dead super pixel (more

than 4 bad pixels in one sp), or more than 30 bad pixels

Category C (20%): two dead double columns or

dead super pixels, or more than 256 bad pixels

Category K (15%): Kidnapper pixel Category Y (5%) : Yelling pixel

S. Kulis

First Timepix3 based TPC


Micromegas: • 50 μm pillars; • square pitch of holes: 60 μm Timepix-3: • no protection layer:

J. Visser M. Van Beuzekom

Hitmap


• Few minutes data at the 2 GeV electron beam at DESY

• Moire pattern due to mismatch of

TPX3 and micromegas grid (55 and 60 um, resp.)


Track projections


Gas: He-Isobutane Gas: Ar-Isobutane


Conclusions

• Timepix3 is a new version of the Timepix chip. Main characteristics: – Simultaneous TOA and TOT measurement – Data driven and zero-suppressed readout (80Mhits/s/chip) – Minimum detectable charge > 500e- (all modes) – Time resolution up to 1.562 ns

• All measurements (without sensor) indicate that the Timepix3 chip

is fully functional as designed

• First wafer probed shows reasonable yield comparable to Medipix3RX

• First assemblies with a semiconductor sensor should be available in

< 2 months


Ack

no

wle

dge

men

ts

University of Canterbury, Christchurch, New Zealand CEA, Paris, France CERN, Geneva, Switzerland, DESY-Hamburg, Germany Albert-Ludwigs-Universität Freiburg, Germany University of Glasgow, Scotland, UK Leiden University, The Netherlands NIKHEF, Amsterdam, The Netherlands Mid Sweden University, Sundsvall, Sweden IEAP, Czech Technical University, Prague, Czech Republic ESRF, Grenoble, France Universität Erlangen-Nurnberg, Erlangen, Germany University of California, Berkeley, USA VTT, Information Technology, Espoo, Finland KIT/ANKA, Forschungszentrum Karlsruhe, Germany University of Houston, USA Diamond Light Source, Oxfordshire, England, UK Universidad de los Andes, Bogota, Colombia University of Bonn, Germany AMOLF, Amsterdan, The Netherlands Technical University of Munich, Germany Brazilian Light Source, Campinas, Brazil


Timepix4?


SPARE


Wafer Probing - Digital Issues

• Dead pixels: Change of pixel configuration (trim DAC, mask, test pulse) is not possible

• Kidnapper pixels: Pixel grabs readout token and does not release it, preventing other pixels from sending data (matrix reset is required)

• Yelling pixels: Once pixel starts sending data, it does not stop (it produces continuous stream of ~400 khits/s)

19/02/2014 Szymon KULIS (CERN) 63/17

S. Kulis


Pixel Operation Modes


Header 4 bits

Address 16 bits

ToA 14 bits

ToT 10 bits

Fine time 4 bits

ToA/ToT Mode:

Header 4 bits

Address 16 bits

ToA 14 bits

Not used 10 bits

Fine time 4 bits

Only ToA mode:

Header 4 bits

Address 16 bits

iToT 14 bits

Event count 10 bits

Not used 4 bits

Event count mode:


Some photos

Diced chips in gelpack


1.00E-09

1.00E-08

1.00E-07

1.00E-06

1.00E-05

1.00E-04

1.00E-03

1.00E-02

1.00E-01

1.00E+00

0.001 0.01 0.1 1 10 100

Non-sparse

Sparse-readout

Motivation: Data driven Readout instead of frame-based


Rea

do

ut

tim

e o

f p

ixel

mat

rix

(s)

% % % % % %

% of pixels hit

Frame-based (Timepix)

Break-even point

Assumptions: 32 bits/pixel 65536 pixels / chip


Voltage DAC INL and DNL


0 16 32 48 64 80 96 112 128 144 160 176 192 208 224 240 2565

4

3

2

1

0

1

2

3

4

5

DNL

INL

+1 LSB

-1 LSB

DAC Code

LS

B


Timepix to Timepix3


Timepix3 (2013) Timepix (2006)


Timepix chip architecture

IO

Logic

LVDS

In

LVDS

Out32-bit CMOS Output

256-bit Fast Shift Register

358

4-b

it P

ixel

Co

lum

n-0

358

4-b

it P

ixel

Co

lum

n-0

Bandgap + 13 DACs

16120

m

14111 m

358

4-b

it P

ixel

Co

lum

n-1

358

4-b

it P

ixel

Co

lum

n-1

358

4-b

it P

ixel

Co

lum

n-2

55

358

4-b

it P

ixel

Co

lum

n-2

55

14080

m (

pix

el a

rray

)

Main Specs:

• 256x256 55µm square pixels

• Analog Power → 440mW

• Bits stored in pixel → 14

• Serial readout (@100Mbps) → 9.17 ms

• Parallel readout (@100Mbps) → 287 µs

• Full custom design

• > 36M Transistors

Dynamic power is mitigated because:

• EoC is a serializer (FSR)

– 256-to-1 in serial readout

• Pixel Matrix frequency clock / 256

– 256-to-32 in parallel readout

• Pixel Matrix frequency clock / 8

• Pixel column sequential readout clock:

– Max readout clock frequency (parallel readout) at pixel matrix is 12.5 MHz for a 3.2 Gbps chip readout

– Column clock tree made by one “large” buffer in the EoC


the timepix3 chip - indico€¦ · tdcpix (na62) ibm 130n 2012 300 45*40 toa and tot 48 0-suppresed...

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