theory related to microprocessors

7/31/2019 Theory Related to Microprocessors

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A Microcontroller is a programmable digital processor with necessary peripcomplex sequential digital circuits meant to carry out job according to the interface makes a part of microcontroller circuit of mix

A microcontroller can be compared to a Swiss knife with multiple functions in

Fig. 1.1 A Microcontroller compared

Microcontrollers Vs Microprocessors

1. A microprocessor requires an external memory for program/data stfrom the external memory to the microprocessor or vice versa. Usuthey have higher clock speed to facilitate faster computation.

2. A microcontroller has required on-chip memory with associated

microprocessor with inbuilt peripherals.3. A microcontroller does not require much additional interfacing ICs

The operation of a microcontroller is multipurpose, just like a Swiss

4. Microcontrollers are also called embedded controllers. A microconMicrocontrollers are numerous and many of them are application sp

Development/Classification of microcontrollers (Invisible)

Microcontrollers have gone through a silent evolution (invisible). The evolapplication of a microcontroller is not well known to a common user, althougchange since early 1970's. Development of some popular microcontrollers is

Intel 4004 4 bit (2300 PMOS trans

Intel 8048 8 bit

Intel 8031 8 bit (ROM-less)Intel 8051 8 bit (Mask ROM)

Microchip PIC16C64 8 bit

Motorola 68HC11 8 bit (on chip ADC)

Intel 80C196 16 bit

Atmel AT89C51 8 bit (Flash memory)

Microchip PIC 16F877 8 bit (Flash memory + A


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Development of microprocessors (Visible)

Microprocessors have undergone significant evolution over the past four dcommon user, especially, in terms of phenomenal growth in capabilities microprocessors can be given as follows.

Intel 4004 4 bit (2300 PMOS transistor

Intel 80808085

8 bit 8 bit

Intel 80888086

16 bit16 bit

Intel 8018680286

16 bit16 bit

Intel 80386 32 bit (275000 transistors)

Intel 80486 SXDX

32 bit32 bit (built in floating point u

Intel 80586 IMMX

Celeron IIIII

IV

64 bit

Z-80 (Zilog) 8 bit

Motorola Power PC 601602

603

32-bit

Module 1 : Introduction to Microcontrollers

Lecture 2 : Basic Architectures of Microcontrollers


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We use more number of microcontrollers compared to microprocessors. purpose, whereas microcontrollers find wide application in devic

Application of microcontrollers are numerous. Starting from domestic airconditioners, microcontrollers are used in automobiles, process control inspace applications.

Microcontroller Chips

Broad Classification of different microcontroller chips could be as follows:

Embedded (Self -Contained) 8 - bit Microcontroller

16 to 32 Microcontrollers

Digital Signal Processors

Features of Modern Microcontrollers

Built-in Monitor Program

Built-in Program Memory

Interrupts

Analog I/O

Serial I/O

Facility to Interface External Memory

Timers

Internal Structure of a Microcontroller


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Fig. 2.1 Internal Structure of a M

At times, a microcontroller can have external memory also (if there is no inEarly microcontrollers were manufactured using bipolar or NMOS technolowith CMOS technology, which leads to reduction in size and power loss. Cur10mA to a few micro Amperes in sleep mode(for a microcontroller running ty

Harvard vs. Princeton Architecture

Many years ago, in the late 1940's, the US Government asked Harvard aarchitecture to be used in computing distances of Naval artillery shell forarchitecture with a single memory interface. It is also known as Von Neumanproject in Princeton University John Von Neumann (1903 - 1957 Born in Bud

Harvard suggested a computer with two different memory interfaces, oneinstructions. Although Princeton architecture was accepted for simplicity andpopular later, due to the parallelism of instruction execution.

Princeton Architecture (Single memory interface)

Fig. 2.2 Princeton Archit

Example : An instruction "Read a data byte from memory and store it in the a

Cycle 1 - ReaCycle 2 - Read Data out of RAM and put into Accumulator

Harvard Architecture (Separate Program and Data Memory interfaces)


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Fig. 2.3 Harvard Arcite

The same instruction (as shown under Princeton Architecture) would be exec

Cycle 1- Complete - Read the "Move Data to Accumulator" instruction

Cycle 2- Execute "Move Data to - Read next instructionHence each instruction is effectively executed in one instruction cycle, excecounter. For example, the "jump" (or call) instructions takes 2 cycles. Thus,

instructions in a given time compared to Princeton Architecture.


Lecture 3: Processor Types & Memory Structures


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Micro-coded and hard-coded processors:

The implementation of a computer architecture can be broadly achieved incircuit with both combinational and sequential circuit components. In a minumber of steps that are implemented using small subroutines. These instruction decode unit. Hence, a micro-coded processor can be called a proc

Micro-coded processor:

Fig.3.1 Architecture of a Micro-Co

Let us take an example. The instruction "Move Acc, Reg" can be executed in

1. Output address to the data memory2. Configure the internal bus for data memory value to be stored in acc3. Enable bus read.

4. Store the data into the accumulator.5. Compare data read with zero or any other important condition and s

6. Disable data bus.Each step of the instruction is realized by a subroutine (micro-code). A set omicro-code for the instruction is located.

Advantages: - 1. Ease2. Easy to debug.

Disadvantage: - Program execution takes longer time.

Hard coded processor:

Each instruction is realized by combinational and/or sequential digital circuitprogram execution is faster.


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Fig 3.2 Architecture of a Hard - Co

Memory types

In a microcontroller, two types of memory are found. They are, program mem

Program memory is also known as 'control store' and 'firm ware'. It is non-volgoes off. Non-volatile memory is also called Read Only Memory(ROM). Ther

1. Mask ROM: Some microcontrollers with ROM are programmed whi

ROM. Since the microcontrollers with Mask ROM are used for speciSome times, this type of manufacturing reduces the cost for bulk pro

2. Reprogrammable program memory (or) Erasable PROM (EPRO

late 1970's. These devices are electrically programmable but are eramemory cell is somewhat like a MOSFET but with a control and floa

Fig 3.3 Structure of an EP

In the unprogrammed state, the 'float' does not have any charge and the M'control' above the 'float' is raised to a high enough potential such that a c


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Hence a channel is formed between 'Source' and 'Drain' in the silicon substr'float' remains for a long time (typically over 30 years). The charge can be rerasable version, the packaging is done in a ceramic enclosure with a glass w

Fig 3.4 UV erasable version of

Usually, these versions of micro controllers are expensive.

3. OTP EPROM: One time programmable (OTP) EPROM based microcontroThese can be programmed only once. This type of packaging results in micro

microcontrollers with UV erase facility(i.e., 1/10th cost).

4. EEPROM: (Electrically Erasable Programmable ROM): This is similar to E

5. FLASH (EEPROM Memory): FLASH memory was This memory is similar to EEPROM but the cells in a FLASH memory are buHence the reprogramming is faster.


Lecture 4: Organization of Data Memory


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DATA Memory

Data memory can be classified into the following categories

Bits

Registers

Variable RAM

Program counter stackMicrocontroller can have ability to perform manipulation of individual bits in cefeature of a microcontroller, not available in a microprocessor.

Eight bits make a byte. Memory bytes are known as file registers.

Registers are some special RAM locations that can be accessed by the proce

Fig 4.1 Static RAM (SRAM) me

Fig 4.2 SRAM memory cell e


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The figure of a single SRAM cell is shown above. This consists of two CMlatch.

Processor stacks store/save the data in a simple way during program execudata is saved in a Last In First Out (LIFO) fashion just like a stack of painstruction and data is read out using a 'pop' instruction.

I/O Registers:In addition to the Data memory, some special purpose registers are requireThese registers are called I/O registers. These are important for microcontrol

Hardware interface registers (I/O Space)

As we already know a microcontroller has some embedded peripherals andplace through I/O registers. In a microprocessor, input /output (I/O) devicmemory address (memory mapped I/O) or a separate I/O address space (I/O

In a microcontroller, two possible architectures can be used i.e., Princeton(V

I/O Register space in Princeton architecture :

In Princeton architecture we have only one memory interface for program memap the I/O Register as a part of data memory or variable RAM area. This amemory mapped I/O. Alternatively a separate I/O register space can be assig

Fig 4.3 I/O Registers in Princeton

The drawback of memory mapped I/O is that a program which wrongly execu

I/O Registers space in Harvard Architecture :

These are the following options available for I/O register space in Harvard Ar

1. I/O registers in program ROM.2. I/O registers in register space (Data Memory area).

3. I/O registers in separate space.


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Fig 4.4 Organisation of I/O registers in H

The first option is somewhat difficult to implement as there is no means to wra separate I/O space as shown in (3). Hence the second option where I/O re

Module 2 : Intel 8051 Microcontroller

Lecture 5 : Introduction to Intel 8051 Microcontroller


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Some of the microcontrollers of 8051 family are given as follows:

DEVICE ON-CHIP DATAMEMORY

(bytes)

ON-CHIP PROGRAMMEMORY

(bytes)

16-TIMER/C

8031 128 None 28032 256 none

8051 128 4k ROM 2

8052 256 8k ROM 3

8751 128 4k EPROM 2

8752 256 8k EPROM 3

AT89C51 128 4k Flash Memory 2

AT89C52 256 8k Flash memory 3

Basic 8051 Architecture

8051 employs Harvard architecture. It has some peripherals such as 32 bit dof 8051 is given in fig 5.1

Fig 5.1 : Basic 8051 Archit

Various features of 8051 microcontroller are given as follows.

8-bit CPU

16-bit Program Counter

8-bit Processor Status Word (PSW)

8-bit Stack Pointer

Internal RAM of 128bytes

Special Function Registers (SFRs) of 128 bytes

32 I/O pins arranged as four 8-bit ports (P0 - P3)

Two 16-bit timer/counters : T0 and T1

Two external and three internal vectored interrupts

One full duplex serial I/O


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Interfacing External Memory

If external program/data memory are to be interfaced, they are interfaced in

Fig 6.1: Circuit Diagram for Interfacing o

External program memory is fetched if either of the following two conditions

1. (Enable Address) is low. The microcontroller by default starts se

2. PC is higher than FFFH for 8051 or 1FFFH for 8052.

tells the outside world whether the external memory fetched is progr

is processor controlled.

8051 Addressing Modes

8051 has four addressing modes.

1. Immediate Addressing :Data is immediately available in the instruction.For example -

ADD A, #77; Adds 77 (decimal) to A and stores in A

ADD A, #4DH; Adds 4D (hexadecimal) to A and stores in A

MOV DPTR, #1000H; Moves 1000 (hexadecimal) to data pointer2. Bank Addressing or Register Addressing :This way of addressing accesses the bytes in the current register bank. DataThe register bank is decided by 2 bits of Processor Status Word (PSW).For example-

ADD A, R0; Adds content of R0 to A and stores in A3.. Direct Addressing :


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Lecture 7 : External Memory Access

Accessing external memory

Access to external program memory uses the signal (Program stor

memory uses (alternate function of P3.7 and P3.6).

For external program memory, always 16 bit address is used. For example -MOVC A, @ A+DPTR

MOVC A, @ A+PCAccess to external data memory can be either 8-bit address or 16-bit addres

8-bit address- MOVX A, @Rp where Rp is either R0 or R1

MOVX @Rp, A

16 bit address- MOVX A,@DPTR

MOV X @DPTR, A

The external memory access in 8051 can be shown by a schematic diagram

Fig 7.1 Schematic diagram of externa

If an 8-bit external address is used for data memory (i.e. MOVX @Rp) ththroughout the external memory cycle. This facilitates memory paging as theDuring any access to external memory, the CPU writes FFH to Port-0 latch


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memory fetch, the incoming byte is corrupted.

External program memory is accessed under the following condition.

1. Whenever is low, or

2. Whenever PC contains a number higher than 0FFFH (for 8051) or 1

Some typical use of code/program memory access:

External program memory can be not only used to store the code, but alsparticular application. Mathematical functions such as Sine, Square root, E(Internal or eternal) and these functions can be accessed using MOVC instru

Fig 7.2 Program memory showing the sto


Lecture 8 : Timers


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Timers / Counters

8051 has two 16-bit programmable UP timers/counters. They can be configThe names of the two counters are T0 and T1 respectively. The timer conteTL0,TH0,TL1 and TH1 respectively.

In the "timer" function mode, the counter is incremented in every machine

cycles. Hence the clock rate is 1/12 th of the oscillator frequency.

In the "counter" function mode, the register is incremented in response to a(T0 or T1). It requires 2 machine cycles to detect a high to low transitiofrequency.

The operation of the timers/counters is controlled by two special function reg

Timer Mode control (TMOD) Special Function Register:

TMOD register is not bit addressable.

TMODAddress: 89 H

Various bits of TMOD are described as follows -

Gate: This is an OR Gate enabled bit which controls the effect of o

program to enable the interrupt to start/stop the timer. If TR1/0 in TCON is scounting using either internal clock (timer mode) or external pulses (counter m

It is used for the selection Mode Select Bits:

M1 and M0 are mode select bits.

Timer/ Counter control logic:


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Lecture 9 : Interrupts in 8051


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Interrupts

8051 provides 5 vectored interrupts. They are -

1.2. TF0

3.

4. TF1

5. RI/TI

Out of these, and are external interrupts whereas Timer and Serinterrupts could be negative edge triggered or low level triggered. All these inflags. Except for serial interrupt, the interrupt flags are cleared when the proThe external interrupt flags are cleared on branching to Interrupt Service triggered. For low level triggered external interrupt as well as for serial intsoftware by the programmer.

The schematic representation of the interrupts is as follows -

InterruptLocation

Fig 9.1 8051 Interrupt De

Each of these interrupts can be individually enabled or disabled by 'settingEnable Register) SFR. IE contains a global enable bit EA which enables/disa

Interrupt Enable register (IE):Address: A8H


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EX0 interrupt (External) enable bit

ET0 Timer-0 interrupt enable bit

EX1 interrupt (External) enable bit


ES Serial port interrupt enable bit


EA Enable/Disable all

Setting '1' Enable the corresponding interrupt

Setting '0' Disable the corresponding interrupt

Priority level structure:Each interrupt source can be programmed to have one of the two priority levein the IP (Interrupt Priority) Register . A low priority interrupt can itself be intlow priority interrupt. If two interrupts of different priority levels are receiveserved. If the requests of the same priority level are received simultaneouslyis to be serviced. Thus, within each priority level, there is a second priority lev

Interrupt Priority register (IP)

'0' low priority

'1' high priority

Interrupt handling:

The interrupt flags are sampled at P2 of S5 of every instruction cycle (Nconsisting of P1 and P2 pulses). The samples are polled during the next maset at S5P2 of the preceding instruction cycle, the polling detects it and the appropriate vector location of the interrupt. The LCALL is generated providedone of the following conditions.

1. An interrupt of equal or higher priority level is already in progress.2. The current polling cycle is not the final cycle in the execution of the

3. The instruction in progress is RETI or any write to IE or IP registers.When an interrupt comes and the program is directed to the interrupt veinterrupted program is stored (pushed) on the stack. The required Interrupt Sthe instruction RETI returns the value of the PC from the stack and the originReset is a non-maskable interrupt. A reset is accomplished by holding thresetting the program starts from 0000H and some flags are modified as follo


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Register Value(He

PC 00

DPTR 00

A 0

B 0

SP 0

PSW 0

Ports P0-3 Latches F

IP XXX

IE 0 XX

TCON 0

TMOD 0

TH0 0

TL0 0

TH1 0

TL1 0

SCON 0

SBUF X

PCON 0 XXX

The schematic diagram of the detection and processing of interrupts is given

Instruction Cycles

Fig 9.2 Interrupt Handling

It should be noted that the interrupt which is blocked due to the three condflag that generated interrupt is not still active when the above blocking condit


Lecture 10 : Program Branching Instructions


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Jump and Call Instructions

There are 3 types of jump instructions. They are:-

1. Relative Jump2. Short Absolute Jump

3. Long Absolute Jump

Relative Jump

Jump that replaces the PC (program counter) content with a new addresinstruction by 127 or less) or less than (the address following the jump by 1relative jump can be shown as follows: -

Fig 10.1 Relative Jum

The advantages of the relative jump are as follows:-

1. Only 1 byte of jump address needs to be specified in the 2's comple

and for jumping back, the range is -1 to -128.2. Specifying only one byte reduces the size of the instruction and spe

3. The program with relative jumps can be relocated without reassemb

Disadvantages of the absolute jump: -

1. Short jump range (-128 to 127 from the instruction following the jum

Instructions that use Relative Jump

SJMP


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In this case only 11bits of the absolute jump address are needed. The absoluIn 8051, 64 kbyte of program memory space is divided into 32 pages of 2 kbgiven as follows:-

Page (Hex) Address (H

00 0000 - 07

01 0800 - 0F

02 1000 - 1703 1800 - 1F

. .

1E F000 - F7

1F F800 - FF

It can be seen that the upper 5bits of the program counter(PC) hold the paddress within that page. Thus, an absolute address is formed by taking pagfollowing the jump and attaching the specified 11bits to it to form the 16-bit ad

Advantage: The instruction length becomes 2 bytes.

However, difficulty is encountered when the next instruction following the jumX800H). This does not give any problem for the forward jump, but results assembler prompts the user to relocate the program suitably.Example of short absolute

ACALL


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Serial Interface

The serial port of 8051 is full duplex, i.e., it can transmit and receive simultan

The register SBUF is used to hold the data. The special function register SBused to hold data to be transmitted out of the 8051 via TXD. The other issources via RXD. Both mutually exclusive registers have the same address 0

Serial Port Control Register (SCON)

Register SCON controls serial Address: 098H (Bit addressable)

Mode select bits

SM2: multi processor REN: Receive enableTB8: Transmitted bit 8 (Normally we havRB8: Received bitTI: Transmit interruptRI: Receive interrupt flag

Power Mode control Register

Register PCON controls processor powerdown, sleep modes and serial dataserial communication. The seventh bit (b7)(SMOD) is used to generate the b

Address: 87H

SMOD: Serial baud rateGF1: General purpose user GF0: General purpose user PD: Power downIDL: Idle mode bit

Data Transmission

Transmission of serial data begins at any time when data is written to SBtransmit data to the serial data network. TI is set to 1 when data has been another byte can be sent.

Data Reception

Reception of serial data begins if the receive enable bit is set to 1 for all m

receive data from the serial data network. Receive interrupt flag, RI, is set agets stored in SBUF register from where it can be read.

Serial Data Transmission Modes:

Mode-0: In this mode, the serial port works like a shift register and the data trfrequency of fosc /12. Serial data is received and transmitted through RXD. 8 boutputs the shift clock pulses of frequency fosc /12, which is connected to the efrequency or baud rate is always 1/12 of the oscillator frequency.


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Lecture 12 : Serial Communication - II

Serial Data Mode-2 - Multiprocessor Mode :

In this mode 11 bits are transmitted through TXD or received through RXD. Tdata bits (LSB first), a programmable 9 th (TB8 or RB8)bit and a stop bit (usua

While transmitting, the 9 th data bit (TB8 in SCON) can be assigned the valube transmitted, the parity bit (P) in PSW could be moved into TB8. On recewhile the stop bit is ignored. The baud rate is programmable to either 1/32 or

fbaud = (2SMOD /64) fosc.

Mode-3 - Multi processor mode with variable baud rate :

In this mode 11 bits are transmitted through TXD or received through RXD. (LSB first), a programmable 9 th bit and a stop bit (usually '1').

Mode-3 is same as mode-2, except the fact that the baud rate in mode-3 is v

fbaud = (2SMOD /32) * ( fosc / 12 (25

This baudrate holds when Timer-1 is programmed in Mode-2.

Operation in Multiprocessor mode :

8051 operates in multiprocessor mode for serial communication Mode-2 andcan communicate with more than one slave processors. The connection dimode is given in fig 12.1.

The Master communicates with one slave at a time. 11 bits are transmitted (LSB first), TB8 and a stop bit (usually '1'). TB8 is '1' for an address byte and

If the Master wants to communicate with certain slave, it first sends the addreall the slaves. Slaves initially have their SM2 bit set to '1'. All slaves checresponds by clearing its SM2 bit to '0' so that the data bytes can be received

It should be noted that in Mode 2&3, receive interrupt flag RI is set if REN=1,1. SM2=1 and RB8=1 and a valid stop bit is received. Or

2. SM2=0 and a valid stop bit is received.


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Fig 12.1 8051 in Multiprocessor C

After the communication between the Master and a slave has been establisHence other slaves do not respond /get interrupted by this data as their SM2

Power saving modes of operation :

8051 has two power saving modes. They are -

1. Idle Mode

2. Power Down mode.

The two power saving modes are entered by setting two bits IDL and PD in t

The structure of PCON register is as follows.

PCON: Address 87H


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The schematic diagram for 'Power down' mode and 'Idle' mode is given as fo

Fig 12.2 Schematic diagram for Power Down and

Idle Mode

Idle mode is entered by setting IDL bit to 1 (i.e., =0). The clock signaserial port functions. The CPU status is preserved entirely. SP, PC, PSW, Ac

IDLE mode. The port pins hold their logical states they had at the time Idlelevels.

Ways to exit Idle Mode:

1. Activation of any enabled interrupt will clear PCON.0 bit and henInterrupt Service Routine (ISR). After RETI is executed at the endfollowing the instruction that enabled Idle Mode.

2. A hardware reset exits the idle mode. The CPU starts from the inmode.

Power Down Mode:The Power down Mode is entered by setting the PD bit to 1. The internalHowever, the program is not dead. The Power down Mode is exited (PCONstarts from the next instruction where the Power down Mode was invoked. Pmode. Vcc can be reduced to as low as 2V in PowerDown mode. HowePowerDown mode is exited.


Lecture 13 : 8051 Instruction Set


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DEC @Ri @Ri @Ri - 1

INC A A A+1

INC Rn Rn Rn + 1

INC direct (direct) (direct) + 1

INC @Ri @Ri @Ri +1

INC DPTR DPTR DPTR +1

MUL AB Multiply A by BA low byte (A*B)B high byte (A* B)

SUBB A, Rn A A - Rn - C

SUBB A, direct A A - (direct) - C

SUBB A, @Ri A A - @Ri - C

SUBB A, #data A A - data - C

Logical Instructions

Mnemonics Description

ANL A, Rn A A AND Rn

ANL A, direct A A AND (direct)

ANL A, @Ri A A AND @Ri

ANL A, #data A A AND data

ANL direct, A (direct) (direct) AND A

ANL direct, #data (direct) (direct) AND data

CLR A A 00H

CPL A A A

ORL A, Rn A A OR Rn

ORL A, direct A A OR (direct)

ORL A, @Ri A A OR @Ri

ORL A, #data A A OR data

ORL direct, A (direct) (direct) OR A

ORL direct, #data (direct) (direct) OR data

RL A Rotate accumulator left

RLC A Rotate accumulator left through car

RR A Rotate accumulator right

RRC A Rotate accumulator right through car

SWAP A Swap nibbles within Acumulator

XRL A, Rn A A EXOR Rn

XRL A, direct A A EXOR (direct)

XRL A, @Ri A A EXOR @Ri

XRL A, #data A A EXOR data

XRL direct, A (direct) (direct) EXOR A

XRL direct, #data (direct) (direct) EXOR data

Data Transfer Instructions


MOV A, Rn A Rn

MOV A, direct A (direct)

MOV A, @Ri A @Ri

MOV A, #data A data

MOV Rn, A Rn A


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MOV Rn, direct Rn (direct)

MOV Rn, #data Rn data

MOV direct, A (direct) A

MOV direct, Rn (direct) Rn

MOV direct1, direct2 (direct1) (direct2)

MOV direct, @Ri (direct) @Ri

MOV direct, #data (direct) #data

MOV @Ri, A @Ri A

MOV @Ri, direct @Ri (direct)

MOV @Ri, #data @Ri data

MOV DPTR, #data16 DPTR data16

MOVC A, @A+DPTR A Code byte pointed by A + D

MOVC A, @A+PC A Code byte pointed by A +

MOVC A, @Ri A Code byte pointed by Ri 8-bit a

MOVX A, @DPTR A External data pointed by DP

MOVX @Ri, A @Ri A (External data - 8bit add

MOVX @DPTR, A @DPTR A(External data - 16bit a

PUSH direct (SP) (direct)POP direct (direct) (SP)

XCH Rn Exchange A with Rn

XCH direct Exchange A with direct byte

XCH @Ri Exchange A with indirect RAM

XCHD A, @Ri Exchange least significant nibble of A windirect RAM

Boolean Variable Instructions


CLR C C-bit 0

CLR bit bit 0

SET C C 1

SET bit bit 1

CPL C C

CPL bit bit

ANL C, /bit C C .

ANL C, bit C C. bit

ORL C, /bit C C +

ORL C, bit C C + bit

MOV C, bit C bit

MOV bit, C bit C

Program Branching Instructions


ACALL addr11 PC + 2 (SP) ; addr 11

AJMP addr11 Addr11 PC

CJNE A, direct, rel Compare with A, jump (PC + rel) if

CJNE A, #data, rel Compare with A, jump (PC + rel) if

CJNE Rn, #data, rel Compare with Rn, jump (PC + rel) i


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CJNE @Ri, #data, rel Compare with @Ri A, jump (PC + rel

DJNZ Rn, rel Decrement Rn, jump if not z

DJNZ direct, rel Decrement (direct), jump if not

JC rel Jump (PC + rel) if C bit =

JNC rel Jump (PC + rel) if C bit = 0

JB bit, rel Jump (PC + rel) if bit = 1

JNB bit, rel Jump (PC + rel) if bit = 0

JBC bit, rel Jump (PC + rel) if bit = 1

JMP @A+DPTR A+DPTR PC

JZ rel If A=0, jump to PC + rel

JNZ rel If A 0 , jump to PC + re

LCALL addr16 PC + 3 (SP), addr16

LJMP addr 16 Addr16 PC

NOP No operation

RET (SP) PC

RETI (SP) PC, Enable Interru

SJMP rel PC + 2 + rel PC

JMP @A+DPTR A+DPTR PCJZ rel If A = 0. jump PC+ rel

JNZ rel If A 0, jump PC + rel

NOP No operation


Lecture 15 : Atmd AT89C51 MicroController Programming


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Programming of Microcontrollers

Programming of microcontrollers means writing to the internal program memwith central program memory (Flash EEPROM) that can be programmed a

AT89C51 is available in a 40 pin DIP so that it can be easily hooked up in abyte of Flash program memory. The AT89C51 program memory is programmemory, the entire program memory has to be erased before programming.

Two versions of AT89C51 are available so far as the programming voltage is5V programming voltage is that a user can program the memory while the ICprogramming voltage is preferred where a separate programmer is required f

For programming the flash memory, the following connections are made.

Programming the Flash Memory:

Fig 15.1 AT89C51 Connection for

Verifying the Flash Memory:


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Fig 15.3 Timing diagram for Programm

The following steps are taken to program the Flash memory

1. Input the desired memory location on the address lines(P1.0-P1.7, 2. Input the appropriate data byte on the data lines(P0.0-P0.7)3. Activate the correct combination of control signals(P2.6,P2.7,P3.6 a

4. Raise to 12V for high voltage programming mode.

5. Pulse once to program a byte in the flash memory or t

Repeat steps from 1 to 5, changing the address and data for the entire progra

Chip Erase : The entire flash memory is erased electrically by suitable comholding low for 10ms. The entire flash memory is written with alLock bits: lock bits are used for prote

A programmed lock bit is An unprogrammed lock bit is denoted by U.

Reading the signature bytes:

The signature bytes are read by the same procedure as a normal verificationand P3.7 are pulled down to a logic low. The values read indicate the followin

(030H) = 1E H indicates (031H) = 51 H


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(032H) = FF H indicates(032 H) = 05 H indicates 5V programming.

Module 3 : PIC Microcontrollers

Lecture 16 : Introduction to PIC Microcontrollers


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PIC Microcontrollers

PIC stands for Peripheral Interface Controller given by Microchip Technodevices have been very successful in 8-bit microcontrollers. The main reupgraded the device architecture and added needed peripherals to the development tools such as assembler and simulator are freely available on th

The architectures of various PIC microcontrollers can be divided as follows.

Low - end PIC Architectures :

Microchip PIC microcontrollers are available in various types. When PIC Instruments in early 1980's, the microcontroller consisted of a simple procefunctions. These devices are known as low-end architectures. They have lirequiring simple interface functions and small program & data memories. Som12C5XX16C5X16C505

Mid range PIC Architectures

Mid range PIC architectures are built by upgrading low-end architectures withand more data/program memory. Some of the mid-range devices are16C6X16C7X16F87XProgram memory type is indicatedC = F =RC = Mask ROM

Popularity of the PIC microcontrollers is due to the following factors.

1. Speed: Harvard Architecture, RISC architecture, 1 instruction cycle 2. Instruction set simplicity: The instruction set consists of just 35 instr3. Power-on-reset and brown-out reset. Brown-out-reset means when

4V), it causes PIC to reset; hA watch dog timer (user programmable) resets the processor if the its normal operation.

4. PIC microcontroller has four optional clock sources.o Low power crystal

o Mid range crystal

o High range crystal

o RC oscillator (low cost).

5. Programmable timers and on-chip ADC.6. Up to 12 independent interrupt sources.7. Powerful output pin control (25 mA (max.) current sourcing capabilit8. EPROM/OTP/ROM/Flash memory option.9. I/O port expansion capability.

10. Free assembler and simulator support from Microchip at www.micro

CPU Architecture:

The CPU uses Harvard architecture with separate Program and Variable (d

and the operation on data/accessing of variables simultaneously.
http://www.microchip.com/http://www.microchip.com/


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Fig 16.3 Data Memory m

The special purpose register file consists of input/output ports and control readdress. However, the instructions that use direct addressing modes in PIConly. Therefore the register bank select (RP0) bit in the STATUS register is u

In indirect addressing FSR register is used as a pointer to anywhere from 00

Module 3 : Introduction to PIC Microcontrollers

Lecture 17 : Basic Architecture of PIC Microcontrollers


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Specifications of some popular PIC microcontrollers are as follows:

Device ProgramMemory (14bits)

Data RAM (bytes) I/O Pins A

16C74A 4K EPROM 192 33 8 b

8 cha16F877 8K Flash 368 (RAM)

256 (EEPROM)33 10 b

8 cha

Device Interrupt Sources

16C74A 12

16F877 15

PIC Microcontroller Clock

Most of the PIC microcontrollers can operate upto 20MHz. One instructions c

Fig 17.1 Relation between instruction cycles and cloc

Instructions that do not require modification of program counter content get e

Although the architectures of various midrange 8 - bit PIC microcontroller areof memory and peripherals. We will discuss here the architecture of a stamentioned otherwise, the information given here is for a PIC 16C74A microco

Architecture of PIC16C74A


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Lecture 18 : Instruction Set of PIC Microcontroller

Guidelines from Microchip Technology

For writing assembly language program Microchip Technology has suggeste

1. Write instruction mnemonics in lower case. (e.g., movwf)2. Write the special register names, RAM variable names and bit name

3. Write instructions and subroutine labels in mixed case. (e.g., Mainlin

Instruction Set:

The instruction set for PIC16C74A consists of only 35 instructions. Some osome are bit oriented instructions.

The byte oriented instructions that require two parameters (For example, m

a special purpose register (e.g., PORTA) or the name of a RAM variable (e.gstands for file register. The F(W) parameter is the destination of the result of F, if the destination is to bW, if the destination is to be the working register (i.e., Accumulator or W regisThe bit oriented instructions also expect parameters (e.g., btfsc f, b). Hereregister or the name of a RAM variable. The 'b' parameter is to be replaced bFor example:

Z equbtfsc STATUS, ZZ has been equated to 2. Here, the instruction will test the Z bit of the STATclear.

The literal instructions require an operand having a known value (e.g., 0AH

For example:

NUM equ 0AH ; Assigns 0AH to thmovlw NUM ; will move 0AH to the W register.Every instruction fits in a single 14-bit word. In addition, every instruction acontent of the Program Counter. These features are due to the fact that PIC RISC (Reduced Instruction Set Computer) architecture.

Instruction set:


bcf f, b Clear bit b of register f

bsf f, b Set bit b of register f

clrw Clear working register W

clrf f Clear fmovlw k Move literal 'k' to W

movwf f Move W to f

movf f, F(W) Move f to F or W

swapf f, F(W) Swap nibbles of f, putting result in F or W

andlw k And literal value into W

andwf f, F(W) And W with F and put the result in W or

andwf f, F(W) And W with F and put the result in W or


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iorlw k inclusive-OR literal value into W

iorwf f, F(W) inclusive-OR W with f and put the result

xorlw k Exclusive-OR literal value into W

xorwf f, F(W) Exclusive-OR W with f and put the result

addlw k Add the literal value to W and store the r

addwf f, F(W) Add W to f and store the result in F or W

sublw k Subtract the literal value from W and sto

subwf f, F(W) Subtract f from W and store the result in

rlf f, F(W) Copy f into F or W; rotate F or W left thro

rrf f, F(W) Copy f into F or W; rotate F or W right th

btfsc f, b Test 'b' bit of the register f and skip the n

btfss f, b Test 'b' bit of the register f and skip the n

decfsz f, F(W)Decrement f and copy the result to F or Wthe result is zero

incfcz f, F(W)Increment f and copy the result to F or Wthe result is zero

goto label Go to the instruction with the label "label

call label Go to the subroutine "label", push the Pr

retrun Return from the subroutine, POP the Pro

retlw kRetrun from the subroutine, POP the Prostack; put k in W

retie Return from Interrupt Service Routine an

clrwdt Clear Watch Dog Timer

sleep Go into sleep/ stand by mode

nop No operation

Encoding of instruction:

As has been discussed, each instruction is of 14-bit long. These 14-bits coninstruction encoding are shown here.

Example-1:

bcf f, b Clear 'b' bit of register 'f'

Operands: 0 0 b 7

Encoding:

The instruction is executed in one instruction cycle, i.e., 4 clock cycles. The a

Example-2:

goto K Go to label 'k' instruction


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Operand: 0 K 2047 (11-bit address is specified)

Operation: K

PCLATH PC

Encoding:

Since this instruction requires modification of program Counter, it takes two in

Q-Cycle activities are shown as follows.


Lecture 19 : I/O Port Configuration

Discussion on I/O ports of PIC16C74A:

PIC16C74A has five I/O ports. Port-B, Port-C and Port-D have 8 pins each. port has bidirectional digital I/O capability. In addition, these I/O ports aredevices on the microcontroller. In general, when a peripheral is enabled, thEach port latch has a corresponding TRIS (Tri-state Enable) register for conport pins are designated by the alphabet R, followed by the respective port (Port-A pins are named as RA0, RA1, etc.

Port-A

Port-A pins RA0-RA3 and RA5 are similar. These pins function (alternaconverter.


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Fig 19.1 RA0-RA3 and RA5 pin

The structure of Port-A pins RA0-RA3 and RA5 is shown in the figure. TRISAan input or as an output (digital) pin. Setting a TRISA register bit puts the cthis mode, the pin can be used as a digital or analog input. Clearing a bit in tthe selected pins, i.e., the pin functions as a digital output. Pins RA0-RA and

The alternate function of RA4 pin is Timer-0 clock input (T0CKI). RA4 pin iswhen configured as output pin. It is shown in the following figure.


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Fig 19.2 RA4 pin Configu

Configuration of Port-A pins

Example : Set RA0-RA3 as outputs and RA4 - RA5 as inputs.

bcf STATUS, RP0 ;clrf PORTA ; Clears bsf STATUS, RP0 ;

movlw 30H ; W 03H

movwf TRISA ; Set RA0-RA3 as outputs, RA4-RA5 as inputsPort-B

Port-B is an 8-bit bidirectional I/O port. The data direction in Port-B is contrputs the corresponding output in high impedance input mode. When a bit inoutputs the content of the latch (output mode).

Each port pin has a weak internal pull-up that can be enabled by clearingconfigured in the output mode, the weak pull-up is automatically turned off.device from the pins.


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Fig 19.3 Pins RB0-RB3 of

Configuration of Port-B pins

Example : Set RB0-RB3 as outputs, RB4-RB5 as inputs, RB7 as outpu

bcf STATUS,clrf PORTBbsf STATUS,movlw 70Hmovwf TRISB


Lecture 20 :Timer modules in PIC Microcontroller


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Overview of Timer Modules :

PIC 16C74A has three modules, viz., Timer-0, Timer-1 and Timer-2. Timer-0Each timer module can generate an interrupt on timer overflow.

Timer-0 Overview:

The timer-0 module is a simple 8-bit UP counter. The clock source can be eit

the clock source is external, the Timer-0 module can be programmed to incrmodule has a programmable pre-scaler option. This pre-scaler can be assigboth.

The Timer-0 Counter sets a flag T0IF (Timer-0 Interrupt Flag) when it oveinterrupt source has been enabled, (T0IE = 1), i.e., timer-0 interrupt enable b

OPTION Register Configuration :

Option Register (Addr: 81H) Controls the prescaler and Timer -0 clock souclock source = fosc /4 and no Watchdog timer.

Timer-0 use without pre-scalar

Internal clock source of fosc /4. (External clock source, if selected, can be ap

The following diagram shows the timer use without the prescaler.

Fig 20.1 Timer - 0 operation with

Timer-0 use with pre-scalar:

The pre-scalar can be used either with the Timer-0 module or with the Watchpre-scalar assignment bit PSA in the OPTION register is 0. Pre-scalar is


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available clock by a pre-specified number before applying to the Timer-0 cou

Fig 20.2 Timer - 0 with pre


Lecture 21 : Timer modules in PIC Microcontroller (contd.)


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Timer - 1 Module

Timer 1 module is a 16-bit timer/counter consisting of two 8-bit registers (TMTMR1 register pair (TMR1H:TMR1L) increments from 0000H to FFFFH angenerated on overflow, which sets the interrupt flag bit TMR1IF (bit-0 of Psetting/clearing TMR1 interrupt enable bit TMR1IE (bit-0 of the PIE1 registe

The operating and control modes of Timer1 are determined by the special p

Various bits of T1CON register are given as follows:-

Fig 21.1 T1CON Regi

TMR1 ON : Timer10 = stops Timer 1; 1 = Enables Timer 1

TMR1CS : Timer 1 Clock 1 = External

0 = Internal Clock ( )

: Timer 1 External Clock (Valid if TMR1 - Do

0 - SynchronizeT1OSCEN: Oscillator enable

1 = Oscillator0 = Oscillator is shut off

Timer 1 Input Clock Prescaler

Select bits Prescaler Value

T1CKPS1 T1CKPS0

1 1 1:8

1 0 1:4

0 1 1:2

0 0 1:1


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Fig 21.2 Operation of T

Timer 1 can operate in one of the two modes

As a timer (TMR1CS = 0). In the timer mode, Timer 1 increment

. Since the internal clock is selected, the timer is asynchronization.

As a counter (TMR1CS = 1). In the counter mode, external clock in

Reading and writing Timer 1

Reading TMR1H and TMR1L from Timer 1, when it is running from an extTMR1H or TMR1L for independent 8 - bit values does not pose any problhigh byte (TMR1H) is read first followed by the low byte (THR1lL). It shouldfrom FFH to 00H) since THR1H was read. This condition is verified by re

value of TMR1H.Example ProgramReading 16bit of free running Timer 1movf TMR1H ; rmovwf TMPH ; movf TMR1L ; rmovwf TMPL ; movf TMR1H, W ; read subwf TMPH, W ; subtract 1 btfsc STATUS, Z ; andgoto next; if the high bytes differ, then ; read the high byte again followmovf TMR1H, W ;movwf TMPH

movf TMR1L, W ; movwf TMPLnext : nop

Timer 2 Overview


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Fig 21.3 Schematic diagram showing

Timer 2 is an 8 - bit timer with a pre-scaler and a post-scaler. It can be ucompare PWM (CCP) modules. The TMR2 register is readable and writable

The input clock ( ) has a pre-scaler option of 1:1, 1:4 or 1:16 wrespectively.

The Timer 2 module has an 8bit period register (PR2). Timer-2 increments on the next clock cycle. PR2 is a readable and writable register. PR2 is inita

The output of TMR2 goes through a 4bit post-scaler (1:1, 1:2, to 1:16) to ge

Fig 21.4 The T2CON Re

Interrupt Logic in PIC 16C74A

PIC 16C74A microcontroller has one vectored interrupt location (i.e., 000priority. Only one interrupt is served at a time. However interrupts can be ma


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Fig 21.5 Schematic diagram showing the


Lecture 22 : CCP Modules


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Capture / Compare /PWM (CCP) Modules:

PIC16C74A has two CCP Modules. Each CCP module contains a 16 bit regthree modes, viz., 16-bit capture, 16-bit compare, or up to 10-bit Pulse Wid(CCP1 and CCp2) are given as follows.

CCP1 Module:

CCP1 Module consists of two 8-bit registers, viz., CCPR1L (low byte) and CCoperation of CCP1 Module.

CCP2 Module:

CCP2 Module consists of two 8 bit registers, viz., CCPR2L (Low byte) and the operation of CCP2 Module.

Both CCP1 and CCP2 modules are identical in operation with the exception o

The following table shows the timer resources for the CCP Mode.

CCP Mode Timer Used

Capture

Compare

PWM

Timer 1

Timer 1

Timer 2

CCP1CON Register (Address 17H )

CCP2CON Register is exactly similar to CCP1CON register. CCP2CONmodule1 where as CCP2CON controls CCP Module2.

Bit 5-4:CCP1X CCP1Y: PWM least significant bits. These bits are of no use in Captuthe PWM duty cycle. The eight Msbs are found in CCPR1L. T

BitCCP1M3:CCP1MO (CCP1 Mode0000=Capture/Compare/PWM Mode0100=Capture mode, every 0101=Capture mode, every0110=Capture mode, every 4 0111=Capture mode, every 16 1000=Compare mode, set output on matc1001=Compare mode, clear output on mat1010=Compare mode, generate software interrupt on match (1011=Compare mode, trigger special event (CCP1IF bit is set;CCP1 resets

A/D module is11XX=PWM mode.

Capture Mode (CCP1):

Capture Mode captures the 16-bit value of TMR1 into CCPR1H:CCPR1LRC2/CCP1 pin. Capture Mode for CCP2 is exactly similar to that of CCP1.

An event on RC2/CCP1 pin is defined as follows:

Every falling edge

Every rising edge.

Every 4 th rising edge.

Every 16 th rising edge.

As mentioned earlier, this event is decided by bit 3-0 of CCP1CON register.


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Lecture 23 : Analog to Digital Convertor Module


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Lecture 24 : Synchronous Serial Port (SSP) Module:

Most of mid range PIC microcontrollers include a Syncto PIC16C74A only. SSP Module section can be configu

Serial Peripheral Interface (SPI)

Inter Integrated Circuit (I2C)Either of these modes can be used to interconnect twcommunication. Alternatively, either can be used to conthe peripheral chip must also have an I 2C interface. Odirect connection to shift registers. This leads to increaconnected to a PIC microcontroller. SPI can also achieare synchronous, i.e., the data transfer is synchronized

Two special purpose registers control the synchronous

SSPCON (Synchronous Serial Port Control Re

SSPSTAT(Synchronous Serial Port status Reg

Serial Peripheral Interface (SPI)

Port-C three pins, viz., RC5/SDO, RC4/SDI and RC3/S

RA5/ /AN4 is used for slave select. The schematic b

Fig 24.1 Sch


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The SPI port requires RC3/SCK pin to be an output thaconfigured in the slave mode, RC3/SCK pin works as tWhen a byte is written to SSPBUF register, it is shifRC3/SCK pin. The MSB of SSPBUF is the first bit to initiates the 8 bit data reception into SSPBUF of whatepin. Hence shifting-in and shifting-out of data occur sim

Fig 24.2 S

The schematic diagram of SPI Master/Slave connection

Timing diagram for data transfer in 'Master mode' :

SSPIF interrupt flag is cleared by the user software iinitiates the data transfer, i.e., transmission and receptioreceived through SDI. When CKP=1 (SSPCON), d

positive clock transition. The idle state of clock is higthrough SDI at negative clock transition. The idle state o


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(i) Ti

(ii) T

Fig 24.3 Tim


Lecture 25 : I/O Port Expansion using Serial Peripheral Interface (SPI)


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Though SPI is a serial communication interface, it can be used to realize muWe will consider this realization of an output parallel port and an input port se

Parallel Output Port Realization

A parallel 8-bit output port can be realized through SPI with the help of a shipin outputs serial data while RC3/SCK oin outputs the serial clock. Since inplatch the shift register data to the output pins of the shift register. Hence RC4

Fig 25.1 PIC connection (in SPI mode

When an 8-bit data is written to SSPBUF, the data is shifted out of RC5/Stransition but changes at the negative transition. The shift shifts the data at are shifted in the shift register. The completion of data transfer is indicated broutine make RC4 ' 1' , thus latching the 8-bit data to the output of the shift rFig 25.2

Port configurations


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Fig 25.2 Various Register Co

Parallel Input Port Realization

A shift register (74HC165) is connected to the PIC microcontroller as shown to load 8-bit data to the shift register. A dummy write to SSPBUF initiates dclock transition (CKP = 0) where the data bit is stable. Data is shifted in the s

timing diagram. After the completion of data transfer, SSPIF interrupt flag gSSPBUF.


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Fig 25.3 Realization of an 8-bit parallel input

Port configurations

Fig 25.4 gives the configurations various registers for inputs parallel port real


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I2C Communication in PIC Microcontroller

I 2C stands for Inter-Integrated circuit. I 2C communication is a two wire bi-dprocessors with one or more slave devices, such as an EEPROM, ADC, RAopen drain I/O pins, viz. SDA (Serial Data) and SCL (Serial Clock).The reason for open drain connection is that the data transfer is bi-directionadrive the data line (SDA). The serial clock line (SCL) is usually driven by the

external pull-up resistances are required for operation of I2

C bus.A typical I2C bus showing the connection of multi-master and multi-slave con

Fig 26.1 Multimaster Multislave

Some conventions are followed in I2C communication. Let us assume that sent. We will initially assume that the master is the transmitter and the slavereceiving 8-bits, an acknowledgement bit is driven by the receiver on SDA

following diagram shows the data communication pattern having 8 data bits a

Fig 26.2 Timing diagram for da

The following features are to be noted -

1. SDA line transmits/ receives data bits. MSB is sent first.2. Data in SDA line is stable during clock (SCL) high. A new bit is in

hold time.3. Serial clock (SCL) is driven by the master.

4. An acknowledgement bit (0) is driven by the receiver after the end oline remains high (1).

I2C bus transfer consists of a number of byte transfers within a START cocondition. During the idle state when no data transfer is taking place, both Sremains high. When a master wants to initiate a data transfer, it pulls SDASTART condition. Similarly, when the processor wants to terminate the datathen SDA. This is called a STOP condition. START and STOP conditions are

Fig 26.3 Timing diagram for START and

START and STOP conditions are unique and they never happen within a dat


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Data Communication Protocol:

In I2C communication both 7-bit and 10-bit slave addressing are possible. Iwith a single master. Similarly, in 10-bit addressing mode, 1024 slaves can baddressing mode only. 10-bit addressing mode is similar to 7-bit addressingmore.Following a 'start' condition, the master sends a 7-bit address of the slave

address of the slave peripheral, a R/ (8th bit) bit is sent by the maacknowledgement bit) is written by the master to the addressed slaveacknowledgement bit) has to be read from the slave by the master.

After sending the 7-bit address of the slave, the master sends the addrewherefrom the data has to be read or written to. The subsequent access is aregister.

The following diagrams give the general format to write and read from severa

Fig 26.4 Data transfer protocol for writi

R/ (Read / Write) bit indicates whether the data is to be written by the ma

data are to be read by the master. If R/ = 0, the subsequent data are to bbe noted that the slave address is sent first, following a 'start' condition. Theready for data transfer.If data has to be read from a specific address of the slave device, the mast

'start' condition. R/ bit is sent as 'low'. The addressed slave acknowledges

8-bit internal address of the slave from which data has to be read. The slmaster is in the write mode. To change this to read mode, the 'start' conditi

slave with R/ = 1. The slave acknowledges. The slave then sends data frThe master acknowledges by pulling ACK bit low. The data transfer storeception and a 'stop' condition is generated.


Lecture 27 : Software for I 2C Communication


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Software for I2 C Communication

The data transfer in I2C mode is not automatically controlled by hardware suitable software to generate 'Start' / 'Stop' conditions, various data bits frosignal. Here, we will discuss some examples of I2C software.Since SDA (RC4) and SCL (RC3) are both open drain pins, they can be conProcessor is configured is I2C master, the SCL pin will function as open drai

open drain output. Hence, the software I2

C will repeatedly access TRISC, this located in bank-1 at an address 87H, which cannot be accessed by directhe following instruction.

bsf STATUS, RP0

Then required bit of TRISC can be changed followed by clearing RP0 and rev

bcf STATUS, RP0

Alternately, the indirect pointer FSR can have the address of TRISC andindirectly.

Consider the following definitions.

SCL equSDA equ 4The instruction bsf INDF, SDA will release the SDA line(as RC4/SDA pin

external pullup resister pull it high or some I 2C Slave device/Chip pull it low.When FSR is used for indirect addressing, care should be taken to restoprogram returns to the main line program.

I 2 C Subroutine

SDA equSCL equ 3

The following subroutine DATA_OUT transfers out three bytes, i.e., ADDRDE

DATA_OUT: call START ;

movf ADDRDEV, W ; Sends call TRBYTE

movf ADDR8, W

movf DATAWRTE, W ; call

call STOP return

The DATA_IN subroutine, which is given below transfers out ADDRDEV (

ADDRDEV (with R/ =1) and read one byte back into RAM variable DATARDATA_IN: call

movf ADDRDEV, W ; Secall

movf ADDR8, Wcall

call START1

movf ADDRDEV, W ; Seiorlwl

callbsf TRBUF, 7

callmovw

callreturn

The 'START' subroutine initializes I2C bus and then generates START condiof I 2C.START: movlw 3BH ;enables I2C

movwfbcf PORTC, SDA ; drive

movlw TRISC ;set


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Lecture 28 : Parallel slave port

Parallel slave port (PSP)

PIC Microcontroller offers a mechanism by which an 8-bit parallel bidirecMicrocontroller and a PC. PIC Microcontroller's Port-D and Port-E are used inMicrocontroller is configured as a Parallel slave Port (PSP) by setting bit-4 o

pins ( , and ) The connection diagram between PC and the PIC Microcontroller in PSP Mo

Fig 28.1 Interfacing a PIC-microcontroller with a

Registers used for PSP Mode

ADCON1:Three low significant bits (PCFG2-PCFG0) are set to enable Port-E pins for d

ADCON1, ADD: 9F H

TRISE:

This register plays a crucial role in PSP configuration and control. The lowefour bits are used in conjunction with parallel slave port as shown here.


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TRISE, ADD: 89 H

As explained, PSP Mode facilitates bidirectional 8-bit parallel data transfer. set by the user program, PORTD and PORTE are configured for PSP. When

PIC microcontroller and the I/O address decoding circuit makes go low spin low and floats the data through its data bus (b7-b0). The data is writindicating that a byte is waiting at PORTD input buffer to be read by the PICand an interrupt is generated if PSPIE, PEIE and GIE bits have been set (idata is read from PORTD, IBF bit automatically becomes zero; however PSPwritten by the PC before the first byte is read, the second byte is lost and theSimilarly a byte can also be read by the PC from the PIC microcontroller.

indicating that the byte is waiting to be read by the PC. When the PC reads cleared and the interrupt flag bit PSPIF is set indicating that the byte has bee

Module 4 : Architecture of Advanced Microprocessor

Lecture 29 : Architecture of 8086


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Architecture of 8086

Unlike microcontrollers, microprocessors do not have inbuilt memory. Moswhere data and program memory are combined in a single memory interfaperipheral, the circuit is purely digital and the clock speed can be anywhereThis increased clock speed facilitates intensive computation that a microproc

We will discuss the basic architecture of Intel 8086 before discussing more a

Internal architecture of Intel 8086:

Intel 8086 is a 16 bit integer processor. It has 16-bit data bus and 20-bit addrlines are multiplexed (AD0-AD15). Since 20-bit address lines are available, memory.

The basic architecture of 8086 is shown below.

Fig 29.1 Basic Architecture of 8086

The internal architecture of Intel 8086 is divided into two units, viz., Bus Inter

Bus Interface Unit (BIU )

The Bus Interface Unit (BIU) generates the 20-bit physical memory addr(ROM/RAM). As mentioned earlier, 8086 has a single memory interface. fetched in advance and kept in a 6-byte Instruction Queue while other instrHence after the execution of an instruction, the next instruction is directly fefor the external memory to send the instruction. This is called pipe-liningprocess.


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8086's BIU produces the 20-bit physical memory address by combining a 16-are four 16-bit segment registers, viz., the code segment (CS), the stack segment (DS). These segment registers hold the corresponding 16-bit segmof the starting address of that segment. The lower 4-bits of the starting addrheld by another 16-bit register. The physical 20-bit address is calculated by that to the offset address.

For Example:

Code segment Register CS holds the segmentInstruction pointer IP holds the offset aThe physical 20-bit address is calculated as follows.Segment address : Offset address :+ Physical address : 46730 H


Lecture 30 : Muti-User/ Multi-Tasking Operating System

Multi-User/ Multi-Tasking Operating System:

The need for advanced Microprocessor architecture mainly arose because oserve a simple user. Hence 8088 (similar to 8086) was initially adopted (in 19Multi-user operating system, as the name implies, is supposed to serve operating system should be capable of running multiple user programs. Eacsystem also called multi-tasking operating system. A schematic diagram of a

Fig. 30.1 Schematic diagram of multi-user/ multi-t

The part of the operating system (OS) that serves various tasks is called a that all users can not be served at the same instant of time. Hence the OS se


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the current user has been served for a specified time. This process is calleThey are as follows.

1. Time slice method : In this method, each task/ user is served for anumber of users is less. Since users are assumed to be slower tcontinuously. However, this method becomes inefficient with the inalso served for the same time as a critical or important task. This, so

2. Pre-emptive priority based scheduling : In this method, each tainterrupted by a high priority task. When the high priority task compl

Important facts in a multi tasking operating system:

1. Preserving theEach task occupies some memory and runs its own program. It shoneeds to be protected from other tasks. In the same time, when thstatus of the currently executed task should be preserved so that time. Hence the environment of each task has to be preserved.

2. ResourceResources are available for the use of various tasks. Some examplEach resource is associated with a flag called "semaphore". When the corresponding semaphore indicating that the resource is in use

its work with the resource, it resets the semaphore so that some oth


Lecture 31 : Memory Management in Advanced Microprocessors

Memory Management

In advanced microprocessor, memory management becomes extremely imfollowing two reasons.

1. Limitation of physicalA microprocessor has limited number of address lines. Hence the pnumber of address lines is not attractive as it makes the archPackaging becomes difficult and expensive. Memory Management memory address into the physical memory address. Virtual memorOnly the programs currently required are brought from the seconda(RAM) for execution.

2. Need for In a multi-user operating system, there is a possibility that a user area of some other user unless a protection mechanism is built. Henthe operating system should be protected from other user (task). T

access to the operating system resources. Hence various privilege privilege levels, 0 is the highest privilege and 3 has the lowest priviUnix operating systemIt has to be noted that the user is at the lowest privilege level, i.e., the highest privilege level, i.e., privilege level 0.


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Fig. 31.1 Protection mechanism and

Kernel, System services and Application services constitute the operating syand can not access the resource available at higher privilege levels directlymemory blocks and they are prote

A microprocessor such as 8086 does not provide this kind of protectionmicroprocessors such as 80286 incorporates this kind of protection for a mul


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Role of Memory Management Unit (MMU):

The virtual address space of a microprocessor may be many times larger thas a microprocessor is supposed to store large programs and data which caUsually programs and data are stored in a secondary storage such as a harspace but not in the physical address space. Faster memory such as RAM is

Fig.31.2 Microprocessor interfacing with primary

When a microprocessor is to execute a program, it checks whether the progprogram is not available in the physical memory, it is brought from the secoavailable space is inadequate in the physical memory, some less importsecondary memory to create space.

Memory Management Unit (MMU)

Memory Management Unit within a microprocessor converts the virtual mememory address is sometimes referred as logical memory address.

MMU can convert logical address into physical address in two ways.

1. Segment orientedIn this case, the logical memory space consists of memory segmdata/ program as is described by a "descriptor". The segment "dsegment size and other attributes. The descriptors of all segments memory.The logical address of a memory location contains two parts, viz, seto the segment "descriptor" in the descriptor table. From the "descrioffset part of the logical address is added to the segment base to ge


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2. Page orientedIn page oriented approach, the logical address space is divided into pages deals with smaller chunk of memory (4 Kbytes), it is easier and faster to swthe physical memory.


Lecture 32 : Architecture of Intel 80286


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Architecture of Intel 80286

Key Features -

16-bit date bus

24-bit non-multiplexed bus

Packaged in a 68-pin ceramic pack

80286 has 2 24 = 16 M Byte of physical memory accessibility

Fig 32.1 Basic Architecture

Memory Bank

Memory of 80286 is setup as an odd bank and an even bank, just as it is foand the odd bank is enabled when is low. To access an aligned word, b


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Lecture 33 : Intel 80386 - A 32-bit Microprocessor with Memory Paging


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Fig. 34.2 Structure of T

Introduction to Intel 80486:

CPU 80486 DX from Intel is the first 32-bit microprocessor to have an inbuset of 80386 but introduced more pipelining for speed enhancement. 80486 used for decoding complex instructions of 80486 architecture. The 80486 is on-chip cache. This 8 Kbytes of cache is a unified data and code cache and Note: 80486 SX does not have32-bit address lines: (A 2 - A 3132-bit data lines: (D 0 - D 31 )


Lecture 35 : Pentium Architecture


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Pentium Architecture

The Pentium family of processors originated from the 80486 microprocessmicroprocessors that share a common architecture and instruction set. The fiat a clock frequency of either 60 or 66 MHz and has 3.1 million transistors. S

Complex Instruction Set Computer (CISC) architecture with Reduce

64-Bit Bus

Upward code compatibility.

Pentium processor uses Superscalar architecture and hence can iss

Multiple Instruction Issue (MII) capability.

Pentium processor executes instructions in five stages. This staginginstructions so that it takes less time to execute two instructions in a

The Pentium processor fetches the branch target instruction before

The Pentium processor has two separate 8-kilobyte (KB) caches onPentium processor to fetch data and instructions from the cache sim

When data is modified, only the data in the cache is changed. Memreplaces the modified data in the cache with a different set of data

The Pentium processor has been optimized to run critical instruction

Fig 35.1 Superscalar Architectur

The Pentium processor has two primary operating modes -

1. Protected Mode - In this mode all instructions and architectural fea

and capability. This is the recommended mode that all new applicati

2. Real-Address Mode - This mode provides the programming e

extensions. Reset initialization places the processor in real mode wmode

The Pentium's basic integer pipeline is five stages long, with the stages broke

1. Pre-fetch/Fetch : Instructions are fetched from the instruction cache

2. Decode1 : Instructions are decoded into the Pentium's internal instr

stage.

3. Decode2 : Same as above, and microcode ROM kicks in here, if ne

stage.

4. Execute : The integer hardware executes the instruction.

5. Write-back : The results of the computation are written back to the


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Fig 35.2 Pentium pipeline

Floating Point Unit :

There are 8 general-purpose 80-bit Floating point registers. Floating point integer unit. Since the possibility of error is more in Floating Point unit (FPUthere in FPU. The floating point unit is shown as below

Fig 35.3 Floating Point

FRD - Floating PFDD - Floating FADD - Floating FEXP - Floating FAND - Floating FMUL - Floating Point Multiply



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Lecture 36 : PowerPC Architecture

In February 1990, IBM introduced RS/6000 microprocessor based on POWwas second generation POWER architecture. It has Reduced Instruction Seto keep the processor as busy as possible. Salient features of RISC architect

Fixed length instructions (4 byte instructions). This allows single dec

Mostly single cycle instruction execution

Less number of instructionsPowerPC was created in 1991 by Apple-IBM-Motorola alliance. Originally insince become popular embedded and high-performance processors as wmicroprocessor. Design features of PowerPC are as follows -

Broad range implementation

Simple processor design

Superscalar architecture

Multiprocessor features

64-bit architecture

Support for operation in both big-endian and little-endian mode. Ptime.

Separate set of floating point instructions for

Separate set of Floating Point Registers (FPRs) for floating-point ins

Motorola PowerPC 601 was the first PowerPC. Few of its features were -

1. 64-bit microprocessor2. 32-bit address lines3. Can handle integer data of 8, 16 and 32 bits4. RISC architecture with 4 byte instruction length

5. PC 601 has virtual memory addressing of 4 penta byte.

Apart from the changes to the instruction set, the most significant changes inmanagement definition. In the POWER Architecture, the processor did accesses or instruction fetches. Software had to manage memory consistmemory to disk, software had to ensure that any modified copies of the memto main memory. Before starting a read from disk, software had to ensure ththe memory area, and software had to invalidate any copy of the memory arethat requested the operation. POWER processors always accessed main mePowerPC memory model, however, provides greater flexibility. It implemrelieving software of the responsibility for the consistency of memory with reaccess to any page unless it has an attribute indicating that it contains I/O or

possible to map I/O into the main memory space.As in the POWER memory model, the PowerPC memory model requires sdata memory. Programs that modify or generate instructions must ensure thinstructions are consistent with the main memory before attempting to execut
http://en.wikipedia.org/wiki/Embedded_systemhttp://en.wikipedia.org/wiki/Embedded_system


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theory related to microprocessors

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