Thermal Magnetic Random Access Memory

IEEE International Conference on Computer DesignNew Memory Technologies

San Jose, CA October 4, 2005

James DeakNVE Corporation

Participants

•Jim Daughton - PI•Art Pohm•Dexin Wang•Dave Brownell•Pete Eames•John Taylor

Supported in part by DARPA

MotivationMRAM combines the non-volatility and infinite endurance of magnetic based memories with silicon processing technology

MRAM Issues: •How to reliably select a random bit for writing•How to combine low power and data retention

existing emerging

Magnetoresistive Random Access Memory, By Saied Tehrani et al.

Outline

• MRAM Introduction• Status• MRAM Background

• MRAM Scaling Issues• Magnetothermal MRAM

• Modes – Curie, Neel/blocking temperature • Design Requirements• Thermal Writing Experiments

• Conclusions

MRAM Technology Status

Currently Sampling Expected 2006

Magnetic Memories• Hard drives• Tape drives• Floppy disks• Magnetic Core Memory – 1948 thru the 1970s

53k bit in 512 cubic inches

http://www.fortunecity.com/marina/reach/435/coremem.htm

Inductive ReadConsider magnetic core memory

Here bits are read destructively by detecting a voltage pulse in a read line.

Voltage pulse created by writing a toroid at the intersection of two write conductors .

•Read signal decreases with decreasing magnetic bit size.

•Does not scale well.

R R

W W

W

W

( )dt

dMVolumeVsense ∝

Simple SDT Storage Element

AFFM

AlOxFM

Ω

Free FM Layer

Tunneling Barrier

Pinned FM LayerAF Layer

TEM Cross-section of NVE SDT Barrier

Die13

590000

600000

610000

620000

630000

640000

650000

660000

670000

-60 -40 -20 0 20 40 60H-EA (Oe)

Ohm

s at

0.1

uA

1

0

Tunneling Magnetoresistance

•Spin conserved during tunneling

•Two independent spin channels

•Parallel – Low Resistance•Majority Majority•Minority Minority

•Anti-Parallel – High Resistance•Majority Minority•Minority Majority

•Room Temperature Max. TMR•AlOx ~ 70%•MgO ~ 260%

Julliere’s ModelPhys. Lett. A 54, 225 (1975)

↑↓↓↑↑↓

↓↓↑↑↑↑

+∝

+∝

RLRL

RLRL

nnnnG

nnnnG

RL

RL

P

PAP

PPPP

RRR

GGG

TMR−

=−=−

=↑↓

↑↓↑↑

12

Parallel

Anti-parallel

Tunnel Conductance

Magnetoresistance

Spin Polarization

↓↑

↓↑

+−=

LL

LLL nn

nnP Left ↓↑

↓↑

+−=

RR

RRR nn

nnP Right

n ~ spin dependent DOS

Typical MRAM Cell

FixedMagnetic Layer

Digit Line

Bit Line

Isolation Transistor “ ON”

Free Magnetic Layer, InformationStorage.

Tunneling Barrier

Sense Current

Read Mode

Program Current He

Program Current Hh

Program Mode

Stoner-Wohlfarth Write Select

Selected Cell

Ix

Iy

Ix

Iy

No Switch

Operating Points

• Ix, Iy Alone Doesn’t Switch Cell• Ix, Iy Together Switch Cell

Switch Switch

Half Selected Cell

Margins With Old Cell - Motorola

“A 0.18 mm 4Mb Toggling MRAM”, M. Durlam et al, 2003 IEEE Publication

Control of the distribution of switching fields makes the SW-MRAM implementation difficult to manufacture and scale.

Becomes more difficult as cell size is reduced

Stability and Thermal Activation

Probability for magnetization to be reversed by thermal activation in time t is

( ) ( )VHMVMNNE easyssxy sinθHθθ hard+−−−= cossin21 22

)τ/exp(1)( ttP −−=

−=TkHEf

B

b )(exp10τ

Magnetic Energy

sc MKH /2=

KVVMNNE sxyb =−= 2)(21

Nx

Ny

whereIncreasing Eb/kBT increases the retention time but also increases programming field

Energy Barrier and Error Rate in MRAM

( ) )3600()(

0 hrsefNWritFrac

hrerr Tk

HE

bitsB

b−

=

( )( )( ) TkfNWrtFrac

hrerrE Bb

−=

)3600(/ln

0

•Required Eb is thus directly related to the desired error rate , T, and Nbits

TBkbEetft

bits

rev eeNNtP

/011)( τ/ −−− −=−==

bits

rev

bits

revTkE

NN

NNetf Bb −≈

−=− − 1ln/0 If Nrev << Nbits

TkEbits

rev BbefNs

errt

N /0

−==

Error Rate is related to the Barrier Height

Energy barrier can thus be determined as

•Eb should be > 66 kBT ~ 3.7e-19 J, for 1 Mbit, 1e-10 err/hr, 400 K

•Small volume lowers thermal stability – need to increase thickness with decreasing size

•For small single layer free layers, increasing stability increases write field/current to impractical values

Single - Domain Ellipse , Aspect Ratio = 1 .5

0

100

200

300

400

500

600

700

800

0 200 400 600 800 1000

W idth ( nm)

KV

/300

kB

KV

Single - Domain Ellipse , 50 nm w ide , AR = 1 .5

0

50

100

150

200

250

300

350

400

450

500

0 2 4 6 8 10Thickness ( nm)

KV

(300

kB)

0

100

200

300

400

500

600

700

Hc (O

e)

KVHc

Write Current and Cell Size

3 nm thick

MRAM Scaling Issues

• Control of switching field distributions

• Large write current required for stability

Alternative Write Methods

Toggle Spin Momentum TransferThermal Writing

–Curie Point Write, Tc

–Neel (TN) or Blocking Temperature (TB) Write–Thermal Spin-Momentum Transfer Write, T-SMT

Savtchenko “Toggle” Write•Enhanced write selectivity due to pulse sequence

•SAF Stack FM/Ru/FM

Toggle Switching Mode

Freescale 4 Mbit MRAM•CMOS 0.18 µm•1T/1MTJ•25 ns Write/read•48 F2 cell (1.55 µm2)

Results•Excellent Selectivity•High write current (~7 mA/line)

Thermal stability at small bit size still an issue high write current

SMT Switching – Basic PictureN Stable FMFree FM

I

•No external field required to reverse magnetization

•Angular momentum exchange between spin polarized current and ferromagnet induces torque and precession

Torque ~ ±J M2 x (M1 x M2); J~107A/cm2Slonczewski (1996)

•At critical I precession large and magnetization precesses into reversed state

•Reversed magnetization stable since torque becomes zero

Free FM NN

e-e-

SMT Ic vs. Eb

simulated SMT

0.0

1.0

2.0

3.0

4.0

5.0

6.0

7.0

0 2E-19 4E-19 6E-19 8E-19 1E-18 1.2E-18KV (J)

Ic (m

A)

AR = 2AR = 1.5AR = 3

Eb must remain high as bit size is scaled down – thickness must increaseSwitching roughly proportional to Eb

At fixed Eb, smaller AR bits require more current

25 nm 25 nm

50 nm 50 nm 50 nm

100 nm

75 nm

100 nm

140 nm

200 nm

AR=1.5 AR=2 AR=3

Vary L,W,t

Smaller dimensions do not guarantee lower write current!

Increasing Eb

Increasing Eb

Magnetothermal MRAM

Principle of operation

•Use a very high stability storage layer to improve data retention.

•Apply current through the tunnel junction to heat the storage layer

•Storage layer coercivity reduced at high temperature

•Storage layer may be an AF/FM bilayer or a low Tc FM

Thermal via

Thermal via

write

Read&Heat

pin

storage

Barrier

Goal: Design for high density Heating current below 100 µA at 100 nm bit size

Curie Point MRAM

Curie

Thermal viaHigh TB AF

FM/Ru/FM pin

Thermal via

LTC FM - storagebarrier

Ru

H H

RRHc

Low T High T

Coercivity drops due to reduction of free layer magnetization

Si-SiN -CoFeNiSiB (16nm)-Ta (10nm)

0

100

200

300

400

500

0 50 100 150 200 250 300

Temperature (deg C)

Ms (

emu/

cc)

100 Oe parallel

Neel Point MRAM

Neel or TB

Thermal viaHigh TB AF

Low TB AF

FM/Ru/FM pin

Thermal via

FM - storagebarrier

Ru

H

R

H

R

Offset field (Hex) drops to zero at high temperature (TB)

Low T High T

Ru(40)/IrMn(x)/CoFeB(40)

50

70

90

110

130

150

170

190

0 20 40 60 80 100

IrMn Thickness (nm)

Blo

ckin

g Te

mep

ratu

re (

C )

Best mode since AF/FM bilayer easy to achieve high EB due to high FM/AF coupling and high AF anisotropy. Also has the best magnetic field immunity.

Previous TB MRAM Work

••Heating through barrier confirmedHeating through barrier confirmed

••TTBB writing mechanism verified w/ 10 ns write pulsewriting mechanism verified w/ 10 ns write pulse

••NOL layers used to increase RA and take stress off the barrier NOL layers used to increase RA and take stress off the barrier –– at the expense of TMR at the expense of TMR –– VVlimlim = 2 V= 2 V

••Not expected to scale well due to stray field interaction in theNot expected to scale well due to stray field interaction in the FM/AF/FM storage layerFM/AF/FM storage layer

••Demonstrated >10Demonstrated >101010 thermal writesthermal writes

498 Ωµm2

Ta

Ta

Freelayer w/ heater

Freelayer w/ heater

CoFe/IrMn/CoFe Storage layer

barrier

barrier

Heating current

Heating in four layers

H

R0 1

Digital value determined by freelayer R(H)

NVE Neel Point (or TB) MRAM Operation

initial state: 1

Write Sequence

off

Apply heating and write currents

Turn off heating current

offon

heat field cool

Turn off write current

final state: 0

off

H

R

H

R

H

R

Neel Point MRAM Considerations• Need margin between high Tb and Low Tb layers

(Easy)• Low thermal conductivity vias to lower write

current (several alternative materials such as PtMn and BiTe)

• Low thermal conductivity encapsulating material to lower write current (process requires some work)

• Barrier RA must be optimized to permit efficient heating at low write current, while maintaining a large TMR (Not too easy, but not impossible)

• AF must have Hex > Hc, Low Hc at TB, TB > 150 C (Easy)

Resistance Area Product Requirements

ARA

IAK

LPRTv

vth

2

2==∆

MTJ - RA

Thermal via

Thermal via

Heating current300 K

300 K

∆T

Lv

Lv Kv

Kv

P = I2R – powerR – junction resistanceA – junction area<RA> = ρt – Junction resistance area productKv – via thermal conductivityLv – via lengthI – heating currentRth = Lv/(2KvA) – thermal resistance from barrier to 300 K heat sink

Junction temperature:

Heating current: ( )RAL

KTATIv

v2∆∆ =

Voltage: ( ) ( )v

v

LRAKT

RTITV2∆

∆∆ == Must limit < ~0.5 V for reliability

Maximum RA:v

vLim

TKLVRA

∆2

2

max ≤ Optimal value depends on Vlim, Rth, and desired ∆T.

Heating current proportional to bit area

Encapsulating Material Optimization

KvKm

•Heat diffuses into the encapsulating material

Lowers heating efficiency

•Looks as if the thermal vias have a larger effective area

60 nm vias, Rtotal = 9 kOhm, Kvia = 0.014 W/cm-K

0

50

100

150

200

250

300

1.E-04 1.E-03 1.E-02 1.E-01 1.E+00Km (W/cm-K)

Cur

ie L

ayer

Avg

. T (K

)

Kv

60 nm vias, Rtotal = 9 kOhm, Kvia = 0.014 W/cm-K

0

2

4

6

8

10

12

14

1.E-04 1.E-03 1.E-02 1.E-01 1.E+00Km (W/cm-K)

Effe

ctiv

e Vi

a A

rea

Heat leak negligible if

Km < Kv/10

Kv

Best if Km<Kv/10

via

veff APL

TKA 1∆2

=

Thermal Via Optimization

max

2

2 RATV

LK Lim

v

v

∆≤

•Need minimum Kv and large Lv

•Can’t increase Lv too much

–Thermal rise time becomes too long

–Roughness becomes too large for low RA barrier

•Settle on 50 nm of PtMn

•low Kv = 0.01 to 0.014 W/cm-K

•Able to fabricate low RA junctions at this thickness

Test Structure Fabrication

Post bit ion mill Post top conductor etch

2000 Al

500 PtMn220 Bit

2000 SiN

150 CrSi

500 PtMn200 Al

PtMn(50)/Ru(4)/IrMn(4)/CoFeB(4)/AlOx(x)/CoFeB(4)/Ru(0.7)/FeCo(4)/PtMn(50)/Al(20)

Anneal Low Tb AF +H Anneal Low Tb AF -H E-beam and optical lithography

Bits patterned from 0.05 µm to 5 µm.

Unpatterned film measurement

Writing accomplished using external field

IrMn Hex >0 IrMn Hex <0

Ru(40)/IrMn(x)/CoFeB(40)

50

70

90

110

130

150

170

190

0 20 40 60 80 100

IrMn Thickness (nm)

Blo

ckin

g Te

mep

ratu

re (

C )

TB ~ 110 CSlightly low

High RA Junction (13 Å Al, 28 MΩµm2)

Device burns out before IrMn Tb is exceeded

die 23 -- 2 µm x 4 µm ellipse -- 28 ΜΩµm2

0.0E+00

2.0E+06

4.0E+06

6.0E+06

8.0E+06

1.0E+07

1.2E+07

-800 -600 -400 -200 0 200 400 600 800H (Oe)

R ( Ω

)

10 nA150 nA500 nA1000 nA

die 23 -- 2 µm x 4 µm ellipse -- 28 ΜΩµm2

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

3.4E+06

-800 -600 -400 -200 0 200 400 600 800H (Oe)

R ( Ω

)

500 nA

Burns out here

no change at 500 nA

die 23 -- 2 µm x 4 µm ellipse -- 28 ΜΩµm2

1.9E+06

1.9E+06

1.9E+06

1.9E+06

1.9E+06

2.0E+06

2.0E+06

2.0E+06

2.0E+06

2.0E+06

-800 -600 -400 -200 0 200 400 600 800H (Oe)

R ( Ω

)

1000 nA

No TMR at 1000 nACheck R(H) at lower currentdie 23 -- 2 µm x 4 µm ellipse -- 28 ΜΩµm2

0.0E+00

2.0E+06

4.0E+06

6.0E+06

8.0E+06

1.0E+07

1.2E+07

-800 -600 -400 -200 0 200 400 600 800 1000H (Oe)

R ( Ω

)

10 nA -- initial10 nA post 1000 nA

Initial 10 nA measurement

Final 10 nA measurement

1

23

4

5

1

4

3

Low RA Junction (6 Å Al, 5 Ωµm2)array 7 die 10 - 2500 nm

0.365

0.37

0.375

0.38

0.385

0.39

0.395

0.4

0.405

0.41

-700 -500 -300 -100 100 300 500 700

H (Oe)

R ( Ω

)

1020304045

array 7 die 9 - 2000 nm

0.477

0.482

0.487

0.492

0.497

0.502

0.507

-700 -500 -300 -100 100 300 500 700

H (Oe)

R +

offs

et ( Ω

)

1020304050

array 7 die 8 - 1500 nm

1.387

1.392

1.397

1.402

1.407

1.412

-700 -500 -300 -100 100 300 500 700

H (Oe)

R +

offs

et ( Ω

)

10203040

array 7 die 6 - 750 nm

10.615

10.625

10.635

10.645

10.655

10.665

-700 -500 -300 -100 100 300 500 700

H (Oe)

R +

offs

et ( Ω

)

25101215

Changes from SV to PSV behavior – Why?

Model Description

dKexcztot EEEEE +++=

( ) ( ) ( )[ ]33322111 cos2coscos φφφ tMtMtMBE sssxz ++−=

( ) ( ) ( )[ ]33322111 sin2sinsin φφφ tMtMtMB sssy ++−

( ) ( )3221 coscos φφφφ −+−= AlORUexc JJE

( ) ( ) ( )32

3322

2212

11 sinsinsin φφφ tKtKtKEK ++=

333022201110 21

21

21

dsdsdsd HMtHMtHMtE µµµ ++=

yj

xj

j yyyx

xyxxy

i

xi

di MM

jiNjiNjiNjiN

HH

H ∑=

==3

1 ),(),(),(),(

Total Energy

External Fields

Interlayer Exchange

Anisotropy

Demagnetization Fields

Pinned layer/barrier/storage layer

Strong coupling Weak coupling

FM1(t1,Ms1,K1)/Ru(JRU)/FM2(t2,Ms2,K2)/AlOx(JAlO)/FM3(t3,Ms3,K3)φ3

Simulated Response

one layer pinned - high temperature

-1.5

-1

-0.5

0

0.5

1

1.5

-0.07 -0.05 -0.03 -0.01 0.01 0.03 0.05 0.07Bx (T)

R (a

rb)

K = 3250,6000t = 4,1Bpin = 0.0, 0.01J = 1e-6

•Coercivity of the storage layer is too high at TB!

both layers pinned - low temperature

-1.5

-1

-0.5

0

0.5

1

1.5

-0.07 -0.05 -0.03 -0.01 0.01 0.03 0.05 0.07Bx (T)

R (a

rb)

K = 100,6000t = 4,1Bpin = 0.04, 0.01J = 1e-6

•Hc IrMn > (Hc + Hex) PtMn

Apparently

H

R Wanted this at TB, Hc < 50 Oe

Got this at TB, Hc > 100 Oe

•And pinned layer SAF not well matched

IrMn Hex and Hc

•Increasing thickness of IrMn decreases Hc and increases He.

•Tb would be increased 50 to 100 K.

•Increasing RA to 10 Ωµm2 would keep the write current at the present value and still permit safe writing

( )RAL

KTATIv

v2∆∆ =

Must increase IrMn layer to 60 nm

Measured Programming Current

wafer 393

y = 8.3116x

05

101520253035404550

0 1 2 3 4 5 6area (µm2)

I (m

Α)

I - TbLinear (I - Tb)

100 nm bit π*(0.1/2)*(0.1/2)*8.31 = 0.065 mA

Current through barrier required to exceed Tb

8.3 mA/µm2

Using only a single barrier and no heater layers

Conclusions• Demonstrated heating through the barrier, and

potential for < 100 µA write currents at 100 nm dimensions

• IrMn thickness needs to be increased• RA needs to be optimized, need roughly 50 Ωµm2

• Need to do a better job matching the SAF• Lower thermal conductivity encapsulating

material like BCB would further decrease write current

• If needed NOL heaters could be added to further decrease write current (at the expense of signal)