thesis on designing, modelling mosfets
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desigining, modelling of mosfets..Vlsi designTRANSCRIPT
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Design, Implementation, Modeling, and Optimization of Next Generation Low-Voltage
Power MOSFETs
by
Abraham Yoo
A thesis submitted in conformity with the requirements for the degree of Doctor of Philosophy
Department of Materials Science and Engineering University of Toronto
Copyright by Abraham Yoo 2010
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Design, Implementation, Modeling, and Optimization of Next
Generation Low-Voltage Power MOSFETs
Abraham Yoo
Doctor of Philosophy
Department of Materials Science and Engineering
University of Toronto
2010
Abstract
In this thesis, next generation low-voltage integrated power semiconductor devices are
proposed and analyzed in terms of device structure and layout optimization techniques.
Both approaches strive to minimize the power consumption of the output stage in DC-DC
converters.
In the first part of this thesis, we present a low-voltage CMOS power transistor layout
technique, implemented in a 0.25m, 5 metal layer standard CMOS process. The hybrid
waffle (HW) layout was designed to provide an effective trade-off between the width of
diagonal source/drain metal and the active device area, allowing more effective
optimization between switching and conduction losses. In comparison with conventional
layout schemes, the HW layout exhibited a 30% reduction in overall on-resistance with
3.6 times smaller total gate charge for CMOS devices with a current rating of 1A.
Integrated DC-DC buck converters using HW output stages were found to have higher
efficiencies at switching frequencies beyond multi-MHz.
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In the second part of the thesis, we present a CMOS-compatible lateral superjunction
FINFET (SJ-FINFET) on a SOI platform. One drawback associated with low-voltage SJ
devices is that the on-resistance is not only strongly dependent on the drift doping
concentration but also on the channel resistance as well. To resolve the issue, a SJ-
FINFET structure consisting of a 3D trench gate and SJ drift region was developed to
minimize both channel and drift resistances. Several prototype devices were fabricated in
a 0.5m CMOS compatible process with nine masking layers. In comparison with
conventional SJ-LDMOSFETs, the fabricated SJ-FINFETs demonstrated approximately
30% improvement in Ron,sp. This is a positive indication that the SJ-FINFET can become
a competitive power device for sub-100V rating applications.
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Acknowledgements
First of all, I would like to thank Prof. Wai Tung Ng for his supervision,
encouragement, and invaluable counsel throughout my Ph.D. program. Without whose
presence my development as both a student and an individual would not have progressed
as rapidly. I wish to further acknowledge Prof. Johnny Sin (Hong Kong University of
Science and Technology) and Yasuhiko Onishi (Visiting Scientist from Fuji Electric
Corp.) who have contributed to my knowledge in the field, which better enabled me to
carry out and finish my research project on time.
I would like to express appreciation to all the members in the Smart Power Integration
& Semiconductor Devices Research Group for their fruitful discussions over the course
of this research, particularly M. Chang, O. Trescases, H. Wang, E. Xu, G. Wei, and Q.
Fung. I would also like to express my appreciation to all the staff in Nanoelectronic
Fabrication Facility (NFF) at HKUST who provided me with various IC fabrication
support.
Financial support from the University of Toronto Open Fellowship, the Natural
Sciences and Engineering Research Council of Canada, and the Auto21 Network of
Centres of Excellence of Canada are gratefully acknowledged.
Lastly, I would like to extend my appreciation to my wife, Mia Yoo for her patience,
consideration and support during the past four years. She has been wonderful and a true
partner. Also, special thanks to my mother and parents-in-law for their constant support
and encouragement throughout the studies.
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Table of Contents
Table of Contents .............................................................................................................. v
List of Tables .................................................................................................................. viii
List of Figures ................................................................................................................... ix
List of Glossary .............................................................................................................. xiv
List of Symbols ............................................................................................................... xvi
Chapter 1 Introduction ..................................................................................................... 1
1.1 Technology and Market Trends in Power Semiconductors ...................................... 1
1.2 Advantages of Power MOSFET Devices ................................................................. 3
1.3 Application Fields for Current and Future Power MOSFETs .................................. 4
1.4 Thesis Objectives and Organization ......................................................................... 6
Chapter 2 Power MOSFETs a Brief Overview ........................................................... 7
2.1 Fundamentals of MOS Device .................................................................................. 7
2.2 Types of Power MOSFETs ..................................................................................... 11
2.2.1 Traditional Vertical Power MOSFETs ............................................................ 12
2.2.2 Traditional Lateral Power MOSFETs .............................................................. 14
2.3 CMOS-based Power MOSFETs ............................................................................. 18
2.3.1 Monolithic Integration: Standard CMOS Process ........................................... 18
2.3.2 CMOS Layout Techniques for Power Integrated Circuits ............................... 20
2.4 Super-Junction (SJ) Power MOSFETs ................................................................... 25
2.4.1 Device Concept and Characteristics ................................................................ 25
2.4.2 Current Status and Challenges of SJ Power MOSFETs .................................. 27
Chapter 3 Analytical Layout Modeling of Power MOSFET ...................................... 30
3.1 Analysis of Basic MOS Finger Structure................................................................ 30
3.2 Modeling of Conventional Multi-Finger (MF) Layout ........................................... 33
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3.3 Modeling of Regular Waffle (RW) Layout ............................................................ 36
3.4 Proposed Hybrid Waffle (HW) Layout ................................................................... 38
3.4.1 Lfinger-Optimization of HW Layout Structure .................................................. 40
3.4.2 Performance Evaluation via FOM ................................................................... 42
3.4.3 Simulated Characteristics of Different Layout Structures ............................... 48
3.5 Summary ................................................................................................................. 53
Chapter 4 High Speed CMOS Output Stage for Integrated DC-DC Converter ...... 54
4.1 Output Stage Design based on 5V Hybrid Waffle Layout ..................................... 55
4.1.1 Design of Low-Side Switch: N-channel MOSFETs ........................................ 56
4.1.2 Design of High-Side Switch: P-channel MOSFETs ........................................ 59
4.1.3 Power Connection Routings ............................................................................ 61
4.1.4 ESD Protection, Power Clamp, and Guard Rings ............................................ 62
4.2 IC Fabrication and Packaging ................................................................................. 66
4.3 Test PCB Design ..................................................................................................... 68
4.4 Experimental Results and Discussion ..................................................................... 70
4.4.1 On-Resistance Measurements .......................................................................... 70
4.4.2 Gate-drive Loss Measurements ........................................................................ 75
4.4.3 Efficiency Measurements ................................................................................. 77
4.5 Summary ................................................................................................................. 79
Chapter 5 Device Structure and Analysis of the SJ-FINFET on SOI ........................ 80
5.1 Device Structure and Operating Concept ............................................................... 81
5.2 Process Simulations ................................................................................................ 87
5.2.1 Simulation of P-body Formation ..................................................................... 87
5.2.2 Simulation of SJ-drift Formation ..................................................................... 89
5.2.3 Simulation of N+ Source/Drain Contact Formation ........................................ 91
5.3 Device Simulations ................................................................................................. 92
5.3.1 Mesh Structure and Grid Refinement .............................................................. 92
5.3.2 Off-State Simulations ....................................................................................... 94
5.3.3 On-State Simulations ....................................................................................... 99
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5.4 Comparison with Conventional SJ-LDMOS and Si Limit ................................... 103
5.4.1 Specific On-Resistance and Mobility Profiles ............................................... 103
5.4.2 Electric Field Distribution .............................................................................. 105
5.4.3 Trade-off Relationship between Ron,sp and BV .............................................. 108
5.5 Summary ............................................................................................................... 109
Chapter 6 Device Fabrication and Characterization of the SJ-FINFET on SOI .... 110
6.1 Process Design Considerations ............................................................................. 110
6.2 SJ-FINFET in a 0.5m Standard CMOS Process Flow ........................................ 116
6.3 Layout, Mask and Test Structures ........................................................................ 127
6.4 Experimental Results and Discussion ................................................................... 132
6.4.1 Transfer Characteristics ................................................................................. 133
6.4.2 Output Characteristics .................................................................................... 134
6.4.3 Specific On-Resistance for Different N/P Pillar Width Ratio ....................... 136
6.4.4 Breakdown Voltage for Different SJ-drift Regions ....................................... 137
6.4.5 Comparison with Fabricated SJ-LDMOSFETs ............................................. 138
6.5 Summary ............................................................................................................... 141
Chapter 7 Conclusions .................................................................................................. 142
References: ..................................................................................................................... 144
APPENDIX-I: Calculation Methods of Parasitic Resistors ...................................... 154
APPENDIX-II: Parameter Extractions for Power MOSFETs ................................. 157
APPENDIX-III: Process Flow of SJ-FINFET ............................................................ 160
List of Publication ......................................................................................................... 167
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List of Tables
Table 3.1 Data for different NN matrix of RW layout structures .................................. 36
Table 3.2 Data for different NN matrix of HW layout structures .................................. 38
Table 3.3 Parameter Summary of Trench-Gate Power MOSFETs ................................... 42
Table 3.4 Parameter Summary of Lateral-Diffusion Power MOSFETs ........................... 42
Table 3.5 Efficiency Simulation Conditions: Conventional Power MOSFETs ............... 43
Table 3.6 Parameter Summary of CMOS-based Power MOSFETs ................................. 44
Table 3.7 Efficiency Simulation Conditions: CMOS-based Power MOSFETs ............... 44
Table 3.8 Simulation Data Summary of MF, RW, and HW Layout Structures ............... 52
Table 4.1 Target Specification .......................................................................................... 54
Table 4.2 Summary of 5V power MOSFETs with Hybrid Waffle Layout Structure ....... 55
Table 4.3 Package Description of the Integrated HW Output Stage ................................ 67
Table 4.4 Summary of on-resistance measurements......................................................... 71
Table 4.5 Data comparison between simulated and measured on-resistances. ................. 75
Table 4.6 Summary of Gate-Drive Power Calculated from Measurements ..................... 76
Table 5.1: Parameters considered for both process and device simulations ..................... 86
Table 6.1 Parameters and specifications of the SOI wafer used in the fabrication ........ 111
Table 6.2 Summary of SJ-FINFET process parameters ................................................. 126
Table 6.3 Summary of SJ-FINFET layout design rules .................................................. 128
Table 6.4 SJ-FINFET Mask Information ........................................................................ 129
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List of Figures
Fig. 1.1 Evolution of power semiconductors. ..................................................................... 2
Fig. 1.2 Annual estimate and forecast of worldwide power semiconductor market........... 3
Fig. 1.3 Power device technologies and applications with respect to their voltages and
current ratings. ....................................................................................................... 5
Fig. 2.1 Basic Structure of a MOS transistor (n-type MOSFET) ....................................... 9
Fig. 2.2 An equivalent circuit for n-type MOSFET showing the parasitic capacitances and
resistances. ............................................................................................................. 9
Fig. 2.3 Types of Power Semiconductor Devices ............................................................. 11
Fig. 2.4 Structure of V-MOSFET. .................................................................................... 12
Fig. 2.5 Structure of DMOSFET....................................................................................... 13
Fig. 2.6 Structure of UMOSFET....................................................................................... 14
Fig. 2.7 Basic Structure of LDMOSFET .......................................................................... 15
Fig. 2.8 A RESURF LDMOSFET structure at full depletion ........................................... 17
Fig. 2.9 Functional elements of smart power technology ................................................. 18
Fig. 2.10 A conventional multi-finger (MF) layout structure ........................................... 21
Fig. 2.11 A modified version of MF layout structure with wider metal layers ................ 22
Fig. 2.12 A conventional Regular Waffle (RW) layout structure ..................................... 22
Fig. 2.13 Cross-section of a SJ-DMOSFET...................................................................... 26
Fig. 2.14 Ron,sp versus BV for different power device technologies [62-70]. ................... 29
Fig. 3.1 A basic MOS finger layout with simple interconnect resistive components. ...... 30
Fig. 3.2 (a) Two different MOS finger layouts with min. and max. metal-1 widths, ....... 31
Fig. 3.3 (a) Ron and (b) Ron,sp vs. Wtotal for different numbers of MOS fingers. ............... 32
Fig. 3.4 Conventional MF layout structure with parasitic resistors. ................................. 33
Fig. 3.5 A MF NMOS layout (10 MOS fingers) structure with minimum design rules. .. 35
Fig. 3.6 Corresponding schematic resistance model of the MF NMOS layout. ............... 35
Fig. 3.7 Schematic of (a) 44 regular waffle layout and (b) the corresponding resistance
model. .................................................................................................................. 37
Fig. 3.8 Hybrid waffle structure: (a) a layout and (b) a corresponding resistance model. 39
Fig. 3.9 Simulated Ron and Qg data for different Lfinger values of HW layouts. ................ 40
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Fig. 3.10 FOM-1 & FOM-2 versus different Lfinger of HW layout structures. .................. 41
Fig. 3.11 FOM vs. Efficiency for conventional power MOSFETs. .................................. 43
Fig. 3.12 Efficiency vs. Conventional FOM for CMOS-based Power MOSFETs. .......... 45
Fig. 3.13 Cross-sectional views of Trench-gate, LDMOS, and CMOS power MOSFETs.
............................................................................................................................ 45
Fig. 3.14 Efficiency vs. New FOM for CMOS-based Power MOSFETs. ........................ 48
Fig. 3.15 Gate charge characteristics of (a) MF and (b) HW layout structures ................ 49
Fig. 3.16 RON and QG plots as a function of MF, RF and HW layout active areas. .......... 50
Fig. 3.17 Comparison of power conversion efficiencies for both MF and HW layout
structures as a function of switching frequency and for different load currents:51
Fig. 4.1 Power MOSFET Output Stage: (a) Layout and (b) Schematic ........................... 55
Fig. 4.2 HW_NMOS unit-cell: (a) Active, (b) M1, (c) M2, (d) M3, (e) M4, and (f) M5. 56
Fig. 4.3 HW_NMOS unit-cell: (a) Layout and (b) Schematic (w/o parasitics) ................ 57
Fig. 4.4 Gate Segmentations of NMOS array: (a) layout and (b) schematic. ................... 58
Fig. 4.5 Layout comparison between segments: (a) Gate_N and (b) Gate_N. .... 58
Fig. 4.6 HW_PMOS unit-cell: (a) Active, (b) M1, (c) M2, (d) M3, (e) M4, and (f) M5 . 59
Fig. 4.7 Gate Segmentations of PMOS array: (a) layout and (b) schematic. .................... 60
Fig. 4.8 Layout comparison between segments: (a) Gate_P and (b) Gate_P. ..... 60
Fig. 4.9 Power Connection Routing Layouts: (a) M1-M3 and (b) M4-M5 layers. .......... 61
Fig. 4.10 Metal stress relief pattern on a routing metal wire. ........................................... 61
Fig. 4.11 2kV HBM and 400 MM ESD protection circuit, (a) layout (b) schematic. ...... 62
Fig. 4.12 ESD Protection Circuit Under Input Pad: (a) layout and (b) schematic. ........... 63
Fig. 4.13 Power Clamp, esd_nclamp5v_ 500p4U, (a) layout and (b) schematic. ............ 64
Fig. 4.14 p-type high resistance poly-resistor, rphripoly, (a) layout and (b) schematic. .. 65
Fig. 4.15 Seal and guard ring layout. ................................................................................ 65
Fig. 4.16 A micrograph of an integrated output stage using Hybrid Waffle layout in
TSMC 0.25m standard CMOS technology...................................................... 66
Fig. 4.17 A micrograph of source/drain metal runners (M3-M5). .................................... 67
Fig. 4.18 A micrograph of the packaged HW chip. .......................................................... 68
Fig. 4.19 a) System Overview and b) X-ray Image of QFN-12 package. ........................ 68
Fig. 4.20 Test PCB: (a) layout (silkscreen-view) and (b) photograph. ............................. 69
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Fig. 4.21 Test circuits for on-resistance measurements: (a) NMOS and (b) PMOS ........ 70
Fig. 4.22 Measured on-resistance vs. # of segments at different voltage ratings. ............ 73
Fig. 4.23 Comparison between simulated and measured on-resistances: ......................... 74
Fig. 4.24 Total dynamic and gate-drive power measurements. ........................................ 76
Fig. 4.25 Measured power conversion efficiency of HW output stage with a test
conditions: fs = 6.25MHz, Vin = 2.7V, Vout = 1.8V, L = 2.2 H, and C = 100nF.
............................................................................................................................ 77
Fig. 4.26 10MHz switching characteristic at Iout = 158mA. ............................................. 78
Fig. 4.27 Measured power conversion efficiency of HW segmented output stage at
10MHz switching frequency: Vin = 3.6V, Vout = 1.8V, L = 1H, and C = 56nF.
............................................................................................................................ 78
Fig. 5.1 Basic idea of SJ-FINFET structure: (a) a fin-gate and (b) with a SJ-drift region 81
Fig. 5.2 (a) Overview of the proposed lateral SJ-FINFET structure and (b) Schematic
cross-sections along the cut-lines: A-A and B-B .............................................. 83
Fig. 5.3 Ideal device structure of the proposed SJ-FINFET. ............................................ 85
Fig. 5.4 P-body formation of the SJ-FINFET: (a) a trench formation by reactive ion
etching process, (b) after 45 tilted B+ ion implantation and thermal annealing
process, (c) a doping concentration profile along X-cut line at X=2, and (d) a
doping concentration profile along Y-cut at Y=-3. ............................................. 88
Fig. 5.5 P-pillar formation of the SJ-FINFET structure: (a)-(d) are the cross-sections
along the B-B cut line after 12 tilted B+ ion implantation (left) and thermal
diffusion (right) steps and (e)-(h) are the corresponding doping profiles for
different B+ ion implantation doses. .................................................................... 90
Fig. 5.6 N+ source/drain contact formation of the SJ-FINFET: (a) after 45 tilted dual-
implant of n-type dopant species (i.e. arsenic and phosphorus) and thermal
diffusion steps, and (b) a doping concentration profile along Y-cut line at Y=-3.
............................................................................................................................. 91
Fig. 5.7 Unit-cell of the SJ-FINFET: a) w/ and b) w/o any oxide materials .................... 93
Fig. 5.8 Contour plots of the electrostatic potential distribution in off-state for a proposed
SJ-FINFET with p-pillar impurity concentration of 9.25 x 1016
cm3
under charge
balance: a) w/ and b) w/o any oxide materials ................................................... 96
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Fig. 5.9 Contour plots of the electric field distribution in off-state for a proposed SJ-
FINFET with p-pillar impurity concentration of 9.25 x 1016
cm3
under charge
balance: a) w/ and b) w/o refined mesh structure. .............................................. 97
Fig. 5.10 The relationship between BV and charge imbalance for the proposed SJ-
FINFET with Ldrift of 3.0 m and 6.0 m, Wn = Wp = 0.3 m and trench depths
(Wside) of 2.0 m and 3.0 m. ............................................................................ 98
Fig. 5.11 I-V characteristics of the proposed SJ-FINFETs during off-state for various drift
region lengths. .................................................................................................... 98
Fig. 5.12 Transfer characteristics of the SJ-FINFET with Ldrift = 3.5 m. ....................... 99
Fig. 5.13 On-state simulations: (a) electron current density distribution and (b) output
characteristics of the SJ-FINFET with Ldrift =4.5 m and device area = 1 mm2.
.......................................................................................................................... 101
Fig. 5.14 I-V characteristics of the proposed SJ-FINFETs during on-state for various drift
region lengths. .................................................................................................. 102
Fig. 5.15 The trade-off relationship between BV and Ron,sp of the SJ-FINFET for different
drift region lengths. .......................................................................................... 102
Fig. 5.16 Specific on-resistance profile along C-C cut line during on-state for
conventional SJ SOI-LDMOS and the proposed SJ-FINFETs ........................ 104
Fig. 5.17 Mobility profile along C-C cut line during on-state for conventional SJ SOI-
LDMOS and the proposed SJ-FINFET with Wside = 3 m. ............................. 105
Fig. 5.18 Comparison of the electric field distribution (along the C-C cut line) for the SJ-
FINFETs with two different values of NA at ND= 7.4 1016
cm3
and Wside = 2
m. ................................................................................................................... 106
Fig. 5.19 Electric field distribution comparison between the conventional SJ-LDMOS and
SJ-FINFETs at NA = 9.25 1016
cm3
and ND = 7.4 1016
cm3
. ................... 107
Fig. 5.20 Performance comparison between SJ simulation results with different trench
gate depths and previously published data. ...................................................... 108
Fig. 6.1 Standard CMOS process flow with additional steps for the lateral SJ-FINFET
implementation. ................................................................................................. 112
Fig. 6.2 Six sequential processing steps required for the deep trench isolation region. . 113
Fig. 6.3 Process Flow of the SJ-FINFET (Part 1 of 5) ................................................... 121
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Fig. 6.4 Layout design rules for the proposed SJ-FINFET device on a SOI platform. .. 127
Fig. 6.5 A full test chip layout of both SJ-FINFET and SJ-LDMOS device. ................. 131
Fig. 6.6 Some of the process structures: (a) critical dimensions and (b)-(c) alignment
marks. ................................................................................................................ 131
Fig. 6.7 Micrograph of the fabricated test integrated chip (Optical: 200). .................. 132
Fig. 6.8 Top-view of SJ-FINFET device: (a) a layout and (b) a corresponding fabricated
structures. .......................................................................................................... 133
Fig. 6.9 SEM images of fabricated SJ-FINFET: (a) a transistor array and (b) a cross-
section after Al and oxide etchings. .................................................................. 133
Fig. 6.10 Ids - Vgs transfer characteristic of the fabricated SJ-FINFET at Vgs = 0.1 V. .. 134
Fig. 6.11Output I-V characteristics of the fabricated (a) SJ-LDMOSFET and (b) SJ-
FINFET devices, Ldrift = 3.5 m and Wtotal = 200 m. .................................... 135
Fig. 6.12 The specific on-resistance of the fabricated SJ-FINFETs for different n/p pillar
width ratios and SJ-drift trench (DTI) widths. ................................................. 136
Fig. 6.13 The relationship between BV and P-pillar dose for the fabricated SJ-FINFET
devices with Ldrift of 3.5 m and 6 m, Wn = Wp = 0.3 m and Wside of 2.7 m.
.......................................................................................................................... 137
Fig. 6.14 On-resistance data comparison as a function of the gate width (W) of the
fabricated SJ-FINFET and SJ-LDMOSFETS, Ldrift = 3.5 m. ........................ 138
Fig. 6.15 Ron,sp data comparison between SJ-FINFET and SJ-LDMOS for different Ldrift.
.......................................................................................................................... 139
Fig. 6.16 Micrographs of the SJ-FINFETs with different drift lengths: (a) Ldrift = 3.5 m,
(b) Ldrift = 6.0 m, (c) ) Ldrift = 10.0 m and (d) ) Ldrift = 12.0 m for Wtotal = 200
m. ................................................................................................................... 139
Fig. 6.17 Performance comparison between the fabricated SJ-devices and previously
published data. Data from [102], [104], [114] are for conventional
LDMOSFETs. Data from [103], [111-113] are for conventional SJ-
LDMOSFETs. .................................................................................................. 140
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List of Glossary
ASIC: Application Specific Integrated Circuits
ASSP: Application-Specific Standard Products
BJT: Bipolar Junction Transistor
BV: Breakdown Voltage
BOX: Buried Oxide Layer (SOI Wafer)
CAGR: Cumulative Average Growth Rate
CMOS: Complementary Metal Oxide Semiconductor
CMP: Chemical Mechanical Polishing
DMOS: Double Diffused MOS
DTI: Deep Trench Isolation
ESD: Electro-Static Discharge
FET: Field Effect Transistor
FOM: Figure of Merit
FINFET: Fin-Field Effect Transistor
GTO: Gate Turn-off Thyristor
HW: Hybrid-Waffle (Layout Style)
HS: High-Side (Output Switch)
HBM: Human Body Model (ESD)
IGBT: Insulated Gate Bipolar Transistor
ICP-RIE: Induced Coupled Plasma RIE
LDMOSFET: Lateral Double-Diffused MOSFET
LS: Low-Side (Output Switch)
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LOCOS: LOCal Oxidation of Silicon
LTO: Low Temperature Oxide
MOS: Metal Oxide Semiconductor
MF: Multi-Finger (Layout Style)
MM: Machine Model (ESD)
PIC: Power Integrated Circuits
PECVD: Plasma Enhanced CVD
QFN: Quad Flat No-Lead (Package Type)
RESURF: Reduced SURface Field
RIE: Reactive Ion Etching
RW: Regular-Waffle (Layout Style)
SOA: Safe Operation Area
SEG: Selective Epitaxial Growth
SAD: Substrate-Assisted Depletion
SJ: Super-Junction
SOI: Silicon-On-Insulator
SFB: Silicon Fusion Bonded (SOI Wafer)
STI: Shallow Trench Isolation
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List of Symbols
Cgd: Gate to Drain Capacitance, or Miller Capacitance
Cgs: Gate to Source Capacitance
Ciss: Input Capacitance
Coss: Output Capacitance
Crss: Reverse Transfer Capacitance
si : Dielectric Constant of Silicon (=1.0310-12
F/cm)
ox : Dielectric Constant of Oxide (=3.4510-12
F/cm)
Ec: Critical Electric Field
fs: Converter Switching Frequency
Lg: Gate or Channel Length
Ldrift: Drift Length
NA: Acceptor or Hole Doping Concentration
ND: Donor or Electron Doping Concentration
in : Intrinsic Carrier Concentration
Pcond: Conduction Power Loss
Pdyn: Dynamic Power Loss
Pgate: Gate-Drive Power Loss
Psw: Switching Power Loss
q : Electronic Charge (=1.6010-19 C)
Qg: Total Gate Charge
Qgs: Gate to Source Charge
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Qgd: Gate to Drain Charge
Rg: Gate Resistance
Ron: On-Resistance
Ron,sp: Specific On-Resistance (Ron Area)
Rp: Project Range of Implant
Sn or Sp: Cross-sectional Area of n-drift or p-drift region
Tox: Oxide Thickness or Gate Oxide Thickness
Tepi: Epi. Thickness (SOI Wafer)
on : Turn-On Delay
off : Turn-Off Delay
ch : Carrier Mobility in the Channel
Vth: Threshold Voltage
Vin: Input Supply Voltage
Vout: Output Voltage
Vgate: Gate Voltage
Vgs: Gate to Source Voltage
Vds: Drain to Source Voltage
Wg: Gate or Channel Width
Wd: Depletion Width
Wn or Wp: n-pillar or p-pillar Width
Wside: Trench Gate Depth
Wtop: Top Gate Width
Wtotal: Total Channel Width
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Chapter 1 Introduction
Over the last decade, there has been a growing research interest in the area of high-
efficient power integrated circuits (PICs) for various electronic applications. Especially
portable electronics products, such as cell phones, laptops, MP3 players, PDAs, digital
cameras, and other compact battery powered products have gained tremendous popularity
in the market place during the last few years. Power management ICs play a critical role
in these systems to offer a long battery operating time and many power-saving features at
the same time. The most important and largest device block in power management IC is
the output power stage, which can switch or regulate large amounts of power using many
parallel-connected power transistors. MOS power transistors have several advantages
over their bipolar counterparts, including a majority carrier device, simpler drive
requirements, and lower forward voltages. These advantages make MOS transistors
extremely useful power devices [1-4]. In this chapter, power device technology, market
trends, advantages/disadvantages, their current and future applications, and the objectives
of this thesis will be addressed.
1.1 Technology and Market Trends in Power Semiconductors
The growth of todays power electronics has been centering on AC-DC inverters and
DC-DC converters as the key system topologies. This has been accelerated by several
evolutionary changes and breakthroughs in the areas of power semiconductor device and
process technologies. Fig. 1.1 shows the historical growth of power semiconductor
devices. In the 1960s, the introduction of the thyristor generated the first wave in the
history of power semiconductor devices and opened up many possibilities for the growth
of power electronics as a whole. In the second half of the 1970s, the bipolar transistor
module and the gate turn-off thyristor (GTO) were introduced for the growing demand of
power conversion equipment and they quickly became the focus of power electronics
growth. This started the second wave in the chronological evolution of power
semiconductor devices [5].
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Fig. 1.1 Evolution of power semiconductors.
In the early 1980s through late 1990s, the third wave started to build up focusing on
MOS-gated controlled devices. The introduction of power MOSFETs enabled compact
and efficient system designs particularly those based on low voltage (less than 200V)
applications. In order to improve both performance and reliability, the trench gate,
DMOS (Double-diffused MOS), IGBT (Insulated Gate Bipolar Transistor), and RESURF
(Reduced SURface Field) technologies were adopted. In particular, these efforts were
aimed at improving performances of MOS gated active switches relating to reduction of
conduction and switching losses for high current and fast switching operations, and
enhancement of Safe Operation Area (SOA) to withstand short circuit stresses [1].
Consequently, power MOSFETs became the predominant options for todays power
device manufacturers.
Power ICs (PIC) are one of the most active electronic devices in the market nowadays.
Their market growth rate is now faster than the overall semiconductor market. Fig. 1.2
presents iSupplis estimate and forecast for power semiconductor shipment revenue
1950 1970 1980 1990 2000 20101950 1970 1980 1990 2000 20101st Wave
(Uncontrollable
Latching
Devices)
2nd Wave(Controllable
Non-Latching
Devices)
3rd Wave(MOS-Gate
Controlled
Devices &
Power ICs)
Triac
Bipolar
Transistor
RC
ThyristorThyristor
GTO
Light Trig. Thyristor
JFET / SIT
Bipolar Tr. ModuleHigh
Bipolar Tr. Module
GCT
RESURF
LDMOSFET
IGBT
NPT-IGBT
Trench
VDMOSFET
Trench
IGBT
FS-IGTBT
Superjunction
VDMOSFET
LDMOSFET
(EDMOS)SOI-
LDMOSFET
Sub-
CMOS
V-shape gate
MOSFET
VDMOSFET
Power
MOSFET
LIGBT[7]
[8]
[9][10]
[11]
[12]
[13]
[14]
[15]
[6]
-
3
during the period from 2006 to 2011 [16]. The power semiconductor market is expected
to increase at a cumulative average growth rate (CAGR) of 8% per year to $15.5 billion
in 2011. Among several different power device technologies, the switching regulator,
power management ASIC/ASSP (Application-Specific Integrated Circuits or Standard
Products), and low voltage power MOSFET applications are currently contributing more
than half of total market revenue. Especially, the switching regulator and low voltage
power MOSFETs are used in almost all portable electronics and automotive components.
In recent years, with the rising output of whole systems, these two products are
developing relatively faster than the others as demonstrated in this figure.
Fig. 1.2 Annual estimate and forecast of worldwide power semiconductor market.
1.2 Advantages of Power MOSFET Devices
In general, bipolar transistors are not suitable for high speed switching applications
because they saturate when their collector-base junctions is forward-biased. Saturation
greatly increases the amount of minority carrier charges stored in both the neutral base
and collector. A transistor cannot turn-off until these stored charges recombine or diffuse
across a junction. A typical power bipolar transistor therefore exhibits a saturation delay
of about a microsecond. This delay effectively places an upper limit on switching speeds
LV LV LV
LV LV
LV
SWR SWR SWR SWR SWR
SWR
$16B
-
4
of about 500 kHz [3]. On the other hand, MOS transistors are majority carrier devices.
They do not exhibit any saturation delay, thus they can switch at speed in excess of multi
MHz [3]. Another advantage of power MOSFETs are their simple drive circuitry. The
average current through the gate drive of a typical one-amp power MOSFET is only a
few milliamps. Bipolar transistors generally require much higher drive currents due to a
low current gain ().
Power MOSFETs can also conduct large currents at very low drain-to-source
voltages. The behavior of a MOS transistor under these conditions can be derived from
the Shichman-Hodges theory for the linear region [17]. The simplified theory reveals a
linear relationship between the drain-to-source voltage and the drain current. The
transistor behaves as if it is a resistor whose value is known as the on-resistance. The on-
resistance can be reduced to arbitrarily small values by increasing the W/L ratio.
However, in practice, considerations such as die size, cost, metallization resistance, and
bond-wire resistance place practical limitation upon the on-resistance. In general, the
limitations are more severe in low voltage power MOSFETs (
-
5
fuel cell vehicles. Low voltage power MOSFETs (
-
6
1.4 Thesis Objectives and Organization
The objectives of the thesis are to design, implement, and optimize the next
generation of low-voltage silicon power MOSFETs. New device structure and layout
optimization techniques are proposed and analyzed for sub-100V applications. Both
approaches strive to minimize the power consumption of the output stage in DC-DC
converters.
Chapter 2 describes the state of the art of power semiconductor devices. It provides a
review of the recent developments in vertical and lateral power semiconductor
technologies. Also, it discusses the fundamental device physics concerning power
semiconductors, several of the important physical models for both circuit and device
simulations, and some of the related topics including layout techniques and super-
junction concept.
In Chapter 3, the analytical layout modeling of three different layout structures is
presented. Specific attention is given to a new layout strategy named Hybrid Waffle
structure. Layout optimization and performance evaluation via simulations are also given.
In Chapter 4, experimental work such as the integrated circuit implementation on a DC-
DC converter, test circuit board design, and various electrical measurements are
presented for verification purposes.
In Chapter 5, a novel device structure that is suitable for practical implementation of
lateral superjunction FINFET (SJ-FINFET) is proposed, simulated and compared with
other conventional power MOSFETs. Both process and device simulation studies are
presented to extract and validate the specific processing conditions and the optimal
device characteristics, respectively. In Chapter 6, the performance advantage of the SJ-
FINFET over the conventional SJ-LDMOSFET is verified experimentally. Detailed
fabrication process scheme is presented followed by various electrical measurement
results of the devices.
Finally, in Chapter 7, conclusions and suggestions for future work are discussed.
-
7
Chapter 2 Power MOSFETs a Brief Overview
2.1 Fundamentals of MOS Device
Metal-oxide-semiconductor (MOS) is a major class of integrated circuits. MOS
technology is used in microprocessors, microcontrollers, static RAM, and other digital
logic circuits. Also, it is used for a wide variety of analog circuits such as image sensors,
data converters, and highly integrated transceivers for many types of applications [3].
Two important characteristics of the Complementary MOS (CMOS) technology are high
noise immunity and low static power consumption. Significant power is only drawn when
the transistors are switching between on and off states. Consequently, MOS circuitry
dissipates less power and is denser than other implementations having the same
functionality. As this advantage has grown and become more important, the vast majority
of modern integrated circuit manufacturing is on CMOS processes.
The basic structure of MOS transistor (i.e. n-type MOSFET) is shown in Fig. 2.1,
where n+ represents heavily doped n-type silicon with low resistivity. The difference
between the source and drain is that the source n+ is shorted to the p-substrate by the
source metal. This is important for fixing the potential of the p-substrate for normal
device operation. For power device applications, the MOSFET is necessary to be off
when the voltage on the gate is zero. The turn-on of the MOSFET relies on the formation
of a conductive channel on the surface of the semiconductor, when a positive (or
negative) voltage is applied on the gate of the n-type (or p-type) MOSFET. For the n-type
MOSFET, as Vg increases, electrons gather at the interface between the oxide and silicon,
and a charged layer is formed to provide a "channel" for the current. When this
phenomenon occurs, the value of Vg is called the threshold voltage (Vth). In
semiconductor physics, the Vth is defined as the applied gate voltage required to make the
surface of the silicon strongly inverted (i.e. as n-type in terms of carrier concentration as
the p-type substrate. The threshold voltage can be written as [32]:
-
8
m sox
ssdep
fpthC
QQV
2 (Eq.2.1)
where i
afp
n
N
q
kTln (Eq.2.2)
afpsidep NqQ 4 (Eq.2.3)
ox
oxox
TC
(Eq.2.4)
The definitions of the other symbols are:
1)` k is the Boltzmann's constant: k =1.3810-23 J/K,
2)`T is the absolute temperature,
3)` q is the electronic charge: q =1.6010-19 C,
4)` aN is the acceptor doping concentration of the substrate,
5)` in is the intrinsic carrier concentration of the silicon,
6)` si is the dielectric constant of silicon: si =1.0310-12
F/cm,
7)` ssQ is the fixed charge located in the oxide close to the oxide-silicon interface,
8)` ox is the dielectric constant of oxide: ox =3.4510-12
F/cm, and
9)` oxT is the thickness of the gate oxide.
The resistance from drain to source of the MOSFET is determined by the property of
the charged layer in the channel, and can be expressed as [32]:
)( thgsoxchg
oxg
chVVW
TLR
(Eq.2.5)
where nch is the carrier mobility in the channel. The definition of gL (gate length) and
gW (gate width) are shown in Fig. 2.1.
-
9
Fig. 2.1 Basic Structure of a MOS transistor (n-type MOSFET)
Other important characteristics of a MOS transistor include its capacitance and gate
charge. A simple equivalent circuit of n-type MOSFET is illustrated in Fig. 2.2, where
the three capacitors, Cgd, Cds, and Cgs represent the parasitic capacitances. These values
can be manipulated to form the input capacitance (Ciss), output capacitance (Coss), and
reverse transfer capacitance (Crss).
Fig. 2.2 An equivalent circuit for n-type MOSFET showing the parasitic capacitances and
resistances.
Gate
Source Drain
Cgs Cgd
Cds
Rg
Rs Rd
N+ N+
Lg
P+
P-substrate or P-well
Drain Source Gate
Oxide
Wg
-
10
Among these capacitors, the gate-drain capacitance Cgd, known as a Miller
capacitance is the most important parameter because it provides a feedback loop between
the devices output and its input. The switching behavior of the MOSFET is also
governed by the charging and discharging of the input capacitance which is the sum of
the gate-to-source capacitance (Cgs) and the gate-to-drain capacitance (Cgd). The gate
resistance (Rg) is also important because the switching delay is directly proportional to a
product of the distributed gate resistance and its capacitance.
However, the nonlinearity of the parasitic capacitances and the incomplete data on
their variation over the full range of relevant voltages, make a gate circuit by
conventional methods exceedingly difficult. To overcome this problem, it has become
standard practice to specify the total gate charge, Qg that has to be supplied in order to
establish a particular drain current under given test conditions. Data sheets from most
manufacturers normally divide the Qg into that required to charge the gate-to-source
capacitance, Qgs, and that required to supply the gate-to-drain capacitance, Qgd. The merit
of the gate charge parameter is that it is relatively insensitive to the drain current and the
precise circuit conditions used, and it is quite independent of temperature [1]. It allows a
very simple design methodology for obtaining the desired switching time, and it enables
the total charge and the total energy required to be easily estimated. The resulting average
current and power needed from the gate circuit can be also obtained throughout a
multiplication of the operating frequency.
Another important parameter of a MOS transistor is the breakdown voltage. It is the
reverse biased voltage in which a substrate-drain (or body-drift) diode breaks down and
significant current starts to flow between the source and drain by the avalanche
multiplication process. For drain voltages below the rated avalanche voltage and with no
bias on the gate, the drain voltage is entirely supported by the reverse biased p-n junction.
With a poor MOSFET design and process, punch-through breakdown can be observed
when the depletion region from the drain (or drift) junction reaches the source region at
drain voltages below the avalanche voltage. This also provides a current path between
source and drain and causes a soft breakdown characteristic.
-
11
2.2 Types of Power MOSFETs
The simple MOS structure was initially not suitable for discrete power ICs, because
in order to achieve the low channel resistance, shorter channel length ( gL ) and thinner
gate oxide ( oxT ) were mandatory. Since both gL and oxT are related to the breakdown
voltage of the MOS device, the MOS structure is not considered for the choice of power
devices, especially in medium and high voltage power ICs. For instance, if gL is too
small, the punch-through of n+pn
+ (or p
+np
+) of N-type (or P-type) MOSFET will occur;
if oxT is too thin, the oxide directly adjacent to the drain can be damaged or destroyed by
the electric field. To alleviate the effect of the electrical field on the gate oxide, several
traditional power MOS device structures have been developed and commercialized, as
illustrated in Fig. 2.3. In terms of a device structure, the power MOSFET family can be
divided into two different categories: lateral and vertical power MOSFETs.
Fig. 2.3 Types of Power Semiconductor Devices
Power Semiconductor Devices
CMOS LDMOS RESURF
2-terminal devices
Schottky diodePiN diode Power MOSFET
3-terminal devices
JFET IGBT BJT Thyristor
Lateral Vertical
UMOS V-MOS DMOS Cool MOS
Traditional Power MOSFETs
Minority carrier devices
Majority carrier devicesPower Semiconductor Devices
CMOS LDMOS RESURF
2-terminal devices
Schottky diodePiN diode Power MOSFET
3-terminal devices
JFET IGBT BJT Thyristor
Lateral Vertical
UMOS V-MOS DMOS Cool MOS
Traditional Power MOSFETs
Minority carrier devices
Majority carrier devices
-
12
Some well known examples of vertical power MOSFETs include V-MOS (V-shaped
MOS), DMOS (Double-diffusion MOS), UMOS (U-shaped MOS), and Cool MOS
(Vertical Super-junction MOS from Infineon Technologies). The common lateral power
devices include LDMOS (Lateral Double-diffused MOS), RESURF (Reduced SURface
Field) LDMOS and CMOS power transistors. In the following sections, both traditional
vertical and lateral power MOSFETs are briefly discussed in terms of their intrinsic
structures and associated operating principles.
2.2.1 Traditional Vertical Power MOSFETs
V-MOSFET
The name, V-MOSFET [33] is derived from the V-shaped groove along which
current flows, as shown in Fig. 2.4. Although the V-MOSFET was the first
commercialized structure of the power MOSFET, it was replaced by the Double-diffusion
MOSFET (DMOSFET) because of the drawback of high electrical field concentrated at
the tip of the V-groove. The diffusion refers to the manufacturing process: the P-well is
obtained by a diffusion process (i.e., actually a double diffusion process to get the P-body
and N+ regions, hence the name double-diffused).
Fig. 2.4 Structure of V-MOSFET.
Gate Source Source
P-body
N+ N+
P-body
N-drift region
N+
Drain
Oxide
-
13
DMOSFET
In Fig. 2.5, the cross-sectional vertical structure of the DMOSFET [33] is illustrated.
When Vg is higher than the threshold voltage and Vds is positive, the electron current of
the DMOSFET travels horizontally through the channel and then vertically down to the
drain. A more direct and shorter current path can be achieved if the channel is orientated
vertically instead of along the silicon surface. This idea is realized later by the structure
of the UMOSFET.
Fig. 2.5 Structure of DMOSFET.
UMOSFET
Similar to V-MOSFET, the UMOSFET is named from the U-shaped groove formed
in the gate region, as shown Fig. 2.6. In comparison with the DMOSFET structure, the
UMOSFET has no JFET effect, which is caused by the depletion of the region between
wells in the DMOSFET. The UMOSFET has higher channel density to significantly
reduce the on-resistance and also it has no sharp oxide tip (as in the V-MOSFET). This is
because that the corners of the gate oxide located in the n-drift region can be rounded by
isotropic etching. In order to prevent the catastrophic destruction of the gate oxide due to
the high electrical field at the corner of the trench, the p-body is usually designed to be
Source Source Gate Oxide
N+ N+
P-body P-body
N-drift region
Drain
N+
-
14
relatively deep. Also, the doping concentration at the bottom of the p-body is high
enough to ensure that the breakdown voltage occurs first at the junction of the p-body and
the n-drift region. As a result, the voltage can be clamped to save the gate oxide [34].
Fig. 2.6 Structure of UMOSFET.
2.2.2 Traditional Lateral Power MOSFETs
Lateral Double Diffused MOSFET (LDMOSFET)
The lateral double diffused MOSFET is the predominant power device in the
implementation of PICs because of many attractive electrical characteristics such as high
input impedance, low on-resistance, high breakdown voltage and fast switching speed. A
typical LDMOSFET structure is as illustrated in Fig. 2.7. In this structure, the current
flows laterally on the surface from the source to the drain electrode and the channel
region is implemented using double implantation of the p-well and the n+ source regions
through the same opening window. One of the main advantages in the LDMOSFET is
that it can be easily integrated into a standard CMOS process. In the on-state, when a
positive voltage, higher than the threshold voltage is applied to the gate, a conductive
channel forms at the surface of the p-well and electrons flow from the n+ source through
the highly conductive channel and the n-drift layer to the n+ drain electrode. In the off-
Drain
Source Source
N-drift region
N+
Source Gate Gate
Oxide
N+ N+ N+ N+
P-body P-body P-body
-
15
state, the depletion region associated with the p-well and the n-drift region, mostly
extends through the drift region and determines the breakdown voltage of the structure.
The drift region length and resistivity should be optimized to achieve a higher BV. In
order to enhance the trade-off relationship between BV and Ron,sp, the drift region length
should be increased while its doping concentration is decreased. In the LDMOSFET, the
trade-off relationship is defined by the equation [35].
25.2, cmBVR spon (Eq.2.6)
This equation provides that the relationship between BV and Ron,sp. It is quadratic in
nature. Hence, a higher BV can result in a significant increase in the on-resistance of the
device. Therefore, the silicon area efficiency is low and the specific on-resistance is
relatively high for those applications that require a high current handling capabilities. In
vertical power MOSFETs, the n-drift region is located inside the silicon. Hence, a current
path can be elongated without sacrificing the silicon area.
Fig. 2.7 Basic Structure of LDMOSFET
N+ N+
Lg
P+
P-substrate
Drain Source Gate
Oxide
Wg
N-drift region
P-well
-
16
RESURF(Reduced SURface Field) LDMOSFET
In 1979, Appels and Vaes suggested the RESURF concept [36], which allows
significant improvement in the voltage blocking capability of lateral device. The cross
section of a RESURF LDMOSFET is as shown in Fig. 2.8. There are two different diodes
shown with the associated junctions such as a lateral junction at the n-drift/p-well
boundary and a vertical junction at the n-drift/p-substrate boundary. At an optimum
thickness and concentration of the n-drift layer, the depletion layer from both horizontal
and vertical n/p junctions allows the electric field at the surface to be lower than the
critical electric field. A higher breakdown occurs at the junction between the p-substrate
and n-drift layer when the electric field reaches the critical value, Ec.
Under the conditions, the thickness of the epitaxial layer, te must equal to the
depletion width, Wd in that layer as defined by the following equation [36].
se
sed
NNq
BVtW
(
)(2 (Eq.2.7)
where s denotes the dielectric constant of silicon, q is the electronic charge, and Ne and
Ns are the doping concentration in the epitaxial layer and the substrate respectively. The
corresponding parallel plane breakdown voltage is then given by [36].
)(2
2
se
Cs
NNq
EBV
(Eq.2.8)
where Ec is the critical electric field in silicon. The charge density, Ne te in the epitaxial
layer is given by [36].
q
EtN Csee (Eq.2.9)
-
17
If Ne >> Ns, (Eq. 2.21) can be simplified to
2121021 cmtN ee (Eq.2.10)
A well designed silicon RESURF device, satisfying the above condition, can withstand
approximately 15 V/m of drift region length.
The RESURF structure allows the optimized performance at high voltages in the off-
state, because the n-drift layer is fully depleted of charge carriers and the surface field is
reduced to a value of less than the critical electric field. The surface electric field profile
is uniform and has a flat shape at the surface. In the past decades, the RESURF
technology has been successfully commercialized for many lateral power semiconductor
devices such as diodes and LDMOS transistors for 20 1200V [37]. Although the
maximum blocking voltage of the RESURF LDMOSFET is greater than the conventional
LDMOSFET, this increase is limited to a few hundred volts because the lightly doped
epitaxial drift layer causes an increase in the on-resistance of the device.
Fig. 2.8 A RESURF LDMOSFET structure at full depletion
N+ P+
N-drift region
N+
P-well
P-substrate
te
E
Y
Ec
Gate
X
E Es < Ec
-
18
2.3 CMOS-based Power MOSFETs
The majority of todays VLSI chips are implemented with deep submicron CMOS
technologies. Therefore, the integration of other types of power MOSFETs into the
design requires additional fabrication process and time. In the following sections, the
monolithic integration of output power transistors and the associated layout techniques,
based on a standard CMOS technology is briefly discussed.
2.3.1 Monolithic Integration: Standard CMOS Process
Monolithic integration of output power semiconductors with digital and analog
circuitry includes power devices, signal processing, sensing, and protection circuits on
the same chip, as illustrated in Fig. 2.9. Monolithic solutions for power conversion and
amplification are highly desirable not only for the reduction of volume, weight and
electromagnetic interferences, but also for increasing efficiency, performance and
reliability of the overall system. A wide range of applications is predictable for these
monolithic solutions, since the power delivered by a power IC into a load can be several
to hundreds of watts. Many approaches are being investigated to search for new strategies
to reduce the cost and size of PICs [38-43].
Fig. 2.9 Functional elements of smart power technology
Smart Power ICs
Power Devices Control CircuitsSensing &
ProtectionInterface
IGBT
LDMOS
VDMOS
SJ-MOS
Bi-CMOS
CMOS
HV Level Shifter
Gate Drive Circuit
Analog Circuits
Over Temperature
Over Current
Under Voltage
Over Voltage
Logic Circuits
CMOS LSI
-
19
Monolithic integration is aimed at performing complex switching functions at high
frequencies, motivating progress in this area, and pushing manufacturers to launch
application-specific PICs into the market, especially for low-voltage power applications.
The impact of smart power technology on the recent advances in telecommunication and
automobile industries is remarkable because the drastic cost and size reductions are
possible by applying these monolithic solutions. For examples, a significant performance
gain and cost reduction can be easily achieved by implementing a standard CMOS or
CMOS-compatible processes to build up all necessary blocks required in smart power ICs.
Previous smart power devices have always used design rules and technologies which
are less efficient than that used for CMOS devices. In the early 80s, the first smart power
devices were fabricated with 2.5 or 4m design rules while CMOS used 1m design
rules. When CMOS devices used submicron IC design rules, smart power devices were
fabricated with 1 or 2m design rules [5]. This difference was essentially linked (i) to the
more complex fabrication that must be taken into account: isolation, edge terminations
for power devices and combination of different kinds of devices, and (ii) to the rapid
development of CMOS devices driven by larger market forces. Recently, the design rules
for smart power devices went down to 0.35-0.13m, which offers a greater possibility of
integrated CMOS-based power ICs. This strong drive towards integration leads to a
single chip system for low voltage power applications. Some manufacturers prefer a
mixed technology (e.g. Bi-CMOS); however, overall design rules do not help to reduce
the device area, because most of the chip size is determined by the on-chip power devices.
Since low voltage power MOSFETs implemented in a deep submicron CMOS process
exhibit much shorter switching delays than those in conventional power MOSFETs, this
allows the CMOS devices to operate in the MHz range for high-efficient mobile
applications. Nevertheless, one of the drawbacks is that more advanced CMOS
technology is accompanied with larger parasitic interconnect resistances and capacitances.
Without any processing and device structural changes, performance improvement can be
only gained by introducing a new layout structure. In the next section, several different
layout techniques for CMOS power device applications will be discussed in detail.
-
20
2.3.2 CMOS Layout Techniques for Power Integrated Circuits
As the switching frequency of power converters continues to increase, both switching
and gate-drive power losses start to limit the efficiency of output power stage.
Particularly, conventional vertical power MOSFETs have relatively large gate to drain
overlap area. This introduces a significant switching delay ( = RC) since a large input
capacitance requires more charging and discharging time for each turn on and off
transition of a power MOSFET. On the other hand, CMOS-based power MOSFETs have
much smaller input gate capacitance due to smaller gate-drain/source overlap capacitance,
gate oxide capacitance and parasitic fringing capacitance. Therefore, CMOS power
MOSFETs have been the best choice for mobile SMPS applications operating in the
multi-MHz range. However, the distributed parasitic resistance associated with metal
interconnects to the source and drain terminals strongly affect the total on-resistance of a
large CMOS device (with a high W/L ratio). The previous research by Kayayama et.al
[18] demonstrated that simple power device models, which do not consider the effects of
metal resistance, can produce more than 50% variation in the Ron simulation for large
power MOS devices. The impact of the parasitic resistance is extremely dependent upon
the layout style of the power MOSFETs and the positioning of external source/drain
connections. Many efforts [41-44] have been made in the past to optimize the CMOS
layout to provide minimum parasitic resistance and capacitance. Some examples are
summarized in the following sections.
Multi-Finger (MF) Layout Structure
The multi-finger (MF) CMOS layout structure has been widely used in almost all
smart PICs. In general, MOS transistor with large device widths are needed to achieve
low channel resistance, and to maximize the operating frequency, the minimum gate or
channel length is used. To reduce the distributed gate resistance, a common layout
practice is to decompose it into many parallel transistors of smaller widths. This
conventional layout technique is known as a multi-finger distribution, as shown Fig. 2.10.
-
21
Fig. 2.10 A conventional multi-finger (MF) layout structure
This technique not only reduces Rg but it also reduces junction capacitances. Further
reduction in gate resistance can be obtained by using multiple contacted gates. However,
for power device applications, the disadvantages of multi-finger layout include: (i) the
increase in the total area of gate-source and gate-drain overlaps, (ii) the increase in gate-
bulk parasitics, and (iii) the increase in metal interconnect resistance [3]. Theoretically,
more transistors that are placed in a parallel configuration, the larger the active area and a
lower channel resistance is achieved at the expense of increasing total gate capacitance.
However, Ron does not continue to decrease as the number of parallel fingers is
increased. In fact, at some point, the interconnect resistance begins to dominate, causing
Ron to be saturated. Further increase in active area leads to higher total gate capacitance
without any Ron reduction. To minimize Ron, many different layout techniques have been
proposed and commercialized [44]. One of modified versions of MF layout [3] is
demonstrated in Fig. 2.11. Although the wider metal layers minimize the overall Ron in
this type of layout structure, there is a trade-off relationship between a number of
source/drain contacts and a width of metal layer. In addition, this layout structure has no
change in device active area; therefore the gate resistance and capacitance remain the
same as those of the conventional MF layout structure.
Gate
Drain: M-1 || Mtop
Source: M-1 || Mtop
Source
Drain
Gate Poly
Contact
Metal-1
-
22
Fig. 2.11 A modified version of MF layout structure with wider metal layers
Regular Waffle (RF) Layout
Although the conventional MF layout arrangement possesses the virtue of simplicity,
it does not produce the densest possible layout. Other designs can achieve lower specific
on-resistances by tightly packing arrays of cleverly shaped source and drain element The
regular waffle (RW) layouts exemplifies this concept and its basic layout structure is
represented in Fig. 2.12.
Fig. 2.12 A conventional Regular Waffle (RW) layout structure
Gate Source: M-2 || Mtop
Drain: M-2 || Mtop
M-1
Source
Drain
Gate Poly
Contact
Metal-1
Via-1
Metal-2
Drain: M1 || Mtop
Source: M1 || Mtop
Gate
Source
Drain
Gate Poly
Contact
Metal-1
-
23
The RW layout uses a mesh of horizontal and vertical poly gate stripes to divide the
source/drain implant into an array of squares. Each square contains a single contact. By
alternately connecting these contacts to the source and drain metallization, one can
arrange four drains around each source and four sources around each drain [44]. The
drain and source metallization consists of a series of diagonal stripes of metal-1 and
upper parallel metal layers as shown in this figure.
An analysis of the W/L ratios achieved for a given device area shows that the waffle
layout structure provides an increase in packing density equal to [3]:
gategate
gate
MF
RW
SL
S
LW
LW
2
)/(
)/( (Eq.2.11)
where RWLW )/( of the waffle layout and MFLW )/( of the conventional multi-finger
layout are measured from two devices consuming equal die areas.
The RW layout offers a better packing density than the MF layout as long as the
spacing between the gates, gateS exceeds the gate length, gateL . Almost all power
MOSFET layout structures meet this requirement. For example, the layout rules specify a
minimum drawn gate length of 2m, a minimum contact width of 1m, and a minimum
spacing poly-to-contact of 1.5m. Using these rules, Eq.2.11 indicates that the waffle
transistor provides approximately 33% higher transconductance than the conventional
multi-finger transistor. By allowing the source/drain area to be shared by more poly-
silicon gates, the waffle layout minimizes the active area, leading to smaller junction
capacitance. A small parasitic capacitance has not only a beneficial effect on the speed
requirement, but also on the power consumption of the chip, which is one of the key
issues in integrated design nowadays. In addition, the characteristic (i.e. compactness) of
the waffle layout leads to the reduction of thermal noise because the gate resistance is
also decreased.
-
24
However, the waffle-type transistor has three crucial deficiencies. First, due to the
restriction of minimum CMOS design rules (e.g. minimum metal width and spacing) of
the first metallization level, the source/drain diffusion area should be larger than the
minimum dimension to accommodate the metal lines connecting the source/drain regions
through the contacts. The metallization invariably contributes a significant portion of the
Ron of the transistor, and in more recent CMOS process technology nodes, it often
becomes the dominant factor. If one assumes that the metallization contributes about half
the total Ron, then the improvement gained by using the waffle layout drops by half, or
from 33% to 16% for the previous example.
The situation is actually even worse, because the waffle layout is difficult to properly
route the metal layers. The metal-1 layer stripes must repeatedly cross the gate poly and
this introduces a significant step-induced metal thinning [44]. Second, the waffle
transistor contains a large number of bends in its channels. These bends produce sharp
corners in the source/drain regions that avalanche at lower voltages than the remaining
parts of the transistors. Such a localized avalanche limits the amount of energy in which
the waffle transistor can dissipate. This limitation becomes more apparent in high voltage
power applications. Third, the waffle layout structure makes no provision for backgate
contacts (e.g. p+ substrate contact or n+ contact for n-well). Unless the transistor is used
in combination with a heavily doped substrate or a buried layer to provide a substrate or
well contact, it is quite susceptible to de-biasing and latch-up issues. In Chapter 3, a new
waffle-type layout structure, named hybrid-waffle will be introduced. This new layout
strategy will provide a breakthrough to overcome those disadvantages of the conventional
waffle layout, described in this section.
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25
2.4 Super-Junction (SJ) Power MOSFETs
A new device concept called Super-Junction (SJ) [11] was introduced about a decade
ago, to improve the trade-off relationship between the breakdown voltage and the specific
on-resistance in medium to high voltage devices. The SJ concept was first applied and
commercialized to vertical structures [45-48]. In the next sub-sections, the basic SJ
structure and its operating principle are reviewed and the current status of SJ vertical
power MOSFETs is briefly discussed followed by the status of fabrication technologies
and challenges.
2.4.1 Device Concept and Characteristics
Vertical superjunction DMOSFETs were introduced commercially and achieved a
significant improvement in the trade-off between Ron,sp and BV over conventional
VDMOSFETs. Vertical SJ devices such as COOLMOSTM
[49] and MDmeshTM
[50]
assume complete charge balance of the depletion layer. This can be achieved by
introducing alternating n- and p-pillars in the drift region, which allows drastically
increasing the doping in this region. Even though the current conduction area is reduced
by additional p-pillars, a significant reduction in Ron,sp of the devices is achieved by using
heavy doping concentrations in the n-pillar.
Fig. 2.13 shows a cross-section of a SJ-DMOSFET, which has a concept similar to a
multi-RESURF idea (refer to the section 2.2.2). The SJ-structure allows a doping level of
the n-drift region, which is typically one order of magnitude higher than that those in
standard high-voltage MOSFETs. The additional charge is counterbalanced by the
adjacent charges of the p-pillar, thus contributing to a horizontal electrical field without
affecting the vertical field distribution. The electric field inside the structure is fixed by
the net charge of the two oppositely doped pillars. As a result, a nearly flat electric field
distribution can be achieved when both regions counterbalance each other perfectly.
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26
Fig. 2.13 Cross-section of a SJ-DMOSFET
For a higher blocking voltage, only the depth of the pillar has to be increased without
any changes of the doping. Considering the drift region of a SJ-DMOSFET has a length
Ld, the p-/n- pillar widths are WP = WN = WPN, and the corresponding doping
concentrations are NA and ND, respectively, and assuming that the both pillars are
completely depleted before breakdown with a perfect charge balanced condition, the BV
and the charge Q of the pillar are given by [51]:
dC LEBV (Eq.2.12)
q
CsiPND E
2
WNQ
(Eq.2.13)
where the critical electric field, Ec is also increased by the increased doping concentration
of the pillar.
W
P
P-body
Gate
Drain
Source
N+
N+
tepi W
N
P-drift pillar N-drift
pillar
Ld
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27
Because the current flows only through the n-pillar, the specific on-resistance can be
expressed as [51]:
2Csin
PN
Dn
dsp on,
E 2
BVW
N q
LR
(Eq.2.14)
This equation clearly shows the linear relationship between the BV and the specific on-
resistance of SJ-DMOSFETs instead of the power relationship for the case of
conventional power MOSFETs. To achieve the best performance in the SJ structure,
precisely charge balanced p- /n- pillars must be formed at exactly the same doping level
to have equal amount of positive and negative charges. By carefully choosing the suitable
pillar width, doping concentration and drift region depth, the SJ device can substantially
outperform over the conventional power MOSFETs, especially in the medium to high
voltage ranges.
2.4.2 Current Status and Challenges of SJ Power MOSFETs
Several fabrication technologies have been implemented to realize SJ power
MOSFETs. The technologies and issues are briefly discussed in the following sections.
Multi-epitaxy technology [52-55]
This is the first technology used to fabricate the SJ device (i.e. COOLMOSTM
). The
devices were manufactured by multiple depositions of epitaxial layers and subsequent
boron and phosphorus implant process steps on a highly doped n+ substrate. The
diffusion process was followed to form vertically alternating n-/p- pillars. This is still
only available technology to fabricate the commercialized SJ power MOSFETs. Similar
to other SJ devices, it is quite difficult to achieve a perfect charge balance in the n-/p-
pillars. Any charge imbalance causes a degradation of the breakdown voltage. The
sensitivity of the BV to the charge imbalance is another difficulty in current
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28
manufacturing environment. The multi-depositions of epitaxial layers are not compatible
with a standard CMOS process technology.
Deep Trench Etching with Vapor Phase Doping [56-58]
In this method, an n-type epitaxial layer was first grown on n+ substrates. After B+
ion implantation, a hexagonal trench was etched all the way down to the bottom of the
substrate and then boron is diffused into the sidewalls of the trench by using a Vapor
Phase Doping (VPD) process. A subsequent thermal annealing was required to drive-in
the boron impurities. The trenches were first deposited by thin dry oxide liners and then
gap-filled by TEOS deposition. Uniformity of p-pillar region formed by VPD process is
one of main processing issues. Also, the half of current conduction area in the drift region
is wasted by the TEOS gap-filling step.
Poly-Si Flanked VDMOS [59]
In this method, a thin thermal oxide liner was added between the n-/p- pillars as an
inter-diffusion barrier. Deep trenches were formed by etching n-epitaxial layer on the n+
substrate and then the thin oxide liner was grown inside the trenches. They were then
gap-filled with p-type polysilicon and then planarized by CMP process. Main issue
within this technology is that the quality of p-pillar region is even worse than the
epitaxial growth method. The polysilicon has a relatively high defect density in
comparison with a single crystalline Si-substrate or epitaxial layer. High temperature
annealing steps may reduce the defect densities (throughout the grain growth); however
the high thermal budget would result in the dopant redistribution. Also, it induces a stress
from various interfaces between the substrate and other deposited layers.
Deep Trench Etching and Selective Epitaxial Growth [60-62]
Similar to the deep trench etching with VPD process, the deep trenches were first
formed on the n-type epi wafer and then the trenches were filled by a selective epitaxial
growth (SEG) technique (e.g. p-type epi. silicon). The device was further improved with
-
29
the SEG process using chlorine source gases for filling the high aspect ratio trenches
without voids. Boron implantation was also used to reduce the leakage current and
improve the avalanche characteristics. It is noted that the SEG process step is currently
not compatible with a standard CMOS process technology. High off-state leakage current
and soft breakdown effects were observed for devices fabricated using this technique.
Fig. 2.14 demonstrates the BV-Ron,sp trade-off relationships of conventional power
MOSFETs in comparison with up-to-date SJ power MOSFETs fabricated in different
device technologies. Except for those data specified for lateral SJ structure, all the other
SJ devices have a vertical DMOS structure. According to this figure, the SJ power
MOSFETs are limited to a medium voltage rating (e.g. > 100V). This is due to the fact
that the channel resistance becomes comparable to the drift region resistance at low
voltage ratings. In Chapter 4 and 5, a CMOS-compatible low voltage lateral SJ structure
will be introduced and discussed to resolve the issue.
Fig. 2.14 Ron,sp versus BV for different power device technologies [62-70].
0.01
0.1
1
10
100
10 100 1000
Breakdown Voltage (V)
Sp
ecif
ic O
n-r
esis
tan
ce (
m
cm
2 )
LDMOS
LDMOS-SOILDMOS-SJ
VDMOSVDMOS-SJ
Si-limit
Low Voltage
-
30
Chapter 3 Analytical Layout Modeling of Power MOSFET
3.1 Analysis of Basic MOS Finger Structure
Prior to detailed analysis and discussion of the proposed new CMOS layout structure,
it is more appropriate to review and analyze a finger of MOS layout structure since
almost all CMOS layout structures consist of several to millions of a unit MOS finger
transistor. Fig. 3.1 represents a basic MOS finger layout with interconnect resistive
components. However, for more precise simulation analysis; each transistor finger is
partitioned into several small unit transistors with one contact for each source/drain, as
illustrated in Fig. 3.1.
Fig. 3.1 A basic MOS finger layout with simple interconnect resistive components.
Several different circuit simulations have been performed by using this simple
resistance model for a better understanding of the effects of parasitic interconnect
resistances in CMOS layout structures. First, the contribution of parasitic interconnect
resistances, Rparasitic in a finger MOS layout with two different metal-1 widths has been
simulated by using TSMCs 0.25m CMOS HSPICE model (see Fig. 3.2). As the finger
length (or gate channel width) increases, both channel resistance and on-resistance
decrease initially. However, after a certain value of the finger length, the on-resistance
starts to increase gradually. This indicates that the interconnect resistance starts to
Rc
Rm1 Rg
Drain
Source Gate
Source
Drain
Gate Poly
Contact
Metal-1
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31
dominate the total on-resistance. The difference between intrinsic channel resistance and
total on-resistance corresponds to the parasitic interconnect resistance. For longer finger
lengths, this difference is even more pronounced.
Fig. 3.2 (a) Two different MOS finger layouts with min. and max. metal-1 widths,
(b) Simulation results of Rchannel, Ron, and Rparasitic for (a).
In addition, the on-resistance models for different numbers of multi-finger layouts
have been studied and the simulation results are given in Fig. 3.3. By increasing the
numbers of MOS layout fingers, both smaller values of Ron and Ron,sp have been observed.
Theoretically, the on-resistance for the same device width is constant; however, this
different observation can be understood that higher number of MOS fingers for the
similar device size leads to the smaller parasitic interconnection resistance. This explains
1
10
100
1000
0 100 200 300 400 500 600 700 800 900 1000 1100 1200 1300
Finger Length, W (m)
Ro
n (
)
Ron @ min. M-1 w idth Rpar @ min. M-1 w idth
Ron @ max. M-1 w idth Rpar @ max. M-1 w idth
Rchannel
Ron
Rparasitic
(a)
(b)
Rparasitic
Vs.
Min. M-1 Width: 0.32m Max. M-1 Width: 1.02m
S
D
S
D
W W
-
32
why many layout designers do not always use the maximum finger length allowed in the
design rule. It is also interesting to note that a smaller technology node of standard
CMOS process provides the smaller on-resistance characteristics for the same device size.
Advanced CMOS technologies have more metal layers and this allows a greater reduction
in parasitic interconnect resistance.
Fig. 3.3 (a) Ron and (b) Ron,sp vs. Wtotal for different numbers of MOS fingers.
0
5
10
15
20
25
30
35
40
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Total Finger Length, Wtotal (m)
Ro
n,s
p (m
m
m2)
Ref[48] (0.8um)
1 finger (TSMC 0.25um)
3 fingers (TSMC 0.25um)
10 fingers (TSMC 0.25um)
20 fingers (TSMC 0.25um)Ref. 0.8m CMOS [71]
1 finger 3 fingers 10 fingers
20 fingers
(b) [71]
1
10
100
1000
0 200 400 600 800 1000 1200 1400 1600 1800 2000
Total Finger Length, W total (m)
Ro
n (
)
Ref [48] (0.8um)
1 finger (TSMC 0.25um)
3 fingers (TSMC 0.25um)
10 fingers (TSMC 0.25um)
20 fingers (TSMC 0.25um)
Ref. 0.8m CMOS [71]
1 finger
3 fingers
10 fingers
20 fingers
(a) [71]
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33
3.2 Modeling of Conventional Multi-Finger (MF) Layout
As described earlier in section 2.3.2, multi-finger layout schemes of CMOS power
ICs are still widely used in many cost-sensitive applications including mobile DC-DC
converts. Although there are many different types of multi-finger layout structures
reported in the literature [17-19], one of the most common MF layout structures as
illustrated in Fig. 3.4 is studied. In order to extract the precise total on-resistance and gate
charge of a device. The MF layout structure with all possible interconnect resistive
components are investigated. A 0.25m standard CMOS process is used to implement the
output stage design. A total of 5 metallization layers with contacts/vias were considered
in the HSPICE circuit modeling. Detailed calculations method and schematic model are
described in the next paragraph.
Fig. 3.4 Conventional MF layout structure with parasitic resistors.
Gate Source: M1
Source
Drain
Gate Poly
Contact
Metal-1
Source: M1
Drain: M1
Gate: Poly
JSOURCEJDRAINSi-Sub
Gate Source: M1
Source
Drain
Gate Poly
Contact
Metal-1
Source