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Verification using Satisfiability Checking, Predicate Abstraction, and Craig Interpolation Himanshu Jain THESIS ORAL TALK

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Page 1: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

Verification using Satisfiability Checking, Predicate Abstraction,

and Craig Interpolation

Himanshu JainTHESIS ORAL TALK

Page 2: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

1

Computer Systems are Pervasive

Computer Systems = Software + Hardware

Software/Hardware Bugs are common as well!

Page 3: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

2

Building Reliable Computer Systems

Testing

Programming Languages

Static Analysis

Model Checking

Theorem Proving

Need for more automatic, scalable, precise verification tools

Abstract Interpretation

Static Analysis

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Decision Procedures

Reasoning engines in verification tools

Satisfiable

Formula

Satisfiable

Unsatisfiable

Example: Boolean Satisfiability (SAT) Solvers

Page 5: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

4

Decision Procedures++

Reasoning engines in verification tools

Satisfiable

Formula

Satisfiable

Unsatisfiable

Example: Boolean Satisfiability (SAT) Solvers

(Craig Interpolants)

Page 6: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

5

Contributions of this thesis

Fast Non-clausal Boolean Satisfiability (SAT) Solvers- Based on Negation Normal Form (NNF), hpgraph, vpgraph- DPLL based algorithm - General Matings based algorithm

Efficient Craig Interpolation for Subsets of IntegerLinear Arithmetic - Integer linear equations, congruences, disequations

Verifying Hardware at Register Transfer Level (RTL)- Model checking RTL Verilog using Predicate Abstraction and Counterexample Guided Abstraction Refinement Loop

Page 7: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

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Contributions of this thesis

Fast Non-clausal Boolean Satisfiability (SAT) Solvers- Based on Negation Normal Form (NNF), hpgraph, vpgraph- DPLL based algorithm - General Matings based algorithm

Efficient Craig Interpolation for Subsets of IntegerLinear Arithmetic - Integer linear equations, congruences, disequations

Verifying Hardware at Register Transfer Level (RTL)- Model checking RTL Verilog using Predicate Abstraction and Counterexample Guided Abstraction Refinement Loop

Page 8: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

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Outline

�Motivation

� Fast Boolean Satisfiability (SAT) Solvers� DPLL Algorithm� Related work� Related work�Negation Normal Form, hpgraph, vpgraph� SAT solving using hpgraph, vpgraph

� Interpolation for Subsets of Integer Linear Arithmetic� An application

� Summary

Page 9: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

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� Applications in verification�Model checking�Equivalence checking�Theorem proving�Test generation

Boolean Satisfiability

∧∧∧∧

∨∨∨∨

output

∨∨∨∨ �Test generation�Static analysis

� Circuits in practice�Thousands of inputs�Millions of gates �Structure sharingBoolean Circuit

∨∨∨∨

a b ¬¬¬¬a ¬¬¬¬b ¬¬¬¬a b

∨∨∨∨

∧∧∧∧ ∧∧∧∧ ∧∧∧∧

Page 10: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

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Davis-Putnam-Logemann-Loveland (DPLL) Algorithm

Input: Boolean Formula φφφφ(x, y, z, ….)Find a satisfying assignment to φφφφ by building a decision tree

0 1 A decision treex

0 1 0 1

�� ��

��

�� Satisfying assignment

No need to explore

Conflicts

y z

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Most solvers apply DPLL on CNF

z

¬¬¬¬z ∨∨∨∨ u

¬¬¬¬z ∨∨∨∨ v

z ∨∨∨∨ ¬¬¬¬u ∨∨∨∨ ¬¬¬¬v

z = u ∧∧∧∧ v

Clausal solvers: RSAT, PicoSat, MiniSat, BerkMin, zChaff, GRASP, …..

∧∧∧∧

∨∨∨∨

output

∨∨∨∨

v

z

uz ∨∨∨∨ ¬¬¬¬u ∨∨∨∨ ¬¬¬¬v

¬¬¬¬u ∨∨∨∨ x ∨∨∨∨ y

u ∨∨∨∨ ¬¬¬¬x

u ∨∨∨∨ ¬¬¬¬y

……….

u = x ∨∨∨∨ y

Conjunctive Normal Form (CNF)

New variables introduced is proportional to number of gates

Boolean Circuit

∨∨∨∨

a b ¬¬¬¬a ¬¬¬¬b ¬¬¬¬a b

∨∨∨∨

∧∧∧∧ ∧∧∧∧ ∧∧∧∧

x y z

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Current SAT solvers

� Davis-Putnam-Logemann-Loveland (DPLL) algorithm� Conversion of circuit to CNF

�Number of variables proportional to number of gates� Can be 103-104 times more than the number of inputs in a circuit� Can be 103-104 times more than the number of inputs in a circuit� Slowdown due to large number of new variables (and clauses)

�Modern CNF solvers use pre-processing techniques� To reduce #variables and #clauses in CNF� But pre-processing has large memory requirements

Page 13: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

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Our SAT solving framework

Boolean Circuit

Negation Normal Form Fewer variables

Requires introductionof new variables

hpgraph vpgraph

Negation Normal Form Fewer variablesthan CNF and more structure

DPLL algorithm

General Matingsalgorithm

Page 14: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

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Negation Normal Form (NNF)

∧∧∧∧

∨∨∨∨ ∨∨∨∨ ∧∧∧∧

∨∨∨∨

¬¬¬¬y

∨∨∨∨

a b y

∧∧∧∧

An NNF formula contains arbitrary

nesting of AND (∧∧∧∧) and OR (∨∨∨∨) gates

- Negations can appear at leaf level - No sharing of sub formulas

∧∧∧∧ ∧∧∧∧

a b

¬¬¬¬a ¬¬¬¬b

¬¬¬¬a b

y y

Page 15: THESIS ORAL TALK - Carnegie Mellon School of Computer …hjain/papers/thesis-oral-final.pdf · Verifying Hardware at Register Transfer Level ... a b y ∧∧∧ An NNF formula contains

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How to obtain NNF from Boolean Circuits

∧∧∧∧

∧∧∧∧

∨∨∨∨ ∨∨∨∨

∧∧∧∧ ∧∧∧∧ ∧∧∧∧

Circuit from converted to NNF byintroducing one new variable y to

remove sharing

out

out

out’

∧∧∧∧

∨∨∨∨ ∨∨∨∨

∧∧∧∧

a b

¬¬¬¬a ¬¬¬¬b

¬¬¬¬a b

y y

∨∨∨∨

¬¬¬¬y

∨∨∨∨

a b y

a b ¬¬¬¬a ¬¬¬¬b ¬¬¬¬a b

Boolean Circuit

NNF

out

∧∧∧∧

∧∧∧∧

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Satisfiability Checking of NNF Formulas

∧∧∧∧

∨∨∨∨ ∨∨∨∨ ∧∧∧∧

∨∨∨∨

¬¬¬¬

∨∨∨∨

a b y

∧∧∧∧

∨∨∨∨ ∨∨∨∨

∧∧∧∧

∧∧∧∧

∧∧∧∧

a b

¬¬¬¬a ¬¬¬¬b

¬¬¬¬a b

y y

¬¬¬¬y a b y

Our SAT algorithms will not add any more new variables

Variables = {a, b, y}

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Why NNF: Number of variables

CNF withoutpre-processinghas 5-10X more variables

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Why NNF: Number of variables

428 points

1705 points

Note no pre-processing for NNF

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Our SAT solving framework

Boolean Circuit

Negation Normal Form

��Peter Andrew’s

hpgraph vpgraph

Negation Normal Form

DPLL algorithm

General Matingsalgorithm

Peter Andrew’s

Horizontal/Vertical

Path Forms (1981)

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Inductively creating hpgraph(φ) from NNF formula φ

φ is a literal m mCreate new node

φ = φ1 ∧∧∧∧ φ2

hpgraph(φ1)R1 L1φ = φ1 ∧∧∧∧ φ2

hpgraph(φ2)R2 L2

Take graph union

φ = φ1 ∨∨∨∨ φ2hpgraph(φ1)R1 L

1

hpgraph(φ2)R2 L2

Add hyperedge from L1 to R2

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φ is a literal m m

φ = φ1 ∧∧∧∧ φ2

Create new node

Add hyperedge

Just interchange the handling of ∧∧∧∧ and ∨∨∨∨

vpgraph(φ1)

R1

L1

Inductively creating vpgraph(φ) from NNF formula φ

φ = φ1 ∧∧∧∧ φ2

φ = φ1 ∨∨∨∨ φ2Take graph

union

Add hyperedge

from L1 to R2

vpgraph(φ2)

R2

L2

vpgraph(φ1)

R1

L1

vpgraph(φ2)

R2

L2

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Formula

p p

p ∨∨∨∨ q p q

Hpgraph Vpgraph

p q

(p ∨∨∨∨ q) ∧∧∧∧ ¬¬¬¬r p q p q

p

(p ∨∨∨∨ q) ∧∧∧∧ ¬¬¬¬r

¬r ¬r

(p ∨∨∨∨ q) ∧∧∧∧ ¬¬¬¬r ∧∧∧∧ ¬¬¬¬q

p q

¬r

¬q

p q

¬r

¬q

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¬p

ExampleFormula F: (((p ∨∨∨∨ q) ∧∧∧∧ ¬¬¬¬r ∧∧∧∧ ¬¬¬¬q) ∨∨∨∨ (¬¬¬¬p ∧∧∧∧ (r ∨∨∨∨ ¬¬¬¬s) ∧∧∧∧ q))

p ∨∨∨∨ q ∨∨∨∨ ¬¬¬¬pp ∨∨∨∨ q ∨∨∨∨ r ∨∨∨∨ ¬¬¬¬sp ∨∨∨∨ q ∨∨∨∨ q¬¬¬¬r ∨∨∨∨ ¬¬¬¬p

horizontal path

p q

r ¬s¬r

¬p

¬q q

hpgraph(F)

R

R

R

L

L

L

R denotes a root node and L denotes a leaf node

¬¬¬¬r ∨∨∨∨ ¬¬¬¬p¬¬¬¬r ∨∨∨∨ r ∨∨∨∨ ¬¬¬¬s¬¬¬¬r ∨∨∨∨ q¬¬¬¬q ∨∨∨∨ ¬¬¬¬p¬¬¬¬q ∨∨∨∨ r ∨∨∨∨ ¬¬¬¬s¬¬¬¬q ∨∨∨∨ q

CNF(F)

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ExampleFormula F: (((p ∨∨∨∨ q) ∧∧∧∧ ¬¬¬¬r ∧∧∧∧ ¬¬¬¬q) ∨∨∨∨ (¬¬¬¬p ∧∧∧∧ (r ∨∨∨∨ ¬¬¬¬s) ∧∧∧∧ q))

p q ¬p

R R R

vertical path

p q

¬r

¬q q

¬p

r ¬s

vpgraph(F)

L L

R denotes a root node and L denotes a leaf node

p ∧∧∧∧ ¬¬¬¬r ∧∧∧∧ ¬¬¬¬qq ∧∧∧∧ ¬¬¬¬r ∧∧∧∧ ¬¬¬¬q¬¬¬¬p ∧∧∧∧ r ∧∧∧∧ q¬¬¬¬p ∧∧∧∧ ¬¬¬¬s ∧∧∧∧ q

DNF(F)

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Representing NNF using Graphs

� Represent NNF formula φ in form of two graphs

� hpgraph(φφφφ)� Implicitly encodes all clauses present in CNF(φ)

vpgraph(φφφφ)� vpgraph(φφφφ)� Implicitly encodes all cubes/terms present in DNF(φ)

� Directed acyclic graphs, linear in the size of φ

� Horizontal/Vertical Path Forms [P. Andrews 1981]� Used in higher order theorem proving (General Matings)�Not been explored for building fast SAT solvers

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Our SAT solving framework

Boolean Circuit

Negation Normal Form

��

hpgraph vpgraph

Negation Normal Form

DPLL algorithm

General Matingsalgorithm

��

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DPLL SAT solver

Boolean Constraint Propagation (BCP)

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Boolean Constraint Propagation (BCP)

� Given a partial assignment σ to variables in a formula φ

� BCP determines if σ falsifies φ (termed as conflict)

� Otherwise, BCP provides implied assignments (literals) due to σ

CNF example:(a ∨∨∨∨ b ∨∨∨∨ c) ∧∧∧∧

(¬a ∨∨∨∨ ¬b) ∧∧∧∧

(¬c ∨∨∨∨ ¬a)

BCP detects a conflict when σ :={a=1, c=1).

For σ := {a=1} BCP detects{c=0,b=0} as implied literals

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Efficient BCP in CNF SAT solvers

Two watched literal scheme [zChaff 2001]

Clause C: l ∨∨∨∨ l ∨∨∨∨ l ∨∨∨∨ l ∨∨∨∨ l ∨∨∨∨ …. ∨∨∨∨ l ∨∨∨∨ …Clause C: l1 ∨∨∨∨ l2 ∨∨∨∨ l3 ∨∨∨∨ l4 ∨∨∨∨ l5 ∨∨∨∨ …. ∨∨∨∨ l100 ∨∨∨∨ …

**

C is examined during BCP only when one of watches (l2 or l5) becomes false

watch 1 watch 2**

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DPLL on hpgraph

hpgraph

Decisions

Top-levelhpgraph

BCP engine

Top-levelDPLLAlgorithm

Conflicts,Implied Literals

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¬¬¬¬p

Meaning of BCP on hpgraph

p q L

Assignment σ1 :={r=1,p=1}

p q ¬p

Assignment σ2 :={q=1,s=1}

¬¬¬¬r r ¬s

¬q q

Conflict clause: ¬¬¬¬r ∨∨∨∨ ¬¬¬¬p

R

horizontal path = clause

¬q

r ¬¬¬¬s¬r

q

Unit clause: ¬¬¬¬q ∨∨∨∨ r ∨∨∨∨ ¬¬¬¬s

Implied literal: r

R

L

A horizontal

path

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Can we generalize the CNF watched literal scheme?

p q

r ¬s¬r

¬pR

R

L

L

Hpgraph

Horizontal path

- Watch two literals (nodes) on each clause (path)- But exponential number of clauses (paths)!

r ¬s¬r

¬q q

R

R

L

L

Horizontal path =

clause

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Two Watched Cut Scheme

Hpgraph

p q

r ¬s¬r

¬pR

R

L

L¬¬¬¬q ∨∨∨∨ r ∨∨∨∨ ¬¬¬¬sr ¬s¬r

¬q q

R

R

L

L

1. A node cut disconnects all horizontal paths2. Watch two node cuts (allows observing two literals on each clause)3. Minimal cuts (covered later)

cut 1 cut 2

watch a node cutp ∨∨∨∨ q ∨∨∨∨ r ∨∨∨∨ ¬¬¬¬s

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Actual picture….An hpgraph

1. Two cuts for each hpgraph component

2. Can be updated locally during BCP

hpgraphcomponents 3. Non-chronological

backtracking is cheap

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Our algorithm generalizes CNF watched literal scheme

An hpgraph Special hpgraph (CNF)

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Acceptable cut

p q

r ¬s¬r

¬pR

R

L

L

A cut is acceptable if no literal appearing in it is false

Cut 2 is:

not acceptable for

Cut 1 is:

acceptable forr ¬s¬r

¬q q

R

R

L

L

cut 1 cut 2

not acceptable forσ:= {p=1}

acceptable forσ:= {p=1}

Now let us see the use of cuts during BCP

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BCP Case 1: Both cuts are acceptable and disjoint

Hpgraph component

p q

r ¬s¬r

¬pR

R

L

Lσ := {s=1}

r ¬s¬r

¬q q

R

R

L

L

cut 1 cut 2

No need to examine the hpgraph component

σ := {s=1}

Intuitively, there will be no conflicts or implied literals

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BCP Case 2 (conflict): No acceptable cut

Hpgraph component

p q

r ¬s¬r

¬pR

R

L

Lσ := {p=1,q=1}

Conflict clause:

¬¬¬¬q ∨∨∨∨ ¬¬¬¬p

r ¬s¬r

¬q q

R

R

L

L

cut 1 cut 2

σ := {p=1,q=1}

An hpgraph has no acceptable cut if and only if currentassignment falsifies the formula

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38BCP Case 3 (Implications): Acceptable cuts but not disjoint

Hpgraph component

p q

r ¬s¬r

¬p

cut 1

For σ := {p=1} we can find two acceptable cuts.

We cannot findtwo completely

r ¬s¬r

¬q q

cut 1

cut 2

We cannot findtwo completely node-disjoint cuts

Intuitively nodes common to both cuts contain implied literals

In our example ¬¬¬¬r and ¬¬¬¬q are implied literals.

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BCP Case 3 (Implications): Acceptable cuts but not disjoint

Hpgraph component

p q

r ¬s¬r

¬p

r ¬s¬r

¬q q

σ := {p=1}

¬¬¬¬r is implied due to unit clause ¬¬¬¬r ∨∨∨∨ ¬¬¬¬p

¬¬¬¬q is implied due to unit clause ¬¬¬¬q ∨∨∨∨ ¬¬¬¬p

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Finding and Maintaining Minimal Cuts

p q

r ¬s¬r

¬pR

R

L

L

1 2 3

4 5 6

hpgraph component

p q

¬r

¬p

r ¬s

R R R

1 2 3

4 5 6

vpgraph component

r ¬s¬r

¬q q

R

R

L

L

minimal cut in hpgraph component =a path in vpgraph component

7 8

¬r

¬q q

r ¬s

L L

4 5 6

7 8

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Finding and Maintaining Minimal Cuts

p q

r ¬s¬r

¬pR

R

L

L

1 2 3

4 5 6

hpgraph component

p q

¬r

¬p

r ¬s

R R R

1 2 3

4 5 6

vpgraph component

r ¬s¬r

¬q q

R

R

L

L

7 8

¬r

¬q q

r ¬s

L L

4 5 6

7 8

Depth first search for an acceptablepath in vpgraph gives us an acceptable cut in hpgraph…

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Overall SolverBoolean Circuit

Negation Normal Form

1. Other features of modern SAT solvers

2. No pre-processing so far (circuit rewriting applicable)

Generalized watched literal scheme

Linear time

vpgraph hpgraph

Clause Database

BCP engine Conflicts,

Implied Literals

Decisions

Top-levelDPLLAlgorithm

Generalized watched literal scheme

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Experimental snapshot

� These techniques implemented in:�NFLSAT (Non-clausal FormuLas SATisfiability checker)

� ~2500 non-clausal circuit formulas (industrial category) � Bounded model checking, k-induction, SW/HW verification� Bounded model checking, k-induction, SW/HW verification� CNF obtained by adding new variables

� Comparing with state-of-the-art solvers� SAT-Race 2008 top two winners: MiniSAT++, Picoaigersat� Top three winners of SAT 2007 comp: RSAT, MiniSAT, PicoSAT� Using the competition binaries or latest source code

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Comparison with SAT 2007 winners

Solver Solved Failed Solved time

Total time

NFLSAT 2364 178 29753 131153

RSAT 2310 231 45794 184394RSAT 2310 231 45794 184394

PicoSAT 2281 260 43298 199298

MiniSAT2 2272 269 50958 212358

MiniSAT2070721

2270 271 39490 202089

Timeout 600 seconds per problem. Total 2541 problems.

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NFLSAT vs. RSAT

NFLSAT solves 54more problems

RSAT uses pre-processing

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NFLSAT vs. PicoSAT

NFLSAT solves 83more problems

PicoSAT does not use pre-processing

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NFLSAT vs. MiniSAT2 070721

NFLSAT solves 94more problems

MiniSAT2 070721 uses pre-processing

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Comparison SAT-Race 2008 winners And Inverter Graph (AIG) Track

Solver Solved Failed Solved time

Total time

NFLSAT 2060 132 26585 105785

MiniSAT++ 2074 118 32457 103257

PicoaigerSAT 2033 159 35892 131292

Timeout 600 seconds per problem. Total 2192 problems.

If we remove 350 SAT 2007 benchmarks, NFLSAT (8504 sec) is twice as faster than MiniSAT++ (18119 sec)

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NFLSAT vs. MiniSAT++

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NFLSAT vs. PicoaigerSAT

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Outline

�Motivation

� Fast Boolean Satisfiability (SAT) Solvers� DPLL Algorithm� Related work� Related work�Negation Normal Form, hpgraph, vpgraph� SAT solving using hpgraph, vpgraph

� Interpolation for Subsets of Integer Linear Arithmetic� An application

� Summary

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Decision Procedures++

Reasoning engines in verification tools

Satisfiable

Formula

Satisfiable

Unsatisfiable(Craig Interpolants)

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Interpolants [Craig 1957]

Given formulas F, G such that F ∧∧∧∧ G is unsatisfiable

An interpolant for (F,G) is a formula I:1. F ⇒ I2. I ∧∧∧∧ G is unsatisfiable2. I ∧∧∧∧ G is unsatisfiable3. I contains only common variables of F and G

I(y)F(x,y) G(y,z)

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Interpolants Example

Example 1 (propositional logic):

F := p ∧∧∧∧ q G := ¬q ∧∧∧∧ r ∧∧∧∧ s

I := q

Example 2 (linear arithmetic):

F := x + 2y ≤ 3 ∧∧∧∧ –x - y ≤ -1

G := y ≥ 3

F ⇒ y ≤ 2

I := y ≤ 2

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Interpolants in Verification [McMillan 2003]

Useful in symbolic model checking

Interpolant based image

Reach1(S)S

Computing Reach1(S) requires existential quantification (costly using BDDs or SAT)

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Interpolants in Verification [Jhala et al. 2004]

Useful for Property Directed Invariant Generation

Program PInvariants for

PredicateAbstraction

Predicates S

Invariants forP expressiblein terms of S

Interpolants help in finding right set of predicates

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How are Interpolants Obtained

F ∧∧∧∧ Gproof of

unsatisfiability

of F ∧∧∧∧ Gof F ∧∧∧∧ G

Interpolant for (F, G)

F, G

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Existing Work on Computing InterpolantsPudlak, McMillan, Jhala et al., Yorsh et al., Kapur et al.,

Rybalchenko et al., Kroening et al., Cimatti et al., Beyer et al.

�Can efficiently compute interpolants �For rational/real linear arithmetic

�For equality with uninterpreted function symbols �For equality with uninterpreted function symbols

�Propositional logic (using SAT solvers)

�No efficient interpolation algorithms for �Integer linear arithmetic

�Bit-vector arithmetic

�Decision problem for conjunctions is itself NP-hard

We make progress in this direction.

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Our results

�Polynomial time interpolation algorithms�For useful subsets of integer linear arithmetic

�Integer (Diophantine) linear equations�E.g. x = 3y ∧∧∧∧ 5x = 3z+u+2 ∧∧∧∧ … �E.g. x = 3y ∧∧∧∧ 5x = 3z+u+2 ∧∧∧∧ …

�Integer linear congruences (modular equations)�E.g. 4x = 2y + 9 (mod 3) ∧∧∧∧ 2z + 5x –y = 7 (mod 4) ∧∧∧∧ …

�Integer linear equations and disequations�E.g. ¬(4x + 5y = 8) ∧∧∧∧ x = 3y ∧∧∧∧ …

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Interpolation for Integer Linear Equations

�F, G be conjuctions of integer linear equations

�We show that interpolant for (F,G) is always:

�An integer linear equation or �An integer linear equation or

�An integer linear congruence

�F := (x = 2y) and G := (x=2z+1)

�An interpolant is x = 0 (mod 2)

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Interpolation Algorithm Step 1

Obtain a proof of unsatisfiability of F ∧∧∧∧ G

(How to get a contradiction from F ∧∧∧∧ G)

F := (30 x + 4y = 2)

1/5 F + 1/5 G is equal to 6x+y+z=4/5 (Contradiction)

F := (30 x + 4y = 2) G := ( y + 5z = 2)

[1/5, 1/5]

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F G

Interpolation Algorithm Step 2

Sum the equations from F according to the proof of unsatisfiability

F G

1/5 (30 x + 4y = 2) + 1/5 (y + 5z = 2)

6 x + 4/5 y = 2/5 Partial interpolant

We do not want x

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6 x + 4/5 y = 2/5

Interpolation Algorithm Step 3

Remove variables not common to F and G

4/5 y -2/5 = -6x⇒ 4/5 y – 2/5 is divisible by 6⇒ 4/5 y – 2/5 = 0 (mod 6)⇒ 4y-2=0 (mod 30)

4y - 2 = 0 (mod 30) is an interpolant for (F, G)We have proved the correctness of above algorithm

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Complexity of the Algorithm

�Obtain proof of unsatisfiability (step 1)�Polynomial time using Hermite Normal Form

�Overall algorithm is polynomial time

�Multiple interpolants can be obtained

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Multiple Interpolants

G := y+5z=2

F := 30x+4y=2

4y – 2 = 0 (mod 30)

4y – 2 = 0 (mod 15)

4y – 2 = 0 (mod 10)

4y – 2 = 0 (mod 5)

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Outline

�Motivation

� Fast Boolean Satisfiability (SAT) Solvers� DPLL Algorithm� Related work� Related work�Negation Normal Form, hpgraph, vpgraph� SAT solving using hpgraph, vpgraph

� Interpolation for Subsets of Integer Linear Arithmetic� An application

� Summary

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Predicate Discovery

void main(){int x=0, y=0;

while(*){

Loop invariant:

x+y is divisible by 4 That is, x+y=0 (mod 4){

x = x + 4*nondet();y = y + 8*nondet();

assert(x+y != 1);assert(x+y != 2);assert(x+y != 3);

}}

That is, x+y=0 (mod 4)

C program

Such predicates can be found using our interpolation algorithms

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Predicate Discovery Experiments

Example Predicates/Interpolants Time (secs)

ex1 y = 1 (mod 2) 2.72

ex2 x + y = 0 (mod 2) 0.83

Existing state-of-the-art tools such as BLAST, SATABS, VCEGAR cannot verify these programs.

With the help of predicates found byour algorithms they can (VCEGAR).

Existing state-of-the-art tools such as BLAST, SATABS, VCEGAR cannot verify these programs.

With the help of predicates found byour algorithms they can (VCEGAR).

ex2 x + y = 0 (mod 2) 0.83

ex4 x + y + z = 0 (mod 4) 0.95

ex5 x=0 (mod 4), y=0 (mod 4) 1.1

ex6 4x+2y+z = 0 (mod 8) 0.93

ex7 4x-2y+z = 0 (mod 222) 0.54

forb1 x + y = 0 (mod 3) 0.1

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Outline

�Motivation

� Fast Boolean Satisfiability (SAT) Solvers� DPLL Algorithm� Related work� Related work�Negation Normal Form, hpgraph, vpgraph� SAT solving using hpgraph, vpgraph

� Interpolation for Subsets of Integer Linear Arithmetic� An application

� Summary

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SummaryBoolean Circuit

Negation Normal Form

Non-Clausal SAT solver

vpgraph hpgraph

Clause Database

BCP engine

Top-levelDPLLAlgorithm

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Summary contd.

�Efficient Interpolation Algorithms�Integer linear equations

�Integer linear congruences

�Integer linear equations and disequations�Integer linear equations and disequations

�Proofs of unsatisfiability�Integer linear congruences

�Integer linear equations and disequations

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Thank you!

� Edmund Clarke� Exemplary advisor

� Randy Bryant, Aarti Gupta, Ken McMillan, Frank Pfenning� Excellent thesis committee members

� Peter Andrews�Math Logic classes and advice

� Daniel Kroening, Orna Grumberg, Constantinos Bartzis� Awesome collaborators

�NEC verification group for great summer internships

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Questions