three-dimensional reram with vertical bjt driver by cmos logic compatible process

2466 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 8, AUGUST 2011

Three-Dimensional 4F2 ReRAM With Vertical BJTDriver by CMOS Logic Compatible Process

Ching-Hua Wang, Yi-Hung Tsai, Kai-Chun Lin, Meng-Fan Chang, Member, IEEE, Ya-Chin King, Chrong Jung Lin,Shyh-Shyuan Sheu, Yu-Sheng Chen, Heng-Yuan Lee, Frederick T. Chen, and Ming-Jinn Tsai

Abstract—A new 3-D vertical bipolar junction transistor(BJT) resistive-switching memory (ReRAM) cell with compli-mentary metal–oxide–semiconductor-compatible process has beendemonstrated and characterized. A new logic-compatible BJTis vertically formed underneath the resistive stacked film ofTiN/Ti/HfO2/TiN as a high-performance current driver and bit–cell selector. Using a shallow and tiny N-type lightly doped drainto be an emitter connects with ReRAM film as the bitline, a verythin and self-aligned P-pocket implant layer to be the wordline,and the N-well is the collector of the cells. As a result, the new3-D ReRAM cell is very area saving and efficiently operated bythe high-gain (β > 50) BJT at a low voltage of 2 V for reset and1.5 V for set. By adapting the highly shrinkable 3-D BJT currentdriver in ReRAM, the ReRAM is fully decoupled with the gatelength and oxide thickness of logic metal–oxide–semiconductorfield-effect transistors; furthermore, it can easily be scaled downto 4F2 under the lithographic limitation of defining ReRAM filmwith F2 area.

Index Terms—Contact resistive RAM (CR-RAM), current biasmethod, high resistance state (HRS), low resistance state (LRS),NVM, set/reset current.

I. INTRODUCTION

CURRENTLY, resistive-switching random access memory(ReRAM) is attracting increasing interest as a potential

candidate for high-density nonvolatile memory. The ReRAMcell has become a public research area by its superior char-acteristics of high set/reset speed, low voltage operations, andremarkable reliability [1]–[17]. With the demand for massstorage and low power in many portable consumer products,ReRAM becomes a more promising candidate as the bestsolution for those issues. Due to the limitations of CMOSprocesses and planer structure of transistors, it is difficult toutilize conventional transistors to satisfy all the requirementsof low voltage operations, high scalability, and large currentdrivability with one single cell.

Manuscript received January 24, 2011; revised May 5, 2011; acceptedMay 5, 2011. Date of current version July 22, 2011. This work was supportedby the National Science Council of the Republic of China, Taiwan. The reviewof this paper was arranged by Editor V. R. Rao.

C.-H. Wang, Y.-H. Tsai, K.-C. Lin, M.-F. Chang, Y.-C. King, and C. J. Linare with the Microelectronics Laboratory, Institute of Electronics Engineering,National Tsing Hua University, Hsinchu 300, Taiwan.

S.-S. Sheu, Y.-S. Chen, H.-Y. Lee, F. T. Chen, and M.-J. Tsai are with theElectronics and Optoelectronics Research Laboratory, Industrial TechnologyResearch Institute, Hsinchu 31040, Taiwan.

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TED.2011.2157928

TABLE IOPERATION CONDITIONS FOR FORMING, SET, RESET, AND READ OF

THE MEMORY CELLS ARRANGED IN A NOR-TYPE ARRAY

In this paper, a new 3-D vertical bipolar junction transistor(BJT) ReRAM cell with pure CMOS compatible process ispresented and demonstrated. A very small 3-D n-p-n BJT isvertically formed just below the resistive stacked films of theReRAM cell for minimizing the Si surface area. By using ashallow and small-area N-type lightly doped drain (NLDD)implant as emitter for connecting the resistive stacked film ofTiN/Ti/HfO2/TiN to be the bitline (BL) and a very thin andself-aligned P-pocket implant to be the wordline (WL), thecollector is commonly formed by the N-well of the regular wellin CMOS logic processes. By adapting the ultrasmall and high-performance (β > 50) vertical BJT to be a ReRAM currentdriver, the cell is very efficiently working at low voltagesof 2 and 1.5 V for reset and set operations, as summarizedin Table I. Since the resistive film is placed on top of thehigh-gain vertical BJT in the 3-D structure, it made the newcell scalability and performance fully free to the conventionalMOSFET’s constraints, such as minimum logic gate lengthand oxide thickness. Because of the superior features, the new3-D ReRAM cell can easily be implemented in advancedCMOS logic platforms for ultrahigh density and very lowvoltage NVM applications.

In this paper, the manufacturing process and the layoutarrangement of NOR-type array are first introduced. Then, wewill describe the electrical characterization and analysis of1 BJT + 1 R cell with the new vertical structure. It also dis-cusses the subsequent BJT ReRAM operation principle and theoptimization of source line and WL voltages during setting andresetting operations. The main difference with MOSFET is theexisting WL current and how to use a series of operation con-ditions to prevent WL (base) leakage and avoid the subsequentreset disturb by unexpected p-n junction turn-ON. Therefore, themechanism and conditions of the unique read operation for 3-DBJT ReRAM are also proposed to solve the issue. Finally, thetemperature effect and the reliability performance of 3-D BJTReRAM are also addressed and characterized in this paper.

0018-9383/$26.00 © 2011 IEEE

WANG et al.: 3-D 4F2 RERAM WITH VERTICAL BJT DRIVER BY CMOS PROCESS 2467

Fig. 1. (a) BJT manufacturing process steps in CMOS logic process andstacked ReRAM film on top of emitter contact. The TEM graph of ReRAMis the stacked TiN/Ti/HfO2/TiN layers. (b) Three-dimensional structure of anew vertical n-p-n BJT vertically formed under ReRAM film for minimizingthe Si surface area.

II. FABRICATION AND EXPERIMENT

The 3-D ReRAM cell was fabricated by standard TaiwanSemiconductor Manufacturing Company 0.18-μm CMOS logicprocesses without additional process and masking step. To min-imize the ReRAM size, a layer of TiN/Ti/HfO2/TiN resistivestacked film is on-top deposited and aligned to the new verticalBJT for forming a 3-D cell structure. Fig. 1(a) exhibits thebrief manufacturing process of two connected BJT ReRAMcells in cross-sectional view. At first, the NLDD of the CMOStransistor was blanket implanted into an N-well region witha junction depth of 60 nm; simultaneously, a p-type pocketwas also implanted by the same masking step in the CMOSprocess with 30◦ tilt angle for forming a layer with a thicknessof 0.15 μm. The doping concentration of the NLDD is around5 × 1019 cm−3 and one order of magnitude higher than thatof the p-pocket implant. The P+ region was then implanted todefine the pick-up of base (WL) connection, which uses thesame process step of CMOS PMOS source/drain implant. Interms of the breakdown of the vertical cell, the emitter of thevertical BJT is formed by the layer of NLDD implant. TheP-pocket and the P+ implant are playing the roles of baseand WL in the vertical BJT. The light and deep collector isestablished by the common N-well. Considering the tilted angleof pocket implantation and the possible masking misalignmentin the ultrasmall cell area, the blanket-implanted NLDD andthe p-type pocket must be able to ensure that the base regionis effectively connected to the P-pickup; therefore, the emitterarea is designed to be defined by P+ implantation. Moreover, toavoid the spiking effect of silicidation in the shallow emitter, the

Fig. 2. (a) Three-dimensional ReRAM in NOR-type array arrangement withPMOS for WL and BL select transistor. (b) Schematic layout view of 3-DReRAM.

resistor–protection–oxide (RPO) layer for blocking the silicideformation is on purpose to be placed on the region of theemitter and the partial base. The layout of the RPO must notonly avoid the shallow emitter area damaged by the spiking ofsilicidation but also prevent the possible junction link betweenp-type base and n-type emitter via residual silicide metal. Afterall, the resistance film of TiN/Ti/HfO2/TiN [1]–[3] is verticallydeposited on top of the contact of the BJT emitter to completethe ReRAM cell process.

As illustrated in Fig. 1(b), the 3-D ReRAM structure issimplified as 1 BJT + 1 R, the base of the vertical BJT servesas WL, and the metal on the ReRAM resist film serves asBL. The common N-well serves as a common source line. The3-D ReRAM can significantly decrease the cell area due to thevertical high efficient BJT and the small on-top defined resistfilm. The diffusion WL is buried under the silicon surface,and its direction is crossing-over with the BL at the center ofemitter contact. Through the vertical BJT of the 3-D structure,the ReRAM cell is entirely decoupled with the logic transistorgate length and the gate oxide thickness; as a result, the cell caneasily be layout and scaled down beyond the planar MOSFETapproach.

According to the new 1 BJT + 1 R structure, we can arrangethe 3-D ReRAM cell in a NOR-type array, as shown in Fig. 2(a).Fig. 2(b) shows the schematic layout of a 2 × 2 ReRAMminiarray. In the layout description, the dimension of the resistfilm is patterned as an F unit, and the resist film spacing is


Fig. 3. DC characterization of 3-D ReRAM for set/reset and forming opera-tions. The plus sign of the BL current indicates the current in reverse direction(emitter to collector), and the minus sign indicates forward current (collector toemitter).

Fig. 4. Minimized HRS read current by (up) constant SL = 1.5 V, then variedWL voltage to observe the saturated voltage for resistance level, and (down)constant WL = 2 V, then varied SL voltage to observe the saturated voltage atreset operation by dc measurement.

scaled as F too. The ideal 3-D ReRAM unit cell size can beshrunk down to 4F2 based on the lithographic limitation of theresist film with F2 area.

III. OPERATION PRINCIPLE AND CHARACTERIZATION

Considering a NOR-type array, the operation conditions ofthe selected and unselected cells are summarized in Table I.To separate the bidirection operation during forming and setoperations, the current flowing from emitter to collector isdefined as the reverse direction. On the contrary, for reset andread operation, the current flowing from collector to emitter isdefined as forward direction. The BJT acts as a switch in thesaturation region in two directions. In the set operation, the BJToperates in the saturated region in the reverse direction, and inreset read operations, the BJT operates in the saturated regionin the forward direction. Fig. 3 shows the forming, set, and resetoperations, and the 3-D ReRAM can well be forming and set tolow resistance state (LRS) at low BL voltages of 2 and 1.5 V,respectively, which can be reset back to high resistance state(HRS) by applying a source line voltage of 1.5 V.

In addition, the dc voltage effect during set and reset op-erations is shown in Figs. 4 and 5. In Fig. 4, the BJT in theforward direction is operating at zero voltage on BL during thereset condition by varying the WL and source line voltages, and

Fig. 5. Maximized LRS read current by (up) constant BL = 1.5 V, then variedWL voltage to observe the saturated voltage for resistance level, and (down)constant and WL = 0.7 V, then varied BL voltage to observe the saturatedvoltage at set operation by dc measurement.

Fig. 6. Forward and reverse reads in both HRS and LRS by double dc sweep.The state switch occurs in the reverse read at BL voltage of about 0.9 V at HRS.

the optimized HRS read current can be obtained at SL = 1.5 Vand WL = 2 V. For the set operation, the optimized LRS readcurrent is at BL = 1.5 V and WL = 0.7 V, as expressed inFig. 5. According to the operation condition in Table I, theleakages through the unselected WL and BL under set operationare about 40 nA and 10 pA, respectively; the WL and the sourceline leakage under reset operation are about 10 pA and 1 nA,respectively. The power consumption with one cycle, includingset and reset operations with 50-ns pulse width in 1-M array, isabout 27 pW.

IV. READ OPTIMIZATION AND TEMPERATURE EFFECT

The read stability of HRS and LRS at forward and reverseread directions is characterized and shown in Fig. 6. The readdisturb only occurs at HRS in the reverse direction, so theforward direction of the read operation is chosen to avoidthe possible state change by reading disturb. In prior studies,MOSFET is used as selecting and driving transistor of ReRAMcells. For minimizing the channel resistance of the transistorduring the read operation, the WL needs to be applied up toVCC to reduce the voltage drop on the channel and increase theread current window. However, due to the specific BJT structureof 3-D ReRAM, the WL leakage needs to further be controlledin case that the base potential is higher than the emitter or col-lector. Furthermore, the WL leakage current flowing from base


Fig. 7. LRS/HRS current ratio characterization by a range of WL voltagesfrom 0.4 to 1 V. The higher WL voltage can minimize the resistance of BJT andgenerate better LRS/HRS current ratio.

Fig. 8. Reverse read disturb characterization for WL = 0.8 and 1.2 V in bothHRS and LRS. Long-term (1000 s) read operation stress, and the disturbanceoccurs in LRS at WL = 1.2 V.

to collector or emitter will result in an unexpected disturbanceagainst the existing stored states. To analyze and realize theconstraint of read operations, the LRS/HRS current ratio andthe read disturb window have been characterized by a rangeof WL voltages, as shown in Figs. 7 and 8. As a result, higherWL voltages will cause a larger read current window for theWL voltages ranging from 0.4 to 1 V, as revealed in Fig. 7.In addition, when the WL voltage becomes higher than 1.2 V,Fig. 8 clearly shows that read disturb subsequently occurs atLRS and creates some unexpected WL leakage flowing to theemitter from the base of the higher potential.

Furthermore, the temperature effect and the correlation ofBJT 3-D ReRAM are also characterized and discussed in termsof LRS and HRS. Fig. 9 shows the resistance variation of BJT3-D ReRAM cell among different temperatures for LRS. It wasfound that the read current is constantly increasing with risingtemperature in the range of WL voltages between 0.8 and 1 V,and the slope becomes a little flatter at higher WL voltagedue to the lower diffusion barrier between the base–emitterjunction. Since the resistances of both BJT and ReRAM arestrongly thermal correlative, as we know, the BJT has a positivecorrelation with temperature, and an observable decrease ofslope with increasing WL voltage can be explained by theReRAM negative temperature correlation. While in Fig. 10,the read current increases with higher temperature with theWL voltage range from 0.8 to 1 V at the slightly increased

Fig. 9. Read current of LRS in 1 BJT + 1 R structure with WL voltage of0.8, 0.9 and 1 V to observe the transistor resistance effect and varied withtemperature from 0 ∼ 100 ◦C.

Fig. 10. Read current of HRS in 1 BJT + 1 R structure with WL voltageof 0.8, 0.9 and 1 V to observe the transistor resistance effect and varied withtemperature from 0 ∼ 100 ◦C.

slope. This indicates that the ReRAM resistance is positivetemperature correlative in 1 BJT + 1 R cell at HRS.

V. RELIABILITY CHARACTERIZATION AND DISCUSSION

Regarding the disturb characterization, we used a NOR-typearray and architecture to be the example. When the unselectedBL or WL is kept to float, the unselected cells are fully immuneto WL disturb when the BL is open or immune to BL disturbwhen the WL is open. In Fig. 11, there is no window narrowingfound after 105 times of disturb cycles regardless of set andreset states. Moreover, an overwrite immunity study of 3-DReRAM is also shown in Fig. 12; it is initially setting theReRAM cell at LRS, and the data plainly reveal that LRS is verystable after the stresses of repeating setting pulses, and finally,the cell can be reset to HRS by a normal pulse completely. TheHRS overwrite is performed by the opposite sequence to againverify the stability, as shown in Fig. 12. As a result, since thereare no gate oxide or weak spots in the cell structure, the newBJT 3-D ReRAM is entirely immune to the serial overset orreset operations without the additional damage created.

In addition, Fig. 13 shows that the set and reset operationscan be finished within 50 ns for high-speed memory appli-cation, and the bi-states are very stable for much longer setand reset pulses. In terms of endurance, Fig. 14 shows thatthe vertical BJT-driven 3-D ReRAM is able to sustain morethan 106 cycling stresses without significant degradation, which


Fig. 11. Disturb test of set and reset operation for unselected cell. (a) Atset operation, the unselected cells endure only BL disturb. BL disturb testsof set operation for the unselect cells at WL = floating, BL = 1.5, and SL =floating. (b) At reset operation, the unselected cells endure only SL disturb. SLdisturb tests of reset for the unselected cells at WL = floating, SL = 1.5, andBL = floating.

Fig. 12. Overwriting immunity of 3-D ReRAM for repeated pulse. HRSoverwriting immunity is demonstrated by setting the ReRAM from HRS to LRSand reset back to HRS. The LRS immunity test is using the opposite measuringsequence.

Fig. 13. In both set and reset operations, the LRS and HRS switch by 50-nmvoltage pulse, and the read current being stable for longer stressed voltage.

is beyond the requirement of Flash memory. Furthermore,Fig. 15 shows the long-term temperature bake at 125 ◦C post106 cycling stresses; the cell has no observable shift from theinitial resistance states.

VI. CONCLUSION

A new 3-D vertical BJT ReRAM with CMOS-compatibleprocess has been demonstrated and characterized. The high-

Fig. 14. Cycling characteristic of 3-D ReRAM operated by the voltage pulseand no window degradation can be observed after 106 cycles.

Fig. 15. Long-term temperature stress for post 1000 h shows no retentionissue on HRS and LRS levels.

density 3-D ReRAM cell can operate with superior set andreset efficiency and good reliability with an extrasmall cell sizeby a high-performance vertical BJT. For ultrahigh density non-volatile memories with low voltage, high scalability, and wideand uniform on/off window, the cell is a promising solution forfuture mass storage and low-power NVM applications.

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Ching-Hua Wang was born in Taiwan, on January4, 1987. She received the B.S. degree in electricalengineering and the M.S. degree in electronic en-gineering from the National Tsing Hua University,Hsinchu, Taiwan, in 2009 and 2011, respectively.

She is currently with Taiwan Semiconductor Man-ufacturing Company, Ltd., Hsinchu, where she workson the integration program. Her research focuses onBJT design.

Yi-Hung Tsai was born in Taiwan. He received theB.S. degree in electrical engineering/computer sci-ence and the Ph.D. degree in electronics engineeringfrom the National Tsing Hua University, Hsinchu,Taiwan, in 2003 and 2009, respectively. His doctoraldissertation was on novel non-volatile memory.

He is currently with Taiwan Semiconductor Man-ufacturing Company, Ltd., Hsinchu, where he workson the development of SPICE modeling.

Kai-Chun Lin, photograph and biography not available at the time ofpublication.

Meng-Fan Chang (S’03–M’05) received the B.S.degree in electrical engineering from the NationalCheng Kung University, Tainan, Taiwan, in 1991,the M.S. degree in electrical engineering from ThePennsylvania State University, University Park, in1996, and the Ph.D. degree from the Institute of Elec-tronic Engineering, National Chiao Tung University,Hsinchu, Taiwan, in 2005.

From 1991 to 1993, he was a Second Lieutenant inelectronic communication with the Army of Taiwan.From 1996 to 1997, he designed SRAM and ROM

compilers with Mentor Graphics Corporation, Warren, NJ. From 1997 to2001, he designed embedded SRAMs and managed the memory-IP validationprogram in the Design Service Division (DSD), TSMC, Hsinchu. From 2001to 2006, he was a Director with the Intellectual Property Library Company(IPLib), Hsinchu, where he developed embedded Flash, SRAM, and ROM com-pilers, flat-cell mask ROMs, and mixed-signal IPs. Since 2006, he has been withthe Electrical Engineering Faculty, National Tsing Hua University, Hsinchu,where he is currently an Assistant Professor. His research interests includevolatile and nonvolatile memory circuit designs, ultralow-voltage circuits, low-power circuits, array structures, and circuit-level design for manufacturing.

Ya-Chin King was born in Taiwan. She received theB.S. degree in electrical engineering from the Na-tional Taiwan University, Taipei, Taiwan, in 1992 andthe M.S. and Ph.D. degrees in electrical engineeringfrom the University of California, Berkeley, in 1994and 1999, respectively. Her doctoral research wason thin oxide technology and novel quasi-nonvolatilememory.

Since August 1999, she has been with the NationalTsing Hua University, Hsinchu, Taiwan, where she iscurrently a Professor with the Electrical Engineering

Department. Her research topics include thin-gate dielectrics, CMOS imagesensors, and nonvolatile memory design.

Chrong Jung Lin received the B.S., M.S. and Ph.D.degrees from the National Tsing Hua University,Hsinchu, Taiwan, in 1991, 1992 and 1996 respec-tively. His Ph.D. research was on developing andmodeling for Flash cell with the 3D tunneling en-hancement effect of Si nanocrystal.

In 1996, he was with the Memory Technol-ogy Department (MTD), Research and Develop-ment (R&D), Taiwan Semiconductor ManufacturingCompany (TSMC), Hsinchu, where his work as aResearch Associate was on embedded memory so-

lutions based on advanced CMOS logic technology. From 2000 to 2003, heled a research group in the development of 0.25-μm high-reliability embeddedFlash memory for automotive MCU applications. From 2003 to 2005, hefurther led the development of 0.18-μm automotive embedded Flash memoryIP and technology. Since 2005, he has been teaching with the Department ofElectrical Engineering, Institute of Electronics Engineering, National TsingHua University. Much of his research now has been on the advanced devicedesign and development of nonvolatile cells and CMOS image sensor pixels insemiconductor memories.

Shyh-Shyuan Sheu is currently working towardthe Ph.D. degree with the Department of ElectricalEngineering, National Central University, Chungli,Taiwan.

Since January 2003, he has been an IC Designerwith the Electronics and Optoelectronics ResearchLaboratories, Industrial Technology Research Insti-tute, Hsinchu, Taiwan. His research involves mem-ory, display, and CMOS image sensor circuit designand technology.


Yu-Sheng Chen is currently working toward the Ph.D. degree with the Instituteof Electronics Engineering, National Tsing Hua University, Hsinchu, Taiwan.

He is currently a Device Engineer with the Industrial Technology ResearchInstitute, Hsinchu. His research interests include CMOS technology, non-volatile memory technology, and circuit design for memory.

Heng-Yuan Lee received the Ph.D. degree in electrical engineering from theNational Tsing Hua University, Hsinchu, Taiwan.

He is currently is a Device Engineer with the Industrial Technology ResearchInstitute, Hsinchu. His research interests include device development of flash,DRAM and emerging memory technologies.

Frederick T. Chen received the Ph.D. degree inapplied physics from Cornell University, Ithaca, NY.

He is currently a RRAM Group Manager anda Deputy Director with the Nanoelectronic Tech-nology Division, Industrial Technology ResearchInstitute, Hsinchu, Taiwan. His research inter-ests include advanced memory technologies, metal-insulator transitions, and nanoscale phenomena.

Ming-Jinn Tsai is currently a Research Directorwith the Electronics and Optoelectronics ResearchLaboratory, Industrial Technology Research Insti-tute, Hsinchu, Taiwan. He is currently involved in thedevelopment of device and process technologies fornew nonvolatile memory and power electronics.

three-dimensional reram with vertical bjt driver by cmos logic compatible process

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