three-level zvs active clamping pwm for the

IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 10, OCTOBER 2009 2249

Three-Level ZVS Active Clamping PWM for theDC–DC Buck Converter

Jean Paulo Rodrigues, Samir Ahmad Mussa, Member, IEEE, Marcelo Lobo Heldwein, Member, IEEE,and Arnaldo Jose Perin, Member, IEEE

Abstract—This paper presents the study of a dc–dc buckconverter with three-level buck clamping (buck–buck), zero-voltage switching (ZVS), active clamping, and constant-frequencypulsewidth modulation (PWM). Other ZVS dc–dc convertertopologies that employ three-level switching cells are introduced,and their steady-state dc gain is analyzed. This analysis showsthat the buck–buck converter has characteristics that warrant amore detailed study. A feature that is common to all the intro-duced topologies is the theoretical reduction of the voltage stressesacross the active semiconductors to 50% of the corresponding two-level converters. Accordingly, the switches of the buck–buck con-verter provide 50% of the blocking voltage of a ZVS two-level buckconverter. The steady-state analysis of the converter is performedaccording to the description of the operation stages of the con-verter. Based on the performed analyses, a comparative discussionto other topologies is given. Furthermore, a topologic derivation ofthe circuit is presented, which provides ZVS operation to all semi-conductors. Finally, a simplified design procedure is proposed, andused to design and build a prototype. Experimental results from alaboratory prototype are presented.

Index Terms—Buck, dc–dc converter, pulsewidth modulation(PWM), soft switching, three levels.

I. INTRODUCTION

BUCK-TYPE dc–dc converters are widely employed in thepower electronics industry. Buck converters are perhaps

most widely used dc–dc converters in the world because no othertopology is as simple. Their applications range from low-powerregulators [1] to very high power step-down converters [2],which are characterized by a low number of components, lowcontrol complexity, and no insulation. In the conventional bucktopology, which uses a single active switch, the maximum volt-age applied across the terminals of the semiconductors equalsthe input voltage, and hard switching is observed. These con-verters are often used in high-power and high-input-to-output-voltage-ratio applications; however, the conventional buck-typetopologies have low efficiencies because of high conductionlosses [3] due to high-voltage-rated devices and high switch-ing losses. Furthermore, for high input voltages, the choice of

Manuscript received December 5, 2008; revised March 23, 2009. Currentversion published September 2, 2009. This work was supported in part by theNational Counsel of Technological and Scientific Development (CNPq), Brazil.Recommended for publication by Associate Editor M. Ferdowsi.

The authors are with the Department of Electrical Engineering, PowerElectronics Institute, Federal University of Santa Catarina, Florianopolis88.040-970, Brazil (e-mail: [email protected]; [email protected];[email protected]; [email protected]).

Color versions of one or more of the figures in this paper are available onlineat http://ieeexplore.ieee.org.

Digital Object Identifier 10.1109/TPEL.2009.2022535

Fig. 1. Two-level ZVS PWM buck–buck converter [6].

switches is limited, which leads to difficulty in selecting tran-sistors or finding low-cost devices.

IN order to overcome the challenges listed before, researchershave been working to develop multilevel techniques [4], [5] andsoft switching [6]–[17], which are capable of reducing voltagestresses and switching losses, and thus, enable higher efficien-cies, smaller dimensions, and lower system costs. In this context,the main objective of this paper is to propose a solution that si-multaneously reduces voltages across the switches and providessoft switching to a buck-type converter.

The main parameters that impose limits on a buck converterwith high-frequency pulsewidth modulation (PWM) operationare the junction capacitances of the semiconductors, parasiticinductances, and the reverse recovery of the diodes. To mini-mize these effects, many soft-switching techniques have beenpresented in the literature. Soft-switching techniques typicallyincrease the current and/or voltage stresses in the semiconduc-tor devices. Zero-voltage switching (ZVS) techniques [6]–[17]typically increase the voltage stress of the active switches,and zero-current switching (ZCS) techniques increase currentstresses [18]. In the case of two-level buck topologies, if atwo-level ZVS converter topology presents a maximum voltageacross the active switches that is higher than twice the input volt-age, this topology is not preferable. This condition is consideredas the starting point of this paper, where the concept is to be ex-tended to a three-level version. In [6], a buck converter topologyemploying a two-level ZVS buck-type active clamping circuit(cf., Fig. 1) was introduced. This topology contains an extraswitch compared to the conventional buck converter. However,this topology allows for ZVS in the turn-off switches, thus pro-viding a higher efficiency at higher switching frequencies. Ananalysis of the two-level ZVS active clamping techniques pro-posed in [6] shows that the two-level ZVS buck–buck converteris the only topology that limits the maximum voltage across theswitches to the same level that is obtained in a conventionalbuck converter. This is the main reason for choosing three-levelbuck-type clamping for further study in this paper.

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2250 IEEE TRANSACTIONS ON POWER ELECTRONICS, VOL. 24, NO. 10, OCTOBER 2009

Fig. 2. Buck converter using different three-level converters for active clamping. (a) Buck–buck. (b) Buck–boost. (c) Buck–cuk. (d) Buck–sepic. (e) Buck–zeta.

Three-level buck nonisolated dc–dc PWM converters havebeen proposed in the literature [8], [9] in order to reduce thevoltage across the switches. In [19], even though these convert-ers operate at constant switching frequency, they do not featuresoft switching. In [20], the converter features soft switching.However, compared to the conventional buck converter, the the-oretical maximum voltage across the active devices in [20] ishigher than half of the input voltage. Furthermore, in this topol-ogy, the converter is frequency-modulated, which is not desir-able in this paper.

Thus, the proposal and analysis of a three-level buck-typeconverter with soft switching is presented in the following sec-tions, where a family of distinct three-level ZVS active clampingtechniques applied to the dc–dc buck converter is presented. Thedifferent clamping strategies are compared, and the selectionof three-level ZVS buck-type clamping for the buck converteris justified. The advantage of employing the three-level ZVSclamping proposed in this paper is the reduction of the maxi-mum voltage across the active switches by 50% compared toother two-level ZVS topologies [7]. Nevertheless, in order toreduce the voltage stress of the switches, the three-level ZVStopology uses two active switches in addition to those includedin other two-level ZVS topologies.

II. THREE-LEVEL ZVS PWM BUCK CONVERTERS

A family of buck-type converters is presented in Fig. 2, wheredifferent active clamping strategies are employed in order toachieve soft switching and blocking voltage reduction. In Fig. 2,index i relates the source to the input port and o relates thesource to the output ports of the converters. The three-levelsoft-switching active clamping cells are classified according to

Fig. 3. Input-to-output voltage characteristic of the buck–boost converter.

the basic topology from which they are generated, and whichare introduced in [6].

The input-to-output characteristics, referred to here as staticgains, and the basic waveforms of the converters shown inFig. 2 are the same as those for the two-level converters pre-sented in [6]. An example of these characteristics is shownin Fig. 3. Furthermore, the two-level buck–boost, buck–cuk,buck–sepic, and buck–buck–boost converters present the sameinput-to-output ratio as given in

Vo

Vi= q = D − 2Ln (1)

where D is the duty cycle, and Ln denotes the normalized outputcurrent that has no dimension and is given by

Ln = LrIofs

Vi. (2)


RODRIGUES et al.: THREE-LEVEL ZVS ACTIVE CLAMPING PWM FOR THE DC–DC BUCK CONVERTER 2251

Fig. 4. Maximum voltage across the active switches of the buck–boost con-verter as a function of the input voltage [8].

Among the topologies that present the same static gain, thebuck–boost converter presents a lower component count andthe same or better functionality as the others. Therefore, aftertaking the topologies shown in Fig. 2 into account, the followingoptions will be considered for a buck converter with three-levelZVS clamping: buck–buck, buck–boost, and buck–zeta.

The transfer function of the buck–buck converter is given inthe next section, while the static gain for the buck–zeta is

Vo

Vi= q =

D

1 − D− 2Ln

(1 − D) [2Ln + (1 − D)]

⇒ buck–zeta. (3)

Zeta-type clamping features ZVS operation throughout thecomplete load range. However, this type of clamping results inapplication of a high voltage across the active switches. There-fore, based on the comments made in Section I, the buck–zetaconverter is not considered further.

Boost-type clamping is advantageous because of the lowerduty cycle loss. The main drawback of this technique is thedependence of the maximum voltage across the switches onduty cycle and power variations. This dependence is clear from

Vo

Vi= q =

D

1 − D− 2Ln

(1 − D) [2Ln + (1 − D)]and

Vswitches =Ln

(1 − D)+

Vi

2⇒ buck –boost. (4)

This characteristic is depicted in Fig. 4, and it clearly makesit more difficult to design the circuit components and achievethe maximum efficiency for a given range of input-to-outputvoltage ratios for this type of clamping.

Buck-type clamping features a maximum voltage across theactive switches that is independent of any design parameter. Thevoltage across the switches is theoretically clamped to half ofthe input voltage. The characteristics of this topology are verybeneficial, and, consequently, the buck–buck converter will bethe focus of analysis in the remainder of this paper.

The two-level converters, forward and flyback, and otherisolated topologies with ZVS have been discussed in the lit-erature [21]–[29]. The forward-boost three-level design foundin [30] can be expanded to five levels using forward-boost [31].

Fig. 5. Three-level ZVS PWM buck–buck converter.

Clamping buck or clamping boost can be applied in flyback orforward converters, as presented in [31].

The three-level buck–boost applied in forward-boost [31] andbuck–buck, as presented in this paper, can be applied directly ina forward-buck, where ZVS and voltage stress reduction havealmost the same characteristics.

III. THREE-LEVEL BUCK–BUCK CONVERTER

For the reasons given in Section II, the topology analyzedin this section is the buck–buck converter. Fig. 5 presents thecommutation cell for the three-level buck–buck converter andits basic circuit configuration. In order to ease the understand-ing of the converter’s operation, the following assumptions areconsidered.

1) Switches are ideal.2) The converter operates in steady state.3) The output inductance Lo is such that, in conjunction with

output voltage Vo , it can be represented as an ideal currentsource (Io).

4) The resonant inductor Lr stores sufficient energy to com-plete the charging and discharging of the resonant capac-itors C1 , C2 ,C3 , and C4 (cf., Fig. 5), with value Cr , dur-ing the switching transitions and to polarize the intrinsicdiodes of the switches.

5) The passive components are considered free from parasiticeffects.

6) The auxiliary bus capacitance CC is much larger than Crand is capable of keeping the voltage unchanged during aswitching cycle. Thus, the auxiliary bus capacitors can berepresented by voltage sources.

A. Converter Operation

Depending on the intervals between the turn-off of theswitches and the value of the resonant capacitors (Cr), the con-verter can operate in nine different operation modes. However,for all cases, the converter operates under ZVS, maintaining itsstatic-gain characteristic. The differences are noted only in afew operation stages for very short durations. For this reason,the analysis developed here is limited to a single representativecase.



Fig. 6. Operation stages of the three-level ZVS buck–buck converter.

In order to simplify the stages, the voltages across capacitorsC5 and C6 are considered balanced and equal to Vi/2. The res-onant capacitor is chosen so that Cr > Cr limit , where Cr limit isdefined in (18). If a voltage imbalance across capacitors C5 andC6 were considered, the number of operation stages would in-crease, but the ZVS of the four transistors would be maintained.

The description of the operation stages is summarized shortly,and they are shown in Fig. 6.First stage [t1–t2]: Switches S1 and S2 are ON. The current

through inductor Lr is negative. Diode Do is forward-biased.Second stage [t2–t3]: Switch S1 is turned off, but S2 is still

ON. The current is divided between the resonant capacitorsC1 , C3 , and C4 . The current through Lr is equal to IM

(cf., Fig. 8), of which two-thirds circulate through C1 andone-third through C3 and C4 . The voltage across capacitorC1 increases from zero to Vx (cf., Fig. 7), which is less thanVi/2, and the voltages across C3 and C4 decrease from Vi/2to (Vi/2 − Vx/2). Voltage Vx depends on the interval betweenthe turning off of switches S1 and S2 .

Third stage [t3–t4]: Switch S2 is turned off, and the currentthrough the four resonant capacitors is IM/2. When thevoltage across capacitor C1 reaches Vi/2, the fourth stagebegins.

Fourth stage [t4–t5]: A current division occurs as in the secondstage. This stage ends as the voltages across capacitors C3and C4 reach zero.



Fig. 7. Main waveforms of the three-level ZVS buck–buck converter.

Fig. 8. Simplified waveforms of the three-level buck–buck converter.

Fifth stage [t5–t6]: Diodes D3 and D4 are forward-biased. Thesediodes conduct the current through inductor Lr .

Sixth stage [t6–t7]: The resonant inductor current becomes pos-itive and switches S3 and S4 start to conduct.

Seventh stage [t7–t8]: This stage starts when the resonant in-ductor current equals Io . The diode Do is reverse-biased.

Eighth stage [t8–t9]: In this stage, S4 is turned off and thevoltage across C4 increases from zero to Vx , which is lessthan Vi/2, and depends on the interval between the turn-offof switches S3 and S4 . When switch S3 turns off, the nextoperation stage begins.

Ninth stage [t9–t10]: The current through the four resonant ca-pacitors is ILr/2. This stage ends when the voltage across C4reaches Vi/2.

Tenth stage [t10–t11]: The voltage across C1 and C2 continuesto decrease until it reaches VCc/2.

Eleventh stage [t11–t12]: In this stage, diode Do is forward-biased.

Twelfth stage [t12–t1]: Diodes D1 and D2 are forward-biasedand conduct the resonant inductor current. After this stage,the circuit is ready to return to first stage again.Fig. 7 presents the main waveforms of the converter, and the

preceding description is considered for a single switching cycle.Each operation interval is described using this figure.

From the analysis, the necessary condition for ZVS to occuris that the switch is turned on only when its parallel capacitoris discharged. In other words, to achieve zero losses in theswitching intervals, the drive signals of switches S1 and S2(VG1,G2) should transition between t12 and t1 , and the drivesignals of S3 and S4 (VG3,G4) should transition between t5 andt6 . The voltage Vx of Fig. 7 is smaller than VCc/2 and dependson the turn-off intervals.

B. Static Gain Characteristic

To simplify the derivation of the input-to-output voltage gaincharacteristic, the very short time intervals (between t2 and t5and from t8 to t11) are neglected in the following. Therefore,Fig. 7 can be redrawn as shown in Fig. 8.

Note that duty cycle D is defined as the interval between theturn-off of switches S1 and S2 and the turn-off of switches S3 andS4 . The duty cycle is defined in this manner since the drive sig-nals of the switches are not necessarily complementary. Basedon these assumptions, the static transfer characteristics of thetwo- and three-level buck–buck converters are strictly the same.

The inductor current of Fig. 11 shows that the current rippleat the output is far from being negligible, and the current cannotbe considered constant; however, the equations presented inthis section are sufficiently robust because even under theseconditions, the static gain depends on the average output current.

The average current through capacitor CC , iCc , is computedusing

iCc(t) = iLr(t) =∫ ∆1

0

[(Vi − VCc)

Lrt + IM

]dt

+∫ DT s−∆1

0(Io)dt +

∫ (1−D )T s

0

[−VCc

Lrt + Io

]dt = 0

(5)

where

IM = Io −VCc

Lr(1 − D)Ts (6)

and

∆1 =(IM + Io)Lr

(Vi − VCc). (7)



Fig. 9. Static transfer characteristic.

The normalized load current or normalized resonant induc-tance “Ln” is defined by

Ln = LrIo

ViTs. (8)

The average value of the average current across CC is zerobecause the system is under steady-state operation. Thus, byintegrating (5) and substituting (6)–(8) into (5), the expressionfor the relationship between voltages VCc and Vi is obtained

VCc =2LnVi

2Ln + (1 − D)2 . (9)

The static gain is given by

Vo = DVi − VCc . (10)

If the system operates in steady state, the gain characteristicis obtained from the sum of the voltages since the average valueof the voltage across inductor Lr is null.

Defining the relationship between input and output voltage as

q =Vo

Vi(11)

and substituting (9) and (11) into (10) gives

q = D − 2Ln

2Ln + (1 − D)2 . (12)

Fig. 9 presents the static-gain characteristic of the buck con-verter employing three-level buck-type clamping as a function ofduty cycle D for different values of normalized inductance Ln .It is seen that a large voltage drop across the resonant inductorleads to a lower input-to-output voltage ratio. This characteris-tic reveals that the resonant inductor value should be limited inorder to obtain a more linear voltage transfer curve.

C. Converter Design

The design of the proposed converter is presented in this sec-tion. The aim was to build a prototype in order to experimentallyverify the theoretical analysis and evaluate the design proce-dure. The adopted specifications do not necessarily demand softswitching due to the relatively low output power. Nevertheless,this design takes advantage of lower voltage switches that offerlower switching losses and costs. The following specificationshave been employed.

1) Vi = 700V⇒ input voltage.2) fs = 20 kHz⇒ switching frequency.3) Vo = 360V⇒ output voltage.4) Po = 550W⇒ output power (Ro ≈ 235Ω).5) ∆Vo = 1%⇒ output voltage ripple.6) t2–3 = 0.01%/fs ⇒ difference in the turn-off times be-

tween switches S1 and S2 and between S3 and S4 .In order to choose an adequate value for the resonant in-

ductance, some gate drive timing adjustments were taken intoconsideration. The drive signals for switches S1 and S2 were tobe applied right after the resonant capacitors C1 and C2 weredischarged. On the other hand, in order to avoid hard switching,these signals had to be applied before the current of inductor Lrbecame positive. In order to allow for a safety margin for thedrive circuitry, an inductance of 100 µH was chosen. The mini-mum inductance value for this design was approximately 50 µH.However, this value led to difficulties in the timing adjustmentfor a wide load variation leading the converter to operate withoutZVS

Lr = 100 µH ⇒ Ln = 0.004.

The duty cycle for rated power was computed from (12). Thus

D = 0.557. (13)

The output current was given by

Io =Vo

Ro= 1.52A. (14)

The output capacitor was sized as for a conventional buck con-verter

Co =Vi

f 2s ∆VoVoπ3Lo

⇒ Co = 78µF. (15)

Because of the current capability of the electrolytic capaci-tors available for use in the experimental prototype, an outputcapacitor of 470 µF was chosen.

The low value for output inductance was chosen to increasethe load variation range beyond which the converter can operatewith ZVS

Lo = 2mH. (16)

The output inductor current ripple was

∆ILo =Vo

Lo

(1 − D)fs

⇒ ∆ILo = 3.9A. (17)

A resonant frequency ten times larger than the switchingfrequency was chosen. Thus, the resonant capacitance was foundwith

Cr =1

Lr(2π10fs)= 8 nF ⇒ Cr = 8.2 nF. (18)

The auxiliary capacitor operates as a constant voltage source.Thus, from the time analysis

2π√

LrCC

2> 3

(1 − D)fs

⇒ CC >9(1 − D)2

π2Lrf 2s

(19)

CC > 3.9µF ⇒ CC = 5µF.



Fig. 10. Schematic of the power circuit for the laboratory prototype.

In order to equally share the voltage in the clamping cell,the values of capacitors C5 and C6 were chosen to be equaland were much larger than the resonant capacitors. Thus, C5 =C6 = 4.4µF.

D. Experimental Results

A prototype of the three-level buck–buck converter was builtaccording to the specifications of Section III-D, and its circuitschematics are presented in Fig. 10. Because the main objectivewas to analyze the power circuit performance, the experimentswere conducted with open-loop control, fixing the duty cycle andobserving the circuit’s performance. Furthermore, the control-oriented modeling of the structures presented here is importantand suitable for a comprehensive study. Gate pulses were gen-erated by the microcontroller PIC18F4331 and isolated by thegate drivers SKHI10op.

Due to limitations of the low-cost microcontroller used inthis study, the chosen switching frequency was 20 kHz. The lowresolution can make it difficult to balance the clamping voltages.On the other hand, closed-loop control of the clamping voltagescan help balance the voltage even with low-resolution PWM.Thus, in this study, high-frequency operation was made possibleby using closed-loop control of the clamping voltages.

At rated power and a measured dc output voltage Vo =358.5V , the waveforms seen in Fig. 11 were recorded. Thevoltage across the switches S1 , S2 , S3 , and S4 , and the reso-nant inductor current are in good agreement with the theoreticalwaveforms presented in Section II-A, except for the output cur-rent ripple, which causes the current iLr to present a rippleaccordingly.

A detailed view of the commutation turn-on process forswitches S1 and S2 is shown in Fig. 12(a), where ZVS oper-ation can be observed. Fig. 12(b) shows S3 and S4 , which alsooperate with ZVS. The measured maximum voltage overshootfor the switches was 375 V, which corresponds to 53% of theinput voltage Vi . This shows that the voltage across the switchesis effectively halved when compared to a conventional buck

Fig. 11. Waveforms for rated power. (a) Voltage across switches S1 and S2 ,drive signal of S1 , and resonant inductor current. (b) Voltage across switchesS3 and S4 , drive signal of S3 , and resonant inductor current.

converter. Thus, the aim of reducing voltage stresses by 2 in theactive switches was achieved in the proposed converter.

The designed converter operates with ZVS from 100% to35% of the rated power. Below a 35% load, ZVS transitionswere observed only during turn-on commutations. Fig. 13 showsthe power transfer efficiency curve for three load conditions. A



Fig. 12. Details for the commutations at rated power. (a) Waveforms VS1 ,VS2 , and iLr during the turn-on transition of S1 and S2 . (b) Waveforms VS3 ,VS4 , and iLr during the turn-on transition of S3 and S4 .

Fig. 13. Buck–buck converter efficiency for 35%, 65%, and 100% of the ratedload.

reduction due to the reactive energy flow generated by the inputinductor current ripple is observed in the efficiency curve.

In order to compare efficiency figures from the built proto-type to other topologies, it is observed that the efficiency isclose to the one presented in [8]. Duarte and Fiori [11] considera two-level ZVS realization and show efficiency data for switch-ing frequencies that are higher than the ones adopted here. The

Fig. 14. Buck–buck converter presenting ZVS at all commutation for all semi-conductor devices.

tendency, as shown in [11], is for the efficiency of the ZVStopologies to become higher than the efficiency of conventionalconverters at higher switching frequencies, input voltage, andoutput power. Consequently, this is highly dependent on appli-cation and specifications.

During the experiments, the clamping voltages across capac-itors C5 and C6 , which ultimately define the voltages across theswitches, remained balanced for input voltage variations fromzero to Vi , and full-load variation even though the circuit wasoperating in open loop. Thus, no clamping balance strategy wasrequired.

However, closed-loop simulations have been performed thatshow that the clamping voltages can be balanced using a sim-ple integral controller that controls the time delays betweenthe gate pulses of different switches. In this context, the out-put voltage is controllable and well regulated through a PIcontroller.

E. ZVS of the Output Diode

Despite the four active switches (S1 , S2 , S3 , and S4) thatpresent ZVS commutations, in the case of the previously pre-sented buck–buck converter, the turn-off transition for the outputdiode Do does not occur under zero-voltage condition, whereasthe turn-on transition does occur. In an application where the as-sociated switching losses are excessively high, ZVS turn-off canbe a helpful solution. For this situation to occur, a diode Do2 canbe added to the circuit [10], [11], as shown in Fig. 14. With thisconfiguration, all semiconductor devices present ZVS commu-tation during both turn-on and turn-off. Furthermore, the staticgain remains unaltered. Considering that the capacitance valuesof the capacitors in parallel with diodes Do1 and Do2 are smallerthan or equal to the parasitic capacitances, the current throughinductor Lr will be slightly larger than that for the previouslypresented buck–buck converter. If this small increase in currentILr compared to Io is ignored, the waveforms are basically thesame as those presented in Fig. 7, where the differences arewithin the details of the commutations of diodes Do1 and Do2 .

IV. CONCLUSION

This paper has presented a family of high-efficiency buck-type dc–dc converters that are well suited for high-voltage



applications. The proposed converters combine the advantagesof a reduction of the voltages across the switches, which wasachieved using a three-level commutation cell, with decreasedswitching losses obtained from a ZVS technique.

Based on the premise that the converter should limit the volt-age across the switches to half of the input voltage, a topol-ogy based on the buck converter and a buck-type three-levelclamping circuit has been identified as the most suitable. Thistopology has been theoretically analyzed, and its operation hasbeen experimentally verified. A limitation posed in this circuitis the reduction of the input-to-output voltage transfer ratio fora high duty cycle; however, this is typically not a limiting factorfor step-down converters. A comparison between the proposedtopology and the two-level ZVS buck–buck converter shows thatthe voltages across the switches are 50% lower. Nevertheless,the three-level converter provides two extra bidirectional cur-rent switches and an additional capacitor for the auxiliary buswhen compared to the two-level converter even though the volt-age ratings for these devices are halved as well. The three-leveltechnique provides more gate driver circuits, thus illustratinganother disadvantage of using two-level topologies. In a closed-loop application, the control of the two clamping voltages needsto be implemented, and, thus, requires more circuit complexityand extra voltage sensors. Consequently, the proposed converteris thought to be a suitable solution in applications where theswitch technology poses a limitation to the available voltageratings, no insulation is needed, and a high efficiency at highswitching frequencies is required.

A further modification has been introduced to the proposedtopology for the achievement of ZVS operation for the outputdiode as well.

The proposed buck–buck converter can be extended tocorresponding insulated topologies (forward-buck) that are ableto reduce the active switches’ voltage ratings while providingZVS. Further extensions are possible which generate five-leveldc–dc converters that reduce the maximum switched voltagesto 25% of the original forward topology. Another advantage ofthe forward-buck converter in relation to other converters, suchas the forward- boost, is that capacitor Cc of the buck clampingcircuit is already placed in series with the transformer, whichprevents saturation of the capacitor. For three-level half-bridgeand full-bridge converters with ZVS, the different types ofthree-level clamping solutions presented here cannot be directlyemployed.

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Jean Paulo Rodrigues received the B.E. and M.S.degrees in electrical engineering in 2002 and 2005,respectively, from the Federal University of SantaCatarina, Florianopolis, Brazil, where he is currentlyworking toward the Ph.D. degree at the Power Elec-tronics Institute.

In 2008, he joined the Mechanic Metal Depart-ment, Federal Institute of Education, Science andTechnology of Santa Catarina (IFSC), Florianopolis,where he is currently a Lecturer, and engaged ineducation and research on power electronics and

mechatronics. His current research interest is multilevel dc-dc converters forreduced stresses across power semiconductors.

Samir Ahmad Mussa (M’06) received the B.E. de-gree in electrical engineering from the Federal Uni-versity of Santa Maria, Florianopolis, Brazil, in 1988,and the M.Eng. and Ph.D. degrees in electrical engi-neering from the Federal University of Santa Catarina(UFSC), Florianopolis, in 1994 and 2003, respec-tively.

He is currently a Lecturer at the Power ElectronicsInstitute (INEP), UFSC. His current research interestsinclude digital control applied to power electronics,power factor correction techniques, and digital signal

processing (DSP)/field-programmable gate array (FPGA) applications.Dr. Mussa is a member of the Brazilian Power Electronics Society

(SOBRAEP).

Marcelo Lobo Heldwein (S’99–M’06) received theB.S. and M.S. degrees in electrical engineering fromFederal University of Santa Catarina, Florianopolis,Brazil, in 1997 and 1999, respectively, and the Ph.D.degree from the Swiss Federal Institute of Technol-ogy (ETH Zurich), Zurich, Switzerland, in 2007.

From 1999 to 2001, he was an R&D Engineer withthe Power Electronics Institute, Federal University ofSanta Catarina, where he is currently a PostdoctoralFellow. From 2001 to 2003, he was an Electrical De-sign Engineer with Emerson Energy Systems, Sao

Jose dos Campos, Brazil, and Stockholm, Sweden. His current research interestsinclude power-factor-correction techniques, static power converters, multilevelconverters, and electromagnetic compatibility for power electronics.

Dr. Heldwein is a member of the Brazilian Power Electronics Society(SOBRAEP).

Arnaldo Jose Perin (M’86) received the B.E. degreein electronic engineering from the Pontificia Univer-sidade Catolica do Rio Grande do Sul, Porto Alegre,Brazil, in 1977, the M.Sc. degree in electrical engi-neering from the Federal University of Santa Catarina(UFSC), Florianopolis, Brazil, in 1980, and the Dr.Ing. degree from the Institut National Polytechniquede Toulouse (INPT), Toulouse, France, in 1984.

In 1980, he joined the Electrical Engineering De-partment, UFSC, where he is currently engaged ineducation and research on power electronics analysis

and design. Since 1993, he has been involved more specifically on electronicballast to use with fluorescent lamps, human interface device lamps, and LEDs.He is the author or coauthor of several research papers presented at Brazilianand international conferences. His current research interests include power elec-tronics, modulation, ac converters, and power factor correction.

Dr. Perin is a member of the Brazilian Power Electronics Society(SOBRAEP).


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