through silicon via (tsv) equalizer - · pdf filetera terahertz interconnection and package...

Terahertz Interconnection and Package Laboratory TERA Terahertz Interconnection and Package Laboratory

*Joohee Kim, *Eakhwan Song, *Jeonghyeon Cho, *Jun So Pak,

**Junho Lee, **Hyungdong Lee, **Kunwoo Park and *Joungho Kim

* Korea Advanced Institute of Science and Technology (KAIST)

** Hynix Semiconductor Inc.

2010. 6. 17.

Agilent Measurement Forum 2010

Through Silicon Via (TSV) Equalizer


Contents

2

Introduction

Analysis of loss mechanism of a TSV

Proposed TSV Equalizer

Simulation-based Verification of the Equalization Performance of the

Proposed TSV Equalizer

Conclusion


PCB

Through Silicon Via (TSV) in 3-dimensional Integrated Circuits

3

Through Silicon Via (TSV) is a vertical interconnection method

between chips in 3-dimensional integrated circuits.

Package

Stacked

Dies

[ 3-dimensional Integrated Circuits ]

Interposer

Interposer

Package

Die

Through Silicon Via


A Through Silicon Via Structure on Double-sided Silicon Substrate

4

1111111111111 TSV Double-sided

Silicon Substrate

Underfill

Insulation layer

Inter-metal Dielectric

Underfill Metal (M1,M2) Bump

Inter-metal Dielectric

Bump Cu SiO2 Si

Cinsulator GSi sub


Frequency-dependent Loss of Through Silicon Via

5

1 -6

-5

-4

-3

-2

-1

0

10 20 0.1

Capacitive

region Resistive

region

Cu SiO2 Si

Leakage current

Frequency

dependent term

Loss term

Cinsulator GSi sub

Tra

nsm

issio

n c

oeffic

ient

(S21)

[dB

]

Frequency [GHz]


Cinsulator Cinsulator

High Speed Signal Performance Degradation caused by TSV

6 Time (ps)

0 100 80 20 40 60 -0.25

0.25

0 V

olta

ge

(V

)

0 100 80 20 40 60 -0.25

0.25

0

Vo

lta

ge

(V

)

Time (ps)

The Eye is Closed!

We Need an Equalizer !

Ground

TSV Signal

TSV


Scalable Equivalent Circuit Model of a TSV

7


Cinsulator Cinsulator Bump Bump

Signal

TSV

Ground

TSV

Structural Parameters

TSV diameter : d

TSV-to-TSV pitch : p

SiO2 thickness : t

Height : h

Bump diameter : D

Equations

Cinsulator (d,h,t)

CSi sub (d,h,p,t)

CBump (p,D)

GSi sub (d,h,p,D)

RTSV (d,h)

LTSV (d,h,p)



GSi sub

CSi sub

RTSV RTSV

LTSV LTSV

CBump

CBump



8

d

)d/

td/(

h)επ(

L

)a

b(

εεπ C r

insulator

2

2ln

42

ln

2

0

0

Cinsulator (d,h,t) : SiO2 insulator capacitance

CSi sub (d,h,p,t) : Silicon substrate capacitance

t h

h

))(d/

tdp(

εεπ

L

)b

a(

εεπ C

r

rsubSi

2

2ln

2

2

1

2ln

2

2

1

0

0_

d

h

p

a b

a b

t

Ref) Matthew N.O. Sadiku, Elements of Electromagnetics, 3th Edition



9

RSi (d,p,h) : Resistance of Silicon

hd)ump

(

ump.

ζS

L R subSi

502

10

3070

_

CBump (d,p,h) : Capacitance between Bumps

h

p

p/2+d+50um

um)D

π(p-D

εε C r

bump 102

0

p

D

10um L




10

RTSV (d,h) : Resistance of TSV

))-δd

()d

((π

h)e.(

A

lρ R

skin depth

TSV

22

22

8721

LTSV (d,h,p,D) : Inductance of TSV

))D/

p(um)()

d/

p((h

π

)eπ(

)a

p(

π

lμ LTSV

2ln20

2ln

74

ln0

h

d

δSkin depth p

h

d

D 10 um

a

l

l



Signal TSV Ground TSV

SiO2

Si

Cu Cu

Signal current

Leakage current

Insertion Loss of a TSV in Low Frequency Range

11

Cinsulator



Cinsulator dominantly affects frequency

dependency of insertion loss of a TSV.

1 -6

-5

-4

-3

-2

-1

0

10 20 0.1 Tra

nsm

issio

n c

oeffic

ient

(S21)

[dB

]

Frequency [GHz]


Signal current

Leakage current


Insertion Loss of a TSV in Mid Frequency Range

12

CSi sub dominantly affects frequency


CSi sub

CSi sub

1 -6

-5

-4

-3

-2

-1

0

10 20 0.1 Tra

nsm

issio

n c

oeffic

ient

(S21)

[dB

]

Frequency [GHz]


Signal current

Leakage current


Insertion Loss of a TSV in High Frequency Range

13

CBump

CBump

CBump

CBump dominantly affects frequency


1 -6

-5

-4

-3

-2

-1

0

10 20 0.1 Tra

nsm

issio

n c

oeffic

ient

(S21)

[dB

]

Frequency [GHz]


14

Re-distribution Layer

(RDL)


Top die

Bottom die

Bump

Re-distribution Layer

(RDL)

Designed TSV Channel for Experimental Verification

Designed TSV Channel with Single-ended Signal TSVs

Re-distribution layer (RDL)

Through Silicon Via

(TSV)

Re-distribution layer (RDL)

for connecting TSVs


15

Probe

Station

Vector

Network

Analyzer

(VNA)

Cascade

probe

High

speed

cable

Measurement Environment for Experimental Verification

Vector Network analyzer (VNA)

Agilent Technologies / N2530A

(300kHz-20GHz)

Cascade Probe

I40-GS/SG 100um pitch

High Speed Cables

Micro-coax

(Frequency range : 0.05-26.5GHz)

(Insertion loss : 1.57dB/m at 26.5GHz)


16

0.1 1 10 -3.5

-3

-2.5

-2

-1.5

-1

-0.5

0

20

Frequency (GHz)

S21 m

agnitude (

dB

)

Measurement Proposed model

Cinsulator

CSi sub

CBump

TSV has capacitive characteristic which brings frequency dependency to

loss of a TSV.

Insulator capacitance, Cinsulator, dominantly affects the overall frequency

dependent loss of a TSV.

Verification of the Analyzed TSV loss by Measurement


Bump Bump

The Proposed TSV Equalizer using an Ohmic Contact

We intentionally made leakage by using an Ohmic contact

resulting in DC attenuation between signal and ground TSV.

17

n-type

Silicon

Substrate

n+ high

doped Silicon

Ohmic contact (Al/n+ type)

Signal

TSV

Ground

TSV



Signal current

Intended Leakage current

Intended DC attenuation of the Proposed TSV Equalizer

18

Ohmic contact brings

DC attenuation!

After Equalization

Before Equalization

1 -6

-5

-4

-3

-2

-1

0

Tra

nsm

issio

n c

oeffic

ient

(S21)

[dB

]

Frequency [GHz]

10 20 0.1

Rcontact Rcontact

Rcontact Rcontact


Metal Patterning

Process of the Proposed TSV Equalizer

19

Lithography

Silicon Substrate

Insulator Deposition

Silicon Doping

Via Etch

Back-grinding

Ohmic contact

Signal

TSV

Ground

TSV

Metal

Silicon

Substrate

Metal Plating

Chemical Mechanical

Polishing (CMP)

Back-side Metal Patterning

Backside Silicon doping

The Proposed TSV Equalizer


Simulation Item for Verification of the TSV Equalizer Performance

20

TSV diameter 75 um

TSV height 90 um

TSV-to-TSV pitch 150 um

SiO2 thickness 0.1 um

TSV dimension

Ohmic Contact information

Junction depth 1 um

Resistivity of

Junction

0.032 Ω·cm

Resistivity of

Silicon

10 Ω·cm

Contact Width 22.5 um

Number of stacked dies 8

Ground Signal Ground


0.1 1 10 -8

-6

-4

-2

0

Tra

nsm

issio

n c

oeffic

ient

(S21)

[dB

]

Frequency [GHz]

20

Flattened from DC to 10GHz

(Nyquist frequency of 20Gbps)

- 4.5

0.7dB 1 dB

-3.8 dB

4.8 dB

Frequency Domain Simulation-based Verification of the TSV Equalizer Performance

21

Insertion loss of 8 TSVs

without TSV equalizer

Insertion loss of 8 TSVs with TSV equalizer

• We successfully flattened frequency dependent loss by 3.8 dB

by using TSV Equalizer.


Time Domain Simulation-based Verification of the TSV Equalizer Performance

Time (ps) 0 100 80 20 40 60

-0.25

0.25

0

Voltage (

V)

• We successfully achieved normalized pk-pk jitter and eye-opening,

32% and 20%,

meanwhile the unequalized eye is completely closed.

22

Time (ps) 0 100 80 20 40 60

-0.25

0.25 Pk-pk jitter : 16 ps

Eye opening: 100mV

0

Voltage (

V)


Conclusion

23

We analyzed the loss mechanism of a TSV with scalable equivalent

circuit model which is verified with measurement.

We analyzed the frequency dependent loss of a TSV which is

capacitive and resistive.

We proposed the TSV Equalizer by using DC attenuation from an

ohmic contact to flatten the frequency dependent loss of a TSV.

With the proposed TSV Equalizer, we achieved normalized timing jitter

and eye opening, 32% and 20%, even with the almost closed eye.

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