time based encryption on network processor team wolfdale the university of southern california 1
TRANSCRIPT
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TIME BASED ENCRYPTION ON NETWORK PROCESSOR
TEAM WOLFDALEThe University of Southern California
Instructor: Dr. Young Cho
Mentor : Siddharth Bhargav
Team Members
Praveen Francis
Gaurav Yadav
Samitsubhro Banerji
Kaushik Raju
Team Wolfdale Members
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A Time Based Content Encryption Algorithm Based
On a Specific Sender-Receiver IP Pairs.
The Project
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Encryption at software level is slow as compared to hardware level
Most encryption algorithms use static keys.
HERE we Use a DYNAMIC KEY
The problems
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Router on NetFPGA
SENDER/RECEIVER IP NO MATCH
The General Concept
Router on NetFPGA
Data
Data
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10.0.2.3 12.0.2.3
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Router on NetFPGA
SENDER/RECEIVER IP MATCHEncrypting…
The General Concept
Router on NetFPGA
Encrypted Data
Data
SENDER/RECEIVER IP MATCHDecrypting…
Data
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10.0.2.3 12.0.2.3
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System Flow Chart
IP Matcher
PayloadProcessor 1
Timestamp
Source
Destination
Processor 2
Yes
Encrypt/Decrypt
Unmodified Packet
Modified Packet
No
Packet
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Multi-threading with branch
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LUT4Rs_data(0)Rs_data(1)
BNSBS
BNS = Branch if not setBS = Branch if set
MU
X
Reg File32*8B
ID StageIF Stage
PC
PC
PC
PC
Mod4 Counter
Instruction Memory
4K
Control Unit
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100
200
300
01
ADD
Rs_data(31:0)
Rt_data(31:0)
BNSBS
Rt_data(11:0)
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Branch
50
Taken
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IP Matcher
Memory Bank 0
Memory Bank 1
64-bit 64-bit
64-bit 64-bit
4 Unit Comparator Block
Payload
Timestamp
Source
Destination
Packet
Processor and
Timestamp Register
Match
Data Out a
Data Out b
Data Out a
Data Out b
Data In
64 bit IP
64 bit IP
NoMatch
If Found
Else
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ENCRYPTER/DECRYPTER
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Timestamp Reg
Table of Keys
ENCRYPT
DECRYPT
EN1
EN2
DATA_IN
DATA_IN
Timestamp from Header
DATA_OUT
DATA_OUT
IN F
IFO
Arbi
ter
IP Matcher
Encrypt / Decrypt
OU
TPU
T Q
UEU
ES
IP Matcher
Encrypt / Decrypt
PF
PF1
PF
PF2PF3PF4PF5PF6PF7PF8
PF
PF1PF2PF3PF4PF5PF6PF7PF8
MATCH!!
PF5PF4
MAC IDs
PF4PF5
NO MATCH!!
DONE!!
Multi-core ImplementationCalculatingchecksum..
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MAC IDs
ComparingMAC ID..Encrypt
data!
Future Scope Of Work
Use of sophisticated encryption/decryption techniques.
Implementation of bloom filter for ip matcher
Two dummy threads to be used for additional network functionalities.
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Evaluation of Project
Evaluation Methods Secure transmission of data in
between nodes Throughput measurement
Project Results evaluation logic functionality Check Bug Analysis Rectify Design Compare With The Software
Emulation Results
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PROGRESS REPORT
Phase Description Date
Single Core Processor with Multi Threading
04/23/2013
Hardware Accelerators Design Simulation
Multi Core Processor with Multithreading
Hardware Accelerators Individual Implementation
Integration of Hardware Accelerators with Multicore
Processors
Evaluation of the System
Status
04/23/2013
05/07/2013
04/30/2013
05/02/2013
05/10/2013
Completed
Completed
Pending
In Progress
In Progress
Pending14
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