timing analysis section 2.4.2. delay time def: time required for output signal y to change due to...

Timing Analysis

Section 2.4.2

Delay TimeDef: Time required for output signal Y to change due to change in input signal X

Up to now, we have assumed this delay time has been 0 seconds.

F(x)X Y

t=0 t=0

Delay Time

In a “real” circuit, it will take tp seconds for Y to change due to X

F(x)X Y

t=0 t=tp

tp is known as the propagation delay time

Timing Diagram

We use a timing diagram to graphically represent this delay

X

Y

time,s

time,s

t=0

t=tp

0

1

0

1

Horizontal axis = time axisVertical axis = Logical level axis (Logic One or Logic Zero)

Timing Diagram

We see a change in X at t=0 causes a change in Y at t=tp

Horizontal axis = time axisVertical axis = Logical level axis (Logic One or Logic Zero)

X

Y

time,s

time,s

t=0

t=tp

0

1

0

1

t=T

t=T+tp

Timing Diagram

We also see a change in X at t=T causes another change in Y at t=T+tp

We see that logic circuit F causes a delay of tp seconds in the signal

X

Y

time,s

time,s

t=0

t=tp

0

1

0

1

t=T

t=T+tp

Simple Example – Not Gate

X Y

Let tp=2 ns Where ns = nanosecond = 1x10-9 seconds

X

Y

time,ns

time,ns

0

2

2ns

Simple Example – 2 Not GatesLet tp=2 ns

X

Z

4

Y0 2 6 8 t,ns

X Z Y

Total Delay = 2ns + 2ns = 4ns

2ns

2ns

4ns

Simple Example – 2 Not GatesNotes:

Time axis is shared among signals Logic levels (1 or 0) are implied, not shown

X

Z

4

Y0 2 6 8 t,ns

Simple Example – 2 Not GatesSometimes dashed vertical lines are added to aid reading diagram

X

Z

4

Y0 2 6 8 t,ns

2ns 2ns 2ns 2ns 2ns

Where does this delay come from?

Circuit Delay

Circuit Delay

All electrical circuits have intrinsic resistance (R) and capacitance (C).

C R

Let’s analyze a simple RC circuit

Circuit Delay – Simple RC Circuit

R

CVin(t)

Vout(t)

1 expout dd

tV t V

RC

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 1 2 3 4 5 6 7

Vout

Vin

0.69 0.5

2.3 0.9

4.6 0.99

x out x dd

x out x dd

x out x dd

t V t V

t V t V

t V t V

Note:

timeconstantRC

Circuit Delay – ExampleR

CVin(t)

Vout(t)

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 1 2 3 4 5 6 7

Vout

Vin

Let R=1ohm, C=1F, so that RC=1 second

Time Delay is 0.7s or 700 ms for 0.5VddTime Delay is 2.3s for 0.9VddTime Delay is 4.6s for 0.99 Vdd

How do we relate this to logic diagrams?

Def: tplhtplh = low-to-high propagation delay time This is the time required for the output to rise from 0V to ½ VDD

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 1 2 3 4 5 6 7

tplh

Def: tphlTphl = high-to-low propagation delay time This is the time required for the output to fall from Vdd to ½ VDD

tphl

0

0.1

0.2

0.3

0.4

0.5

0.6

0.7

0.8

0.9

1

0 1 2 3 4 5 6 7

Def: tp (propagation delay time)

Let’s define tp = propagation delay time as

1

2p plh phlt t

This will be the “average” delay through the circuit

Gate Delay – Simple RC Model

R

Vin(t)

Vout(t)

C

Vout(t)Vin(t)

Ideal gate with RC network Equivalent model withGate delay of tp_not

Ideal gate with tp=0 delayRC network

Tp=tp_not

Gate Delay - Example

X

0 25ns

0 5ns 30ns

Y

X Y

5ns

tp_not

We indicate tp on the gate

Combinational Logic Delay

A

B

CD

Y

5ns

5ns

5ns

5ns

5ns

Shortest delay

Longest delay

Longest delay = 20nsShortest delay = 5ns

This circuit has multiple delay pathsA-Y = 5ns+5ns+5ns=15nsB-Y = 5ns+5ns+5ns+5ns=20nsC-Y = 5ns+5ns+5ns=15nsD-Y = 5ns

, , ,F a b c d D AB B C

Combinational Logic Delay

A

B

CD

Y

5ns

5ns

5ns

5ns

5ns

Shortest delay

Longest delay

Longest delay = 20ns

We’ll use the longest delay to representthe logic function F.

Let’s call it Tcl for time, combinational logic


Combinational Logic (CL) Cloud Model

A

B

C

DE

Y

5ns5ns

5ns

5ns

5ns

F

tcl

X Y

Tcl=20ns

Tcl=20ns


Logic Simulators

Used to simulate the output response of a logic circuit.

Logic Simulations

Three primary types Circuit simulator (e.g. PSPICE)

“Exact” delay for each gate Most accurate timing analysis Very slow compared to other types

Functional Simulation (e.g. Quartus ) Assumes one unit delay for each gate Very fast compared to other types Most inaccurate timing analysis

Timing Simulation (e.g. Quartus) Assumes “average” tp delay for each gate Not the fastest or slowest timing analysis Provides “pretty good” timing analysis

TPS Quizzes

Timing Quiz 1

Calculate all delay paths through the circuit shown below

A

B

CD

Y

2ns

5ns

8ns

5ns

10ns

What is the shortest and longest delay?

Solution: Calculate all delay paths through the circuit shown below

A

B

CD

Y

2ns

5ns

8ns

5ns

10ns

This circuit has multiple delay pathsA-Y = 5ns+5ns+10ns=20nsB-Y = 2ns+5ns+5ns+10ns=22nsB-Y = 8ns+5ns+10ns=23nsC-Y = 8ns+5ns+10ns=23nsD-Y = 10ns

Shortest path=10nsLongest path=23ns

Timing Quiz 2

Given the circuit below, find(a) Expression for the logic function(b) Longest delay in original circuit

Solution: Given the circuit below, find(a) Original logic function(b) Longest delay in original circuit

Y AC B C C Longest Delay = 7ns+7ns = 14ns

Timing Quiz 3

Given the circuit below,(a) Using Boolean Algebra, minimize the logic function(b) Longest delay in minimized circuit

Delay times are NOT gates= 2ns; AND,OR gates= 5ns NAND, NOR gates= 7ns; XOR gates: 10ns XNOR gates: 12ns

Solution: Given the circuit below, find(a) Minimized logic function(b) Longest delay in minimized circuit


You can show

Y AC

Solution: Given the circuit below, find(a) Minimized logic function(b) Longest delay in minimized circuit


Y AC

Longest delay is 7ns

Y AC

Solution Expanded

Y AC B C C

( )

Y AC B C C AC B C C

AC C A C C AC

Given the circuit below,(a) Using a Truth Table and a K-map, minimize the logic function

Solution

Do yourself!

D-FF Timing

Section 6.3.3

Def: Clock Period and Switching Frequency

ClK

Tc = cycle period, seconds

0 Tc

Switching frequency,

1

c

fT

D-FF Timing Parameters

Q

QSET

CLR

D Qn+1D

Pre

Rst

Clk

tsu thd

tq

Clk

D

q

Timing Diagram

0Tsu= setup time D must be stable (unchanging) tsu seconds before the clock edgeThd = hold time D must be stable thd seconds after the clock edge.Tq = register delay time Q becomes valid tq seconds after the clock edge.

time

If Tsu or Thd are violated, data are NOT stored in D-FF

Maximum Switching Frequency

How fast can our circuits operate

CLK

Reset

No delay on this net

CLFtcl

REG

IN OUT

tin

Input Buffer Output Buffer

X Ytouttq

thdtsu

Maximum Switching Frequency Model

W

We need to find the minimum time, Tc,min, needed to propagate a signal from input X to node W.

No feedback and thd=0ns

CLK

Reset


CLFtcl

REG

IN OUT

tin


X Ytouttq

thdtsu

Maximum Switching Frequency Model

W

From the model, we see that the minimum cycle time is

,minc in cl suT t t t Register Setup time

No feedback and thd=0ns

Timing Diagram Maximum Switching Frequency

tin+tcl tsu tin+tcl tsu

ClK

W

Y tq+tout tq+tout

X Tc.min Tc.min

Tc,min

,minc in cl suT t t t max,min

1

c

fT

This model assumes tq+tout < tin+tcl+tsu

Setup Time Violation

tsu

tin+tcl tin+tcl

tin+tcl

0 Tc

Clock

Ideal Case

Clock tooFast

tin+tld

tin+tld

tsu

tsu

We have a setup time violation because the clock is too fast!!!

Clock is too fast!!!

Correcting a Setup Time Violation

1. Slow down the clock so that

c in cl suT t t t

However, in most cases, Tc is a system parameter which cannotbe changed. Plus, most users want their designs to go faster notslower.

2. Use a pipeline design. Let’s examine this option more closely.

CLK

Reset


CLFtcl

REG

IN OUT

tin


X Ytouttq

thdtsu

Original Design

W

max,

1 1,original cl in su

in cl su cl

f for t t tt t t t

CLF1tcl1

Y

tcl2

CLF2X

F Logic

Let’s break the F Logic into two components, so that F = F1 + F2 and tcl = tcl1 + tcl2

Pipeline Design

CLK

Reset


IN OUT

tin


X Ytout

REGtq

thdtsu

CLF1

tcl1

REGtq

thdtsu

CLF2

tcl2

Pipeline Design

Now, let’s add two register blocks. One between F1 and F2 andanother one at the output.

CLK

Reset


IN OUT

tin


X Ytout

REGtq

thdtsu

CLF1

tcl1

REGtq

thdtsu

CLF2

tcl2

Pipeline DesignMinimum Cycle Time for Each Stage

,1 ,1c in cl suT t t t ,2 ,2c q cl suT t t t

Stage 1 Stage 2

in qLet t t

Stage 1 Stage 2

For simplicity,

CLK

Reset


IN OUT

tin


X Ytout

REGtq

thdtsu

CLF1

tcl1

REGtq

thdtsu

CLF2

tcl2

Pipeline DesignMaximum Switching Frequency Calculation

Stage 1 Stage 2

,min ,1 ,2max ,c c cT T T max,min

1

c

fT


,1 ,1c q cl suT t t t ,2 ,2c q cl suT t t t

,min ,1 ,2max ,c c cT T T

where

,1 ,2 2cl

cl cl

tLet t t

,min ,2 2 2cl cl cl

c q su su q

t t tT t t for t t

;

max, max,,min

1 22PL original

c cl

f fT t

We have,

or,

so,

CLK

Reset


IN OUT

tin


X Ytout

REGtq

thdtsu

CLF1

tcl1

REGtq

thdtsu

CLF2

tcl2


Stage 1 Stage 2

In other words, the pipeline design can run 2x as fast as the original design. Let’s look at a timing diagram to see why.

Pipeline Design Timing Diagram

tq+tcl

0 Tc

Clock

tsu

tsu

2Tc

tq+tcl1 tsutq+tcl1

tsutsutq+tcl2 tq+tcl2

OriginalDesign

Stage1

Stage2

Stages 1

and 2 run

in parallel

Too Slow

End of Lecture

N-stage Pipeline Design

Pipeline Design

Reg

tsu,thd,tq

CLTld,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTld,2

Stage 2

Reg

tsu,thd,tq

CLTld,n-1

Stage n-1

Reg

tsu,thd,tq

CLTld,n

Stage n

OutputsINPUTS

PIPE

Let’s extend this concept to an N stage pipe

What is the maximum switching frequency?

Let the total logic delay Tcl = Tcl1+Tcl2+ …. + Tcl,N

Pipeline Design

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

,cl

q in cl n

TLet t t and t

N i.e. all stages have equal delays.

We have for each stage: ,cl

c n q su

TT t t

N

Pipeline Design

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

Now, assume cl

su q

Tt t

N

,min ,cl cl

c c n q su

T TT T t t

N N So

max,min

1original

c cl

Nf Nf

T T

Or,

Pipeline Design

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

In other words, the pipelined design will operate N times faster than the original design.

pipe originalf Nf

Pipeline Design

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

Now, let’s set N

,min ,cl

c c n q su q su

TT T t t t t

N So

0 0 0 0

0

,minc q suT t t Or, constant

Pipeline Design

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

So,

max,min

1 1

c q su

fT t t

constant

Pipeline Design

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

In other words, the absolute maximum frequency of any design is fixed at

max,min

1 1

c q su

fT t t

We can use this formula to perform a “back of the envelope” calculation todetermine if a desired switching frequency is “feasible”

Pipeline Design- Tradeoffs

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

The pipeline approach is a very powerful design technique. However, we have two major trade-offs using a pipelined design. They are

1. Data Load Time and 2. Data Latency Time

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

DATA Load Time

At power-up, we must first “load” the pipeline. This will require a time of

,mincl

load c q su q su cl

TT NT N t t N t t T

N

N Note as, loadT we find,

unacceptable

Reg

tsu,thd,tq

CLTcl,1

Out

tout


Stage 1

.....Inptin

Reg

tsu,thd,tq

CLTcl,2

Stage 2

Reg

tsu,thd,tq

CLTcl,n-1

Stage n-1

Reg

tsu,thd,tq

CLTcl,n

Stage n

OutputsINPUTS

PIPE

DATA Latency Time

Data will require a finite time to progress through the pipe, this is equivalent to the Data load time.

,mincl

latency c q su q su cl

TT NT N t t N t t T

N

N Note as, latencyT we find, unacceptable

timing analysis section 2.4.2. delay time def: time required for output signal y to change due to...

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