timing variations

8/3/2019 Timing Variations

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2/13/2003 Liang-Teck Pang 1

Death, Taxes and Failing ChipsChandu Visweswariah

IBM Thomas J. Watson Research Center, Yorktown Heights, NYDAC 2003

Courtesy C. Visweswariah


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Outline Why do we need Statistical Design?

What is a Statistical Timer?

Methodologies Wish-list of a statistical timer

Synthesis

Modeling and characterization

Conclusion


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Breakdown of Static Timer Increase in significance and independence of the

sources of variation.

Critical dimensions scaling faster than our control of them,eg L/L increasing

Within-chip variations are significant, eg Across-the-ChipLinewidth Variation (ACLV), temperature and voltagegradients across chip

Case analysis overly pessimistic & number of sign-offtiming runs too large

Pessimistic and Risky!


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Improvement with Statistics Reduce inaccuracies in modeling

eg same gate used in a data path and the correspondingclock path that latches it, inaccuracy in modeling cancels out

Treat coupling noise and other noise in probabilisticmanner instead of assuming worst case scenario

Reduction in number of sign-off timing runs


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Statistical Timer


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Approaches and Methods Block Based vs Path Based

Performance-space methods vs Parameter-space methods

4-Pronged Effort

Modeling Analysis

Methodology

Synthesis


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Performance-space vs Parameter-space

Circuit performance constraints

JPDF of underlyingsources of variation



Methodology ASIC vs Microprocessor


Risk management

with PSROs(Performance-SensitiveRing Oscillators) andappropriate sign-offcriteria

Environmental vs.manufacturing variations



Wish List of a Statistical Timer Correlations

Bounded vs statistical analysis

Slew and load dependance Within-die variation

Accuracy

Flexibility


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Correlation Importance of correlations

consider a circuit with 50K latches, each with a

setup and hold test, each of which has a 99.99%probability of being met

if all tests are perfectly correlated, yield=99.99%

if all tests are perfectly independent, yield is

0.005% the truth is closer to the perfectly correlated case!


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Examples of Correlations Reconvergent Fanout (path sharing)

Clock correlation (commonality between data and clock path)

Dependence on global parameters (chip-to-chip, wafer-to-wafer,

lot-to-lot) Dependence on proximity (temperature, voltage, ACLV, within-

die)



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Bounded vs Statistical Analysis Treat each source of variation in either a bounded or

statistical manner

Certain variables should be bounded (environmental

parameters)

Random variables with small variation should be bounded toreduce number of random variables

Reduce computation complexity and allows fast initialanalysis


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Slew and Load Dependence Delay depends on input slew and output load

Both vary with process and environment



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Flexibility Flexibility

fit well with rest of existing methodology

reduce number of timing runs required

provide diagnostics



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Other AttributesAbility to handle within-die variation

Accurate prediction of the tail of theslack distribution

Avoid pessimism

Capture correlations


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Statistical Synthesis Use statistical timer to determine impact of changes

Maximise sharing between launching and capturingpaths to minimize effects of variability

Error correction and dynamic body bias control

Use regular layouts when performance loss isacceptable

Tradeoff between catastrophic yield improvementand parametric yield improvement


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Modeling and Characterization Statistical model of transistors, gates and wires are

required

Challenging and difficult task!


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Conclusion Outlines importance of statistical timer

Describes the desired attributes of a

statistical timer


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Paper Review II

Statistical Delay Computation ConsideringSpatial Correlation Aseem Agarwal et al,

ASP-DAC 2003


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Outline Path-Based Statistical Timing Analysis Model

Inter and intra-die analysis method

Model and analysis of spatial correlations Experimental results

Conclusion


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Path-Based Statistical Timing Analysis Full-chip analysisreconvergence problem

Path-basedspatial correlation

Goal:

perform statistical analysis on top-k critical paths of a design include all paths that have possibility of being critical

formulation of gate length, but extensible to other variations

accurate analysis

Consider in the analysis:

inter- and intra-die variation

spatial correlation of intra-die gate length variations

slope propagation

capacitance variation


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Gate Length Model Considers variation due to inter- and intra-die variations

extend later to spatial correlations

Simplifying assumption

Inter-die analysis ( )

all gate delays share a single random variable computed through enumeration ofL

interdistribution

Intra-die analysis ( )

multiple independent random variables with identical distribution


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Use linear approximation to model functional dependence ofdelay, slope and capacitance on the dependent parameters

Collect gate delay coefficients w.r.t each intra-die device length

Given mean and sigma for the normal distribution of

Lintra,i

Delay Computation Using Sensitivities


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Spatial Correlation Model

Courtesy A. Agarwal


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Spatial Correlation Example The path delay due to spatially correlated device length

variation

Delay variation for these gates can be expressed as

Compute analytical solution for the delay distribution


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Experimental Results

comparison with monte carlo for combined inter- and intra-die variability


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Experimental ResultsComparison of

traditional approach lumping intra-die variation with inter-die variation

proposed approach modeling separate inter- and intra-die gate length variation


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Results w/ and w/o intra-die variation


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Results w/ and w/o intra-die variation


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Conclusion Path-based analysis

A method for computing delay distribution of

critical paths

Combining inter- and intra-die variations

Model for spatial correlations

Combined analysis using the above model


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2/13/2003 Li T k P 31

END

timing variations

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