tips and tricks to get more out of your spice models

A-63 Fairchild Power Seminar 2007

Tips and Tricks to Get More Out of Your SPICE Models Scott Pearson, Alain Laprade

Abstract — Circuit simulation tools are useful supplements

to breadboarding for gaining fast and detailed design insight. A collection of simulation tips and tricks used by our applications support group is presented. Fairchild Semiconductor offers interactive on-line design simulation tools and device models for off-line simulations.

I. INTRODUCTION

The various simulation tips presented demonstrate methods to accomplish simulations not possible using only native models included with the ORCAD® simulator. Examples are a resistor with dynamic temperature feedback, voltage controlled reactive models (capacitors and inductors) and analog behavioral models for complex waveforms. Also included in this paper is a discussion of the thermal model and its importance to the designer. Use of the thermal model will give an indication of the junction temperature ensuring device specification are not exceeded. Detailed instructions on how to use the models provided by Fairchild Semiconductor will be provided. Models and instructions given here are applicable for ORCAD® simulation products, but assistance with other simulation tools is available. Another option offered to designers is on-line simulation tools such as FETBench®, which will be introduced here.

Finally, circuit simulation convergence can be a frustrating issue. Tips are described which can minimize such issues. Fixes which improve convergence can also result in reduced simulation times.

II. A PSPICE RESISTOR MODEL HAVING

DYNAMIC TEMPERATURE CAPABILITY

Use of dynamic temperature information within a closed loop system simulation can run into algorithm limitations with some simulation software such as PSPICE. The SPICE resistor model may be set to have temperature dependence as in the listing from Table I. PSPICE will only run simulations at a single temperature defined in the simulation setup menu, and this temperature setting cannot be varied

dynamically during the simulation. A temperature sweep will perform independent static simulations at various temperatures.

TABLE I RESISTOR TEMPERATURE COEFFICIENT SPICE LISTING Rvtemp 18 19 RvtempMOD 1 MODEL RvtempMOD RES (TC1=-2.5e-3 TC2=1e-6)

The ability to describe the value of a resistor and

its temperature coefficients as an analog behavioral model (ABM) referenced to a voltage node (making use of electrical thermal analogy) is necessary to express dependence on operating temperature. Voltage node references within PSPICE resistor models are not permitted. Dynamic temperature dependence of resistive elements (expressed as separate lumped elements) cannot be implemented without a resistor ABM.

This limitation is overcome with a voltage-controlled current source ABM expression (Fig. 1). By using the nodes of the current source for voltage control, resistor behaviour may be expressed as a current source as in (1). Resistance R(Td) is replaced with a behavioral mode analytical expression that is a function of the electrical analogy voltage node Td as shown in the next section. The form for the ABM netlist expression is described in Table II.

)T(RV

Id

= (1)

I=V/R(Td)

+

-

I

+

-

Fig. 1 Implementing a voltage dependent ABM resistor model. TABLE II Voltage Dependent ABM resistor model netlist. G_Resistor Node1 Node2 Value=V(node1,Node2)/ +function(V(Td))


III. THERMAL MODELING

Semiconductor devices often operate at high junction temperatures. Understanding their thermal limitations is important to achieve good device reliability and system performance targets. Circuit designers are responsible for performing junction temperature calculations to verify that their devices operate within manufacturer specifications.

Measurement of semiconductor thermal response involves a calibrated power pulse. Power dissipated within a device causes a junction temperature rise because of the thermal impedance from the die and package. (2) describes thermal impedance as the result of a change in junction temperature divided by power dissipation.

D

JJ

D

JJC P

)0(T)t(TP

)t(T)t(Z

−=∆=θ (2)

A basic semiconductor thermal model and its

electrical analogue is shown in Fig.2. Heat is generated at the device junction and flows through the silicon to the case, and finally to the heat sink.

PowerDissipation

G_Pdiss

ZθJC ZθSAZθCS

Die

Transistor

Tcase

Heat sink

Tambient

Insulator &interface

Tjunction Tsink

PowerDissipation

G_Pdiss

ZθJC ZθSAZθCS

Die

Transistor

Tcase

Heat sink

Tambient

Insulator &interface

Tjunction Tsink

Fig. 2 Semiconductor thermal impedance model.

Junction temperature information is determined

by the inclusion of the device’s thermal network ZθJC and current source G_PDISS. The thermal network parameters are supplied in Fairchild Semiconductor data sheets. G_PDISS is the semiconductor’s instantaneous operating loss, and expresses the result in the form of a current. This is

a circuit form representation of the junction temperature as expressed in (3).

)ZZZ(Pdiss_GTT SACSJCambientJ θθθ ++•+= (3)

where

TJ = junction temperature G_Pdiss = instantaneous power loss ZθJC = thermal impedance junction-to-case ZθCS = thermal impedance case-to-heat sink ZθSA = thermal impedance heat sink-to-ambient.

The unit conversion for the electrical analogy of the thermal system is listed in Table III. ZθJC is provided in manufacturer data sheets using the single pulse normalized thermal impedance curve as in Fig. 3. ZθJC may be represented using an equivalent electrical analogy model as in Fig. 4. TABLE III ELECTRICAL/THERMAL ANALOGY

Electrical ⇔ Thermal Ohm (resistance) oC/Watt (thermal resistance) Farad (capacitance) Joules/oC (thermal capacitance) Amp (current) Watt (power) Volt (voltage) oC (temperature)

Fig. 3 Normalized maximum transient thermal impedance.

Fig. 4 Semiconductor thermal impedance model. When model parameters are unavailable, they may be derived from the datasheet RθJC and from the single pulse normalized thermal transient impedance curve data points. The electrical analog model may be expressed as in (4). The R-C parameters may be obtained by using curve fitting software such as TableCurve 2D® [15].

)e1(R)e1(R)t(Z 6611 CR

t

6CR

t

1⋅

−⋅

−

−⋅++−⋅= Κ (4)


Knowing operating waveforms and system level

thermal impedance information, thermal response to complex waveforms may be analyzed. An example circuit and simulation result for a MOSFET operated under continuous conduction is shown in Fig. 5, where a 60A/40ms current pulse is applied to an FDB8445 MOSFET [12] having a case temperature of 120oC. The simulation is in closed loop form. The temperature dependent RDS(on) and junction temperature responses are shown in Fig. 6.

Fig. 5 Electrical analogy of system losses.

0

10

20

30

40

50

60

70

0 5 10 15 20 25 30 35 40 45 50

Time (ms)

Cu

rren

t (A

)

100

120

140

160

180

200

220

240

Tem

per

atu

re (o

C)

I(I4) (A) V(Tjunction) (C)

0

5

10

15

20

25

0 5 10 15 20 25 30 35 40 45 50

Time (ms)

Res

ista

nce

(mO

hm

s)

V(Vds)/ I(V4) (mOhms)

Fig. 6 Simulation results.

The FDB8445 MOSFET thermal impedance

model is provided by an RC ladder network (R1-R6, C1-C6). The MOSFET RDS(on) is modeled with a voltage dependent current source ABM model G6.

Instantaneous power dissipation information is evaluated with ABM current source G8 by multiplying the drain-source voltage with current I(V4) flowing through the MOSFET resistance. (Zero-volt source V4 is included to measure current.) Case temperature is set with voltage source Vcase. A more detailed system level thermal impedance network could be implemented in place of Vcase. Instantaneous junction temperature information Tjunction is the result from the closed loop simulation.

IV. SIMPLE VOLTAGE CONTROLLED REACTIVE

MODELS

In this section, simple non-linear inductor and capacitor SPICE model implementations are described. These models are most suited when device non-linear performance characteristics are known, but their non-linear physical characteristics are difficult to derive. PSPICE includes in its ANL_MISC.LIB library a 5-terminal non-linear inductor model ZX (Fig. 7) and a non-linear capacitor model YX. The ZX and YX node definitions are listed in Tables IV and V. Functional blocks from these library models were recreated in Figs 8 and 10 using available PSPICE symbols to facilitate the numerical derivation of the library functions. Node numbers 1 through 5 are marked to facilitate functional reference with the existing PSPICE ZX and YX library files. Node 5 would normally be connected to a load. With a device specific behavioral voltage source model, the ZX and YX models can be made to operate non-linearly with the use of voltage dependent input nodes 1 and 2 which multiply the voltage from node 3.

Fig. 7 PSPICE ANL_MISC.LIB ZX Symbol

A. Non-Linear Inductance Model.

Power supply filter inductors and solenoid coil inductance are examples of devices having non-linear properties.


The equivalent schematic representation of the non-linear inductance model ZX is shown in Fig. 8. Model response to a sudden change of inductance value is shown in Fig. 9. The simulation consists of an AC voltage source connected in parallel to a non-linear 1µH inductor having a series resistance of 0.01Ω. Rin is used to aid with convergence.

Fig. 8 Voltage-controlled inductance model.

TABLE IV ZX MODEL NODE DEFINITION

1: control input voltage (+) 2: control input voltage (-) 3: reference inductor/resistor (connect other lead to ground) 4: output (floating impedance) 5: output (floating impedance)

Fig. 9 Voltage-controlled inductor model response.

When an inductor is energized, current cannot change instantaneously. By Faraday’s law:

td

idLrefV Lref

3 ⋅= (5)

By substitution (Fig. 8),

3control4 VVV ⋅= (6)

td

id)LrefV(V Lref

control4 ⋅⋅= (7)

RinductorLref ii = (8)

td

id)LrefV(V Rinductor

control4 ⋅⋅= (9)

The simulated inductor voltage drop VL corresponds to the total voltage drop between nodes 4a and 5 (to include winding resistance Rinductor).

RinductorRinductor

controlL iRinductortd

id)LrefV(V ⋅+⋅⋅= (10)

where VL = voltage across the non-linear inductor iRinductor = non-linear inductor current 0 < Vcontrol < 1.

B. Non-Linear Capacitor Model

Capacitor models that can be expressed using a non-linear model include certain ceramic capacitor types and MOSFET capacitance which have non-linear voltage dependent properties. The equivalent schematic representation of the non-linear capacitor model YX is shown in Fig. 10. Model response to a sudden change of capacitance value is shown in Fig. 11. The simulation consists of an AC voltage source connected in parallel to a non-linear 1µF capacitor. Rin is used to aid with convergence.

Fig. 10 Voltage-controlled capacitor model YX.

-2.0-1.5-1.0-0.50.00.51.01.52.0

140 145 150 155 160 165

Time (µs)

Vo

ltag

e o

r C

urr

ent

I(Rinductor) (A) V(4a) (V)

0.00

0.25

0.50

0.75

1.00

1.25

140 145 150 155 160 165

Time (µs)

Indu

ctan

ce (

µH)

V(4a)/d(I(Rinductor)) (uH)

L = 0.25µH

L = 1µH

Vcontrol = 0.25VVcontrol = 1.0V


TABLE V YX MODEL NODE DEFINITION

1: control input voltage (+) 2: control input voltage (-) 3: reference capacitor (connect other lead to ground) 4: output (floating impedance) 5: output (floating impedance)

Fig. 11 Voltage-controlled capacitor model response. Capacitor voltage may be expressed as

∫ ⋅⋅= tdiCref

1V CrefCref (11)

FCOPYCREF ii =

∫ ⋅⋅= tdiCref

1V FCOPYCref (12)

4Cref VVcontrolV ⋅= (13)

∫ ⋅⋅⋅

= tdiCrefVcontrol

1V FCOPY4 (14)

where V4 = non-linear capacitor voltage iFCOPY = non-linear capacitor current 0 < Vcontrol < 1

V. USING BEHAVIORAL MODELING FOR

COMPLEX WAVEFORM CIRCUITS

Evaluating device performance with non-repetitive waveform topologies can be a daunting task. In situations in which IGBT and diode losses require accurate modeling, meaningful results may be a difficult to obtain. Device models, if existent, may have limited accuracy. Simulations required to

achieve steady state information may also require significant run-time. Through the use of characterization data selected under relevant operating conditions, device behavioral models may be prepared. These models may then be used as building blocks for complex topologies.

A. Complex Waveform Circuit

Application of modern high speed IGBTs in SMPS circuits can provide cost and conduction loss advantages. In PFC circuits (Fig. 12), each switching operation occurs at a different current and duty cycle. IGBT losses (Fig. 13) are a non-linear function of the collector current, collector voltage and junction temperature. The loss plane represents IGBT turn-off losses at a single clamp voltage (400 VDC).

Current Sense Resistor

D1 D2

D3 D4

VacInput

VacABS Vout

C1IGBT

Boost DiodeBoost Inductor

PFC ControlCircuit

IL1

390Vdc

90 Vrms50Hz

Fig. 12 Boost PFC circuit block diagram.

Eoff (µ joules)

Tj (oC)

Icollector (amps)

Fig. 13 Three-dimensional Eoff plot.

A behavioral modeling technique for determining losses and junction temperature of an IGBT operating in a switched mode power circuit is described. Full PFC circuit implementation in

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0 5 10 15 20 25

Time (µs)

Vo

ltag

e o

r C

urr

ent

I(V2) V(4)

0

200

400

600

800

1000

1200

0 5 10 15 20 25

Time (µs)

Cap

acit

ance

(n

F)

(1/V(4))*S(I(Fcopy))

C = 0.25µH

C = 1µFVcontrol = 0.25V

Vcontrol = 1.0V


closed loop form using behavioral modeling for switching information, loss calculations and control are described in detail in [2, 4]. The transistor transient thermal impedance model is used within this feedback loop.

B. Behavioral Model Equations

Techniques expressing empirical IGBT test data into loss equations are described in [1]. The on-state voltage (VCE(sat)), turn-off loss (Eoff) and turn-on loss (Eon) expressions are described in equations (15)–(17) for typical performance of the HGTG12N60A4D IGBT [3].

( )( )( )( )

+⋅+⋅

+⋅+⋅+⋅

+⋅⋅+⋅+⋅

=

a9Tja82Tja7

a11Ia6Tja52Tja4

Ia10ea3Tja22Tja1

I,TjVsat (15)

( )

( )( )( )

⋅+⋅

+⋅⋅+

+⋅⋅⋅+

⋅⋅+⋅

=

TjbIb

ITjbb

IbeTjbb

IbbclampV

,I,TjclampVEoff

726

54

321

98400

(16)

( ) ( )( )

⋅+⋅⋅++⋅+⋅+⋅⋅+⋅

=⋅

Tj8cITj7c6cI5cTj4ce3c2cV1c

TjIVEon2Tj10c

9c

),,(

(17)

Turn-off expression (16) and coefficients b1 through b7 correspond to IGBT performance in a clamped inductive turn-off switching circuit. Expression (17) describes the hard-switched Eon2 turn-on losses with the IGBT which includes losses from an external diode (equivalent to that in the co-packaged version of the IGBT) reverse recovery current. The junction temperature of this external diode is assumed to correspond to that of the co-packaged HGT12N60A4D IGBT (a semiconductor characterization practice). The loss coefficients were developed using a 15V IGBT gate drive waveform. These equations may be used to represent other IGBT types by developing a new set of coefficients [1]. The outputs of (16) and (17) are the IGBT turn-off and turn-on losses in joules per switching-cycle. Coefficient values are provided in [3].

C. IGBT Behavioral Model Input Voltages and Currents

To demonstrate the SPICE implementation of (15)-(17), an HGTP12N60A4D IGBT behavioral model was developed [2] using the Intusoft SPICE simulator “B” function as shown in Fig. 14. A basic sub-circuit avgIGBT was developed to provide an effective means of adding additional IGBT model types. The sub-circuit was designed to receive six inputs and provide three outputs, all referenced to Tcase. Two bi-directional terminals, Tj and Zjc, provide a circuit interface to the IGBT's thermal impedance model. A schematic symbol avgIGBT was generated to provide a simple method of implementing this component in a SPICE schematic. Model and symbol input are defined as: Iton = Load current at IGBT turn-on Ion = Average IGBT collector current during conduction Itoff = Collector current at IGBT turn-off Tj = IGBT and clamp diode junction temperature Vton = IGBT collector voltage at turn-on Vtoff = IGBT collector clamp voltage at turn-off

Output Eon represents the Eon2 turn-on energy loss (J) for the Iton, Vton and Tj input values. Output Eoff represents the turn-off energy loss (J) for the Itoff, Vtoff and Tj input values. Output Vsat is the saturated on-state voltage for the Ion and Tj inputs. The IGBT’s junction to case thermal impedance is represented as a multi-stage RC ladder network internally connected between Zjc and Tcase. Whereas the Tj schematic-symbol terminal is provided for open-loop simulation, the Zjc terminal is used for closed-loop simulation by connecting it to Tj and supplying this node with a current equal to total IGBT losses (W). Because the thermal impedance network is internally connected between Zjc and Tcase, the voltage at terminal Zjc is equal to the IGBT junction temperature (1V = 1oC) as long as Tcase is set to a voltage equal to the case temperature.


6 Eoff

2

1

Icollector

Tjunction 5 Vsat

4

7 Eon

Ion

Iton

Itof f

Vton

Tj

Eon

Eof f

Vsat

Vtof f Tcase

Zjc

X2HGTP12N60A4

V3 V5390

V6

Turn-Off Loss (joules)

Turn-On Loss (joules)

Vsat (volts)

Icollector (amps)

Tjunction (degrees C)

V(1)

Tran

21.0

-1.003.000 tim e

V(2)

Tran

127

72.53.000 time

V(5)

Tran

2.03

621M3.000 time

V(6)

Tran

434U

-18.7U3.000 time

V(7)

Tran

635U

-20.5U3.000 time

Fig. 14 Basic IGBT behavioral model avgIGBT.

45

23

42A

B

A/B

1

9

PACKAGE

5

4

28

15

17

24

22

SwitchingFreq

Pk toPkRippleI

SwitchingFreq

VacInput

Ccase_sink5.75E-1

Rsink_amb1.15

Rcase_sink.55

X25

G11

Csink_amb1

ON_STATE_LOSS

Tjunc tion

Eon_Joules

Duty_Cycle

VAC_IN

Eoff_Joules

VCE_ON

TURN_OFF_LOSS

DutyCycle

DutyCycle

VinABS

21

Vout390

Vout

Vout

V_Initial_Temp110V

SUM2

K1

K2

18

36

X8K1 = 1K2 = 0.5

SUM2

K1

K2

X15K1 = -0.5K2 = 1

PktoPkRippleI

PktoPkRippleI

EonWatts

Turn_On_Loss

Iton

Itoff

Ion

26

X9SWITCH

V6

DutyCycle

T_Sink

Ion

Iton

Itoff

Vton

Tj

Eon

Eoff

Vsat

Vtoff Tcase

Zjc

X2HGTP12N60A4

AC Input Voltage

AC Input Current1 Volt per Amp

ABS6

X3ABS

ABS

X17ABS

A

B

A/B

X12DIVIDE

SUM2

K1

K2

X11K1 = 1K2 = -1

VacABS

IGBT Duty Cycle

Switching Frequency1 Volt/Hz

Av erage On-State Current1V/amp

Vpout500V

Power Out1V=1W

Pout

Vrms90

VinRMS

Vrms Input1V=1V

V9

1.4142 Vpeak50Hz

A

B

K*A*B

X10MULK = 1Vref

A

B

A/B30

X13DIVIDE A

B

K*A*B

X18MULK = 1

A

B

K*A*B

X19K = 1

A

B

K*A*B

X20K = 1

Value of Boost Inductor1V=1Henry

Vamb50Vdc

T_Case

Ambient Temp1V=1 degree C

Peak-to-PeakBoost InductorRipple Current

Ripple_Current

Tj

Junction Temperature

VacABS

DC Output Voltage

VL1500uV

Vfreq100kV

A

B

K*A*B

X5K = 1

A

B

K*A*B

X6K = 1

EoffWatts

A

B

C

K*A*B*C

X1K = 1

OnStateWatts

SUM3

K1

K2

K3

X7K1 = 1K2 = 1K3 = 1

Total IGBT Losses

DUTY CYCLE

Tran

1.02

657M500M480M time

V(18)

Tran

8.25

-393M500M480M time

RIPPLE_CURRENT

Tran

1.80

-85.7M500M480M time

V (5)

Tran

39.1

-264M500M480M time

TJ

Tran

113

104500M480M time

VA CABS

Tran

134

-6.36500M480M time

Fig. 15 PFC behavioral model implementation.


D. Behavioral Model Implementation

In Fig. 14, a 0 to 20V 1Hz ramp is applied to the model Iton, Ion and Itoff terminals representing a 0 to 20A 1Hz collector current. The junction temperature is stepped from 75 to 150oC 1.5 seconds into the simulation while the turn-on (Vton) and turn-off (Vtoff) voltages are maintained at 390V. Analysis of the wave shapes on the right side of the schematic reveal the impact the current and temperature changes have on the model outputs. Fig. 15 illustrates a closed loop form implementation of the behavioral model within a power factor controller circuit. Functional description is provided in [2]

VI. DIODE REVERSE RECOVERY CURRENT

WAVEFORMS: ACCURACY LIMITATIONS

Diode reverse recovery current (IRM) is an included function with each of Fairchild’s MOSFET PSPICE models. It is modeled with a diode in PSPICE. The simulated reverse recovery for the FDB8441 40V 2.5mΩ MOSFET [14] at 25oC for a slew rate of 100A/µs is shown in Fig. 16. Measured results are shown in Fig. 17. Simulated reverse recovery time trr is 50.5ns (di/dt = 100A/µs, 25oC) while the data sheet typical is 52ns thus showing good agreement. While it is accurate under data sheet conditions it may not track over a wide range of operating conditions.

Time

1.95us 2.00us 2.05us 2.10us 2.15us 2.20us 2.25us 2.30usI(X1:s)

-5A

0A

5A

10A

15A

20A

25A

Fig. 16 Simulated FDB8441 diode reverse recovery waveform at 25oC, 100A/µs.

Fig. 17 Measured FDB8441 diode reverse recovery waveform at 25oC, 100A/µs. The vertical scale is 5A per division.

A limitation of this diode model is that there is little trr variation as a function of operating conditions, and simulations at various forward conduction currents show little change in the reverse recovery waveform. For many real devices, however, trr becomes significantly longer at higher forward current, higher di/dt, and higher temperature. Results are summarized in tables VI and VII.

TABLE VI DIODE REVERSE RECOVERY AT VARIOUS TEMPERATURES

ISD=20A, di/dt=100A/µs

Temp (°C) Trr (ns) Irm (A) 25 simulated 50.50 -3.40 25 measured 56 -2.4 125 simulated 49.44 -3.27 125 measured 58 -2.8

TABLE VII SIMULATED DIODE REVERSE RECOVERY AT VARIOUS CURRENTS

Temp=25°C, di/dt=100A/µs

ISD (A) Trr (ns) Qrr (nC) Irm (A) 15 50.39 81.70 -3.45 35 49.70 81.14 -3.54 50 49.35 80.57 -3.53 75 49.51 80.73 -3.52

While these intrinsic body diode models provide

good results, it is important to be aware of their limitations. In practice, the reverse recovery is modeled under data sheet conditions.

These limitations are due to the diode models as implemented in SPICE. The SPICE primitive diode


model is limited in its ability to represent minority charge concentration under operating conditions. Therefore, all SPICE MOSFET intrinsic body diodes and diode models will have these limitations regardless of device manufacturer. Other simulators (e.g. Saber) may overcome these problems but that has not been explored at this time.

VII. CONVERGENCE ISSUES

There are many issues that can lead to simulation convergence problems. Complexity of the circuit being simulated can be a leading cause. As the circuit becomes more complex there are more node voltages and device currents that need to be calculated. Not only can convergence be a problem, but long run times can be a problem with highly complex circuits. One solution here is to simplify the circuit whenever possible. Can the circuit be implemented with a simplified model instead of a detailed complex model? For instance, if one is only concerned with on-state circuit losses, a MOSFET model could be replaced with an ABM resistor model (previously described). The ABM resistor would be modeled to describe the RDS(on) vs. temperature characteristics of the MOSFET. This ABM model could then replace the complex MOSFET model.

Careful placement of large value resistors around parasitic elements can help overcome convergence issues. In circuits where layout parasitic elements must be simulated, placing a 1MΩ in parallel with parasitic capacitors or inductors is recommended. OrCAD® recommends that all inductors have a parallel resistor [5]. Doing so models eddy current losses and bandwidth limitations of inductors at high frequencies. (18) describes the recommended parallel resistance value for a given inductance, where fq is the roll-off frequency resulting from the inductor’s interwinding capacitance.

L*f*2R qπ= (18)

Simulation time and convergence may also be

improved by defining circuit initial conditions. Both capacitors and inductors have initial condition parameters that may be defined. By setting these conditions to the expected operating values, convergence can be greatly improved. Setting

proper initial conditions can also reduce the number of cycles necessary to reach a steady state solution. In some circumstances, a significant reduction in simulation time to reach steady state may be achieved.

Adjusting simulation tolerance settings can also help. These can be set in the simulation profile under the options tab shown in Fig. 18. DC convergence problems can be reduced by selecting the GMIN stepping option.

Fig. 18 PSPICE simulation profile.

Other frequently adjusted options are ABSTOL

and VNTOL. ABSTOL is the accuracy of currents. In most circuits using power devices, accuracy down to the default value 1pA is not required. This can be set to 1µA to improve convergence and simulation time with no noticeable degradation of the simulation output. VNTOL is the accuracy of voltages. The default value of 1µV is generally a good setting. VNTOL can also be relaxed to improve convergence.

Accuracy of charges is defined with CHGTOL. Its default value of 0.01pC can be relaxed to 1.0pC and give good simulation results.

Increasing the various iteration limits ITL1, ITL2 and ITL4 can also be helpful. Each of these can be set to 150 for improved results with complex circuits.

Perhaps the biggest improvement in simulation and convergence can be realized by using Fairchild’s new Bsim3 MOSFET models [13]. The Bsim3 uses a greatly reduced sub circuit macro model to represent the MOSFET. The previous


generation Fairchild Semiconductor SPICE level 1 model has a component count of 36 compared to 14 used in the Bsim3. When running a simplified DC-DC converter, simulation time was reduced by 52%.

VIII. MOSFET SYMBOL USAGE

Fairchild Semiconductor provides MOSFET symbols for use in OrCAD® schematic capture tools. A link to the symbol files can be found in [6]. The symbols files provided are for either OrCAD® Capture or OrCAD® Schematic. The file should be saved in the directory where model library files are located.

From an open schematic, select the icon or menu item to place a new part. The Place Part window is shown in Fig. 19.

Fig. 19 Place Part menu. In this window select Add Library. Browse to

and open the symbol file that was downloaded, and saved to the working directory. From this new library, select the symbol Fairchild MOS Std and place into schematic. Once the MOSFET symbol has been placed the model name will need to be changed. Double click Fairchild MOSFET on symbol just placed and enter the model name to be simulated.

The final step is to add the library to the simulation profile. Within Capture open a

simulation profile and select Configuration Files tab and category Library as shown in Fig. 20.

Fig. 20 Simulation settings menu.

Select the Browse button to locate the library file containing the model to be simulated. Next select the Add to Design button to make the model ready for simulation.

If a different model is to be used at a later point in time, not all of these steps are required. From the schematic, simply change the name of the MOSFET model. Then add the library file to the simulation profile if this has not been previously added.

Alternatively, a library can be added globally to Capture. When adding the library file to the simulation profile shown in Fig. 20 select the Add as Global button. This library file will then be available for all designs in Capture.

IX. FAIRCHILD SEMICONDUCTOR ON-LINE TOOLS

FETBench® is a Fairchild Semiconductor SPICE based design aide that helps designers shorten design times and reduce time to market. This design tool incorporates a wide range of Fairchild low-voltage MOSFETs targeting computing and ultra-portable applications. FETBench® can save, recall and share design simulations. MOSFET models are based on Berkeley SPICE BSIM3 version 3.1 device models, offering broad simulator compatibility. This tool (Fig. 21) may be found on-line [7].

Design activity may be saved for future use. Key FETBench features include:


- MOSFET device selection - Application analysis - Thermal simulation

Fig. 21 Web site FETBench menus

A. Device Analysis Module

This module offers a search capability based on either prior knowledge of an existing device of interest, or on required parametric characteristics. (While this search is limited to MOSFETs suitable for computing and ultra-portable applications, all Fairchild MOSFETs may be searched by selecting “MOSFETs” on the Fairchild home page.) Once a device has been selected, a device analysis menu can perform a number of types of analysis. This module offers:

- Curve Tracer Analysis

i. ID vs VDS (vary VGS, TJ)

ii. RDS(on) vs ID (vary VGS, TJ)

iii. Gate charge vs VGS (vary VDS)

iv. RDS(on) vs VGS (vary ID, TJ)

v. Reverse conduction characteristics ID vs VDS (vary VGS)

- Dynamic Characteristics

i. Switching characteristics

ii. Reverse recovery characteristics

B. Application Analysis Module

Applications analysis along with device selection is made within this module. Key features include:

- Circuit selection

i. Synchronous rectifier buck

ii. Synchronous rectifier buck with FAN5236 controller

iii. Boost converter

iv. Load switch

v. Bi-directional load switch

- Input and output requirement definitions.

- Device selections (device combinations may are permissible)

- In-circuit device analysis

C. Thermal Analysis Module

Once inputs to the Application Analysis Module have been completed and the average power dissipation in each device of interest has been determined, a thermal analysis may be performed with the use of the Thermal Analysis module (Fig. 22). Key features include:

Fig. 22 Example FETBench thermal analysis menus

- Definition of the thermal environment

- Definition of the multilayer PCB design

- Definition of airflow


- Placement of power dissipating components.

X. SUMMARY

Electrical and thermal simulation models as well as behavioral models are useful tools in the hands of the design engineer to gain further design insight. Understanding methods to model real device characteristics not captured in the basic models, plus methods to improve simulation convergence, can increase the value of simulation in the design process. Ultimately improved design robustness can be achieved.

REFERENCES [1] R. H. Randall, A. Laprade, B. Wood "Characterizing IGBT Switching

Losses for Switched Mode Circuits", PCIM Europe 2000, pp. 269-275, June 2000.

[2] R. H. Randall, A. Laprade, A. Craig, "Analyzing IGBT Losses by Translating Empirical Data Into SPICE Behavioral Models", PCIM Europe 2000, pp. 263-268, June 2000.

[3] Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet HGTP12N60A4D, http://www.fairchildsemi.com.

[4] R. H. Randall, A. Laprade, “Behavioral Model Analyzes IGBT Losses in Sinusoidal Circuits“ PCIM Europe 2001, pp. 165-170, June 2001.

[5] “Exploring the Nature of Spice Convergence Problems”, OrCAD Design Network, 5/99.

[6] http://www.fairchildsemi.com/models/PSPICE/Discrete/MOSFET.html [7] http://www.fairchildsemi.com/designcenter/index.html [8] http://www.transim.com/fairchild/index.html [9] http://www.fairchildsemi.com/whats_new/spm_tool.html [10] http://www.fairchildsemi.com/whats_new/offline_smps_toolkit.html [11] http://www.fairchildsemi.com/whats_new/pfc_toolkit.html [12] Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet

FDB8445, http://www.fairchildsemi.com. [13] http://www.fairchildsemi.com/models/Pspice_Bsim3.1/Discrete/MOSF

ET.html [14] Fairchild Semiconductor Corporation, Mountaintop, PA, Data Sheet

FDB8441, http://www.fairchildsemi.com. [15] http://www.systat.com/products/TableCurve2D/

Scott Pearson has worked in the semiconductor industry for the past 17 years. For the past 12 years Scott has been involved in MOSFET characterization, testing and Spice modeling. He has been with Fairchild Semiconductor since May 1989. Scott obtained his B. Eng. from Penn State University. Alain Laprade has worked as a power supply designer for 14 years in applications including computer power, high power telecommunications and space designs. He has been with Fairchild Semiconductor Corporation since February 1998 working in industrial, cell phone and automotive applications. Alain obtained his B.Eng. from McGill University in 1982 and his M.Eng. from McGill

University in 1984.

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