tiva c series tm4c1290nczad microcontroller data sheet … · 2020. 12. 13. · 9...

Tiva™ TM4C1290NCZAD Microcontroller

DATA SHEET

Copyr ight © 2007-2014Texas Instruments Incorporated

DS-TM4C1290NCZAD-15863.2743SPMS430B

TEXAS INSTRUMENTS-PRODUCTION DATA

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June 18, 20142Texas Instruments-Production Data

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Table of ContentsRevision History ............................................................................................................................. 40About This Document .................................................................................................................... 43Audience .............................................................................................................................................. 43About This Manual ................................................................................................................................ 43Related Documents ............................................................................................................................... 43Documentation Conventions .................................................................................................................. 44

1 Architectural Overview .......................................................................................... 461.1 Tiva™ C Series Overview .............................................................................................. 461.2 TM4C1290NCZAD Microcontroller Overview .................................................................. 471.3 TM4C1290NCZAD Microcontroller Features ................................................................... 501.3.1 ARM Cortex-M4F Processor Core .................................................................................. 501.3.2 On-Chip Memory ........................................................................................................... 521.3.3 External Peripheral Interface ......................................................................................... 541.3.4 Cyclical Redundancy Check (CRC) ............................................................................... 561.3.5 Serial Communications Peripherals ................................................................................ 561.3.6 System Integration ........................................................................................................ 611.3.7 Advanced Motion Control ............................................................................................... 681.3.8 Analog .......................................................................................................................... 701.3.9 JTAG and ARM Serial Wire Debug ................................................................................ 711.3.10 Packaging and Temperature .......................................................................................... 721.4 TM4C1290NCZAD Microcontroller Hardware Details ....................................................... 721.5 Kits .............................................................................................................................. 721.6 Support Information ....................................................................................................... 73

2 The Cortex-M4F Processor ................................................................................... 742.1 Block Diagram .............................................................................................................. 752.2 Overview ...................................................................................................................... 762.2.1 System-Level Interface .................................................................................................. 762.2.2 Integrated Configurable Debug ...................................................................................... 762.2.3 Trace Port Interface Unit (TPIU) ..................................................................................... 772.2.4 Cortex-M4F System Component Details ......................................................................... 772.3 Programming Model ...................................................................................................... 782.3.1 Processor Mode and Privilege Levels for Software Execution ........................................... 782.3.2 Stacks .......................................................................................................................... 792.3.3 Register Map ................................................................................................................ 792.3.4 Register Descriptions .................................................................................................... 812.3.5 Exceptions and Interrupts .............................................................................................. 972.3.6 Data Types ................................................................................................................... 972.4 Memory Model .............................................................................................................. 972.4.1 Memory Regions, Types and Attributes ......................................................................... 1002.4.2 Memory System Ordering of Memory Accesses ............................................................ 1012.4.3 Behavior of Memory Accesses ..................................................................................... 1012.4.4 Software Ordering of Memory Accesses ....................................................................... 1022.4.5 Bit-Banding ................................................................................................................. 1032.4.6 Data Storage .............................................................................................................. 1052.4.7 Synchronization Primitives ........................................................................................... 106

3June 18, 2014Texas Instruments-Production Data


2.5 Exception Model ......................................................................................................... 1072.5.1 Exception States ......................................................................................................... 1082.5.2 Exception Types .......................................................................................................... 1082.5.3 Exception Handlers ..................................................................................................... 1132.5.4 Vector Table ................................................................................................................ 1132.5.5 Exception Priorities ...................................................................................................... 1142.5.6 Interrupt Priority Grouping ............................................................................................ 1152.5.7 Exception Entry and Return ......................................................................................... 1152.6 Fault Handling ............................................................................................................. 1182.6.1 Fault Types ................................................................................................................. 1192.6.2 Fault Escalation and Hard Faults .................................................................................. 1192.6.3 Fault Status Registers and Fault Address Registers ...................................................... 1202.6.4 Lockup ....................................................................................................................... 1202.7 Power Management .................................................................................................... 1212.7.1 Entering Sleep Modes ................................................................................................. 1212.7.2 Wake Up from Sleep Mode .......................................................................................... 1212.8 Instruction Set Summary .............................................................................................. 122

3 Cortex-M4 Peripherals ......................................................................................... 1293.1 Functional Description ................................................................................................. 1293.1.1 System Timer (SysTick) ............................................................................................... 1303.1.2 Nested Vectored Interrupt Controller (NVIC) .................................................................. 1313.1.3 System Control Block (SCB) ........................................................................................ 1323.1.4 Memory Protection Unit (MPU) ..................................................................................... 1323.1.5 Floating-Point Unit (FPU) ............................................................................................. 1373.2 Register Map .............................................................................................................. 1413.3 System Timer (SysTick) Register Descriptions .............................................................. 1443.4 NVIC Register Descriptions .......................................................................................... 1483.5 System Control Block (SCB) Register Descriptions ........................................................ 1583.6 Memory Protection Unit (MPU) Register Descriptions .................................................... 1873.7 Floating-Point Unit (FPU) Register Descriptions ............................................................ 196

4 JTAG Interface ...................................................................................................... 2024.1 Block Diagram ............................................................................................................ 2034.2 Signal Description ....................................................................................................... 2034.3 Functional Description ................................................................................................. 2044.3.1 JTAG Interface Pins ..................................................................................................... 2044.3.2 JTAG TAP Controller ................................................................................................... 2064.3.3 Shift Registers ............................................................................................................ 2074.3.4 Operational Considerations .......................................................................................... 2074.4 Initialization and Configuration ..................................................................................... 2104.5 Register Descriptions .................................................................................................. 2104.5.1 Instruction Register (IR) ............................................................................................... 2114.5.2 Data Registers ............................................................................................................ 212

5 System Control ..................................................................................................... 2155.1 Signal Description ....................................................................................................... 2155.2 Functional Description ................................................................................................. 2155.2.1 Device Identification .................................................................................................... 2165.2.2 Reset Control .............................................................................................................. 2165.2.3 Non-Maskable Interrupt ............................................................................................... 223


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5.2.4 Power Control ............................................................................................................. 2245.2.5 Clock Control .............................................................................................................. 2255.2.6 System Control ........................................................................................................... 2335.3 Initialization and Configuration ..................................................................................... 2405.4 Register Map .............................................................................................................. 2415.5 System Control Register Descriptions (System Control Offset) ....................................... 248

6 Processor Support and Exception Module ........................................................ 5046.1 Functional Description ................................................................................................. 5046.2 Register Map .............................................................................................................. 5046.3 Register Descriptions .................................................................................................. 504

7 Hibernation Module .............................................................................................. 5127.1 Block Diagram ............................................................................................................ 5147.2 Signal Description ....................................................................................................... 5147.3 Functional Description ................................................................................................. 5157.3.1 Register Access Timing ............................................................................................... 5167.3.2 Hibernation Clock Source ............................................................................................ 5167.3.3 System Implementation ............................................................................................... 5197.3.4 Battery Management ................................................................................................... 5207.3.5 Real-Time Clock .......................................................................................................... 5207.3.6 Tamper ....................................................................................................................... 5237.3.7 Battery-Backed Memory .............................................................................................. 5267.3.8 Power Control Using HIB ............................................................................................. 5267.3.9 Power Control Using VDD3ON Mode ........................................................................... 5277.3.10 Initiating Hibernate ...................................................................................................... 5277.3.11 Waking from Hibernate ................................................................................................ 5277.3.12 Arbitrary Power Removal ............................................................................................. 5287.3.13 Interrupts and Status ................................................................................................... 5297.4 Initialization and Configuration ..................................................................................... 5297.4.1 Initialization ................................................................................................................. 5297.4.2 RTC Match Functionality (No Hibernation) .................................................................... 5307.4.3 RTC Match/Wake-Up from Hibernation ......................................................................... 5307.4.4 External Wake-Up from Hibernation .............................................................................. 5317.4.5 RTC or External Wake-Up from Hibernation .................................................................. 5327.4.6 Tamper Initialization ..................................................................................................... 5327.5 Register Map .............................................................................................................. 5327.6 Register Descriptions .................................................................................................. 534

8 Internal Memory ................................................................................................... 5818.1 Block Diagram ............................................................................................................ 5818.2 Functional Description ................................................................................................. 5838.2.1 SRAM ........................................................................................................................ 5838.2.2 ROM .......................................................................................................................... 5838.2.3 Flash Memory ............................................................................................................. 5858.2.4 EEPROM .................................................................................................................... 5968.2.5 Bus Matrix Memory Accesses ...................................................................................... 6028.3 Register Map .............................................................................................................. 6028.4 Internal Memory Register Descriptions (Internal Memory Control Offset) ......................... 6058.5 EEPROM Register Descriptions (EEPROM Offset) ........................................................ 6318.6 Memory Register Descriptions (System Control Offset) .................................................. 648



9 Micro Direct Memory Access (μDMA) ................................................................ 6599.1 Block Diagram ............................................................................................................ 6609.2 Functional Description ................................................................................................. 6609.2.1 Channel Assignments .................................................................................................. 6619.2.2 Priority ........................................................................................................................ 6629.2.3 Arbitration Size ............................................................................................................ 6639.2.4 Request Types ............................................................................................................ 6639.2.5 Channel Configuration ................................................................................................. 6649.2.6 Transfer Modes ........................................................................................................... 6669.2.7 Transfer Size and Increment ........................................................................................ 6749.2.8 Peripheral Interface ..................................................................................................... 6749.2.9 Software Request ........................................................................................................ 6759.2.10 Interrupts and Errors .................................................................................................... 6759.3 Initialization and Configuration ..................................................................................... 6759.3.1 Module Initialization ..................................................................................................... 6759.3.2 Configuring a Memory-to-Memory Transfer ................................................................... 6769.3.3 Configuring a Peripheral for Simple Transmit ................................................................ 6779.3.4 Configuring a Peripheral for Ping-Pong Receive ............................................................ 6799.3.5 Configuring Channel Assignments ................................................................................ 6829.4 Register Map .............................................................................................................. 6829.5 μDMA Channel Control Structure ................................................................................. 6839.6 μDMA Register Descriptions ........................................................................................ 690

10 General-Purpose Input/Outputs (GPIOs) ........................................................... 72310.1 Signal Description ....................................................................................................... 72410.2 Pad Capabilities .......................................................................................................... 72910.3 Functional Description ................................................................................................. 72910.3.1 Data Control ............................................................................................................... 73110.3.2 Interrupt Control .......................................................................................................... 73310.3.3 Mode Control .............................................................................................................. 73410.3.4 Commit Control ........................................................................................................... 73510.3.5 Pad Control ................................................................................................................. 73510.3.6 Identification ............................................................................................................... 73610.4 Initialization and Configuration ..................................................................................... 73610.5 Register Map .............................................................................................................. 73810.6 Register Descriptions .................................................................................................. 741

11 External Peripheral Interface (EPI) ..................................................................... 79911.1 EPI Block Diagram ...................................................................................................... 80011.2 Signal Description ....................................................................................................... 80111.3 Functional Description ................................................................................................. 80211.3.1 Master Access to EPI .................................................................................................. 80311.3.2 Non-Blocking Reads .................................................................................................... 80311.3.3 DMA Operation ........................................................................................................... 80411.4 Initialization and Configuration ..................................................................................... 80511.4.1 EPI Interface Options .................................................................................................. 80611.4.2 SDRAM Mode ............................................................................................................. 80611.4.3 Host Bus Mode ........................................................................................................... 81011.4.4 General-Purpose Mode ............................................................................................... 83111.5 Register Map .............................................................................................................. 838


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11.6 Register Descriptions .................................................................................................. 840

12 Cyclical Redundancy Check (CRC) .................................................................... 93012.1 Functional Description ................................................................................................. 93012.1.1 CRC Support .............................................................................................................. 93012.2 Initialization and Configuration ..................................................................................... 93212.2.1 CRC Initialization and Configuration ............................................................................. 93212.3 Register Map .............................................................................................................. 93312.4 CRC Module Register Descriptions .............................................................................. 933

13 General-Purpose Timers ...................................................................................... 93913.1 Block Diagram ............................................................................................................ 94013.2 Signal Description ....................................................................................................... 94113.3 Functional Description ................................................................................................. 94213.3.1 GPTM Reset Conditions .............................................................................................. 94313.3.2 Timer Clock Source ..................................................................................................... 94313.3.3 Timer Modes ............................................................................................................... 94413.3.4 Wait-for-Trigger Mode .................................................................................................. 95313.3.5 Synchronizing GP Timer Blocks ................................................................................... 95413.3.6 DMA Operation ........................................................................................................... 95513.3.7 ADC Operation ............................................................................................................ 95513.3.8 Accessing Concatenated 16/32-Bit GPTM Register Values ............................................ 95513.4 Initialization and Configuration ..................................................................................... 95613.4.1 One-Shot/Periodic Timer Mode .................................................................................... 95613.4.2 Real-Time Clock (RTC) Mode ...................................................................................... 95713.4.3 Input Edge-Count Mode ............................................................................................... 95713.4.4 Input Edge Time Mode ................................................................................................. 95813.4.5 PWM Mode ................................................................................................................. 95813.5 Register Map .............................................................................................................. 95913.6 Register Descriptions .................................................................................................. 960

14 Watchdog Timers ............................................................................................... 101314.1 Block Diagram ........................................................................................................... 101414.2 Functional Description ............................................................................................... 101414.2.1 Register Access Timing ............................................................................................. 101514.3 Initialization and Configuration .................................................................................... 101514.4 Register Map ............................................................................................................ 101514.5 Register Descriptions ................................................................................................. 1016

15 Analog-to-Digital Converter (ADC) ................................................................... 103815.1 Block Diagram ........................................................................................................... 103915.2 Signal Description ..................................................................................................... 104015.3 Functional Description ............................................................................................... 104115.3.1 Sample Sequencers .................................................................................................. 104215.3.2 Module Control .......................................................................................................... 104215.3.3 Hardware Sample Averaging Circuit ........................................................................... 104815.3.4 Analog-to-Digital Converter ........................................................................................ 104815.3.5 Differential Sampling .................................................................................................. 105015.3.6 Internal Temperature Sensor ...................................................................................... 105215.3.7 Digital Comparator Unit .............................................................................................. 105315.4 Initialization and Configuration .................................................................................... 1058



15.4.1 Module Initialization ................................................................................................... 105815.4.2 Sample Sequencer Configuration ............................................................................... 105915.5 Register Map ............................................................................................................ 105915.6 Register Descriptions ................................................................................................. 1062

16 Universal Asynchronous Receivers/Transmitters (UARTs) ........................... 114716.1 Block Diagram ........................................................................................................... 114816.2 Signal Description ..................................................................................................... 114816.3 Functional Description ............................................................................................... 115016.3.1 Transmit/Receive Logic .............................................................................................. 115116.3.2 Baud-Rate Generation ............................................................................................... 115116.3.3 Data Transmission ..................................................................................................... 115216.3.4 Serial IR (SIR) ........................................................................................................... 115216.3.5 ISO 7816 Support ...................................................................................................... 115416.3.6 Modem Handshake Support ....................................................................................... 115416.3.7 9-Bit UART Mode ...................................................................................................... 115516.3.8 FIFO Operation ......................................................................................................... 115616.3.9 Interrupts .................................................................................................................. 115616.3.10 Loopback Operation .................................................................................................. 115716.3.11 DMA Operation ......................................................................................................... 115716.4 Initialization and Configuration .................................................................................... 115816.5 Register Map ............................................................................................................ 115916.6 Register Descriptions ................................................................................................. 1161

17 Quad Synchronous Serial Interface (QSSI) ..................................................... 121317.1 Block Diagram ........................................................................................................... 121317.2 Signal Description ..................................................................................................... 121417.3 Functional Description ............................................................................................... 121617.3.1 Bit Rate Generation ................................................................................................... 121617.3.2 FIFO Operation ......................................................................................................... 121617.3.3 Advanced, Bi- and Quad- SSI Function ....................................................................... 121717.3.4 SSInFSS Function ..................................................................................................... 121817.3.5 High Speed Clock Operation ...................................................................................... 121917.3.6 Interrupts .................................................................................................................. 121917.3.7 Frame Formats ......................................................................................................... 122017.3.8 DMA Operation ......................................................................................................... 122717.4 Initialization and Configuration .................................................................................... 122717.4.1 Enhanced Mode Configuration ................................................................................... 122917.5 Register Map ............................................................................................................ 123017.6 Register Descriptions ................................................................................................. 1231

18 Inter-Integrated Circuit (I2C) Interface .............................................................. 126218.1 Block Diagram ........................................................................................................... 126318.2 Signal Description ..................................................................................................... 126418.3 Functional Description ............................................................................................... 126518.3.1 I2C Bus Functional Overview ...................................................................................... 126518.3.2 Available Speed Modes ............................................................................................. 127118.3.3 Interrupts .................................................................................................................. 127318.3.4 Loopback Operation .................................................................................................. 127418.3.5 FIFO and µDMA Operation ........................................................................................ 127418.3.6 Command Sequence Flow Charts .............................................................................. 1276


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18.4 Initialization and Configuration .................................................................................... 128418.4.1 Configure the I2C Module to Transmit a Single Byte as a Master .................................. 128418.4.2 Configure the I2C Master to High Speed Mode ............................................................ 128518.5 Register Map ............................................................................................................ 128618.6 Register Descriptions (I2C Master) .............................................................................. 128818.7 Register Descriptions (I2C Slave) ............................................................................... 131718.8 Register Descriptions (I2C Status and Control) ............................................................ 1334

19 Controller Area Network (CAN) Module ........................................................... 134319.1 Block Diagram ........................................................................................................... 134419.2 Signal Description ..................................................................................................... 134419.3 Functional Description ............................................................................................... 134519.3.1 Initialization ............................................................................................................... 134619.3.2 Operation .................................................................................................................. 134619.3.3 Transmitting Message Objects ................................................................................... 134719.3.4 Configuring a Transmit Message Object ...................................................................... 134819.3.5 Updating a Transmit Message Object ......................................................................... 134919.3.6 Accepting Received Message Objects ........................................................................ 134919.3.7 Receiving a Data Frame ............................................................................................ 135019.3.8 Receiving a Remote Frame ........................................................................................ 135019.3.9 Receive/Transmit Priority ........................................................................................... 135119.3.10 Configuring a Receive Message Object ...................................................................... 135119.3.11 Handling of Received Message Objects ...................................................................... 135219.3.12 Handling of Interrupts ................................................................................................ 135419.3.13 Test Mode ................................................................................................................. 135519.3.14 Bit Timing Configuration Error Considerations ............................................................. 135719.3.15 Bit Time and Bit Rate ................................................................................................. 135719.3.16 Calculating the Bit Timing Parameters ........................................................................ 135919.4 Register Map ............................................................................................................ 136219.5 CAN Register Descriptions ......................................................................................... 1363

20 Universal Serial Bus (USB) Controller ............................................................. 139420.1 Block Diagram ........................................................................................................... 139520.2 Signal Description ..................................................................................................... 139520.3 Register Map ............................................................................................................ 1396

21 Analog Comparators .......................................................................................... 140321.1 Block Diagram ........................................................................................................... 140421.2 Signal Description ..................................................................................................... 140421.3 Functional Description ............................................................................................... 140521.3.1 Internal Reference Programming ................................................................................ 140621.4 Initialization and Configuration .................................................................................... 140821.5 Register Map ............................................................................................................ 140921.6 Register Descriptions ................................................................................................. 1409

22 Pulse Width Modulator (PWM) .......................................................................... 141922.1 Block Diagram ........................................................................................................... 142022.2 Signal Description ..................................................................................................... 142222.3 Functional Description ............................................................................................... 142222.3.1 Clock Configuration ................................................................................................... 142222.3.2 PWM Timer ............................................................................................................... 1423



22.3.3 PWM Comparators .................................................................................................... 142322.3.4 PWM Signal Generator .............................................................................................. 142422.3.5 Dead-Band Generator ............................................................................................... 142522.3.6 Interrupt/ADC-Trigger Selector ................................................................................... 142522.3.7 Synchronization Methods .......................................................................................... 142622.3.8 Fault Conditions ........................................................................................................ 142722.3.9 Output Control Block .................................................................................................. 142822.4 Initialization and Configuration .................................................................................... 142822.5 Register Map ............................................................................................................ 142922.6 Register Descriptions ................................................................................................. 1432

23 Quadrature Encoder Interface (QEI) ................................................................. 149823.1 Block Diagram ........................................................................................................... 149823.2 Signal Description ..................................................................................................... 150023.3 Functional Description ............................................................................................... 150023.4 Initialization and Configuration .................................................................................... 150323.5 Register Map ............................................................................................................ 150323.6 Register Descriptions ................................................................................................. 1504

24 Pin Diagram ........................................................................................................ 152125 Signal Tables ...................................................................................................... 152225.1 Signals by Pin Number .............................................................................................. 152325.2 Signals by Signal Name ............................................................................................. 154025.3 Signals by Function, Except for GPIO ......................................................................... 155625.4 GPIO Pins and Alternate Functions ............................................................................ 156925.5 Possible Pin Assignments for Alternate Functions ....................................................... 157425.6 Connections for Unused Signals ................................................................................. 1580

26 Electrical Characteristics .................................................................................. 158126.1 Maximum Ratings ...................................................................................................... 158126.2 Operating Characteristics ........................................................................................... 158226.3 Recommended Operating Conditions ......................................................................... 158326.3.1 DC Operating Conditions ........................................................................................... 158326.3.2 Recommended GPIO Operating Characteristics .......................................................... 158326.4 Load Conditions ........................................................................................................ 158626.5 JTAG and Boundary Scan .......................................................................................... 158726.6 Power and Brown-Out ............................................................................................... 158926.6.1 VDDA Levels .............................................................................................................. 158926.6.2 VDD Levels ................................................................................................................ 159026.6.3 VDDC Levels .............................................................................................................. 159126.6.4 Response ................................................................................................................. 159226.7 Reset ........................................................................................................................ 159426.8 On-Chip Low Drop-Out (LDO) Regulator ..................................................................... 159726.9 Clocks ...................................................................................................................... 159826.9.1 PLL Specifications ..................................................................................................... 159826.9.2 PIOSC Specifications ................................................................................................ 160026.9.3 Low-Frequency Internal Oscillator Specifications ......................................................... 160026.9.4 Hibernation Clock Source Specifications ..................................................................... 160026.9.5 Main Oscillator Specifications ..................................................................................... 160126.9.6 System Clock Specification with ADC Operation .......................................................... 1605


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26.9.7 System Clock Specification with USB Operation .......................................................... 160526.10 Sleep Modes ............................................................................................................. 160626.11 Hibernation Module ................................................................................................... 160826.12 Flash Memory ........................................................................................................... 161026.13 EEPROM .................................................................................................................. 161126.14 Input/Output Pin Characteristics ................................................................................. 161226.14.1 Types of I/O Pins and ESD Protection ......................................................................... 161426.15 External Peripheral Interface (EPI) .............................................................................. 161626.16 Analog-to-Digital Converter (ADC) .............................................................................. 162426.17 Synchronous Serial Interface (SSI) ............................................................................. 163026.18 Inter-Integrated Circuit (I2C) Interface ......................................................................... 163326.19 Universal Serial Bus (USB) Controller ......................................................................... 163426.20 Analog Comparator ................................................................................................... 163626.21 Pulse-Width Modulator (PWM) ................................................................................... 163826.22 Current Consumption ................................................................................................ 1639

A Package Information .......................................................................................... 1643A.1 Orderable Devices ..................................................................................................... 1643A.2 Device Nomenclature ................................................................................................ 1643A.3 Device Markings ........................................................................................................ 1643A.4 Packaging Diagram ................................................................................................... 1645



List of FiguresFigure 1-1. Tiva™ TM4C1290NCZAD Microcontroller High-Level Block Diagram ....................... 49Figure 2-1. CPU Block Diagram ............................................................................................. 76Figure 2-2. TPIU Block Diagram ............................................................................................ 77Figure 2-3. Cortex-M4F Register Set ...................................................................................... 80Figure 2-4. Bit-Band Mapping .............................................................................................. 105Figure 2-5. Data Storage ..................................................................................................... 106Figure 2-6. Vector Table ...................................................................................................... 114Figure 2-7. Exception Stack Frame ...................................................................................... 117Figure 3-1. SRD Use Example ............................................................................................. 135Figure 3-2. FPU Register Bank ............................................................................................ 138Figure 4-1. JTAG Module Block Diagram .............................................................................. 203Figure 4-2. Test Access Port State Machine ......................................................................... 207Figure 4-3. IDCODE Register Format ................................................................................... 213Figure 4-4. BYPASS Register Format ................................................................................... 213Figure 4-5. Boundary Scan Register Format ......................................................................... 213Figure 5-1. Basic RST Configuration .................................................................................... 219Figure 5-2. External Circuitry to Extend Power-On Reset ....................................................... 219Figure 5-3. Reset Circuit Controlled by Switch ...................................................................... 219Figure 5-4. Power Architecture ............................................................................................ 225Figure 5-5. Main Clock Tree ................................................................................................ 228Figure 5-6. Module Clock Selection ...................................................................................... 236Figure 7-1. Hibernation Module Block Diagram ..................................................................... 514Figure 7-2. Using a Crystal as the Hibernation Clock Source with a Single Battery Source ...... 518Figure 7-3. Using a Dedicated Oscillator as the Hibernation Clock Source with VDD3ON

Mode ................................................................................................................ 518Figure 7-4. Using a Regulator for Both VDD and VBAT ............................................................ 519Figure 7-5. Counter Behavior with a TRIM Value of 0x8002 ................................................... 523Figure 7-6. Counter Behavior with a TRIM Value of 0x7FFC .................................................. 523Figure 7-7. Tamper Block Diagram ....................................................................................... 523Figure 7-8. Tamper Pad with Glitch Filtering ......................................................................... 524Figure 8-1. Internal Memory Block Diagram .......................................................................... 582Figure 8-2. Flash Memory Configuration ............................................................................... 586Figure 8-3. Single 256-Bit Prefetch Buffer Set ....................................................................... 587Figure 8-4. Four 256-Bit Prefetch Buffer Configuration .......................................................... 587Figure 8-5. Single Cycle Access, 0 Wait States ..................................................................... 588Figure 8-6. Prefetch Fills from Flash ..................................................................................... 589Figure 8-7. Mirror Mode Function ......................................................................................... 590Figure 9-1. μDMA Block Diagram ......................................................................................... 660Figure 9-2. Example of Ping-Pong μDMA Transaction ........................................................... 667Figure 9-3. Memory Scatter-Gather, Setup and Configuration ................................................ 669Figure 9-4. Memory Scatter-Gather, μDMA Copy Sequence .................................................. 670Figure 9-5. Peripheral Scatter-Gather, Setup and Configuration ............................................. 672Figure 9-6. Peripheral Scatter-Gather, μDMA Copy Sequence ............................................... 673Figure 10-1. Digital I/O Pads ................................................................................................. 730Figure 10-2. Analog/Digital I/O Pads ...................................................................................... 731Figure 10-3. GPIODATA Write Example ................................................................................. 732


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Figure 10-4. GPIODATA Read Example ................................................................................. 732Figure 11-1. EPI Block Diagram ............................................................................................. 801Figure 11-2. SDRAM Non-Blocking Read Cycle ...................................................................... 808Figure 11-3. SDRAM Normal Read Cycle ............................................................................... 809Figure 11-4. SDRAM Write Cycle ........................................................................................... 810Figure 11-5. iRDY Access Stalls, IRDYDLY==01, 10, 11 .......................................................... 820Figure 11-6. iRDY Signal Connection ..................................................................................... 820Figure 11-7. PSRAM Burst Read ........................................................................................... 823Figure 11-8. PSRAM Burst Write ........................................................................................... 823Figure 11-9. Read Delay During Refresh Event ...................................................................... 824Figure 11-10. Write Delay During Refresh Event ....................................................................... 825Figure 11-11. Example Schematic for Muxed Host-Bus 16 Mode ............................................... 826Figure 11-12. Host-Bus Read Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 829Figure 11-13. Host-Bus Write Cycle, MODE = 0x1, WRHIGH = 0, RDHIGH = 0 .......................... 829Figure 11-14. Host-Bus Write Cycle with Multiplexed Address and Data, MODE = 0x0, WRHIGH

= 0, RDHIGH = 0 ............................................................................................... 830Figure 11-15. Host-Bus Write Cycle with Multiplexed Address and Data and ALE with Dual or

Quad CSn ......................................................................................................... 830Figure 11-16. Continuous Read Mode Accesses ...................................................................... 830Figure 11-17. Write Followed by Read to External FIFO ............................................................ 831Figure 11-18. Two-Entry FIFO ................................................................................................. 831Figure 11-19. Single-Cycle Single Write Access, FRM50=0, FRMCNT=0, WR2CYC=0 ............... 834Figure 11-20. Two-Cycle Read, Write Accesses, FRM50=0, FRMCNT=0, WR2CYC=1 ............... 835Figure 11-21. Read Accesses, FRM50=0, FRMCNT=0 ............................................................. 835Figure 11-22. FRAME Signal Operation, FRM50=0 and FRMCNT=0 ......................................... 836Figure 11-23. FRAME Signal Operation, FRM50=0 and FRMCNT=1 ......................................... 836Figure 11-24. FRAME Signal Operation, FRM50=0 and FRMCNT=2 ......................................... 836Figure 11-25. FRAME Signal Operation, FRM50=1 and FRMCNT=0 ......................................... 836Figure 11-26. FRAME Signal Operation, FRM50=1 and FRMCNT=1 ......................................... 837Figure 11-27. FRAME Signal Operation, FRM50=1 and FRMCNT=2 ......................................... 837Figure 11-28. EPI Clock Operation, CLKGATE=1, WR2CYC=0 ................................................. 837Figure 11-29. EPI Clock Operation, CLKGATE=1, WR2CYC=1 ................................................. 838Figure 13-1. GPTM Module Block Diagram ............................................................................ 940Figure 13-2. Input Edge-Count Mode Example, Counting Down ............................................... 948Figure 13-3. 16-Bit Input Edge-Time Mode Example ............................................................... 950Figure 13-4. 16-Bit PWM Mode Example ................................................................................ 952Figure 13-5. CCP Output, GPTMTnMATCHR > GPTMTnILR ................................................... 952Figure 13-6. CCP Output, GPTMTnMATCHR = GPTMTnILR ................................................... 953Figure 13-7. CCP Output, GPTMTnILR > GPTMTnMATCHR ................................................... 953Figure 13-8. Timer Daisy Chain ............................................................................................. 954Figure 14-1. WDT Module Block Diagram ............................................................................. 1014Figure 15-1. Implementation of Two ADC Blocks .................................................................. 1039Figure 15-2. ADC Module Block Diagram ............................................................................. 1040Figure 15-3. ADC Sample Phases ....................................................................................... 1045Figure 15-4. Doubling the ADC Sample Rate ........................................................................ 1046Figure 15-5. Skewed Sampling ............................................................................................ 1047Figure 15-6. Sample Averaging Example .............................................................................. 1048Figure 15-7. ADC Input Equivalency .................................................................................... 1049



Figure 15-8. ADC Voltage Reference ................................................................................... 1049Figure 15-9. ADC Conversion Result ................................................................................... 1050Figure 15-10. Differential Voltage Representation ................................................................... 1052Figure 15-11. Internal Temperature Sensor Characteristic ....................................................... 1053Figure 15-12. Low-Band Operation (CIC=0x0 and/or CTC=0x0) .............................................. 1056Figure 15-13. Mid-Band Operation (CIC=0x1 and/or CTC=0x1) ............................................... 1057Figure 15-14. High-Band Operation (CIC=0x3 and/or CTC=0x3) .............................................. 1058Figure 16-1. UART Module Block Diagram ........................................................................... 1148Figure 16-2. UART Character Frame .................................................................................... 1151Figure 16-3. IrDA Data Modulation ....................................................................................... 1153Figure 17-1. QSSI Module with Advanced, Bi-SSI and Quad-SSI Support .............................. 1214Figure 17-2. TI Synchronous Serial Frame Format (Single Transfer) ...................................... 1221Figure 17-3. TI Synchronous Serial Frame Format (Continuous Transfer) ............................... 1222Figure 17-4. Freescale SPI Format (Single Transfer) with SPO=0 and SPH=0 ........................ 1223Figure 17-5. Freescale SPI Format (Continuous Transfer) with SPO=0 and SPH=0 ................ 1223Figure 17-6. Freescale SPI Frame Format with SPO=0 and SPH=1 ....................................... 1224Figure 17-7. Freescale SPI Frame Format (Single Transfer) with SPO=1 and SPH=0 ............. 1225Figure 17-8. Freescale SPI Frame Format (Continuous Transfer) with SPO=1 and SPH=0 ...... 1225Figure 17-9. Freescale SPI Frame Format with SPO=1 and SPH=1 ....................................... 1226Figure 18-1. I2C Block Diagram ........................................................................................... 1263Figure 18-2. I2C Bus Configuration ....................................................................................... 1265Figure 18-3. START and STOP Conditions ........................................................................... 1266Figure 18-4. Complete Data Transfer with a 7-Bit Address ..................................................... 1267Figure 18-5. R/S Bit in First Byte .......................................................................................... 1267Figure 18-6. Data Validity During Bit Transfer on the I2C Bus ................................................. 1267Figure 18-7. High-Speed Data Format .................................................................................. 1273Figure 18-8. Master Single TRANSMIT ................................................................................ 1277Figure 18-9. Master Single RECEIVE ................................................................................... 1278Figure 18-10. Master TRANSMIT of Multiple Data Bytes ......................................................... 1279Figure 18-11. Master RECEIVE of Multiple Data Bytes ............................................................ 1280Figure 18-12. Master RECEIVE with Repeated START after Master TRANSMIT ....................... 1281Figure 18-13. Master TRANSMIT with Repeated START after Master RECEIVE ....................... 1282Figure 18-14. Standard High Speed Mode Master Transmit ..................................................... 1283Figure 18-15. Slave Command Sequence .............................................................................. 1284Figure 19-1. CAN Controller Block Diagram .......................................................................... 1344Figure 19-2. CAN Data/Remote Frame ................................................................................. 1345Figure 19-3. Message Objects in a FIFO Buffer .................................................................... 1354Figure 19-4. CAN Bit Time ................................................................................................... 1358Figure 20-1. USB Module Block Diagram ............................................................................. 1395Figure 21-1. Analog Comparator Module Block Diagram ....................................................... 1404Figure 21-2. Structure of Comparator Unit ............................................................................ 1405Figure 21-3. Comparator Internal Reference Structure .......................................................... 1406Figure 22-1. PWM Module Diagram ..................................................................................... 1421Figure 22-2. PWM Generator Block Diagram ........................................................................ 1421Figure 22-3. PWM Count-Down Mode .................................................................................. 1424Figure 22-4. PWM Count-Up/Down Mode ............................................................................. 1424Figure 22-5. PWM Generation Example In Count-Up/Down Mode .......................................... 1425Figure 22-6. PWM Dead-Band Generator ............................................................................. 1425


Table of Contents

Figure 23-1. QEI Block Diagram .......................................................................................... 1499Figure 23-2. QEI Input Signal Logic ...................................................................................... 1500Figure 23-3. Quadrature Encoder and Velocity Predivider Operation ...................................... 1502Figure 24-1. 212-Ball BGA Package Pin Diagram (Top View) ................................................. 1521Figure 26-1. Load Conditions ............................................................................................... 1586Figure 26-2. JTAG Test Clock Input Timing ........................................................................... 1588Figure 26-3. JTAG Test Access Port (TAP) Timing ................................................................ 1588Figure 26-4. Power and Brown-Out Assertions vs VDDA Levels .............................................. 1590Figure 26-5. Power and Brown-Out Assertions vs VDD Levels ................................................ 1591Figure 26-6. POK Assertion vs VDDC ................................................................................... 1592Figure 26-7. POR-BOR VDD Glitch Response ....................................................................... 1592Figure 26-8. POR-BOR VDD Droop Response ...................................................................... 1593Figure 26-9. Digital Power-On Reset Timing ......................................................................... 1594Figure 26-10. Brown-Out Reset Timing .................................................................................. 1595Figure 26-11. External Reset Timing (RST) ............................................................................ 1595Figure 26-12. Software Reset Timing ..................................................................................... 1595Figure 26-13. Watchdog Reset Timing ................................................................................... 1595Figure 26-14. MOSC Failure Reset Timing ............................................................................. 1596Figure 26-15. Hibernation Module Timing ............................................................................... 1609Figure 26-16. ESD Protection ................................................................................................ 1614Figure 26-17. ESD Protection for Non-Power Pins (Except WAKE Signal) ................................ 1615Figure 26-18. SDRAM Initialization and Load Mode Register Timing ........................................ 1617Figure 26-19. SDRAM Read Timing ....................................................................................... 1617Figure 26-20. SDRAM Write Timing ....................................................................................... 1618Figure 26-21. Host-Bus 8/16 Asynchronous Mode Read Timing ............................................... 1619Figure 26-22. Host-Bus 8/16 Asynchronous Mode Write Timing ............................................... 1619Figure 26-23. Host-Bus 8/16 Mode Asynchronous Muxed Read Timing .................................... 1620Figure 26-24. Host-Bus 8/16 Mode Asynchronous Muxed Write Timing .................................... 1620Figure 26-25. General-Purpose Mode Read and Write Timing ................................................. 1621Figure 26-26. PSRAM Single Burst Read ............................................................................... 1622Figure 26-27. PSRAM Single Burst Write ............................................................................... 1623Figure 26-28. ADC External Reference Filtering ..................................................................... 1629Figure 26-29. ADC Input Equivalency .................................................................................... 1629Figure 26-30. SSI Timing for TI Frame Format (FRF=01), Single Transfer Timing

Measurement .................................................................................................. 1631Figure 26-31. Master Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 .............. 1631Figure 26-32. Slave Mode SSI Timing for SPI Frame Format (FRF=00), with SPH=1 ................ 1632Figure 26-33. I2C Timing ....................................................................................................... 1633Figure 26-34. ULPI Interface Timing Diagram ......................................................................... 1635Figure A-1. Key to Part Numbers ........................................................................................ 1643Figure A-2. TM4C1290NCZAD 212-Ball BGA Package Diagram .......................................... 1645



List of TablesTable 1. Revision History .................................................................................................. 40Table 2. Documentation Conventions ................................................................................ 44Table 1-1. TM4C1290NCZAD Microcontroller Features .......................................................... 47Table 2-1. Summary of Processor Mode, Privilege Level, and Stack Use ................................ 79Table 2-2. Processor Register Map ....................................................................................... 80Table 2-3. PSR Register Combinations ................................................................................. 86Table 2-4. Memory Map ....................................................................................................... 97Table 2-5. Memory Access Behavior ................................................................................... 101Table 2-6. SRAM Memory Bit-Banding Regions ................................................................... 103Table 2-7. Peripheral Memory Bit-Banding Regions ............................................................. 103Table 2-8. Exception Types ................................................................................................ 109Table 2-9. Interrupts .......................................................................................................... 110Table 2-10. Exception Return Behavior ................................................................................. 118Table 2-11. Faults ............................................................................................................... 119Table 2-12. Fault Status and Fault Address Registers ............................................................ 120Table 2-13. Cortex-M4F Instruction Summary ....................................................................... 122Table 3-1. Core Peripheral Register Regions ....................................................................... 129Table 3-2. Memory Attributes Summary .............................................................................. 133Table 3-3. TEX, S, C, and B Bit Field Encoding ................................................................... 135Table 3-4. Cache Policy for Memory Attribute Encoding ....................................................... 136Table 3-5. AP Bit Field Encoding ........................................................................................ 136Table 3-6. Memory Region Attributes for Tiva™ C Series Microcontrollers ............................. 137Table 3-7. QNaN and SNaN Handling ................................................................................. 140Table 3-8. Peripherals Register Map ................................................................................... 141Table 3-9. Interrupt Priority Levels ...................................................................................... 166Table 3-10. Example SIZE Field Values ................................................................................ 194Table 4-1. JTAG_SWD_SWO Signals (212BGA) ................................................................. 203Table 4-2. JTAG Port Pins State after Power-On Reset or RST assertion .............................. 205Table 4-3. JTAG Instruction Register Commands ................................................................. 211Table 5-1. System Control & Clocks Signals (212BGA) ........................................................ 215Table 5-2. Reset Sources ................................................................................................... 216Table 5-3. Clock Source Options ........................................................................................ 226Table 5-4. Clock Source State Following POR ..................................................................... 227Table 5-5. System Clock Frequency ................................................................................... 230Table 5-6. System Divisor Factors for fvco=480 MHz ............................................................ 232Table 5-7. Actual PLL Frequency ........................................................................................ 232Table 5-8. Peripheral Memory Power Control ...................................................................... 238Table 5-9. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 238Table 5-10. MOSC Configurations ........................................................................................ 241Table 5-11. System Control Register Map ............................................................................. 242Table 5-12. MEMTIM0 Register Configuration versus Frequency ............................................ 271Table 5-13. MOSC Configurations ........................................................................................ 275Table 5-14. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 294Table 5-15. Maximum System Clock and PIOSC Frequency with Respect to LDO Voltage ....... 297Table 5-16. Module Power Control ........................................................................................ 436Table 5-17. Module Power Control ........................................................................................ 438


Table of Contents

Table 5-18. Module Power Control ........................................................................................ 441Table 5-19. Module Power Control ........................................................................................ 447Table 5-20. Module Power Control ........................................................................................ 449Table 5-21. Module Power Control ........................................................................................ 451Table 5-22. Module Power Control ........................................................................................ 453Table 5-23. Module Power Control ........................................................................................ 456Table 5-24. Module Power Control ........................................................................................ 458Table 5-25. Module Power Control ........................................................................................ 462Table 5-26. Module Power Control ........................................................................................ 464Table 5-27. Module Power Control ........................................................................................ 466Table 5-28. Module Power Control ........................................................................................ 468Table 5-29. Module Power Control ........................................................................................ 470Table 5-30. Module Power Control ........................................................................................ 472Table 5-31. Module Power Control ........................................................................................ 474Table 5-32. Module Power Control ........................................................................................ 476Table 6-1. System Exception Register Map ......................................................................... 504Table 7-1. Hibernate Signals (212BGA) .............................................................................. 515Table 7-2. HIB Clock Source Configurations ........................................................................ 517Table 7-3. Hibernation Module Register Map ....................................................................... 533Table 8-1. MEMTIM0 Register Configuration versus Frequency ............................................ 586Table 8-2. Flash Memory Protection Policy Combinations .................................................... 591Table 8-3. User-Programmable Flash Memory Resident Registers ....................................... 595Table 8-4. MEMTIM0 Register Configuration versus Frequency ............................................ 598Table 8-5. Master Memory Access Availability ..................................................................... 602Table 8-6. Flash Register Map ............................................................................................ 603Table 9-1. μDMA Channel Assignments .............................................................................. 661Table 9-2. Request Type Support ....................................................................................... 663Table 9-3. Control Structure Memory Map ........................................................................... 665Table 9-4. Channel Control Structure .................................................................................. 665Table 9-5. μDMA Read Example: 8-Bit Peripheral ................................................................ 674Table 9-6. μDMA Interrupt Assignments .............................................................................. 675Table 9-7. Channel Control Structure Offsets for Channel 30 ................................................ 676Table 9-8. Channel Control Word Configuration for Memory Transfer Example ...................... 677Table 9-9. Channel Control Structure Offsets for Channel 7 .................................................. 678Table 9-10. Channel Control Word Configuration for Peripheral Transmit Example .................. 678Table 9-11. Primary and Alternate Channel Control Structure Offsets for Channel 8 ................. 680Table 9-12. Channel Control Word Configuration for Peripheral Ping-Pong Receive

Example ............................................................................................................ 680Table 9-13. μDMA Register Map .......................................................................................... 682Table 10-1. GPIO Pins With Special Considerations .............................................................. 724Table 10-2. GPIO Pins and Alternate Functions (212BGA) ..................................................... 724Table 10-3. GPIO Drive Strength Options .............................................................................. 736Table 10-4. GPIO Pad Configuration Examples ..................................................................... 737Table 10-5. GPIO Interrupt Configuration Example ................................................................ 738Table 10-6. GPIO Pins With Special Considerations .............................................................. 739Table 10-7. GPIO Register Map ........................................................................................... 740Table 10-8. GPIO Pins With Special Considerations .............................................................. 754Table 10-9. GPIO Pins With Special Considerations .............................................................. 760



Table 10-10. GPIO Pins With Special Considerations .............................................................. 762Table 10-11. GPIO Pins With Special Considerations .............................................................. 765Table 10-12. GPIO Pins With Special Considerations .............................................................. 771Table 10-13. GPIO Drive Strength Options .............................................................................. 784Table 11-1. External Peripheral Interface Signals (212BGA) ................................................... 801Table 11-2. EPI Interface Options ......................................................................................... 806Table 11-3. EPI SDRAM x16 Signal Connections .................................................................. 807Table 11-4. CSCFGEXT + CSCFG Encodings ...................................................................... 811Table 11-5. Dual- and Quad- Chip Select Address Mappings ................................................. 812Table 11-6. Chip Select Configuration Register Assignment ................................................... 813Table 11-7. Capabilities of Host Bus 8 and Host Bus 16 Modes .............................................. 813Table 11-8. EPI Host-Bus 8 Signal Connections .................................................................... 815Table 11-9. EPI Host-Bus 16 Signal Connections .................................................................. 817Table 11-10. PSRAM Fixed Latency Wait State Configuration .................................................. 822Table 11-11. Data Phase Wait State Programming .................................................................. 827Table 11-12. EPI General-Purpose Signal Connections ........................................................... 833Table 11-13. External Peripheral Interface (EPI) Register Map ................................................. 838Table 11-14. CSCFGEXT + CSCFG Encodings ...................................................................... 864Table 11-15. CSCFGEXT + CSCFG Encodings ...................................................................... 870Table 12-1. Endian Configuration ......................................................................................... 931Table 12-2. Endian Configuration with Bit Reversal ................................................................ 931Table 12-3. CCM Register Map ............................................................................................ 933Table 13-1. Available CCP Pins ............................................................................................ 940Table 13-2. General-Purpose Timers Signals (212BGA) ..................................................