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ApplicationReport
1997 Digital Signal Processing Solutions
Printed in U.S.A., February 1997 SPRA156
TMS320C80 Frame Buffer
Application Report
SPRA156February 1997
Printed on Recycled Paper
IMPORTANT NOTICE
Texas Instruments (TI) reserves the right to make changes to its products or to discontinue anysemiconductor product or service without notice, and advises its customers to obtain the latestversion of relevant information to verify, before placing orders, that the information being reliedon is current.
TI warrants performance of its semiconductor products and related software to the specificationsapplicable at the time of sale in accordance with TI’s standard warranty. Testing and other qualitycontrol techniques are utilized to the extent TI deems necessary to support this warranty.Specific testing of all parameters of each device is not necessarily performed, except thosemandated by government requirements.
Certain applications using semiconductor products may involve potential risks of death,personal injury, or severe property or environmental damage (“Critical Applications”).
TI SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED, INTENDED, AUTHORIZED, ORWARRANTED TO BE SUITABLE FOR USE IN LIFE-SUPPORT APPLICATIONS, DEVICESOR SYSTEMS OR OTHER CRITICAL APPLICATIONS.
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In order to minimize risks associated with the customer’s applications, adequate design andoperating safeguards should be provided by the customer to minimize inherent or proceduralhazards.
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Copyright 1997, Texas Instruments Incorporated
iii TMS320C80 Frame Buffer
Contents1 Introduction 1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Video Timing 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Pixel Clock 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.2 Shift Clock 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.3 Frame Clock 2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Video Controller 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.1 Frame Timer Registers 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3.1.1 FTCTL Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.2 Horizontal and Vertical Timing Relationship 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 VRAM Overview 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.1 Memory-to-Register Transfers 10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.2 Block Write 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 SRT Controller Register Programming 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 FMEMCTL Register 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 Address Tracking 17. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 TVP3020 Overview 18. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1 TVP3020 Clocking 20. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 System Overview 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.1 Video Signals 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2 VRAM Connection 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.3 Address Lines 22. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.4 Data Lines 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5 Glue Logic 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7.5.1 RAS Generation 23. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.2 Serial Output Enable 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.5.3 Cycle-Configuration Inputs 24. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Timing Analysis 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Pixel Port Timing 36. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 PCB Layout Considerations 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.1 Power Planes 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10.2 Supply Decoupling 37. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 Clock Considerations 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.1 Screen Resolution 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.2 Monitor Specifications 39. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.3 Pixel Clock Selection 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 Frame Timer Register Programming 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12.1 Procedure 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 SRT Controller Registers 46. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents
SPRA156iv
14 A Note on Frame-Timer Interrupts 48. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix A Bill of Materials A-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix B Schematics B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Appendix C ABEL Files C-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Figures
v TMS320C80 Frame Buffer
List of Figures
1 TMS320C80 Video Controller 3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
2 Frame Timer 0 Register Map 4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3 Frame Timer 1 Register Map 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4 FTCTLx Register 6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
5 Horizontal and Vertical Timing Relationship 7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
6 Video Porches 8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
7 VRAM Architecture 9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
8 Split-Register Read Transfer Operation 11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
9 Example of Block-Write 13. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
10 SRT Controller Register Map 15. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
11 FMEMCTLx Register 16. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
12 TVP3020 Block Diagram 19. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
13 System Block Diagram 21. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
14 VRAM Read Cycle (Page Mode) 33. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
15 VRAM Write Cycle (Page Mode) 34. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
16 VRAM Refresh Cycle 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
17 TVP3020 Interface Timing 35. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
18 Component Placement for Split Power Plane 38. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
19 Noninterlaced Monitor Timing (Separate SYNC) 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
20 1024 × 768 Display (Noninterlaced) 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–1 Schematics B-1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–2 TMS320C80-GF B-2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–3 TMS320C80 Power and Ground Connections B-3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–4 Address Buffers B-4. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–5 Data Transceivers (Big-Endian Configuration) B-5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–6 VRAM Bank 0 B-6. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–7 VRAM Bank1 B-7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–8 TVP3020 Pallette B-8. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–9 TVP3020 Power and Ground Connections B-9. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–10 Logic B-10. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
B–11 TMS320C80-Decoupling Caps B-11. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Tables
SPRA156vi
List of Tables1 Video-Timing Registers for Noninterlaced Video 5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 BS[1:0] Clock-Write Codes 12. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Component Delays 27. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 VRAM Timing Parameters – Access Times (2 cycles / column at 40 MHz) 27. . . . . . . . . . . . . 5 VRAM Timing Parameters – Setup and Hold Times (2 cycles / column; 40 MHz) 28. . . . . . . 6 VRAM Timing Parameters – Delay Times (2 cycles/column at 40 MHz) 29. . . . . . . . . . . . . . . 7 VRAM Timing Parameters – Access Times (3 cycles/column at 50 MHz) 29. . . . . . . . . . . . . . 8 VRAM Timing Parameters – Setup and Hold Times (3 cycles / column at 50 MHz) 29. . . . . . 9 VRAM Timing Parameters – Delay Times (3 cycles / column at 50 MHz) 31. . . . . . . . . . . . . . . 10 TVP3020 Interface Timing Parameters (50 MHz) 32. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Monitor Timings (Typical)† 40. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 TVP3020 Register Settings 42. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Video Timing Registers (Noninterlaced) 43. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Frame Timer Register Programming† 44. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Frame Timer Registers 45. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 SRT Controller Register Values 47. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 TMS320C80 Frame Buffer
TMS320C80 Frame Buffer
ABSTRACTThe TMS320C80 digital signal processor (DSP) provides direct support for twoindependent frame memories through on-chip controllers. This application reportpresents a 4M-byte video random-access memory (VRAM) based frame bufferinterface to the ’C80 DSP.
The report discusses the hardware interface for the frame buffer card palette. Also,included are a VRAM overview, information on frame-timer interrupts, andappendices covering materials, schematics, and ABEL files.
1 IntroductionHigh-end graphics and imaging applications often rely on a sophisticatedframe-buffering mechanism, wherein large amounts of data are displayedquickly and efficiently, without imposing significant constraints on thesystem’s ability to process the data. The TMS320C80 is well suited for suchapplications. The ’C80 provides direct support for two independent framememories through on-chip frame controllers. Additionally, the ’C80’sexternal bus interface directly provides the address multiplexing, bus-widthselection, wait-state support, configurable page size, and refresh controlrequired for multiple banks of dynamic memory typically used in framebuffers.
This application report discusses a 4M-byte VRAM (video random-accessmemory) based frame buffer interface to the TMS320C80 DSP. A 4M-byteframe buffer is large enough to support double buffering of most of the largerresolutions and also addresses the issue of serial output multiplexing. TheVRAMs’ serial ports feed directly to a color palette, the TVP3020 RAMDAC.Control of the TVP3020 is maintained by the ’C80. This report discusses thehardware interface for the frame buffer and palette.
ABEL is a trademark of DATA I /O.
Video Timing
SPRA1562
2 Video Timing
It is important to understand the many timing relationships that must existfrom one part of the system to the next in order to construct a complete framebuffer and display system. The three most important clocks in video — thepixel clock, the shift clock, and the video, or frame, clock — are discussedin the following paragraphs.
2.1 Pixel Clock
Pixel clock frequency refers to the conversion frequency. This is thefrequency at which the digital-to-analog converters (DACs) of the palettemust be able to convert the digital data stored in the frame buffer to analogred, green, and blue (RGB) outputs to drive the display device. The pixelclock rate is influenced by the amount of horizontal and vertical blankingrequired to conform to the monitor specifications.
2.2 Shift Clock
The serial shift clock (SCLK) is required to control the transfer of digital pixelinformation from the VRAM frame buffer to the RAMDAC pixel port. SCLKis normally a divide-down of the pixel clock frequency, where the divisorvalue is determined by the ratio of pixel port width to pixel size. For example,if 8-bit pixels are stored in the frame buffer that interfaces with a 64-bit serialbus, then eight pixels can be transferred in each SCLK cycle. SCLK is,therefore, pixel clock divided by 8. Shift clock is slightly different from theother clocks in that it is not continuous. SCLK does not function duringperiods of blanking, since no pixel data is to be displayed then. TheTVP3020 used in this design provides this feature.
2.3 Frame Clock
The video, or frame, clock is used to produce the horizontal timing signalsrequired to drive the display device. The frame clock also indirectly producesthe vertical timing signals. For many processors, this requires an externalframe timing chip to generate the sync and blanking signals from the frameclock. The ’C80 has two on-chip frame timers that can produce all therequired signals. These signals are derived from the frame clock (FCLK)input. The duration of blanking, sync, and a general-purpose area signal arecompletely programmable, allowing for many standards to be supported.Additionally, each frame timer can be user-programmed to interrupt themaster processor during a frame. ’C80 frame timers support both interlacedand non-interlaced modes.
Video Controller
3 TMS320C80 Frame Buffer
3 Video ControllerThe TMS320C80 provides two identical on-chip frame timers. Each frametimer has its own frame clock and operates asynchronously to the rest of the’C80. Each timer can be programmed to generate timing pulses on five videosignals that can be used to control a capture or display device. Figure 1shows the functional block diagram of the TMS320C80 video controller.
VC Register Interface
SRTController
SC
LK0
FrameTimer0
FrameTimer1
FC
LK0
32
SC
LK1
FC
LK1
MU
X
On-Chip Register Bus (MP)
FT0 Events
FT1 EventsCBLNK1 /VBLNK1
CSYNC1/HBLNK1
CAREA1
VSYNC1
HSYNC1
CBLNK0 /VBLNK0
CSYNC0/HBLNK0
CAREA0
VSYNC0
HSYNC0
VCRequest
(to TC)
Figure 1. TMS320C80 Video Controller
The five video signals are described below:
HSYNC I / O / Hi-Z Horizontal sync
VSYNC I / O / Hi-Z Vertical sync
CSYNC / HBLNK I / O / Hi-Z Composite sync / horizontal blank(user-selectable)
CBLNK / VBLNK O Composite blank / vertical blank (user-selectable)
CAREA O Composite area (general purpose)NOTE: I = input
O = outputHi-Z = high impedance
Video Controller
SPRA1564
3.1 Frame Timer Registers
All horizontal timing, and horizontal timing components of compositesignals, are programmed in terms of an integral number of frame clockperiods. Vertical timing parameters are programmed in terms of an integralnumber of lines (half-lines for interlaced). In this report, only thenon-interlaced mode is discussed.
The duration of sync, blanking, and area signals is completelyuser-programmable on the ’C80. Control is maintained though on-chipmemory-mapped registers. In this example, only frame timer 1 is used.Frame timer 1 is chosen because it allows more system flexibility. If acapture device is also to be controlled by the ’C80 in the system, it isdesirable to use frame timer 1 for the display. This allows the display systemto be clocked from the input if desired (frame timer 1 can be clocked fromFCLK0, but the contrary is not true).
Figure 2 and Figure 3 show the frame timer registers. As shown, horizontaltiming registers are located at even halfword addresses; their verticalcounterparts are located at odd halfword addresses.
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0x01820206 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
SETHCT0 ÁÁÁÁÁÁÁÁÁÁ
0x01820204ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VFTINT0 ÁÁÁÁÁÁÁÁÁÁ
0x0182020A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HESERR0 ÁÁÁÁÁÁÁÁÁÁ
0x01820208ÁÁÁÁÁÁÁÁÁVESYNC0 ÁÁÁÁÁ0x0182020E ÁÁÁÁÁÁÁÁÁÁÁÁHESYNC0 ÁÁÁÁÁ0x0182020CÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁVEBLNK0
ÁÁÁÁÁÁÁÁÁÁ0x01820212
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁHEBLNK0
ÁÁÁÁÁÁÁÁÁÁ0x01820210
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁVSAREA0
ÁÁÁÁÁÁÁÁÁÁ0x01820216
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁHSAREA0
ÁÁÁÁÁÁÁÁÁÁ0x01820214
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VEAREA0ÁÁÁÁÁÁÁÁÁÁ
0x0182021AÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HEAREA0ÁÁÁÁÁÁÁÁÁÁ
0x01820218ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VSBLNK0 ÁÁÁÁÁÁÁÁÁÁ
0x0182021E ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HSBLNK0 ÁÁÁÁÁÁÁÁÁÁ
0x0182021CÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VTOTAL0 ÁÁÁÁÁÁÁÁÁÁ
0x01820222 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HTOTAL0 ÁÁÁÁÁÁÁÁÁÁ
0x01820220ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HALINE0 ÁÁÁÁÁÁÁÁÁÁ
0x01820224ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HBLINE0 ÁÁÁÁÁÁÁÁÁÁ
0x01820228ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁVCOUNT0 ÁÁÁÁÁ0x0182023E ÁÁÁÁÁÁÁÁÁÁÁÁHCOUNT0ÁÁÁÁÁ0x0182023CÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁFigure 2. Frame Timer 0 Register Map
Video Controller
5 TMS320C80 Frame Buffer
ÁÁt
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ADDRESSÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ADDRESS ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
FTCTL1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x01820240 ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
SETVCT1 ÁÁÁÁÁÁÁÁÁÁ
0x01820246ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
SETHCT1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x01820244 ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VFTINT1 ÁÁÁÁÁÁÁÁÁÁ
0x0182024AÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HESERR1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x01820248 ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VESYNC1 ÁÁÁÁÁÁÁÁÁÁ
0x0182024EÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HESYNC1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x0182024C ÁÁÁÁÁÁÁÁÁVEBLNK1 ÁÁÁÁÁ0x01820252ÁÁÁÁÁÁÁÁÁÁÁÁHEBLNK1ÁÁÁÁÁÁ0x01820250 ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁVSAREA1
ÁÁÁÁÁÁÁÁÁÁ0x01820256
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁHSAREA1
ÁÁÁÁÁÁÁÁÁÁÁÁ0x01820254
ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VEAREA1ÁÁÁÁÁÁÁÁÁÁ
0x0182025AÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HEAREA1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x01820258ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VSBLNK1ÁÁÁÁÁÁÁÁÁÁ
0x0182025EÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HSBLNK1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x0182025CÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
VTOTAL1 ÁÁÁÁÁÁÁÁÁÁ
0x01820262ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HTOTAL1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x01820260 ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HALINE1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x01820264 ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
HBLINE1ÁÁÁÁÁÁÁÁÁÁÁÁ
0x01820268 ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁVCOUNT1 ÁÁÁÁÁ0x0182027EÁÁÁÁÁÁÁÁÁÁÁÁHCOUNT1ÁÁÁÁÁÁ0x0182027C ÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁFigure 3. Frame Timer 1 Register Map
Table 1 summarizes the programming of the frame timer registers fornoninterlaced mode. For a more detailed description of each of the frametimer registers, please refer to the TMS320C80 Video Controller User’sGuide, (literature number SPRU111A). Note that the programming of theregisters is the same for both composite and non-composite modes.
Table 1. Video-Timing Registers for Noninterlaced Video
ÁÁÁÁÁREGISTER ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁIS PROGRAMMED TO ...ÁÁÁÁÁÁÁÁÁÁHTOTAL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(The number of FCLKs per line) – 1ÁÁÁÁÁ
ÁÁÁÁÁHESYNC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of FCLKs in horizontal sync) – 1ÁÁÁÁÁÁÁÁÁÁ
HESERRÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of FCLKs in horizontal serration) – 1ÁÁÁÁÁÁÁÁÁÁ
HEBLNK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of FCLKs from the start of horizontal sync to the end of horizontal blank) – 1
ÁÁÁÁÁÁÁÁÁÁ
HSAREA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of FCLKs from the start of horizontal sync to the start of horizontal area) – 1
ÁÁÁÁÁÁÁÁÁÁ
HEAREA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of FCLKs from the start of horizontal sync to the end of horizontal area) – 1
ÁÁÁÁÁÁÁÁÁÁ
HSBLNK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of FCLKs from the start of horizontal sync to the start of horizontal blank) – 1
ÁÁÁÁÁVTOTAL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(The number of lines per frame) – 1ÁÁÁÁÁÁÁÁÁÁVESYNC
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(Twice the number of lines in vertical sync) – 1ÁÁÁÁÁ
ÁÁÁÁÁVEBLNK
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of lines from the start of vertical sync to the end of vertical blank) – 1ÁÁÁÁÁÁÁÁÁÁ
VSAREAÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of lines from the start of vertical sync to the start of vertical area) – 1ÁÁÁÁÁÁÁÁÁÁ
VEAREA ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of lines from the start of vertical sync to the end of vertical area) – 1ÁÁÁÁÁÁÁÁÁÁ
VSBLNK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of lines from the start of vertical sync to the start of vertical blank) – 1
ÁÁÁÁÁÁÁÁÁÁ
VFTINT ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(The number of lines from the start of vertical sync to the interrupt point) – 1
NOTES: 1. HESERR needs to be programmed only for composite mode; it is unused when separate horizontal and verticalsyncs are used.
2. VFTINT is discussed in more detail in Section 14.
Video Controller
SPRA1566
3.1.1 FTCTL Register
Control of the frame timer is maintained through the FTCTL register. Bits inthis register enable / disable the frame timer, select between interlaced andnon-interlaced modes, and control the direction of the frame timer pins(CAREA is always an output). See Figure 4 for FTCTLx register description.For a complete description of the FTCTL register, please refer to theTMS320C80 Video Controller User’s Guide, (literature number SPRU111A).
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTE IFD IIM SSE FLE CPM VPM HPM
Legend:
FTE – Frame timer enable VPM – VSYNC pin mode
IFD – Interlaced frame disable 00 – Hi-Z 10 – Output
IIM – Interlace interrupt mode 01 – Input 11 – Reserved
SSE – Set synchronization enable HPM – HSYNC pin mode
FLE – Frame lock enable 00 – Hi-Z 10 – Output
CPM – CSYNC/HBLNK pin mode 01 – Input 11 – Reserved
00 – CSYNC Hi-Z 10 – CSYNC output
01 – CSYNC input 11 – HBLNK output
Figure 4. FTCTLx Register
3.2 Horizontal and Vertical Timing Relationship
In this application report, a non-interlaced display is considered. Thefollowing figure illustrates the relationship between the horizontal andvertical timing signals, and the frame timer registers that control the signaltransitions for non-interlaced video.
• The horizontal sync and blanking signals span a single horizontal scanwithin the frame and are repeated for each line.
• The vertical sync and blanking signals span one complete frame.
The relationship between the sync and blanking pulses shown in Figure 5defines what are commonly called the porches in video timing. The videoporches are shown in Figure 6.
Video Controller
7 TMS320C80 Frame Buffer
Active Display
Horizontal Interval
(VESYNC–1)/2
VEBLNK
VCOUNT = 0
HSYNC
HBLNK
VSBLNK
VTOTAL
HE
SY
NC
Vertical Interval
HC
OU
NT
= 0
HE
BLN
K
HS
BLN
K
HTO
TAL
VB
LNK
VS
YN
C
unblanked display
blanked display
Figure 5. Horizontal and Vertical Timing Relationship
Video Controller
SPRA1568
ÇÇÇÇ
ÇÇÇÇÇÇ
Active Display
HSYNC
HBLNK
unblanked display
blanked display
ÇÇÇÇ
VB
LNK
VS
YN
C
ÍÍÍÍ
Horizontal backporch
Horizontal frontporch
Vertical backporch
Vertical frontporch
The interval between the end of horizontal sync and theend of horizontal blanking
The interval between the beginning of horizontal blankingand the beginning of horizontal sync
The interval between the end of vertical sync and theend of vertical blanking
The interval between the beginning of vertical blankingand the beginning of vertical sync
ÍÍÍÍ
Figure 6. Video Porches
Note that in Figure 5 it was assumed that the ’C80 directly drove the syncand blanking signals to the display device. These signals can be driven fromthe RAMDAC instead. Skews through the RAMDAC affect the position of thesync and blanking transitions in an absolute sense; however, as the skewis constant, it does not affect the programming of most of the timingregisters.
VRAM Overview
9 TMS320C80 Frame Buffer
4 VRAM OverviewArchitecturally, VRAM is very similar to DRAM. In fact, VRAM is actually thesame dynamic memory array, with several key additions that optimize it forframe buffer designs. The two key features are the support for block writecycles, which is a special write cycle that allows the user to efficientlyprocess pixel data, and the addition of a serial access port.
In this report, the frame buffer is made up of TMS55161 (-60) VRAMs (x8).The TMS55161 (-60) VRAMs are organized as 512 rows × 512 columns ×16 I / Os. The serial port is organized as 256 × 16 I / Os and is connected tothe pixel port of the TVP3020. Data is written into the memory array from the’C80 by way of the parallel interface. Figure 7 is a simplified block diagramshowing a portion of a VRAM. Notice that when used with TMS55161s, thisstructure is replicated four times, providing sixteen bit planes in one device.
Multiplexing Hardware
SAM Length
DQ2
DQ3
DQ1
DQ0
SQ0
Output Drivers/Transceivers (Parallel I/O)
Row Length
MemoryCell
Row
Column
BitPlane
Page
Serial Output Buffer
Serial DataRegister
Figure 7. VRAM Architecture
VRAM Overview
SPRA15610
Each TMS55161 features a 256-bit-long register, referred to as theserial-access memory (SAM). Each bit plane in the VRAM (16 total), has itsown dedicated SAM. Data stored into the memory array is transferred intothe SAM in a memory-to-register transfer. The data is then shifted outserially to the RAMDAC on the SQ outputs (SQ15–SQ0), at the rate of theshift clock (SCLK) input to the VRAMs.
4.1 Memory-to-Register Transfers
Each TMS55161 supports two modes of memory-to-register transfers:full-register transfers and split-register transfers. In both modes, the basicoperation is the same: data from the memory array is copied into the SAM.The TMS55161 allows either the entire SAM, or half of the SAM to be writtenin each memory-to-register transfer. The split- (half-) register transfer iswidely used in the following two cases:
• In systems where there is not enough data in the register to completeone horizontal line, and therefore new data must be transferred in themiddle of an active scan line.
• When the resolution does not match the amount of information storedin a row of the memory array, and therefore the information needs to bepacked as tightly as possible.
In the split-register transfer operation, the serial register is divided into twohalves. While one half is being read out of the SAM port, the other half canbe loaded from the memory array. This requires precise synchronization tomaintain a smooth display. If the register-to-memory transfers are notscheduled at the proper time, the display can be corrupted. With manyprocessors, this requires a complex array of counters, comparators, andlogic to maintain synchronization. The TMS320C80 video controller alsohas two separate SRT (serial-register transfer) controllers to complementthe frame timers. The SRT controllers are identical, and each can be usedto control a frame memory for either capture or display. The scheduling ofboth full- and split-register transfers, as well as the generation of the properbus cycles, is provided by the TMS320C80 video and transfer controllers.The SRT controllers are described in Section 13.
The SAM register of each TMS55161 is 256 bits in length, or one-half thelength of a VRAM row; therefore, full transfers move either bits 0–255 or256–511 of a VRAM row into the SAM. A split-register transfer transfers bits0–127, 128–255, 256–383, or 384–512 into bits 1–127 or 128–255 of theSAM. This is illustrated in Figure 8.
VRAM Overview
11 TMS320C80 Frame Buffer
A B C DE
A B
5110
Full XFER
A B C DE
C B
5110
Split XFER
A B C DE
C D
5110
Split XFER
A B C DE
E D
5110
Split XFER
SQ SQ SQ SQ
0 255 0 255 0 255 0 255
Figure 8. Split-Register Read Transfer Operation
The SQ arrow shown in Figure 8 indicates the active SAM half, the part ofthe SAM that is being serially shifted out to the RAMDAC. Split transfers,which occur during active display, are always done to the inactive SAM half.This prevents corruption of the displayed video. The ’C80’s SRT controllerhandles the scheduling of all full and split transfers for the system.
4.2 Block Write
A second feature that makes VRAM unique is support for special writecycles known as block-writes. Block-write is a high-level function that cangreatly enhance applications such as rectangle-fill, rapid text, and clearscreen operations. Many types of block-writes are available to match themany sizes of VRAM available. In general, a block-write is expressed inthree dimensions.
column locations per color register × length of color register × number of color registers
The TMS320C80 supports both 8x and 4x block-write cycles; this featureallows up to 64 bits of data to be written simultaneously to each device in thememory bank. This is accomplished by transferring a color value from aninternal (to the VRAM) register to the memory, in what is called aload-color-register (LCR) cycle. The ’C80 performs an LCR cycle at the startof a block-write cycle. The color register value is defined in thepacket-transfer parameter table which sets up the block-write. For moreinformation on block-write packet transfers, please refer to the TMS320C80(MVP) Transfer Controller User’s Guide (literature number SPRU105A).TMS55161s described in this application report implement4 × 4 × 4 block-write cycles.
VRAM Overview
SPRA15612
In the case of 4x block-writes, the ’C80 writes 32 bytes in a single access.This requires some bit manipulation by the transfer controller. Normally, the’C80 bus size (BS[1:0] pins) indicates the bus width of the memory bankbeing addressed. However, since the ’C80 supports only 64-bit-wideblock-write cycles, the BS inputs are used to define the block-write mode forthese cycles. The status code 001001 is output on STATUS[5:0] to indicatethat the block-write is occurring, and must be decoded by external hardwareto indicate the block-write mode. The codes listed in Table 2 are defined forthe BS inputs during block-write.
Table 2. BS[1:0] Clock-Write Codes
ÁÁÁÁÁÁÁÁ
BS[1:0]ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
BLOCK-WRITE MODE
ÁÁÁÁÁÁ
0ÁÁÁÁ
0ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Simulated
ÁÁÁ0ÁÁ1ÁÁÁÁÁÁÁÁReservedÁÁÁÁÁÁ1ÁÁÁÁ0ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ4xÁÁÁ
ÁÁÁ1ÁÁÁÁ
1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
8x
The “blocks” in block-writes (4x) cross four columns of a row of the VRAMarray, therefore, there are 128 blocks per row (512 / 4). During the 4xblock-write cycles, only the seven most significant bits (MSBs) of the columnaddress are latched (with CAS) to decode one of the 128 blocks. Each bitof the source data can force up to four consecutive columns to be written ata time. Note that the data written to the memory array is actually data fromthe color register, not the VRAM data inputs. An example of block-write isshown in Figure 9. It should be noted, however, that Figure 9 cannot beinterpreted as an actual block-write cycle, nor does it accurately describe theVRAM hardware that implements block writes. It is included to demonstratethe relationship between data bits during block-write cycles and the valuestored in the color register of the VRAM, and the writes that they produceduring block-write cycles.
VRAM Overview
13 TMS320C80 Frame Buffer
Bit Plane 15
1111111101010101
0000111101100111
0011110011101111
0010000011000011
0111111110101110
1010000000000000
0001010011110011
0010010000101000
1001011011110001
0110011001101010
0000010011111111
0010110011101111
0100011111111111
1010111010101110
0011110011010111
0000110000000100
Bit Plane 15
Memory Before Block Write:0x163EB1E30x17EE31320x538EF35F0xD3DFF123
Block-Write CycleColor Register = 0x2A2ASrc Data = 0xF00F
Memory After Block Write:0x2A2A2A2A0x17EE31350x538EF35F0x2A2A2A2A
Bit Plane 0 Bit Plane 0
0110011100001111
0101010111111111
LCR15 0LCR14 0
LCR13 1LCR12 0
0110011100001111
0101010111111111
0110011100001111
0101010111111111
0110011100001111
0101010111111111
Src2
Src14
Src0
LCR11 1LCR10 0
LCR9 1LCR8 0
Src2
Src14
Src0
LCR7 0LCR6 0
LCR5 1LCR4 0
Src3
Src15
Src1
LCR3 1LCR2 0
LCR1 1LCR0 0
Src3
Src15
Src1
00
10
10
10
00
10
10
10
Figure 9. Example of Block-Write
VRAM Overview
SPRA15614
Support for block-write is not mandatory. Block-write is most often used forhigh-end graphics applications where speed is critical. Block-write is aninherently little-endian function. In little-endian systems, byte 0 correspondsto CAS0, which is controlled by bit 0 of the source data. In big-endiansystems, byte 0 corresponds to CAS7, but still must be controlled by databit 0. Therefore, data lines connected to the VRAM bank must bebit-reversed, on a by-device-width basis. For the 16-bit-wide VRAMS usedhere, a complete reversal of 16 bits (63–48, 47–32, 31–16, and 15–0) isrequired in order to support block-writes. Additionally, the pixel portconnection to the VRAMs’ SQ outputs needs to be swapped accordingly. Asecond implementation is used in this application report, which involves onlyone bus swap. While both methods are acceptable, this single swap can bemore desirable as it often simplifies board routing and decreases thenumber of layers required to interface to the VRAM. The single swap alsorequires that the CAS lines be swapped as well. Schematics for thisimplementation are shown in Appendix B.
Normal reads and writes are not affected. The bus is bit-reversed for bothreads and writes, and therefore, functions as if the data line connection isdirect. In this design, which is big-endian, the data lines are bit-reversed andblock-write (4x) is supported.
SRT Controller Register Programming
15 TMS320C80 Frame Buffer
5 SRT Controller Register ProgrammingAs mentioned in Section 4.1, the TMS320C80 has two on-chip SRTcontrollers that are responsible for scheduling the full- and split-registertransfers. Requests are passed onto the transfer controller, which, in turn,actually performs the memory-to-register (read) transfer. The SRTcontrollers are clocked by the system shift clock (SCLK); the same SCLKthat controls the serial port of the VRAMs. Like the frame timers, the SRTcontrollers are programmed through on-chip memory-mapped registers.The SRT controller registers are shown in Figure 10.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ADDRESSÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ADDRESSÁÁÁÁÁÁÁÁÁÁÁFMEMCTL0ÁÁÁÁÁ0x01820300ÁÁÁÁÁÁÁÁÁÁÁÁFMEMCTL1ÁÁÁÁÁ0x01820340ÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁF1STADR0
ÁÁÁÁÁÁÁÁÁÁ0x01820304
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁF1STADR1
ÁÁÁÁÁÁÁÁÁÁ0x01820344
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
F0STADR0ÁÁÁÁÁÁÁÁÁÁ
0x01820308ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
F0STADR1ÁÁÁÁÁÁÁÁÁÁ
0x01820348ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
LINEINC0ÁÁÁÁÁÁÁÁÁÁ
0x0182030CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
LINEINC1ÁÁÁÁÁÁÁÁÁÁ
0x0182034CÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
SAMMASK0ÁÁÁÁÁÁÁÁÁÁ
0x01820310ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
SAMMASK1ÁÁÁÁÁÁÁÁÁÁ
0x01820350ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
NEXTADR0ÁÁÁÁÁÁÁÁÁÁ
0x01820314ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
NEXTADR1ÁÁÁÁÁÁÁÁÁÁ
0x01820354ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
CRNTADR0ÁÁÁÁÁÁÁÁÁÁ
0x0182033CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁ
CRNTADR1ÁÁÁÁÁÁÁÁÁÁ
0x0182037CÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Figure 10. SRT Controller Register Map
5.1 FMEMCTL Register
Similar to the FTCTL (frame timer control) register, control over each SRTcontroller is facilitated through the FMEMCTL register (see Figure 11). Bitsin this register control half-length SAM select, interlaced line-repeat option,and frame-timer selection among others. Also, events are selected with thisregister.
SRT Controller Register Programming
SPRA15616
31 30 2829 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FTS
HSS
ILR
PTS
TMS
EMS
UED
HSS – Half-SAM select TMS – Transfer-mode select UED – Unblanked event disableILR – Interlace line repeat 00 – Display 10 – Capture FTS – Frame timer sequencerPTS – Packet-transfer select 01 – Reserved 11 – Merge capture 00 – ft0 /disabled 10 – ft1 /disabled
EMS – Event-mode select 01 – ft0 /enabled 11 – ft1 /enabled00 – SOF, line, SAM 10 – SOF, line01 – SOF, EOF, SAM 11 – none
Figure 11. FMEMCTLx Register
There are four events that determine when SRT events are to be scheduled
• Start of field End of vertical blanking (once per frame)
• End of field Start of vertical blanking (once per frame)
• Line Start of horizontal blanking (once per line)
• SAM overflow Current address increment > previous tap point + SAMlength
SAM overflow events are distinguished from the other event types in thatthey are generated from within the SRT controller itself. The point at whicha SAM overflow is generated is dependent on the bus width to the VRAMport and the size of the SAM in each VRAM. These two pieces of informationare stored in the SAMMASK register of the ’C80.
There are two rules that should be observed when programming theSAMMASK register.
• There are n contiguous 1’s in SAMMASK, where n = log2(split SAMlength)
• The least significant 1 of SAMMASK should be aligned to correspondwith the bit that increments in CRNTADR with every SCLK. Since a 64-bitbus is considered here, this is bit 3 (bits 0–2 are ignored, since the CASlines serve as byte strobes to the VRAM).
Programming for SAMMASK is shown in Section 13.
SRT Controller Register Programming
17 TMS320C80 Frame Buffer
5.2 Address Tracking
The SRT controller tracks the address of the current pixel. The addressincrements on every SCLK; the increment position corresponds to the leastsignificant bit in the SAMMASK register (that is, if the least significant (LS)bit of SAMMASK is bit 3, the current address increments by 8 on eachSCLK). The address is tracked in the CRNTADR register. The next addressregister (NEXTADR) tracks the address of the first pixel on the next line,when line events are enabled. Line and field events automatically updatethis register. Line events force NEXTADR to be updated by adding the lineincrement (LINEINC) to NEXTADR. It should be noted that the SRT addressis taken from NEXTADR before it is updated. This pre-updated address isalso stored into CRNTADR. The value in the LINEINC register representsthe number of bytes between two vertically adjacent pixels in a frame.
Field events cause one or more SRTs to be performed at the address storedin the field-start-address (F0STADR) register. This register is copied intoCRNTADR, and the value of F0STADR plus LINEINC is stored intoNEXTADR. F1STADR is used in interlaced mode to identify the start of theother field. End-of-field events look like line events, and are used only forcapture systems.
TVP3020 Overview
SPRA15618
6 TVP3020 OverviewThe TVP3020 video interface palette provides extensive flexibility throughseveral key features. Among these are support for both big- and little-endianpixel formats, variable pixel bus size, and support for 24-bit true-colormodes. The TVP3020 has an internal frequency doubler that providesconvenient and cost-effective clock sources. The TVP3020 generates theserial shift clock, video clock, and reference clock required by the system.Additionally, the RCLK / SCLK / LCLK pixel-latching mechanism of theTVP3020 allows for very flexible control of VRAM timing.
The TVP3020 has three 8-bit digital-to-analog converters (DACs) which aresufficient to drive the RGB inputs of most monitors directly. Horizontal andvertical sync signals are passed through the device. As an option, thesesync signals can be inverted. Three 256-by-8-color lookup tables (RAMs)are also provided, and are completely user-programmable. Data out of theRAMs is multiplexed with optional cursor data and overscan-boundary data(if oversacan is used) before being passed to the DACs. All color RAMs aredual-ported to support extremely fast operation. The TVP3020 comes inthree speed grades: 135 MHz, 175 MHz, and 200 MHz; the speed gradesare indicative of the maximum pixel clock frequency. A block diagram of theTVP3020 is shown in Figure 12.
TVP3020 Overview
19TMS320C80 Frame Buffer
Inpu
tLa
tch
2:1
MU
X64
True
-Col
orM
ultip
lexe
r32
32
8-8-
8
6-6-
4
5-6-
6
5-5-
5
4-4-
4
24 16P
[63:
0]
6412
–24
24S
tuffi
ngLo
gic
Dire
ct C
olor
Pip
elin
e D
elay
256
x 8
Red
RA
M
256
x 8
Gre
enR
AM
256
x 8
Blu
eR
AM
1 x
24C
urso
rC
olor
0
1 x
24O
vers
can
8 8 8 24 24
Out
put
MU
X
Vre
f1.
235
V
CO
MP
16 15 12
Pse
udo-
Col
orM
UX
1:1
2:1
4:1
8:1
16:1
32:1
32
1 2 4 8
8
Rea
dM
ask
8In
put
Latc
hV
GA
[7:0
] 8
8
Pag
eR
egD
AC
Fre
quen
cyD
oubl
er
MP
U R
egis
-te
rs a
nd C
ontr
olLo
gic
Clo
ck S
elec
tan
dC
ontr
ol
8
88 8 8
Col
or K
eyS
witc
h
64x6
4C
urso
rR
AM
and
Con
trol
8
2 4
Aux
iliar
y W
indo
wan
dP
ort S
elec
t
Test
Fun
ctio
nan
dS
ense
Com
para
tor
8
DA
C8
DA
C8
1 x
24C
urso
rC
olor
1
24
Vid
eo-S
igna
lC
ontr
ol
RESET
I/O[4:0]
CLK0
CLK1
CLK2/CLK2
SFLAG
LCLKRCLKSCLKVCLK
8/6OVS
SYSHS
SYSVSSYSBLVGAHS
VGAVSVGABL
PSEL
HS
YN
CO
UT
VS
YN
CO
UT
RE
F
FS
AD
J
D[7
:0]
RS
[2:0
]
WR
RD
52
2
IOR
IOB
IOG
SE
NS
E
1
Fig
ure
12.
TV
P30
20 B
lock
Dia
gram
SPRA15620
6.1 TVP3020 Clocking
The TVP3020 is responsible for providing all of the clocks in the frame buffersystem. All clock outputs are generated from an input reference clock. TheTVP3020 allows selection between one of two TTL-compatible, or oneECL-compatible reference clock. These can be selected to drive the pixelclock directly, or can be doubled internally to produce faster pixel clock rates.
The TVP3020 provides three clock outputs: RCLK (reference clock), SCLK(shift clock), and VCLK (video or frame clock). RCLK is continuous, and isnot disabled during blanking. For most applications, it is tied back into thepalette as the LCLK (latch clock) input. Pixel data is latched into the deviceon the rising edge of LCLK. Data is requested out of the VRAMs by the risingedge of SCLK; therefore, SCLK is the same as RCLK, but it is disabledduring blanking.
Because multiple pixels can be transferred on a single cycle, both theRCLK / LCLK and SCLK frequencies are a function of the desiredmultiplexing ratio. VCLK is used as the reference clock for generating theSYSBL (system blank, composite), SYSHS (horizontal sync), and VSYNC(vertical sync) input signals. Since these signals are provided by the ’C80,the VCLK output is tied to the ’C80’s FCLK input. Like RLCK / LCLK andSCLK, the VCLK output can be programmed as a divide-down version of thereference input.
TVP3020 Overview
System Overview
21 TMS320C80 Frame Buffer
7 System Overview
The frame buffer system described in this application report has thefollowing architecture.
TMS320C80
HVRGB
TVP3020
GlueLogic
LATCH
BUFFERS
VRAM Bank 0
VRAM Bank 1(Optional)
PS[3:0]
CT[2:0]
AS[2:0]
BS[1:0]
VSYNC
HSYNC
CBLNK
Address
Status
RAS
RAS0
Pixel Data64
W
TRG
DSF
Data
RD
WR
RS[2:0]
64
8
RAS1
DB15 out
SCLK
FCLK
CAS[7:0]
Figure 13. System Block Diagram
System Overview
SPRA15622
7.1 Video Signals
The ’C80 accepts the FCLK and SCLK inputs provided by the TVP3020.These signals are 5-V signals and, therefore, they must be buffered. A244-type LVT buffer is used to buffer these signals. The clock inputs serveto drive one of the ’C80’s frame timers and one of the SRT controllers. In thisexample, frame timer 1 and SRT controller 1 are used. In turn, the ’C80output drives HSYNC, VSYNC, and CBLNK to the SYSHS, SYSVS, andSYSBL inputs of the RAMDAC. In this example, the sync signals to thedisplay device (DB15 connector) are driven by the palette, along with theRGB data.
7.2 VRAM Connection
The VRAM serial ports are connected to the pixel input port of the TVP3020.As discussed in Section 4.2, the pixel port does not need to be bit-reversed(the reversal is handled on the TMS320C80 side). SCLK from the TVP3020controls the transfer of data from the VRAM banks.
The ’C80’s address and data buses interface with the VRAM banks, as isnormally done by other banks of dynamic memory, with exception to theswapped data lines (for little-endian designs, the swap is not necessary).The data connections are made to the parallel I / O (DQ) side of the VRAMs.In this design, LVT16245 drivers are used for the data-bus connections. TheVRAM banks are interfaced at 2 cycles / column for a 40-MHz design; at50 MHz, 3 cycles / column must be used since the cycle time is violated at2 cycles / column. Address, CAS, W, DSF, and the TRG signals are alsobuffered to the VRAM devices. This is not necessary, since the 3.3-V drivelevel meets the VIH specification of the TMS55161 VRAMs. However, sincethese lines are typically heavily loaded, the addition of transceivers isadvantageous.
7.3 Address Lines
The TMS55161s are arranged as 256K × 16-bit memories. As indicated onpage 7–13 of the TMS320C80 (MVP) Transfer Controller User’s Guide(literature number SPRU105A), a 256K × n device, AS[2:0] = 010 should beused. Since the VRAM banks are addressed as 64-bit-wide memory(BS[1:0] = 11), the three least significant bits of the column address areignored (CAS lines select bytes). Therefore, bit 3 is the least significant bitthat should address the VRAM bank. For AS[2:0] = 010, bit 3 correspondsto C80A12. C80A12, is therefore, connected to A0 of the TMS55161s. Sincenine bits are required for each VRAM, address lines C80A12–C80A20 aresufficient to address the entire memory array. Bank selection for the optionalbank is controlled using C80A21 (see Section 7.5).
System Overview
23 TMS320C80 Frame Buffer
Address lines 2–0 (buffered C80A[2:0]) are also required to interface withthe TVP3020. These signals are connected to the RS[2:0] inputs of theTVP3020, which decode the internal register file of the palette.
7.4 Data Lines
The TMS55161s are 5-V parts, and therefore, the data lines must bebuffered to interface with the ’C80. This design supports 4x block-writes andoperates in big-endian mode. This creates the need to bit-reverse the entire64-bit data bus between the ’C80 and the VRAM bank(s). This swap isperformed on the VRAM side of the data transceivers (SN74LVT16245s).While a swap on either side is acceptable, this implementation allows thetransceivers to be used by other memories and peripherals withoutperforming a dual-swap.
7.5 Glue Logic
There is a minimal amount of glue logic associated with this design. Thelogic in this report is implemented in PAL / GAL devices, though theequations presented here are valid for ASIC and FPGA designs as well.External logic is used to generate the cycle-configuration inputs to the ’C80,the serial-output-enables of the VRAM banks (2), separate RAS signals forthe two banks, and the control inputs (RD and WR) for the palette. Twobanks of VRAM (4M bytes total) are considered here. Many resolutions andframe rates do not require this much frame buffer space. The inclusion of thesecond bank of VRAM is done here to illustrate the necessary pixel-muxingand serial output-enable-decoding that is required for a system that uses thelarger frame buffer.
7.5.1 RAS Generation
In order to address the two banks of VRAM separately, a RAS signal mustbe generated for each bank. The signals are generated by conditioning the’C80’s RAS signal on a valid address decode, status decode (masking outSDRAM MRS, SDRAM DCAB, and refresh cycles), and bank-select, whichis determined by a latched address bit (latched with the RL output of the ’C80at row time). Refreshes are separated into two areas (accounts for memoryexpansion), 0 and 1, of the refresh map; which is decoded with C80A16 andC80A17 of the refresh pseudo-address. The VRAM banks are decoded at0xA0000000. An expression for the VRAS signals might look like thefollowing:
!_VRAS0 = (!_RAS & VRAM_AV & !LC80A21 & !SDRAM_cyc & !refresh).#(!_RAS & refresh & !LC80A17 & !LC80A16);
!_VRAS1 = (!_RAS & VRAM_AV & LC80A21 & !SDRAM_cyc & !refresh).#(!_RAS & refresh & !LC80A17 & LC80A16);
System Overview
SPRA15624
where
S5 = STATUS5; externally latched by RL
S4 = STATUS4; externally latched by RL
S3 = STATUS3; externally latched by RL
S2 = STATUS2; externally latched by RL
S1 = STATUS1; externally latched by RL
S0 = STATUS0; externally latched by RL
VRAM_AV = !LC80A31 & LC80A30 & !LC80A29 & LC80A28;
SDRAM_cyc = !S5 & !S4 &!S3 &!S2 & S1 & S0#!S5 & !S4 & S3 & S2 & !S1 & !S0;
refresh = !S5 & !S4 &!S3 &!S2 & S1 & !S0;
7.5.2 Serial Output Enable
In order to safely connect the serial outputs of both VRAM banks to the TVPpixel port, control logic for the VRAM serial-output-enables must begenerated. This is a normal process, as the ’C80 performs the SRT cyclesfor both banks. While there are many solutions, one of the simplest is shownbelow. Again, bit A21 is used as the bank select.
_VSE1 = (SRT & LC80A21 & !_RAS)
#(_VSE1 & !SRT)
#(_VSE1 & _RAS);
_VES0 = !_VSE1;
SRT as indicated by row time status
_VSE1 serial output enable for bank 1
_VSE1 serial output enable for bank 0
This simple implementation guarantees that both serial outputs cannot beenabled at the same time.
7.5.3 Cycle-Configuration Inputs
The cycle-configuration inputs are made up of the AS[2:0] (address shift),BS[1:0] (bus size and block-write mode), CT[2:0] (cycle timing), and PS[3:0](page size) signals. These signals are read in at row time, and dictate howthe ’C80’s transfer controller should continue with the rest of the cycle.Additionally, the ’C80 also reads in the UTIME input, which selects theuser-timed modified cycle modes. These cycles are used to interface withthe TVP3020.
System Overview
25 TMS320C80 Frame Buffer
Column timing is dependent on the system operating speed. For 50-MHzdesigns, 3 cycles / column must be specified (CT[2:0] = 111). At 40-MHzCLKOUT speed, 2 cycles / column (CT[2:0] = 110) can be used. Equationsare presented in this application report for both a 40- and a 50-MHz system.Page size can be calculated as row length X bus width (512 X 64), which isequal to 4K bytes (PS[3:0] = 1010). Note that this page size exists for eachbank individually, since both banks cannot be accessed simultaneously.Address shift (AS[2:0]) is set to 010 as shown in Section 7.3, and bus size(BS[1:0]) is 11 (64 bits).
The glue logic must also respond with cycle configuration inputs whenaddressing the TVP3020 palette. The palette interface, which is SRAM-likein nature, requires the user to modify the timing cycles. To enable thesecycles, UTIME must be sampled low at row time during the r2 state. The RASsignal is significantly modified for the user-timed accesses. It does nottransition until column time, and only remains low for 1 CLKOUT cycle.External logic must use these transitions to generate the read and writesignals to the RAMDAC. The TVP3020 specifies a minimum RD or WRpulse width of 50 ns. This requires a 3-cycle / column user-timed cycle withone wait state inserted by pulling the READY signal low. The cycle diagramfor the palette read and writes is shown in Figure 17.
Bus size for the palette is 8 bits (BS[1:0] = 00), and page-mode cycles aredisabled (PS[3:0] = 1000). Since the palette is a non-paged device,AS[2:0] = 000 for palette reads and writes.
Expressions for the cycle configuration inputs might look like those shownin the following example. In this application, VRAM banks are decoded at0xA0000000. The optional bank 1 is contiguous to bank 0. The palette isdecoded at 0x80000000. Note that in the following equations, S5–S0 referto STATUS5–STATUS0 signals from the ’C80. These signals should betaken from the ’C80 directly without latching in order to meet access time.Refresh cycles are decoded using the ’C80’s pseudo-address output onC80A[31:16]. VRAM banks 1 and 0 are decoded to refresh banks 1(C80A17 = 0, C80A16 = 1) and 0 (C80A17 = 0, C80A16 = 0), respectively.
Equations
AS2 = SYSTEM_SPECIFIC_REQUIRING_AS2=1;
AS1 = (VRAM_AV) & !(SDRAM_cyc # refresh)#(SYSTEM_SPECIFIC_REQUIRING_AS1=1);
AS0 = (SYSTEM_SPECIFIC_REQUIRING_AS0=1);
BS1 = (VRAM_AV) & !(SDRAM_cyc)#(VRAM_AV) & block_wrt#(SYSTEM_SPECIFIC_REQUIRING_BS1=1);
BS0 = (VRAM_AV) & !(SDRAM_cyc # blk_wrt)#(SYSTEM_SPECIFIC_REQUIRING_BS0=1);
CT2 = (VRAM_AV) & !(SDRAM_cyc # refresh)# VRAM_refresh#(TVP_AV) & !(SDRAM_cyc # refresh)#(SYSTEM_SPECIFIC_REQUIRING_CT2=1);
CT1 = (VRAM_AV) & !(SDRAM_cyc # refresh)# VRAM_refresh#(TVP_AV) & !(SDRAM_cyc # refresh)#(SYSTEM_SPECIFIC_REQUIRING_CT1=1);
CT0 = (VRAM_AV) & !(SDRAM_cyc # refresh)# VRAM_refresh#(TVP_AV) & !(SDRAM_cyc # refresh)#(SYSTEM_SPECIFIC_REQUIRING_CT0=1);
PS3 = (VRAM_AV) & !(SDRAM_cyc # refresh)#(TVP_AV) & !(SDRAM_cyc # refresh)#(SYSTEM_SPECIFIC_REQUIRING_PS3=1);
PS2 = (SYSTEM_SPECIFIC_REQUIRING_PS2=1);
PS1 (VRAM_AV) & !(SDRAM_cyc # refresh)#(SYSTEM_SPECIFIC_REQUIRING_PS1=1););
PS0 = (SYSTEM_SPECIFIC_REQUIRING_PS0=1);
!UTIME = (TVP_AV) & !(SDRAM_cyc)#(!RESETIN);
Constants and alias names:S5 = STATUS5;
S4 = STATUS4;
S3 = STATUS3;
S2 = STATUS2;
S1 = STATUS1;
S0 = STATUS0;
VRAM_AV = C80A31 & !C80A30& C80A29 & !C80A28;
TVP_AV = C80A31 & !C80A30 &!C80A29 & !C80A28;
block_wrt = !S5 & !S4 & S3 & !S2 &!S1 & S0;
SDRAM_cyc = !S5 & !S4 &!S3 &!S2 &S1 & S0 #!S5 & !S4 &S3 & S2 & !S1 & !S0;
refresh = !S5 & !S4 &!S3 &!S2 &S1 & !S0;
VRAM_refresh = !S5 & !S4 &!S3 &!S2 &S1 & !S0 &((!C80A17 &C80A16) #(!C80A17 &!C80A16));
NOTES:SYSTEM_SPECIFIC_REQUIRING_xxx conditionsshould not set the cycle configuration inputs for theVRAM cycles.
Signal SDRAM_cyc does not need to be generated ifSDRAM is not present in the system.
RESETIN is the system reset signal (active low).
Equations have not been simplified.
System Overview
SPRA15626
Example 1.
ÁÁÁÁÁÁÁÁÁÁCYCLE CODE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁVALUE (VRAM)ÁÁÁÁÁ
ÁÁÁÁÁAS[2:0]
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
010 (512K X n)ÁÁÁÁÁÁÁÁÁÁ
BS[1:0]ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
11 (64-bit bus)ÁÁÁÁÁÁÁÁÁÁ
CT[2:0] ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
111 or 110
ÁÁÁÁÁÁÁÁÁÁ
PS[3:0] ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1010 (4K)
ÁÁÁÁÁÁÁÁÁÁCYCLE CODE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁVALUE (TVP3020)ÁÁÁÁÁ
ÁÁÁÁÁAS[2:0]
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
000 (static)ÁÁÁÁÁÁÁÁÁÁ
BS[1:0]ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
00 (8-bit bus)ÁÁÁÁÁÁÁÁÁÁ
CT[2:0] ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
111 (3 cycles / column)
ÁÁÁÁÁÁÁÁÁÁ
PS[3:0] ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
1000 (bus size)
Timing Analysis
27 TMS320C80 Frame Buffer
8 Timing AnalysisThe VRAM interface must meet a considerable number of timingparameters. Among these are access times from both RAS and CAS,address setup and hold times, data setup and hold times, and propagationdelays from input to input for read, write, and refresh cycles. The parametersof interest are presented in the following timing diagrams for page-modereads, page-mode writes, and refresh cycles, just as a standard DRAMinterface. Additionally, the special VRAM cycles of block-write and load colorregister (LCR) must be examined. Table 4 through Table 10 containequations and values for each of the calculated parameters. Datatransceiver, W, DSF, TRG, CAS, and address delays are considered. Also,since RAS signals for the VRAM bank(s) are generated in external logic, amaximum logic delay is considered. The following parameters are used inthe timing calculations.
Table 3. Component Delays
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DESCRIPTION ÁÁÁÁÁÁÁÁÁÁÁÁ
MNEUMONICÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁMaximum logic delay
ÁÁÁÁÁÁÁÁÁÁÁÁtPROPPALMAX
ÁÁÁÁÁÁÁÁÁÁÁÁ7.5 nsÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁMaximum transceiver delayÁÁÁÁÁÁÁÁÁÁÁÁtPxx245MAX†
ÁÁÁÁÁÁÁÁÁÁÁÁ4.1 nsÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁMinimum transceiver delay
ÁÁÁÁÁÁÁÁÁÁÁÁ
tPxx245MINÁÁÁÁÁÁÁÁÁÁÁÁ
1.0 nsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Maximum buffer delay ÁÁÁÁÁÁÁÁÁÁÁÁ
tPxx244MAXÁÁÁÁÁÁÁÁÁÁÁÁ
4.1 nsÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Minimum buffer delay ÁÁÁÁÁÁÁÁÁÁÁÁ
tPxx244MINÁÁÁÁÁÁÁÁÁÁÁÁ
1.0 ns
† x replaced by L and H where applicable. For example, tPHL indicateshigh-to-low transition; tPLH indicates low-to-high transition.
In addition to the VRAM interface timing, the timing for the ’C80 cycleconfiguration inputs should also be evaluated. As these signals aregenerated in external logic and feed directly back to the ’C80, the analysisis simple:
ta(MIDV-CFGV) = tPROPPAL= 7.5 ns
The ’C80 only requires that ta(MIDV-CFGV) be less than 20 ns (3tH–10) at50 MHz.
Table 4. VRAM Timing Parameters – Access Times (2 cycles / column at 40 MHz)
ÁÁÁÁÁÁ
NO.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULA(WITHOUT CAS BUFFERS)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
’C80 SPECIFICATION (ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
40 MHzRESULT
(ns)ÁÁÁÁ
26ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, addressÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁtAA + tPxx244MAX + tPxx245MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ta(OUTV-DV) = 4tH – 9= 41ÁÁÁÁÁÁÁÁÁÁ
38.2ÁÁÁÁ
24ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, CASL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁtCAC + tPxx245MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ta(CASL-DV) = 3tH –12=25.5ÁÁÁÁÁÁÁÁÁÁ
21.1
ÁÁÁÁ
25ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, CASH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁtCPA + tPxx245MAX ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁta(OUTV-DV) = 4tH –9=41 ÁÁÁÁÁ
ÁÁÁÁÁ39.1
ÁÁÁÁ
27ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, RASL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁtRAC + tPROPPALMAX + tPxx245MAX ÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁta(OUTV-DV) = 8tH – 8 = 92ÁÁÁÁÁ
ÁÁÁÁÁ71.6
Timing Analysis
SPRA15628
Table 5. VRAM Timing Parameters – Setup and Hold Times(2 cycles / column; 40 MHz)
ÁÁÁÁÁÁÁÁÁ
NO.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULA(WITHOUT CAS BUFFERS)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VRAMSPECIFICATION
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁ
40 MHzRESULT
(ns)
ÁÁÁÁÁÁÁÁÁ
15ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Cycle time, randomÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 14tH – 5.5) –tPROPPALMAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRC = 110ÁÁÁÁÁÁÁÁÁÁÁÁ
162
ÁÁÁ14ÁÁÁÁÁÁÁÁÁCycle time, page mode ÁÁÁÁÁÁÁÁÁÁÁÁ(th(OUTV-OUTV) = 4tH – 6.5) ÁÁÁÁÁÁtPC = 35 ÁÁÁÁ43.5ÁÁÁÁÁÁÁÁÁ
2
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, RAS high
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(OUTV) = 6tH – 5.5) –tPROPPALMAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRP = 60
ÁÁÁÁÁÁÁÁÁÁÁÁ
67.5
ÁÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, RAS lowÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(OUTV) = 8tH – 5.5) –tPROPPALMAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRASP = 60ÁÁÁÁÁÁÁÁÁÁÁÁ
87
ÁÁÁÁÁÁ
5ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, CAS low ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(CASL) = 3tH –11) ÁÁÁÁÁÁÁÁÁÁÁÁ
tCAS = 15 ÁÁÁÁÁÁÁÁ
26.5
ÁÁÁÁÁÁ
6ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, CAS high ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(CASH) = tH –2) ÁÁÁÁÁÁÁÁÁÁÁÁ
tCPN = 10 ÁÁÁÁÁÁÁÁ
10.5
ÁÁÁÁÁÁ
32ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, W ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(OUTV) = 8tH –5.5) –tPHL244MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tWP = 10 ÁÁÁÁÁÁÁÁ
91.4
ÁÁÁÁÁÁ
11ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, address (column) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-CASL) = tH –4.5) – tPxx244MAXÁÁÁÁÁÁÁÁÁÁÁÁ
tASC = 0 ÁÁÁÁÁÁÁÁ
1.4ÁÁÁÁÁÁ
13ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, address (column) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(CASL-OUTV) = 3tH –11) + tPxx244MINÁÁÁÁÁÁÁÁÁÁÁÁ
tCAH = 10 ÁÁÁÁÁÁÁÁ
27.5
ÁÁÁÁÁÁÁÁÁ
8ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, address (row)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tsu(OUTV-OUTV) = 6tH –5.5) –tPxx244MAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tASR = 0ÁÁÁÁÁÁÁÁÁÁÁÁ
65.4
ÁÁÁÁÁÁ
9ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, address (row) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH –6.5) –tPROPPALMAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tRAH = 10 ÁÁÁÁÁÁÁÁ
37
ÁÁÁÁÁÁ
34ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, data to CASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-CASL) = tH –5) – tPxx245MAXÁÁÁÁÁÁÁÁÁÁÁÁ
tDSC = 0ÁÁÁÁÁÁÁÁ
0.9ÁÁÁÁÁÁ
35ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, data from CAS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(CASL-OUTV) = 3tH –11) + tPxx245MINÁÁÁÁÁÁÁÁÁÁÁÁ
tDH = 15 ÁÁÁÁÁÁÁÁ
27.5ÁÁÁÁÁÁ
31ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, W to CASH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 7tH –6.5) – tPHL244MAXÁÁÁÁÁÁÁÁÁÁÁÁ
tCWL = 15 ÁÁÁÁÁÁÁÁ
76.9
ÁÁÁÁÁÁÁÁÁ
33ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, W to RASHÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 7tH –5.5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRWL = 15ÁÁÁÁÁÁÁÁÁÁÁÁ
75.5
ÁÁÁÁÁÁ
21ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, W (row) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 5tH –5.5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁ
tWSR = 0 ÁÁÁÁÁÁÁÁ
52.9
ÁÁÁÁÁÁÁÁÁ
18ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, DSF to RASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = tH –5.5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tFSR = 0ÁÁÁÁÁÁÁÁÁÁÁÁ
2.9
ÁÁÁÁÁÁ
17ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, DSF from RASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 9tH – 5.5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tFHR = 30ÁÁÁÁÁÁÁÁ
100.5ÁÁÁÁÁÁÁÁÁ
17
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, DSF from RAS(bw)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH – 5.5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRFH = 10
ÁÁÁÁÁÁÁÁÁÁÁÁ
25.5
ÁÁÁÁÁÁÁÁÁ
19ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, TRG to RASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 5tH –5.5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tTHS = 0ÁÁÁÁÁÁÁÁÁÁÁÁ
52.9
ÁÁÁÁÁÁ
20ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, TRG from RAS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH –5.5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tTHH = 10 ÁÁÁÁÁÁÁÁ
25.5
ÁÁÁÁÁÁ
28ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, DSF to CASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH –6.5) – tPHL244MAXÁÁÁÁÁÁÁÁÁÁÁÁ
tFSC = 0ÁÁÁÁÁÁÁÁ
39.4ÁÁÁÁÁÁ
29ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, DSF from CASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH –5.5) + tPHL244MINÁÁÁÁÁÁÁÁÁÁÁÁ
tCFH = 10ÁÁÁÁÁÁÁÁ
45.5ÁÁÁÁÁÁÁÁÁ
30ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, W (row)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH –5.5) –tPROPPALMAX + tPHL244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tWHR = 10ÁÁÁÁÁÁÁÁÁÁÁÁ
25.5
Timing Analysis
29 TMS320C80 Frame Buffer
Table 5. VRAM Timing Parameters – Setup and Hold Times(2 cycles / column; 40 MHz) (Continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
40 MHzRESULT
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VRAMSPECIFICATION
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULA(WITHOUT CAS BUFFERS)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁ
NO.
ÁÁÁÁ
23ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, read from RAS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 17tH –5.5) – tPROPPALMAX +tPHL244MIN
ÁÁÁÁÁÁÁÁÁÁ
tRRH = 0 ÁÁÁÁÁÁÁÁÁÁ
200.5ÁÁÁÁ22ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁSetup time, read to CAS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(th(OUTV-CASL) = 10tH – 3.5) – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁtRCS = 0
ÁÁÁÁÁÁÁÁÁÁ117.4
Table 6. VRAM Timing Parameters – Delay Times (2 cycles/column at 40 MHz)
ÁÁÁÁÁÁ
NO.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULA(WITHOUT CAS BUFFERS)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VRAMSPECIFICATION
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
40 MHzRESULT
(ns)
ÁÁÁÁ
38ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RASL to CASH (refresh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 8tH – 6.5) – tPROPPALMAXÁÁÁÁÁÁÁÁÁÁ
tCHR = 10ÁÁÁÁÁÁÁÁÁÁ
86
ÁÁÁÁ
3ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CASH to RASL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 6tH –5.5) + tPROPPALMIN ÁÁÁÁÁÁÁÁÁÁ
tCRP = 0 ÁÁÁÁÁÁÁÁÁÁ
69.5
ÁÁ10ÁÁÁÁÁÁÁÁÁRASL to CASH ÁÁÁÁÁÁÁÁÁÁÁÁÁ(th(OUTV-OUTV) = 8tH –6.5) – tPROPPALMAXÁÁÁÁÁtCSH = 60ÁÁÁÁÁ86ÁÁÁÁ37ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁCASL to RASL (refresh)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(th(OUTV-OUTV) = 2tH –5.5) + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁtCSR = 10
ÁÁÁÁÁÁÁÁÁÁ19.5ÁÁ
ÁÁ12ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Column address to CASHÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH –6.5) – tPxx244MAXÁÁÁÁÁÁÁÁÁÁ
tCAL = 30ÁÁÁÁÁÁÁÁÁÁ
39.4ÁÁÁÁ
4ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RASL to CASLÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-CASL) = 5tH –3.5) – tPROPPALMAXÁÁÁÁÁÁÁÁÁÁ
tRCD = 20ÁÁÁÁÁÁÁÁÁÁ
51.5ÁÁÁÁ
36ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RASH to CASL (refresh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-CASL) = 4tH –3.5) – tPROPPALMAXÁÁÁÁÁÁÁÁÁÁ
tRPC = 0 ÁÁÁÁÁÁÁÁÁÁ
39
ÁÁÁÁ
7ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CASL to RASH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(CASL-OUTV) = 3tH –11) + tPROPPALMIN ÁÁÁÁÁÁÁÁÁÁ
tRSH = 17ÁÁÁÁÁÁÁÁÁÁ
26.5
Table 7. VRAM Timing Parameters – Access Times (3 cycles/column at 50 MHz)ÁÁÁÁÁÁ
NO.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETER
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULA
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
’C80 SPECIFICATION (ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
50 MHzRESULT
(ns)ÁÁÁÁ
26ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, addressÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tAA + tPxx244MAX + tPxx245MAXÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ta(OUTV-DV) = 6tH – 7 = 53ÁÁÁÁÁÁÁÁÁÁ
38.2ÁÁÁÁ
24ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, CASLÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCAC + tPxx245MAXÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ta(CASL-DV) = 4tH – 7 = 33ÁÁÁÁÁÁÁÁÁÁ
21.1ÁÁÁÁ
25ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, CASHÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCPA + tPxx245MAXÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ta(OUTV-DV) = 6tH –7 = 53 ÁÁÁÁÁÁÁÁÁÁ
39.1
ÁÁÁÁ
27ÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Access time, RASL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRAC + tPROPPALMAX + tPxx245MAXÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ta(OUTV-DV) = 10tH – 6.5 = 93.5ÁÁÁÁÁÁÁÁÁÁ
71.6
Table 8. VRAM Timing Parameters – Setup and Hold Times(3 cycles / column at 50 MHz)
ÁÁÁÁÁÁ
NO.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULAÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VRAMSPECIFICATION
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
50 MHzRESULT
(ns)ÁÁÁÁÁÁ
15ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, randomÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 18tH – 5) –tPROPPALMAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRC = 110ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
168.5
ÁÁÁÁ
14ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, page mode ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 6tH – 5.5) – tPxx244MAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁ
tPC = 35 ÁÁÁÁÁÁÁÁÁÁ
51.4
ÁÁÁÁÁÁ
2ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, RAS highÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(OUTV) = 8tH – 5) –tPROPPALMAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRP = 60ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
67.5
Timing Analysis
SPRA15630
Table 8. VRAM Timing Parameters – Setup and Hold Times(3 cycles / column at 50 MHz) (Continued)
ÁÁÁÁÁÁÁÁÁÁÁÁ
50 MHzRESULT
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VRAMSPECIFICATION
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULAÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁÁÁÁ
NO.
ÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RAS low ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(OUTV) = 10tH – 5) –tPROPPALMAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tRASP = 60 ÁÁÁÁÁÁÁÁ
87.5ÁÁÁÁÁÁÁÁÁ
5
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CAS low
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(CASL) = 4tH – 5.5) –tPxx244MAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCAS = 15
ÁÁÁÁÁÁÁÁÁÁÁÁ
31.4
ÁÁÁÁÁÁÁÁÁ
6ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CAS highÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(CASH) = 2tH –2) –tPxx244MAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCPN = 10ÁÁÁÁÁÁÁÁÁÁÁÁ
14.9
ÁÁÁÁÁÁ
32ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, W ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(OUTV) = 8tH –5) –tPHL244MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tWP = 10 ÁÁÁÁÁÁÁÁ
71.9
ÁÁÁÁÁÁÁÁÁ
11ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, address (column)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 2tH –5.5) –tPxx244MAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tASC = 0ÁÁÁÁÁÁÁÁÁÁÁÁ
11.4
ÁÁÁÁÁÁ
13ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, address (column) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4th –5.5) –tPxx244MAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tCAH = 10 ÁÁÁÁÁÁÁÁ
31.4ÁÁÁÁÁÁÁÁÁ
8
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, address (row)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tsu(OUTV-OUTV) = 8tH –5) –tPxx244MAX + tPROPPALMIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tASR = 0
ÁÁÁÁÁÁÁÁÁÁÁÁ
70.9
ÁÁÁÁÁÁÁÁÁ
9ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, address (row)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH –5.5) –tPROPPALMAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRAH = 10ÁÁÁÁÁÁÁÁÁÁÁÁ
36
ÁÁÁÁÁÁ
34ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, data to CAS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 2tH – 5.5) +tPxx244MIN – tPxx245MAX
ÁÁÁÁÁÁÁÁÁÁÁÁ
tDSC = 0 ÁÁÁÁÁÁÁÁ
11.4
ÁÁÁÁÁÁÁÁÁ
35ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, data from CASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH – 6.5) –tPxx244MAX + tPxx245MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tDH = 15ÁÁÁÁÁÁÁÁÁÁÁÁ
30.4
ÁÁÁÁÁÁ
31ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, W to CASH ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 7tH – 5.5) –tPHL244MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tCWL = 15 ÁÁÁÁÁÁÁÁ
61.4ÁÁÁÁÁÁÁÁÁ
33
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, W to RASH
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 7tH – 5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRWL = 15
ÁÁÁÁÁÁÁÁÁÁÁÁ
58.5
ÁÁÁÁÁÁÁÁÁ
21ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, W (row)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 7tH – 5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tWSR = 0ÁÁÁÁÁÁÁÁÁÁÁÁ
60.9
ÁÁÁÁÁÁ
18ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, DSF to RAS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH – 5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁ
tFSR = 0 ÁÁÁÁÁÁÁÁ
20.9
ÁÁÁÁÁÁÁÁÁ
17ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, DSF from RASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 9tH – 5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tFHR = 30ÁÁÁÁÁÁÁÁÁÁÁÁ
78.5
ÁÁÁÁÁÁ
17ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, DSF from RAS(bw)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH – 5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tRFR = 10 ÁÁÁÁÁÁÁÁ
18.5ÁÁÁÁÁÁÁÁÁ
19
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, TRG to RAS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 7tH – 5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tTHS = 0
ÁÁÁÁÁÁÁÁÁÁÁÁ
60.9
ÁÁÁÁÁÁÁÁÁ
20ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, TRG from RASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH – 5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tTHH = 10ÁÁÁÁÁÁÁÁÁÁÁÁ
18.5
ÁÁÁÁÁÁ
28ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, DSF to CAS ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH – 5.5) –tPHL244MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
tFSC = 0 ÁÁÁÁÁÁÁÁ
21.4
ÁÁÁÁÁÁÁÁÁ
29ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, DSF from CASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 5tH – 5) +tPHL244MIN – tPHL244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCFH = 10ÁÁÁÁÁÁÁÁÁÁÁÁ
41.9
Timing Analysis
31 TMS320C80 Frame Buffer
Table 8. VRAM Timing Parameters – Setup and Hold Times(3 cycles / column at 50 MHz) (Continued)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
50 MHzRESULT
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VRAMSPECIFICATION
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULAÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁ
NO.
ÁÁÁÁ
30tÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, W hold (row) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 3tH –5) –tPROPPALMAX + tPHL244MIN
ÁÁÁÁÁÁÁÁÁÁ
tWHR = 10ÁÁÁÁÁÁÁÁÁÁ
18.5ÁÁÁÁÁÁ
23
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, read from RAS
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 21tH –5) –tPROPPALMAX + tPHL244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRRH = 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
198.5
ÁÁÁÁÁÁ
22ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, read to CASÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 13tH – 5.5) –tPHL244MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRCS = 0ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
121.4
Table 9. VRAM Timing Parameters – Delay Times (3 cycles / column at 50 MHz)
ÁÁÁÁÁÁ
NO.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULAÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VRAMSPECIFICATION
(ns)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
50 MHzRESULT
(ns)
ÁÁÁÁ
38ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RASL to CASH (refresh)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 10tH – 5.5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁ
tCHR = 10ÁÁÁÁÁÁÁÁÁÁ
88ÁÁÁÁÁÁ
3
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CASH to RASL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 8tH –5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCRP = 0
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
70.9
ÁÁÁÁÁÁ
10ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RASL to CASHÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 10tH – 5.5) –tPROPPALMAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCSH = 60ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
88
ÁÁÁÁ
37ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CASL to RASL (refresh) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH –5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁ
tCSR = 10ÁÁÁÁÁÁÁÁÁÁ
30.9
ÁÁÁÁÁÁ
12ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Column address to CASHÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 6tH – 5.5) –tPxx244MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tCAL = 30ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
51.4
ÁÁÁÁ
4ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RASL to CASL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 6tH – 5.5) –tPROPPALMAX + tPHL244MIN
ÁÁÁÁÁÁÁÁÁÁ
tRCD = 20ÁÁÁÁÁÁÁÁÁÁ
48
ÁÁÁÁÁÁ
36ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RASH to CASL (refresh)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH – 5.5) –tPROPPALMAX + tPHL244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
tRPC = 0ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
28
ÁÁÁÁ
7ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
CASL to RASHÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 4tH – 5) +tPROPPALMIN – tPLH244MAX
ÁÁÁÁÁÁÁÁÁÁ
tRSH = 17ÁÁÁÁÁÁÁÁÁÁ
30.9
Timing Analysis
SPRA15632
Table 10. TVP3020 Interface Timing Parameters (50 MHz)
ÁÁÁÁÁÁÁÁÁ
NO.ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PARAMETERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FORMULAÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SPECIFICATIONÁÁÁÁÁÁÁÁÁÁÁÁ
50 MHzRESULT
(ns)ÁÁÁÁÁÁÁÁÁ
39ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Hold time, address from WÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 12tH –5) –tPxx244MAX + tPHL244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
10ÁÁÁÁÁÁÁÁÁÁÁÁ
111.9
ÁÁÁÁÁÁ
40ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, address to W ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 8tH –5.5) –tPHL244MAX + tPxx244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
10 ÁÁÁÁÁÁÁÁ
71.4
ÁÁÁÁÁÁ
41ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pulse duration, WÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(tw(OUTV) = 7tH) – tPROPPALMAXÁÁÁÁÁÁÁÁÁÁÁÁ
50ÁÁÁÁÁÁÁÁ
62.5ÁÁÁÁÁÁÁÁÁ
42ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, data to WÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(th(OUTV-OUTV) = 7tH –5) –tPxx245MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
10ÁÁÁÁÁÁÁÁÁÁÁÁ
60.9
ÁÁÁÁÁÁ
43ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Setup time, data to read ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(8th – (ten1 = 40) –tPxx245MAX + tPLH244MIN
ÁÁÁÁÁÁÁÁÁÁÁÁ
6.1 ÁÁÁÁÁÁÁÁ
36.9
Timing Analysis
33 TMS320C80 Frame Buffer
15
RAS
CAS
ADDRESS
DSF
TRG
W
DQ15–DQ0
1
2
4
3 56
7
13
14
8
911
12
23
27
25
18
19
21
17
10
24
22
26
20
Figure 14. VRAM Read Cycle (Page Mode)
Timing Analysis
SPRA15634
15
RAS
CAS
ADDRESS
DSF
TRG
W
DQ15–DQ0
1
2
4
3 56
7
13
14
8
911
18
19
21
17
10
ROW COLUMN COLUMN
33
3534
12
32
3130
2928
NOTE: Parameters apply to block-write and read SRTs also.
Figure 15. VRAM Write Cycle (Page Mode)
Timing Analysis
35 TMS320C80 Frame Buffer
RAS
CAS
W
DQ15–DQ0
36
37
38
21
30
Figure 16. VRAM Refresh Cycle
CLKOUT
A[31:0]
RL
READY
RAS
WR
D[63:56](reads)
RD
r1 r2 r3 r4 r5 r6 c1 c3c2 c4
D[63:56](writes)
42
4041
39
42
TVP3020 Addressed
Valid Data
Figure 17. TVP3020 Interface Timing
Pixel Port Timing
SPRA15636
9 Pixel Port TimingIn addition to the ’C80 interface timing, attention should be paid to thelatching of data from the VRAM serial outputs into the RAMDAC pixel port(P[63:0]).
The TVP3020 latches pixel data on the P[63:0] bus on the rising edge oflatch clock (LCLK). In this application, the LCLK input is tied directly to theRCLK output. An internal delay on the LCLK input guarantees properoperation. When the SYSBL signal goes high (beginning of active line), thefirst SCLK pulse is generated, which causes the VRAM serial outputs topush out the first group of data. On the next SCLK positive-going edge, thefirst group of data is latched into the RAMDAC, and the VRAM clocks out thesecond group. This action continues throughout the active line, andconsequently, the last SCLK pulse occurs after the SYSBL signal has gonelow to force the VRAM to output the final data group. Since this “pipeline”exists at both the beginning and end of a line, the net effect is not noticeableby the ’C80 or in the display.
A timing parameter of particular importance is the VRAM serial outputaccess time from the SCLK input, as this determines the maximum SCLKfrequency. The TMS55161s used in this application report specify ta(SQ) at15 ns, which limits the maximum SCLK frequency to 67 MHz. Generally, theSQ outputs of the VRAM are tied directly to the P port of the RAMDAC. Asthis path can be a very high-speed one, care should be taken to make it asshort as possible.
In some systems, the access time from SE also requires a strongconsideration. However, as this signal is generated from logic tied to the’C80 and not the SCLK input, it is not an issue in this design. Note that theswitch from one bank to another (SE toggle) is expected to be performedduring vertical blanking, presumably during a switching of frame buffers.Switching between the two VRAM banks in general should be avoidedduring display, as it can produce undesirable results.
PCB Layout Considerations
37 TMS320C80 Frame Buffer
10 PCB Layout ConsiderationsAs the TVP3020 is a mixed-signal (analog and digital) part, specialconsiderations must be made during the PCB layout stage. It isrecommended that at least four layers be provided for the TVP interface: onefor 5-V power, one for ground, and two signal layers. The layout should beoptimized for low noise on the power and ground planes by shielding digitalinputs and good decoupling. Additionally, the VRAM banks should be asclose as possible to the TVP pixel port.
10.1 Power Planes
Split power planes are recommended for the TVP3020. One of these planesis for the TVP’s analog circuitry, the other is for the digital interface. The splitin the two planes should be made underneath the TVP3020, as shown inFigure 18. Connection between the two planes is made with a Ferrite Bead(Fair-Rite 2743001111) — this bead should be located as close as possibleto where the power supply connects to the board.
The ground plane for both the analog and digital planes is the same. The useof separate ground planes is not recommended and should be activelydiscouraged.
10.2 Supply Decoupling
For optimal performance, a 0.1-µF and 0.01-µF capacitor pair should beused to decouple each of the groups of power terminals to ground. Thesecapacitors should be placed as close as possible to the device, as shownin Figure 18.
PCB Layout Considerations
SPRA15638
TVP3020144-Pin
QFP
C122
C113
C123
C114
C151
C120
C11
8
C12
8
C11
7
C12
6
C11
2
C11
1
C12
7
C11
5
C12
4
C11
9
R21
R22
R24
R20
R25
L1
R19
C121
C152
DigitalPower
AnalogPower
DB15 VideoConnector
C116
C125
6160
Figure 18. Component Placement for Split Power Plane
Clock Considerations
39 TMS320C80 Frame Buffer
11 Clock ConsiderationsThis section discusses several considerations regarding the frame timerand video clocks as they relate to the display that the system is meant tocontrol. In this application report, a 1024 × 768 frame buffer is implemented,using 16-bit pixels. The equations presented in the following sections canbe easily modified for other resolutions.
11.1 Screen Resolution
Screen resolution is a function of several factors, including the monitortiming, VRAM size and speed, and pixel size. The maximum possible screenresolution is determined by the pixel clock frequency necessary to displayit, whether or not the hardware supports it, and the size of the VRAM beingused. To determine if the resolution desired is supported by the VRAM, onemust first determine the pixel size. This is often a function of the palletteand/or RAMDAC that interfaces with the monitor. To determine the requiredframe memory size, multiply the pixel size times the number of pixels perscreen . For example, two megabytes of VRAM memory would support thefollowing screen resolutions:
• 1024 by 512 pixels at 32 bits/pixel
• 1024 by 1024 pixels at 16 bits/pixel
• 1280 by 1024 pixels at 8 bits/pixel
In this application report, four megabytes of VRAM are used, so many moreresolutions are possible. For the purposes of this example, a 1024 x 768display with 16-bit pixels is considered.
11.2 Monitor Specifications
The monitor in this example has the following specifications. Thisinformation can typically be found in the user’s guide supplied with themonitor.
Clock Considerations
SPRA15640
HBLNK
D
HSYNC
VBLNK
VSYNC
VIDEO
CE
B
A
I
VIDEO
HJ
G
F
Figure 19. Noninterlaced Monitor Timing (Separate SYNC)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 11. Monitor Timings (Typical) †
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
LINERATE
ÁÁÁÁÁÁÁÁÁÁÁÁ
48.5 kHz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁ
FRAMERATE
ÁÁÁÁÁÁÁÁÁÁÁÁ
60 Hz
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁA (µs) ÁÁÁÁ
ÁÁÁÁ20.625ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
LD – line duration ÁÁÁÁÁÁÁÁ
F (ms)ÁÁÁÁÁÁÁÁ
16.665ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FD – frame duration
ÁÁÁÁÁÁÁÁÁÁ
B (µs) ÁÁÁÁÁÁÁÁ
1.0 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
HS – horizontal sync ÁÁÁÁÁÁÁÁ
G (µs)ÁÁÁÁÁÁÁÁ
83 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VS – vertical sync
ÁÁÁÁÁÁÁÁÁÁ
C (µs) ÁÁÁÁÁÁÁÁ
2.875 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
HBP – horizontal back porch ÁÁÁÁÁÁÁÁ
H (µs)ÁÁÁÁÁÁÁÁ
660ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VBP – vertical back porch
ÁÁÁÁÁD (µs) ÁÁÁÁ16.0 ÁÁÁÁÁÁÁÁÁHAT – horizontal active time ÁÁÁÁI (µs) ÁÁÁÁ15.84ÁÁÁÁÁÁÁÁÁVAT – vertical active timeÁÁÁÁÁÁÁÁÁÁE (µs)
ÁÁÁÁÁÁÁÁ0.75
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁHFP – horizontal front porch
ÁÁÁÁÁÁÁÁJ (µs)
ÁÁÁÁÁÁÁÁ82
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁVFP – vertical front porch
† Resolution: 1024 pixels by 768 lines
11.3 Pixel Clock Selection
The timing specifications of the monitor limit the available pixel clockfrequencies. The pixel clock rate is influenced by the amount of horizontaland vertical blanking needed to conform to the monitor specifications. Usethe following horizontal timing information to determine the appropriateFCLK frequency:
horizontal active time (HAT) = LD – HS – HPB – HFP = 16.000 µs
Clock Considerations
41 TMS320C80 Frame Buffer
At 1024 pixels per line, this corresponds to 15.625 ns/pixel. This is knownas the dot clock rate, or the rate at which pixels must be output from theRAMDAC.
In this design, the VRAM frame buffers are 64 bits wide; therefore, four 16-bitpixels can be output on each SCLK cycle and, consequently, SCLK shouldbe dot clock/4. To support the required pixel rate, dot clock needs to be64 MHz (1/15.625 ns); therefore, SLCK is 16 MHz. The maximum FCLKfrequency is determined by the speed grade of the ’C80 that is used. Whilemany combinations of FCLK frequency and register setting provide asuitable result, a few guidelines ensure that an optimal solution is achieved.The first point is that it should be noted that the FCLK/SCLK ratio determinesthe overall granularity with which a display can be controlled. For example,if FCLK is set to SCLK/4, then the display can only be of certain widths equalto four times the number of pixels shifted out per SCLK cycle. The secondpoint is that the FCLK should not be greater than SCLK as this can causeundesirable effects with some RAMDACs (for example, SYSBL switching inthe middle of an SCLK cycle, rather than at the end). For this application, anFCLK frequency of 16 MHz was chosen. Previously, it was mentioned thatthe VCLK output of the TVP3020 is intended to be used to generate theSYSBL input. As this is provided from the ’C80 (CBLNK1 output), VCLKshould be connected to FCLK1; while SCLK goes to both the ’C80’s SCLK1input and the VRAM SCLK inputs.
Clock Considerations
SPRA15642
The TVP3020 drives both of the clock signals to the ’C80. Both signals arederived from the reference (dot) clock input of the TVP, which can be up to140 MHz. In this example, a 64-MHz TTL-type oscillator is used to drive theCLK0 input of the TVP3020, and serves as the dot clock directly. Thedivide-down ratios for SCLK and FCLK (VCLK) are programmed in theTVP’s output-clock-selection register (indirect address 0x1B). A completeset of register settings is provided in Table 12.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 12. TVP3020 Register Settings
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
TVP REGISTER ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VALUE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
MUX control register 1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0x45 (see Note 3)
ÁÁÁÁÁÁÁÁÁÁMUX control register 2 ÁÁÁÁÁÁÁÁÁÁ0x04 (see Note 3)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁInput clock selection register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0x00 (CLK0 input)ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁOutput clock selection registerÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0x52 (VCLK = SCLK = CLK0/4)ÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁGeneral control register
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0x48 (see Note 4)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Auxiliary control register ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0x08 (seld clock select)
NOTES: 3. Mux control registers 1 and 2 select the pixel format and multiplexingratios for the TVP3020. The above settings are valid for 16-bit truecolor pixels in the 5-6-5 format. For a complete set of registersettings, please refer to the TVP3020 Video Interface Palette DataManual (literature number SLAS080A)
4. This register setting selects the big-endian pixel format and enablesoverlay. While not required (or used in this design), the overlayfeature is useful for a variety of applications. The ’C80’s CAREAoutput is a general-purpose output that provides the overscan inputto the TVP. Please refer to the TVP3020 Video Interface Palette DataManual (literature number SLAS080A) for more information onoverscan.
Frame Timer Register Programming
43 TMS320C80 Frame Buffer
12 Frame Timer Register ProgrammingTable 13 summarizes frame timer regiser configurations for noninterlacedvideo. The horizontal timing registers are programmed in terms of anintegral number of FCLK cycles. VCOUNT increments only afterHCOUNT = HTOTAL for noninterlaced video. Therefore, with oneexception, all of the vertical timing registers are programmed in terms of anintegral number of horizontal lines. For purposes associated with compositeinterlaced video, the VESYNC register detects the end of vertical sync at halfthe value it is programmed to, and therefore represents twice the numberof horizontal lines in vertical sync. Since all of the timing registers beginat 0, their contents represent the number of appropriate events minus one,as described in Table 13.
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 13. Video Timing Registers (Noninterlaced)
ÁÁÁÁÁÁÁÁÁÁ
REGISTERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
IS PROGRAMMED TO ...
ÁÁÁÁÁÁÁÁÁÁ
HESYNC ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(number of FCLKS in horizontal sync) – 1
ÁÁÁÁÁÁÁÁÁÁ
HEBLNK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(number of FCLKS from start of horizontal sync to end of horizontal blanking) – 1
ÁÁÁÁÁHSBLNK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(number of FCLKS from start of horizontal sync to start of horizontal blanking) – 1ÁÁÁÁÁÁÁÁÁÁHTOTAL
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ(number of FCLKS in horizontal line) – 1ÁÁÁÁÁ
ÁÁÁÁÁHESERR†
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(number of FCLKS in horizontal serration) – 1ÁÁÁÁÁÁÁÁÁÁ
VESYNCÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(twice the number of lines in vertical sync) – 1ÁÁÁÁÁÁÁÁÁÁ
VEBLNK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(number of lines from start of vertical sync to end of vertical blanking) – 1
ÁÁÁÁÁÁÁÁÁÁ
VSBLNK ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(number of lines from start of vertical sync to start of vertical blanking) – 1
ÁÁÁÁÁÁÁÁÁÁ
VTOTAL ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
(number of lines in the frame) – 1† HESERR can be left unprogrammed for noncomposite video.
12.1 Procedure
Use the steps in Table 14 and refer to Figure 20 to configure the frame timerregisters for a 1024 × 768 display. Use the monitor timings described inTable 15. Remember that FCLK is 16 MHz (T = 62.5 ns).
Frame Timer Register Programming
SPRA15644
Table 14. Frame Timer Register Programming †
STEP CALCULATE FORMULA RESULT REGISTER VALUE
1 Number of FCLKs per lineLD
TFCLK330 HTOTAL = Result – 1 = 0x149
2 Number of FCLKs in horizontal syncHS
TFCLK16 HESYNC = Result – 1 = 0x000F
3 Number of FCLKs in horizontal back porch HBPTFCLK
46 N/A
4Number of FCLKs from start of horizontalsync to end of horizontal blank
Add results fromstep 2 and step 3
62 HEBLNK = Result – 1 = 0x003D
5 Number of FCLKs in horizontal front porch HFPTFCLK
12 N/A
6Number of FCLKs from start of horizontalsync to start of horizontal blank
Subtract theresult of step 5
from step 1318 HSBLNK = Result – 1 = 0x013D
7 Number of lines per frame FDLD
808 VTOTAL = Result – 1 = 0x0327
8 Number of lines in vertical sync VSLD
4 VESYNC = 2 × Result – 1 = 0x0007
9 Number of lines in vertical back porch VBPLD
32 N/A
10Number of lines from start of vertical syncto end of vertical blank
Add results fromstep 8 and step 9
36 VEBLNK = Result – 1 = 0x0023
11 Number of lines in vertical front porch VFPLD
4 N/A
12Number of lines from start of vertical syncto start of vertical blank
Subtract theresult of step 11
from step 7804 VSBLNK = Result – 1 = 0x0323
† All results rounded to the nearest whole number.
Frame Timer Register Programming
45 TMS320C80 Frame Buffer
Active Display
330
HSYNC
HBLNK
808 Lines
VB
LNK
VS
YN
C
unblanked display
blanked display
62
16
12
436
256
768
1024 Pixels
768 Lines
Figure 20. 1024 × 768 Display (Noninterlaced)
Table 15. Frame Timer Registers
ÁÁÁÁÁÁÁÁÁÁ
FT REGISTERÁÁÁÁÁÁÁÁ
VALUE
ÁÁÁÁÁÁÁÁÁÁ
HESYNC1 ÁÁÁÁÁÁÁÁ
0x000F
ÁÁÁÁÁHEBLNK1 ÁÁÁÁ0x003DÁÁÁÁÁÁÁÁÁÁHSBLNK1
ÁÁÁÁÁÁÁÁ0x013DÁÁÁÁÁ
ÁÁÁÁÁHTOTAL1
ÁÁÁÁÁÁÁÁ
0x0149ÁÁÁÁÁÁÁÁÁÁ
VESYNC1ÁÁÁÁÁÁÁÁ
0x0007ÁÁÁÁÁÁÁÁÁÁ
VEBLNK1 ÁÁÁÁÁÁÁÁ
0x0023
ÁÁÁÁÁÁÁÁÁÁ
VSBLNK1 ÁÁÁÁÁÁÁÁ
0x0323
ÁÁÁÁÁÁÁÁÁÁ
VTOTAL1 ÁÁÁÁÁÁÁÁ
0x0327
SRT Controller Registers
SPRA15646
13 SRT Controller RegistersProgramming the SRT controller registers requires information about theVRAMs that are used. To program these registers, calculate the memoryaddress of the first pixel displayed and the difference in the memoryaddresses between two vertically adjacent pixels; 1024 × 2 bytes = 2048 (inthis case). This should be placed in the LINEINC register. The address of thefirst pixel displayed is most often the base address of the VRAM, though the’C80 places no restrictions on this. This address should be programmed intoF0STADR, F1STADR, NEXTADR, and CRNTADR. NEXTADR andCRNTADR are automatically updated by the VC during display, but need tobe programmed during initialization.
The TMS55161 VRAMs have a row length of 512 bits with a SAM length of256 bits. The split SAM length is therefore 128 bits. The ’C80’s SRTcontroller is responsible for scheduling SRT events to the TC, which in turnperforms either full- or split-register transfers. These transfers move datafrom the VRAM memory array to the SAM inside the VRAM, which, is then,transferred out serially to the TVP3020 at the SCLK rate. To preventcorruption of the display, the register transfers must be scheduled andperformed such that the inactive half of the SAM is updated (see Figure 8).
In order to ensure that memory-to-register transfers occur at proper times,the SRT controller must know the size of the VRAM being used. Thisinformation is entered in two registers: FMEMCTL and SAMMASK. TheSAMMASK register is programmed with a number of contiguous 1’s (n),where 2n is the split SAM length. In this example, n is 7 since 27 = 128. Theplacement of these seven contiguous 1s in the SAMMASK register dependson what address pins are wired to the VRAM bank. In this application, eachVRAM bank is 64 bits wide, and therefore, the least significant logical bit ofaddress is A3 (this is the bit that toggles from one column address to anadjacent one). The least significant bit of the contiguous 1s in SAMMASKshould correspond to the least significant bit of the address bus wired to theVRAM. Therefore, SAMMASK1 should be programmed to 0x000003F8(that is, seven contiguous 1s, least significant 1 in bit 3).
SRT Controller Registers
47 TMS320C80 Frame Buffer
The FMEMCTL0 register controls how and when data is transferred to andfrom the VRAM. In this example, FMEMCTL1 is programmed to0x00004043. This enables clocking from frame timer 1 and sets the HSS(half SAM select) bit, since the SAM is half the length of a VRAM row. SRTevents (see Table 16) are scheduled at the start of the field and when theSAM overflows (end of field events are for capture only). Line events are notused in this application. For systems that require line events, they can beenabled through the FMEMCTLx register. In those systems, the HALINE orHBLINE register must also be programmed to schedule the line events,presumably during blanking to prevent corruption of the display (forexample, HALINE/HBLINE = HSBLNK + 1).
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Table 16. SRT Controller Register Values
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
SRT CONTROLLER REGISTERÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
VALUE
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
FMEMCTL1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0x00004043
ÁÁÁÁÁÁÁÁÁSAMMASK1 ÁÁÁÁÁÁÁÁÁÁÁÁ0x000003F8ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁLINEINC1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ0x00000800 (1024 2-byte pixels)ÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁCRNTADR1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0xA0000000 (base of VRAM)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
NEXTADR1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0xA0000000 (base of VRAM)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
F0STADR1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0xA0000000 (base of VRAM)
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
F1STADR1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0xA0000000 (base of VRAM)
A Note on Frame-Timer Interrupts
SPRA15648
14 A Note on Frame-Timer InterruptsAnother key feature of the ’C80’s on-chip frame timer mechanism is theability to interrupt the MP to maintain synchronization between theapplication code and the display. Frame-timer interrupts are controlled byway of a memory-mapped register in the VC, VFTINTx. VFTINT, like the restof the vertical timing registers, is programmed in terms of horizontal lines(halflines for interlaced modes).
Setting up a frame-timer interrupt involves three steps:• Programming VFTINTx• Setting up the interrupt vector• Enabling the interrupt
VFTINTx should be programmed to the line number after which you want theinterrupt to occur. For many applications, this corresponds to the last line ofactive display, as this identifies the point at which it is all right to begin writingover the entire frame buffer for the next frame. However, the ’C80 places norestrictions on the location of the interrupt. The interrupt is generated whenthe condition HCOUNT=HTOTAL (end of a line) on the line in whichVCOUNT = VFTINT.
The frame-timer-interrupt vectors are located at the following addresses, inthe MP’s parameter RAM:
Frame Timer 0 0x010101A0
Frame Timer 1 0x010101A4
The interrupt vector should be loaded with the address of the first instructionto be executed when the interrupt occurs.
The final step is to enable the interrupt by setting the appropriate bits in theMP’s INTEN register. As a good practice, you should clear the INTPENregister before doing this to avoid unwanted interrupts. The enable bits forthe frame-timer interrupts are bit 8 (frame timer 0) and bit 9 (frame timer 1).When an interrupt occurs, the correcponding bit in the MP’s INTPEN registeris set. The interrupt-service routine should clear this bit by writing a 1 to itin the INTPEN register before exiting.
Frame-timer interrupts are often used for double-buffering applications, iswhich a frame is being drawn in one part of the memory while the previousframe is being displayed. The frame-timer interrupt is used to reprogram theF0STADR0, F0STADR1, CRNTADR, and NEXTADR registers to display thenext frame. The ISR also tracks the current frame so that the applicationmaintains syncronization and does not write to the active frame. It should benoted that in this application, the VFTINT register should be programmedto a value between VSBLNK and VTOTAL, so that the writing of theaforementioned registers does not occur during the active display.
Bill of Materials
A-1 TMS320C80 Frame Buffer
Appendix A Bill of MaterialsÁÁÁÁÁÁÁÁ
QUANTITYÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
TYPEÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
DESIGNATORSÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
62
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0.1 µF
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
C111 C112 C113 C114 C115 C116 C117 C118 C119 C120 C121 C55 C56C57 C58 C59 C60 C61 C62 C63 C64 C65 C66 C67 C68 C69 C70 C71 C72C73 C74 C75 C76 C77 C78 C79 C80 C81 C82 C83 C84 C85 C86 C87 C88C89 C90 C91 C92 C93 C94 C95 C96 C97 C98 C99 C100 C101 C102 C103C104 C105
ÁÁÁÁÁÁÁÁ
8 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
0.01 µF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
C122 C123 C124 C125 C126 C127 C128 C151
ÁÁÁÁ3 ÁÁÁÁÁÁÁÁÁ4.7 µF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁC106 C107 C108ÁÁÁÁÁÁÁÁ6
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ10 kΩ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁR1 R2 R3 R4 R7 R18ÁÁÁÁ
ÁÁÁÁ1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
523 ΩÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
R19ÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Ferrite BeadÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
L1ÁÁÁÁÁÁÁÁ
5 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
75 Ω ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
R20 R21 R22 R23 R24
ÁÁÁÁÁÁÁÁ
4 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
22 Ω ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
RP5 RP6 RP7 RP8
ÁÁÁÁÁÁÁÁ
2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
22 µF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
C109 C110
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
33 µF ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
C152
ÁÁÁÁÁÁÁÁ
2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
74LVT16244 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
U47 U48
ÁÁÁÁ4 ÁÁÁÁÁÁÁÁÁ74LVT16245 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁU26 U27 U28 U34ÁÁÁÁÁÁÁÁ1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ74LVT16373
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁU45ÁÁÁÁ
ÁÁÁÁ1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
14-pin headerÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
U14ÁÁÁÁÁÁÁÁ
1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
HD15 connector (female)ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
U46ÁÁÁÁÁÁÁÁ
2 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Crystal oscillators ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
U2 U12
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Crystal oscillator (3.3 V) ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
U1
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
Pushbutton switch ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
S1
ÁÁÁÁÁÁÁÁ
1 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
TL7705A ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
U49
ÁÁÁÁ8 ÁÁÁÁÁÁÁÁÁTMS55161-60 ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁU15 U16 U18 U19 U20 U22 U24 U25ÁÁÁÁÁÁÁÁ1
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁTMS320C80GF-50
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁU13ÁÁÁÁ
ÁÁÁÁ1ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
TVP3020ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
J1ÁÁÁÁÁÁÁÁ
4ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
PAL22LV10ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
U35 U36 U37 U43
SPRA156A-2
Schem
atics
B-1
TM
S320C
80 Fram
e Buffer
Appendix B SchematicsTMS320C80c80.sch
Data Bus Tranceiverstrans.sch
VRAM Bank 0vram0.sch
VRAM Bank 1vram1.sch
Address Buffersbuffers.sch
Glue Logiclogic.sch
TVP3020tvp3020.sch
TVP3020 Powertvppwr.sch
Decoupling Capacitorscaps.sch
TMS320C80 Powerc80pwr.sch
Figure B–1. Schematics
Schem
atics
B-2
SP
RA
156
AC
33
AM
8
C25
B26
A31
E19RLA21RASB22TRG / CASC23WA23DSF
CAS7/DQM7
W35
D63
T32
D62
U33
D61
AB
34D
60W
33D
59A
E35
D58
AG
35D
57Y
34D
56A
B32
D55
AH
34D
54A
L35
D53
D52
AE
33D
51A
M34
D50
AF
34D
49A
L33
D48
AP
32D
47A
F32
D46
AN
31D
45A
H32
D44
AR
31D
43A
J33
D42
AP
28D
41A
R27
D40
AP
26D
39A
L29
D38
AN
25D
37A
R23
D36
AN
29D
35A
P22
D34
AM
28D
33A
L27
D32
DBEN
DDINE25
CLKOUT
D31
D30
D29
D28
D27
D26
D25
D24
D23
D22
D21
D20
D19
D18
D17
D16
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
AM
26A
R21
AL2
5A
N23
AK
22A
P20
AM
22A
L21
AM
20A
N19
AL1
9A
L17
AM
16A
N17
AP
16A
L15
AR
15A
M14
AP
14A
N13
AR
13A
L11
AN
11A
P10
AR
9A
M10
AP
8A
L9A
L7
AN
7A
R5
AS2C7
AS1E1
AS0D8
BS1B4
BS0E11
CT2 (VCC5)F18
CT1A5
CT0C11
PS3 (VCC5)U5
PS2C13
PS1B8
PS0F14
UTIMED10
READYE9
RETRYD2
FAULTE3
HSYNC0E33
VSYNC0D34
CSYNC0 / HBLNK0B32
CBLNK0 / VBLNK0C31
CAREA0C29
PCLK0B28
SCLK0D28
HSYNC1K34
VSYNC1K32
CSYNC1 / HBLNK1H32
CBLNK1 / VBLNK1G33
CAREA1D26
FCLK1D22
SCLK1A27
LINT4E27
EINT3E29
EINT2G31
EINT1A31
RESETD14
CLKINC17
HREQE15
HACKA9
REQ1B10
REQ0D16
FF1 (VCC5)U31
FF2 (VCC5)K18
TMSN33
TCKE35
TDIH34
TDOP32
EMU1J35
EMU0T34
TRSTL33
VCC3
1113714132
TMSTCKTDI
TDOEMU1EMU0TRST
9TCKRET
5
468
1012
PD
GNDGNDGNDGNDGND
VCC3
U14
Emulator Header
U1
12 – 100 MHzOscillator (3.3 V)
8OUT
1NC
OSC14
CLKIN
!RESET
R610 k
VCC3
R710 k
D [32:63]
AS [0:2]
BS [0:1]
CT [0:2]
PS [0:3]
D [0:31]
C80A[0:31]
STAT [0:5]
!RL
!RAS
!TRG
!CAS [0:7]
!DBEN
!DDIN
U13A
AJ3 C80A31
A30 AH4 C80A30
A29 AN5 C80A29
A28 AF4 C80A28
A27 AP4 C80A27
A26 AE3 C80A26
A25 AL3 C80A25
A24 AM2 C80A24
A23 AL1 C80A23
A22 AC3 C80A22
A21 AB4 C80A21
A20 AH2 C80A20
A19 Y4 C80A19
A18 W3 C80A18
A17 AF2 C80A17
A16 AG1 C80A16
A15 AE1 C80A15
A14 AB2 C80A14
A13 T4 C80A13
A12 Y2 C80A12
A11 W1 C80A11
A10 U3 C80A10
A9 P4 C80A9
A8 N3 C80A8
A7 L3 C80A7
A6 K4 C80A6
A5 T2 C80A5
A4 P2 C80A4
A3 H4 C80A3
A2 G3 C80A2
A1 G5 C80A1
A0 L1 C80A0
STATUS5 E21 STAT5
STATUS4 K2 STAT4
STATUS3 C5 STAT3
STATUS2 E7 STAT2
STATUS1 J1 STAT1
STATUS0 H2 STAT0
A13 !CAS7
CAS6/DQM6 B14 !CAS6
CAS5/DQM5 A15 !CAS5
CAS4/DQM4 E17 !CAS4
CAS3/DQM3 B16 !CAS3
CAS2/DQM2 C19 !CAS2
CAS1/DQM1 B20 !CAS1
CAS0/DQM0 D20 !CAS0
!CAS[0:7]
CLKOUT
!W
READY
!UTIME
!HSYNC1!VSYNC1!CSYNC1!CBLNK1CAREA1FCLK1SCLK1
DSF
R310 k
R410 k
Device configured for big endian operation,and powers up running. Assumes boot codeloaded at upper memory.
Figure B–2. TMS320C80-GF
B-3 TMS320C80 Frame Buffer
VSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCCVSS VCC
A11A19A25C3C9
C27D6
D12D18D24D30
E5E13E23E31
F4F10F16F22F26F32
J3J33L5
L31M4
M32N5
N31R1
R35V4
V32
V2V34AA3AA5AA31AC1AC35AD2AD34AG5AG31AJ1AJ35AK2AK8AK12AK16AK24AK28AK34AM4AM32AN15AN21AN33AP6AP12AP18AP24AP30AR7AR19AR29
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
SV
SS
VS
S
W5
A7
W31
A17
AA
1A
29A
A35
B6
AC
5B
12A
C31
B18
AD
4B
24A
D32
B30
AE
5C
15A
E31
C21
AG
33D
4A
J5D
32A
J31
F2
AK
4F
8A
K10
F12
AK
14F
20A
K20
F24
AK
26F
28A
K32
F34
AL5
G1
AL1
3G
35A
L23
J5A
L31
J31
AM
6M
2A
M12
M34
AM
18N
1A
M24
N35
AM
30R
3A
N9
R5
AN
27R
31A
R11
R33
AR
17U
1A
R25
U35 U13B
VCC3
TMS320C80-GF POWERV
VSS VCCAG3 AA33
Figure B–3. TMS320C80 Power and Ground Connections
Schematics
Schem
atics
B-4
SP
RA
156
1314161719202223
C80A12C80A13C80A14C80A15C80A16C80A17C80A18C80A19
C80A[0..31]U47
30
1244825
4140
3738
4443
4647
1OE3OE2OE4OE
C80A20C80A2C80A1C80A0
3635
3233
3A13A23A33A44A14A24A34A4
292726
74LVT16244
3
7
2
U49TL7705A
CT
SEN
RESIN
REF
RST
RSET
1
6
5
C1040.1 F
C1050.1 F
VCC3
VCC5
S1SW SPST
R710 k
R1810k
!RST
Pushbutton Is Optional
1Y11Y21Y31Y42Y12Y22Y32Y4
2356891112
12345678
3Y13Y23Y33Y44Y14Y24Y34Y4
1A11A21A31A42A12A22A32A4
12345678
161514131211109
BC80A12BC80A13BC80A14BC80A15BC80A16BC80A17BC80A18BC80A19
161514131211109
BC80A20BC80A2BC80A1BC80A0
BC80A[12..20]22 RP5
22 RP6 C80A[0..2]
!RESET
1314161719202223
!CAS7!CAS6!CAS5!CAS4!CAS3!CAS2!CAS1!CAS0
CAS[0..7] U48
1244825
4140
3738
4443
4647
1OE3OE2OE4OE
3A13A23A33A44A14A24A34A4
74LVT16244
1Y11Y21Y31Y42Y12Y22Y32Y4
2356891112
12345678
3Y13Y23Y33Y44Y14Y24Y34Y4
1A11A21A31A42A12A22A32A4
12345678
161514131211109
!BCAS0!BCAS1!BCAS2!BCAS3!BCAS4!BCAS5!BCAS6!BCAS7
161514131211109
!BCAS[0..7]22 RP8
22 RP7
!BTRG!BWBDSF
FCLK1
SCLK1
!TRG!WDSF
5VFCLK1
5VSCLK1
3635333230292726
Figure B–4. Address Buffers
Schem
atics
B-5
TM
S320C
80 Fram
e Buffer
D0D1D2D3D4D5D6D7
D[0..63]
U26
1244825
4140
3738
4443
4647
1DIR2DIR1G2G
74LVT16245
1B11B21B31B41B51B61B71B8
2356891112
1A11A21A31A41A51A61A71A8
BD63BD62BD61BD60BD59BD58BD57BD56
BD[0..63]
D8D9D10D11D12D13D14D15
3029
2627
3332
3536 2B1
2B22B32B42B52B62B72B8
1314161719202223
2A12A22A32A42A52A62A72A8
BD55BD54BD53BD52BD51BD50BD49BD48
D16D17D18D19D20D21D22D23
U34
1244825
4140
3738
4443
4647
74LVT16245
1B11B21B31B41B51B61B71B8
2356891112
1A11A21A31A41A51A61A71A8
BD47BD46BD45BD44BD43BD42BD41BD40
D24D25D26D27D28D29D30D31
BD39BD38BD37BD36BD35BD34BD33BD32
D32D33D34D35D36D37D38D39
U27
1244825
4140
3738
4443
4647
74LVT16245
1B11B21B31B41B51B61B71B8
2356891112
1A11A21A31A41A51A61A71A8
BD31BD30BD29BD28BD27BD26BD25BD24
BD23BD22BD21BD20BD19BD18BD17BD16
D48D49D50D51D52D53D54D55
U28
1244825
4140
3738
4443
4647
74LVT16245
1B11B21B31B41B51B61B71B8
2356891112
1A11A21A31A41A51A61A71A8
BD15BD14BD13BD12BD11BD10
BD9BD8
D56D57D58D59D60D61D62D63
BD7BD6BD5BD4BD3BD2BD1BD0
!DDIN
!DBEN
1DIR2DIR1G2G
D40D41D42D43D44D45D46D47
3029
2627
3332
3536 2B1
2B22B32B42B52B62B72B8
1314161719202223
2A12A22A32A42A52A62A72A8
1DIR2DIR1G2G
3029
2627
3332
3536 2B1
2B22B32B42B52B62B72B8
1314161719202223
2A12A22A32A42A52A62A72A8
1DIR2DIR1G2G
3029
2627
3332
3536 2B1
2B22B32B42B52B62B72B8
1314161719202223
2A12A22A32A42A52A62A72A8
Figure B–5. Data Transceivers (Big-Endian Configuration)
Schem
atics
B-6
SP
RA
156
BC80A20
BC80A [12..20]
BC80A19
BC80A18
BC80A17
BC80A16
27
28
29
30
31
BC80A15
BC80A14
BC80A13
BC80A12
34
35
36
37
BC80A (12..20)
U15
A8
A7
A6
A5
A4
A3
A2
A1
A0
!BCAS1 39
!BCAS0
!BTRC
!BW
24
2
25
CASU
CASL
TRG
WE
!URAS0 26 RAS
BDSF 41
38
DSF
QSF
!VSE0 63
64SE
SC
BD15
BD14
BD13
BD12
BD11
60
58
55
53
50
BD10
BD9
BD8
BD7
48
45
43
22
BD620
BD517
BD415
BD312
BD210
BD17
BD05
SD0
SD1
SD2
SD3
SD4
4
6
9
11
14
SD5
SD6
SD7
SD8
16
19
21
44
SD946
SD1049
SD1151
SD1254
SD1356
SD1459
SD1561
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
SQ0
SQ1
SQ2
SQ3
SQ4
SQ5
SQ6
SQ7
SQ8
SQ9
SQ10
SQ11
SQ12
SQ13
SQ14
SQ15
!VRAS0
BC80A20
BC80A19
BC80A18
BC80A17
BC80A16
27
28
29
30
31
BC80A15
BC80A14
BC80A13
BC80A12
34
35
36
37
U16
A8
A7
A6
A5
A4
A3
A2
A1
A0
39
24
2
25
CASU
CASL
TRG
WE
26 RAS
BDSF 41
38
DSF
QSF
63
64
BD31
BD30
BD29
BD28
BD27
60
58
55
53
50
BD26
BD25
BD24
BD23
48
45
43
22
BD2220
BD2117
BD2015
BD1912
BD1810
BD177
BD165
SD16
SD17
SD18
SD19
SD20
4
6
9
11
14
SD21
SD22
SD23
SD24
16
19
21
44
SD2546
SD2649
SD2751
SD2854
SD2956
SD3059
SD3161
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
SQ0
SQ1
SQ2
SQ3
SQ4
SQ5
SQ6
SQ7
SQ8
SQ9
SQ10
SQ11
SQ12
SQ13
SQ14
SQ15
BC80A20
BC80A19
BC80A18
BC80A17
BC80A16
27
28
29
30
31
BC80A15
BC80A14
BC80A13
BC80A12
34
35
36
37
U18
A8
A7
A6
A5
A4
A3
A2
A1
A0
39
24
2
25
CASU
CASL
TRG
WE
26 RAS
BDSF 41
38
DSF
QSF
63
64
BD47
BD46
BD45
BD44
BD43
60
58
55
53
50
BD42
BD41
BD40
BD39
48
45
43
22
BD3820
BD3717
BD3615
BD3512
BD3410
BD337
BD325
SD32
SD33
SD34
SD35
SD36
4
6
9
11
14
SD37
SD38
SD39
SD40
16
19
21
44
SD4146
SD4249
SD4351
SD4454
SD4556
SD4659
SD4761
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
SQ0
SQ1
SQ2
SQ3
SQ4
SQ5
SQ6
SQ7
SQ8
SQ9
SQ10
SQ11
SQ12
SQ13
SQ14
SQ15
BC80A20
BC80A19
BC80A18
BC80A17
BC80A16
27
28
29
30
31
BC80A15
BC80A14
BC80A13
BC80A12
34
35
36
37
U19
A8
A7
A6
A5
A4
A3
A2
A1
A0
39
24
2
25
CASU
CASL
TRG
WE
26 RAS
BDSF 41
38
DSF
QSF
63
64
BD63
BD62
BD61
BD60
BD59
60
58
55
53
50
BD58
BD57
BD56
BD55
48
45
43
22
BD5420
BD5317
BD5215
BD5112
BD5010
BD497
BD485
SD40
SD49
SD50
SD51
SD52
4
6
9
11
14
SD53
SD54
SD55
SD56
16
19
21
44
SD5746
SD5849
SD5951
SD6054
SD6156
SD6259
SD6361
DQ15
DQ14
DQ13
DQ12
DQ11
DQ10
DQ9
DQ8
DQ7
DQ6
DQ5
DQ4
DQ3
DQ2
DQ1
DQ0
SQ0
SQ1
SQ2
SQ3
SQ4
SQ5
SQ6
SQ7
SQ8
SQ9
SQ10
SQ11
SQ12
SQ13
SQ14
SQ15
!BCAS3
!BCAS2
!BTRC
!BW
!URAS0
!VSE0
!BCAS5
!BCAS4
!BTRC
!BW
!URAS0
!VSE0
!BCAS7
!BCAS6
!BTRC
!BW
!URAS0
!VSE0
BD[0..63]
!BCAS[0..7]
SD[0..63]SD[0..63]
BDSF
!VSE0
5VSCLK1
!BTRG
!BW
!VRAS0
!BCAS[0..7]
BDSF
!VSE0
5VSCLK1
!BTRG
!BW
TMS55161TMS55161TMS55161TMS55161
BD(0..63]
SE
SCSE
SC
SE
SC
Figure B–6. VRAM Bank 0
Schematics
B-7TMS320C80 Frame Buffer
BC
80A
[12.
.20]
BC
80A
20
BC
80A
19
BC
80A
18
BC
80A
17
BC
80A
16
27 28 29 30 31
BC
80A
15
BC
80A
14
BC
80A
13
BC
80A
12
34 35 36 37
U25
A8
A7
A6
A5
A4
A3
A2
A1
A0
!BC
AS
139
!BC
AS
0
!BT
RG
!BW
24
2
25
CA
SU
CA
SL
TR
G
WE
!VR
AS
126
RA
S
BD
SF
41 38D
SF
QS
F
!VS
E1
63 64S
E
SC
BD
15
BD
14
BD
13
BD
12
BD
11
60 58 55 53 50
BD
10
BD
9
BD
8
BD
7
48 45 43 22
BD
620
BD
517
BD
415
BD
312
BD
210
BD
17
BD
05
SD
0
SD
1
SD
2
SD
3
SD
4
4691114
SD
5
SD
6
SD
7
SD
8
16192144
SD
946
SD
1049
SD
1151
SD
1254
SD
1356
SD
1459
SD
1561
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
SQ
0
SQ
1
SQ
2
SQ
3
SQ
4
SQ
5
SQ
6
SQ
7
SQ
8
SQ
9
SQ
10
SQ
11
SQ
12
SQ
13
SQ
14
SQ
15
!VR
AS
1
BC
80A
20
BC
80A
19
BC
80A
18
BC
80A
17
BC
80A
16
27 28 29 30 31
BC
80A
15
BC
80A
14
BC
80A
13
BC
80A
12
34 35 36 37
U24
A8
A7
A6
A5
A4
A3
A2
A1
A0
39 24
2
25
CA
SU
CA
SL
TR
G
WE
26R
AS
BD
SF
41 38D
SF
QS
F
63 64
BD
31
BD
30
BD
29
BD
28
BD
27
60 58 55 53 50
BD
26
BD
25
BD
24
BD
23
48 45 43 22
BD
2220
BD
2117
BD
2015
BD
1912
BD
1810
BD
177
BD
165
SD
16
SD
17
SD
18
SD
19
SD
20
4691114
SD
21
SD
22
SD
23
SD
24
16192144
SD
2546
SD
2649
SD
2751
SD
2854
SD
2956
SD
3059
SD
3161
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
SQ
0
SQ
1
SQ
2
SQ
3
SQ
4
SQ
5
SQ
6
SQ
7
SQ
8
SQ
9
SQ
10
SQ
11
SQ
12
SQ
13
SQ
14
SQ
15
BC
80A
20
BC
80A
19
BC
80A
18
BC
80A
17
BC
80A
16
27 28 29 30 31
BC
80A
15
BC
80A
14
BC
80A
13
BC
80A
12
34 35 36 37
U22
A8
A7
A6
A5
A4
A3
A2
A1
A0
39 24
2
25
CA
SU
CA
SL
TR
G
WE
26R
AS
BD
SF
41 38D
SF
QS
F
63 64
BD
47
BD
46
BD
45
BD
44
BD
43
60 58 55 53 50
BD
42
BD
41
BD
40
BD
39
48 45 43 22
BD
3820
BD
3717
BD
3615
BD
3512
BD
3410
BD
337
BD
325
SD
32
SD
33
SD
34
SD
35
SD
36
4691114
SD
37
SD
38
SD
39
SD
40
16192144
SD
4146
SD
4249
SD
4351
SD
4454
SD
4556
SD
4659
SD
4761
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
SQ
0
SQ
1
SQ
2
SQ
3
SQ
4
SQ
5
SQ
6
SQ
7
SQ
8
SQ
9
SQ
10
SQ
11
SQ
12
SQ
13
SQ
14
SQ
15
BC
80A
20
BC
80A
19
BC
80A
18
BC
80A
17
BC
80A
16
27 28 29 30 31
BC
80A
15
BC
80A
14
BC
80A
13
BC
80A
12
34 35 36 37
U20
A8
A7
A6
A5
A4
A3
A2
A1
A0
39 24
2
25
CA
SU
CA
SL
TR
G
WE
26R
AS
BD
SF
41 38D
SF
QS
F
63 64
BD
63
BD
62
BD
61
BD
60
BD
59
60 58 55 53 50
BD
58
BD
57
BD
56
BD
55
48 45 43 22
BD
5420
BD
5317
BD
5215
BD
5112
BD
5010
BD
497
BD
485
SD
40
SD
49
SD
50
SD
51
SD
52
4691114
SD
53
SD
54
SD
55
SD
56
16192144
SD
5746
SD
5849
SD
5951
SD
6054
SD
6156
SD
6259
SD
6361
DQ
15
DQ
14
DQ
13
DQ
12
DQ
11
DQ
10
DQ
9
DQ
8
DQ
7
DQ
6
DQ
5
DQ
4
DQ
3
DQ
2
DQ
1
DQ
0
SQ
0
SQ
1
SQ
2
SQ
3
SQ
4
SQ
5
SQ
6
SQ
7
SQ
8
SQ
9
SQ
10
SQ
11
SQ
12
SQ
13
SQ
14
SQ
15
!BC
AS
3
!BC
AS
2
!BT
RG
!BW
!VR
AS
1
!VS
E1
!BC
AS
5
!BC
AS
4
!BT
RG
!BW
!VR
AS
1
!VS
E1
!BC
AS
7
!BC
AS
6
!BT
RG
!BW
!VR
AS
1
!VS
E1
BD
[0..6
3]
!BC
AS
[0..7
]
SD
[0..6
3]
BD
SF
!VS
E1
5VS
CLK
1
!BT
RG
!BW
TM
S55
161
TM
S55
161
TM
S55
161
TM
S55
161
SE
SC
SE
SC
SE
SC
Fig
ure
B–7
.V
RA
M B
ank1
Schem
atics
B-8
SP
RA
156
VGA7VGA6VGA5VGA4
VGA3VGA2VGA1VGA0
85848382
81807978
D7D6D5D4
D3D2D1D0
41424344
45464748
RS2RS1RS0RD
WR
51504938
37
SYSHSSYSVSSYSBLVGAHS
VGAVSVGABL
89909192
9394
LCLKCLK0CLK1CLK2
CLK2
109969798
99
SD
31
SD
30
SD
29
SD
28
SD
27
SD
26
SD
25
SD
24
SD
23
SD
22
SD
21
SD
19
SD
18
SD
17
SD
16
SD
15
SD
14
SD
13
SD
12
SD
11
SD
10
SD
9
SD
8
SD
7
SD
6
SD
5
SD
4
SD
3
SD
2
SD
1
SD
0
SFLAG95
OVSPSEL8 / 6
868788
RESETFSADJ
5770
3 4 5 6 7 8 9 10 11 12 13 14 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
SD
20
P31
P30
P29
P28
P27
P26
P25
P24
P23
P22
P21
P20
P19
P18
P17
P16
P15
P14
P13
P12
P11
P10
P9
P8
P7
P6
P5
P4
P3
P2
P1
P0
P63
P62
P61
P60
P59
P58
P57
P56
P55
P54
P53
P52
P51
P50
P49
P48
P47
P46
P45
P44
P43
P42
P41
P40
P39
P38
P37
P36
P35
P34
P33
P32
SD
63
SD
62
SD
61
SD
60
SD
59
SD
58
SD
57
SD
56
SD
55
SD
54
SD
53
SD
51
SD
50
SD
49
SD
48
SD
47
SD
46
SD
45
SD
44
SD
43
SD
42
SD
41
SD
40
SD
39
SD
38
SD
37
SD
36
SD
35
SD
34
SD
33
SD
32
100
101
102
103
104
105
106
113
114
115
116
117
118
119
120
121
124
125
126
127
135
136
137
138
139
140
141
142
143
144
1 2
SD
52
BD0BD1BD2BD3
BD4BD5BD6BD7
BC80A2BC80A1BC80A0
!DACRD!DACWR
!HSYNC1!VSYNC1!CBLNK1
BD80A[0..2]
VCC5
CAREA1
!RESET
BD[0..63]
OUTOUT
NC
OSC14
1
U2
OUT
NC
OSC14
1
U12
8
8
DOT0
DOT1
STANDARD TTL–type oscillators
Use 1% resistor R19523
RCLK
SD[0..63]
I/O4I/O3I/O2I/O1
I/O0
RCLKVCLKSCLK
IORIOGIOB
56555453
52
110111112
646668
HSYNCOUTVSYNCOUT
6162
REFCOMP
7271
SENSE58
NCNC
77130
6172
8394
105
11
12
13
14
15
!HS
!VS
R2075
R2175
R2275
R2375
R2475
AVDD
5VSCLK1
5VFCLK1
Use 1% resistors
U46 HD15
RED
GRN
BLURCLK
C1110.1 F
J1A
TVP3020
SD[0..63]
Note data line swap to compensate for data lineswap at buffer outputs
C1120.1 F
Figure B–8. TVP3020 Pallette
Schem
atics
B-9
TM
S320C
80 Fram
e Buffer
VCC5
C1210.1F
C1200.1 F
C1190.1 F
C1180.1 F
C1170.1 F
C1160.1 F
C1150.1 F
Note - For actual layout, please refer to AP Note text.
L1
Ferrite Bead
757369676563604010812212813113315
C151C128C127C126C125C124
DVDDDVDDDVDDDVDDDVDDDVDDDVDDDVDD GND
GNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGNDGND
C113.01F
C114.01F
C122.01F
C123.01F
C15233F
AVDDAVDD
391075916
123129132134
7476
TVP3020 J1B
0.01 F0.01 F0.01 F0.01 F0.01 F0.01 F
Figure B–9. TVP3020 Power and Ground Connections
SPRA156B-10
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
ÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁÁ
!RAS
!CAS7
LC80A[16..17]
LC80A21
LC80A[28..31]
LSTAT[0..5]
CLKOUT
READY
!DACRD!DACWR
!VSE1!VSE0
!VRAS0!VRAS1
LC80A16LC80A17
LSTAT5
LSTAT3LSTAT4
LSTAT0LSTAT1LSTAT2
LC80A31LC80A30LC80A29LC80A28
2345679
1011121316
I/CLKII
II
IIII
I
II
I/OI/O
I/OI/O
I/OI/OI/OI/O
I/OI/O
27262524232120191817
U37
PAL22LV10PLCC
VRAMCTL.ABL
I I/O209LSTAT0
PAL22LV10PLCC
13LC80A28!CAS7 16 I
I
LC80A30LC80A29
LC80A31
1112 I
I
10 I
I/OI/OI/O
1817
19
I/CLK
I
LSTAT2LSTAT1
LSTAT3
I67 I
5 I
LSTAT4LSTAT5CLKOUT
43 I
U432
I/O
I/OI/O
I/O2321
24
I/OI/O
252627
DACCTL.ABL
!RL
!RESET
C80A[0..31]
STAT[0..5]
2548241
1OE
1LE2OE
2LE
2D8
2D62D7
2D5
26272930
C80A16C80A17
LC80A[16..17]
LC80A[28..31]
LC80A16LC80A17LC80A28LC80A29LC80A30LC80A31
232220191716
LSTAT[0..5]
LC80A21LSTAT4LSTAT5
U45
3LSTAT3LSTAT2
56
1Q11Q21Q31Q41Q51Q61Q71Q8
LSTAT1LSTAT0
89
LC80A211112
1D246
1D31D4
4443
STAT4
STAT2STAT3
1D51D6
4140
1D73837
STAT0STAT1
C80A21
1D1STAT5 47 2
1314
2D13635
2D333
2D2C80A30C80A31
C80A29C80A28 32
2D4
74LVT16373
1D8
AS[0..2]
!UTIME
C80CODES2.ABL
BS[0..1]
27
AS22625
I/OI/O
AS124
BS12123 AS0
I/O
I/OI/O
I/O
2U35
I34
STAT5STAT4STAT3
I5
I76
I
STAT2
STAT0STAT1
I
I/CLK
19
1718
I/OI/OI/O
I10
II
1211
C80A30
C80A28C80A29
II
16C80A16C80A17 13
PAL22LV10PLCC
C80A31 9 20I/OI
BS0
CT2CT1CT0PS0PS1PS2PS3
CT[0..2]
PS[0..3]
C80CODES1.ABL
PAL22LV10PLCC
U36
17181920212324252627
I/OI/O
I/OI/OI/OI/O
I/OI/O
I/OI/O
II
I
IIII
II
III/CLK
16131211109765432
C80A16C80A17C80A28C80A29C80A30
STAT1STAT0C80A31
STAT3STAT2
STAT4STAT5
2Q12Q22Q32Q42Q52Q62Q72Q8
Figure B–10. Logic
Schematics
Schem
atics
B-11
TM
S320C
80 Fram
e Buffer
VCC3
C810.1 F
C800.1 F
C790.1 F
C780.1 F
C770.1 F
C760.1 F
C750.1 F
C740.1 F
C730.1 F
C720.1 F
C710.1 F
C700.1 F
C910.1 F
C890.1 F
C880.1 F
C870.1 F
C680.1 F
C670.1 F
C660.1 F
C650.1 F
C900.1 F
C560.1 F
C550.1 F
C1030.1 F
C1020.1 F
C1010.1 F
C1000.1 F
C11022 F
C10922 F
C690.1 F
C640.1 F
C630.1 F
C620.1 F
C610.1 F
C600.1 F
C590.1 F
C580.1 F
C570.1 F
C1084.7 F
C860.1 F
C990.1 F
C980.1 F
C970.1 F
C960.1 F
C950.1 F
C940.1 F
C930.1 F
C920.1 F
C850.1 F
C840.1 F
C830.1 F
C820.1 F
VCC3
VCC5
PALs
BUFFERS/LATCH
OSC
RESET (7705A)
+
C1074.7 F
+C1064.7 F
+
Note - TVP decoupling caps are included in tvppwr.sch
C80 Caps
VRAM Caps
++
Figure B–11. TMS320C80-Decoupling Caps
SPRA156B-12
ABEL Files
C-1 TMS320C80 Frame Buffer
Appendix C ABEL Filesmodule C80codes1
title’
DWG NAME LOGIC.SCH
PAL # U36
COMPANY TEXAS INSTRUMENTS INCORPORATED
ENGINEER C80 APPLICATIONS
DATE 02_28_96’
xx_001 device ’P22V10C’; ” PAL22LV10–7 PLCC
STAT5 Pin 2; ”C80 STATUS[5]
STAT4 Pin 3; ”C80 STATUS[4]
STAT3 Pin 4; ”C80 STATUS[3]
STAT2 Pin 5; ”C80 STATUS[2]
STAT1 Pin 6; ”C80 STATUS[1]
STAT0 Pin 7; ”C80 STATUS[0]
A31 Pin 9; ”C80 address line 31
A30 Pin 10; ”C80 address line 30
A29 Pin 11; ”C80 address line 29
A28 Pin 12; ”C80 address line 28
A17 Pin 13; ”C80 address line 17
A16 Pin 16; ”C80 address line 16
vss Pin 14; ”Ground
vcc Pin 28; ”Power
”NC Pin 27;
”NC Pin 26;
PS3 Pin 25; ”C80 PS[3] input (page size)
PS2 Pin 24; ”C80 PS[2] input (page size)
PS1 Pin 23; ”C80 PS[1] input (page size)
PS0 Pin 21; ”C80 PS[0] input (page size)
CT0 Pin 20; ”C80 CT[0] input (cycle timing)
CT1 Pin 19; ”C80 CT[1] input (cycle timing)
CT2 Pin 18; ”C80 CT[2] input (cycle timing)
”NC Pin 17;
ABEL is a trademark of DATA I /O.
ABEL Files
SPRA156C-2
”constants and alias names
ADDR = [A31..A28] ;
REFADD = [A17..A16] ;
STAT = [STAT5..STAT0] ;
refr1 = 0 ; ”VRAM bank refresh pseudo–address
refr2 = 1 ; ”VRAM bank refresh pseudo–address
MRS = 12 ;
DCAB = 3 ;
REFRESH = 2 ;
READ = 0 ;
WRITE = 1 ;
SDRAM_cyc =(!STAT5 & !STAT4 & !STAT3 & !STAT2 & STAT1 & STAT0)#(!STAT5 & !STAT4 & STAT3 & STAT2 & !STAT1 & !STAT0);
VRAM_refresh =(!STAT5 & !STAT4 & !STAT3 & !STAT2 & STAT1 & !STAT0) &(( !A17 & A16) # (!A17 & !A16));
REFH = (!STAT5 & !STAT4 & !STAT3 & !STAT2 & STAT1 & !STAT0);
VRAM_AV = A31 & !A30 & A29 & !A28 ;
TVP_AV = A31 & !A30 & !A29 & !A28 ;
equations
PS3 = (VRAM_AV) & !(SDRAM_cyc # REFH)
#(TVP_AV) & !(SDRAM_cyc # REFH);
”#(SYSTEM_SPECIFIC_REQUIRING_PS3=1)
PS2 = 0 ;
”#(SYSTEM_SPECIFIC_REQUIRING_PS2=1)
PS1 = (VRAM_AV) & !(SDRAM_cyc # REFH);
”#(SYSTEM_SPECIFIC_REQUIRING_PS1=1);
PS0 = 0 ;
”#(SYSTEM_SPECIFIC_REQUIRING_PS0=1)
CT2 = (VRAM_AV) & !(SDRAM_cyc # REFH)
#VRAM_refresh
#(TVP_AV) & !(SDRAM_cyc # REFH);
”#(SYSTEM_SPECIFIC_REQUIRING_CT2=1)
CT1 = (VRAM_AV) & !(SDRAM_cyc # REFH)
#VRAM_refresh
#(TVP_AV) & !(SDRAM_cyc # REFH);
”#(SYSTEM_SPECIFIC_REQUIRING_CT1=1)
ABEL Files
C-3 TMS320C80 Frame Buffer
CT0 = (VRAM_AV) & !(SDRAM_cyc # REFH)
#(VRAM_refresh)
#(TVP_AV) & !(SDRAM_cyc # REFH);
”#(SYSTEM_SPECIFIC_REQUIRING_CT0=1)
test_vectors”PS3
([ ADDR , STAT ] –> [PS3])
[ 0 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 1 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 8 , .X. ] –> [ 1 ] ;” TVP3020 addressed
[ 9 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 10 , 0 ] –> [ 1 ] ;” VRAM addressed, reads
[ 10 , 1 ] –> [ 1 ] ;” VRAM addressed, writes
[ 10 ,REFRESH] –> [ 0 ] ;” VRAM addressed, refresh cycle
[ 10 , MRS ] –> [ 0 ] ;” VRAM addressed, MRS cycle
[ 10 , DCAB ] –> [ 0 ] ;” VRAM addressed, DCAB cycle
[ 11 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ;” VRAM not addressed
test_vectors”PS2
([ ADDR , STAT ] –> [PS2])
[ 0 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 1 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ;” TVP3020 addressed
ABEL Files
SPRA156C-4
[ 9 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 10 , 0 ] –> [ 0 ] ;” VRAM addressed, reads
[ 10 , 1 ] –> [ 0 ] ;” VRAM addressed, writes
[ 10 ,REFRESH] –> [ 0 ] ;” VRAM addressed, refresh cycle
[ 10 , MRS ] –> [ 0 ] ;” VRAM addressed, MRS cycle
[ 10 , DCAB ] –> [ 0 ] ;” VRAM addressed, DCAB cycle
[ 11 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ;” VRAM not addressed
test_vectors”PS1
([ ADDR , STAT ] –> [PS1])
[ 0 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 1 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ;” TVP3020 addressed
[ 9 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 10 , 0 ] –> [ 1 ] ;” VRAM addressed, reads
[ 10 , 1 ] –> [ 1 ] ;” VRAM addressed, writes
[ 10 ,REFRESH] –> [ 0 ] ;” VRAM addressed, refresh cycle
[ 10 , MRS ] –> [ 0 ] ;” VRAM addressed, MRS cycle
[ 10 , DCAB ] –> [ 0 ] ;” VRAM addressed, DCAB cycle
[ 11 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ;” VRAM not addressed
test_vectors”PS0
([ ADDR , STAT ] –> [PS0])
[ 0 , .X. ] –> [ 0 ] ;” VRAM not addressed
ABEL Files
C-5 TMS320C80 Frame Buffer
[ 1 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ;” TVP3020 addressed
[ 9 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 10 , 0 ] –> [ 0 ] ;” VRAM addressed, reads
[ 10 , 1 ] –> [ 0 ] ;” VRAM addressed, writes
[ 10 ,REFRESH] –> [ 0 ] ;” VRAM addressed, refresh cycle
[ 10 , MRS ] –> [ 0 ] ;” VRAM addressed, MRS cycle
[ 10 , DCAB ] –> [ 0 ] ;” VRAM addressed, DCAB cycle
[ 11 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ;” VRAM not addressed
test_vectors”CT2
([ ADDR , STAT, REFADD ] –> [ CT2 ])
[ 0 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 1 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 2 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 3 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 4 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 5 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 6 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 7 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 8 , READ, .X. ] –> [ 1 ] ;” TVP3020 addressed
[ 8 ,WRITE, .X. ] –> [ 1 ] ;” TVP3020 addressed
[ 9 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 10 , READ, .X. ] –> [ 1 ] ;” VRAM addressed
[ 10 ,WRITE, .X. ] –> [ 1 ] ;” VRAM addressed
[ 11 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 12 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 13 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
ABEL Files
SPRA156C-6
[ 14 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 15 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ .X. ,REFRESH,refr1 ] –> [ 1 ] ;” VRAM refresh
[ .X. ,REFRESH,refr2 ] –> [ 1 ] ;” VRAM refresh
[ .X. ,REFRESH, 2 ] –> [ 0 ] ;” refresh– not VRAM
[ .X. ,REFRESH, 3 ] –> [ 0 ] ;” refresh– not VRAM
[ .X. , MRS , .X. ] –> [ 0 ] ;” MRS
[ .X. , DCAB, .X. ] –> [ 0 ] ;” DCAB
test_vectors”CT1
([ ADDR , STAT, REFADD ] –> [ CT1 ])
[ 0 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 1 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 2 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 3 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 4 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 5 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 6 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 7 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 8 , READ, .X. ] –> [ 1 ] ;” TVP3020 addressed
[ 8 ,WRITE, .X. ] –> [ 1 ] ;” TVP3020 addressed
[ 9 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 10 , READ, .X. ] –> [ 1 ] ;” VRAM addressed
[ 10 ,WRITE, .X. ] –> [ 1 ] ;” VRAM addressed
[ 11 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 12 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 13 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 14 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 15 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ .X. ,REFRESH,refr1 ] –> [ 1 ] ;” VRAM refresh
[ .X. ,REFRESH,refr2 ] –> [ 1 ] ;” VRAM refresh
[ .X. ,REFRESH, 2 ] –> [ 0 ] ;” refresh– not VRAM
[ .X. ,REFRESH, 3 ] –> [ 0 ] ;” refresh– not VRAM
[ .X. , MRS , .X. ] –> [ 0 ] ;” MRS
[ .X. , DCAB, .X. ] –> [ 0 ] ;” DCAB
ABEL Files
C-7 TMS320C80 Frame Buffer
test_vectors”CT0
([ ADDR , STAT, REFADD ] –> [ CT0 ])
[ 0 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 1 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 2 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 3 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 4 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 5 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 6 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 7 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 8 , READ, .X. ] –> [ 1 ] ;” TVP3020 addressed
[ 8 ,WRITE, .X. ] –> [ 1 ] ;” TVP3020 addressed
[ 9 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 10 , READ, .X. ] –> [ 1 ] ;” VRAM addressed
[ 10 ,WRITE, .X. ] –> [ 1 ] ;” VRAM addressed
[ 11 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 12 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 13 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 14 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ 15 , .X. , .X. ] –> [ 0 ] ;” VRAM not addressed
[ .X. ,REFRESH,refr1 ] –> [ 1 ] ;” VRAM refresh
[ .X. ,REFRESH,refr2 ] –> [ 1 ] ;” VRAM refresh
[ .X. ,REFRESH, 2 ] –> [ 0 ] ;” refresh– not VRAM
[ .X. ,REFRESH, 3 ] –> [ 0 ] ;” refresh– not VRAM
[ .X. , MRS , .X. ] –> [ 0 ] ;” MRS
[ .X. , DCAB, .X. ] –> [ 0 ] ;” DCAB
end C80codes1
ABEL Files
SPRA156C-8
module C80codes2
title’
DWG NAME LOGIC.SCH
PAL # U35
COMPANY TEXAS INSTRUMENTS INCORPORATED
ENGINEER C80 APPLICATIONS
DATE 02_28_96’
xx_001 device ’P22V10C’; ” PAL22LV10–7C PLCC
STAT5 Pin 2; ”C80 STATUS[5]
STAT4 Pin 3; ”C80 STATUS[4]
STAT3 Pin 4; ”C80 STATUS[3]
STAT2 Pin 5; ”C80 STATUS[2]
STAT1 Pin 6; ”C80 STATUS[1]
STAT0 Pin 7; ”C80 STATUS[0]
A31 Pin 9; ”C80 address line 31
A30 Pin 10; ”C80 address line 30
A29 Pin 11; ”C80 address line 29
A28 Pin 12; ”C80 address line 28
A17 Pin 13; ”C80 address line 17
A16 Pin 16; ”C80 address line 16
vss Pin 14; ”Ground
vcc Pin 28; ”Power
_RESET Pin 27; ”C80 _RESET – used as an input here
_UTIME Pin 26; ”C80 /UTIME input (user timed cycles)
AS2 Pin 25; ”C80 AS[2] input (address shift)
AS1 Pin 24; ”C80 AS[1] input (address shift)
AS0 Pin 23; ”C80 AS[0] input (address shift)
BS1 Pin 21; ”C80 BS[1] input (bus size)
BS0 Pin 20; ”C80 BS[0] input (bus size)
”NC Pin 19;
”NC Pin 18;
”NC Pin 17;
”constants and alias names
ADDR = [A31..A28] ;
REFADD = [A17..A16] ;
STAT = [STAT5..STAT0];
refr1 = 0 ; ”VRAM bank refresh pseudo–address
ABEL Files
C-9 TMS320C80 Frame Buffer
refr2 = 1 ; ”VRAM bank refresh pseudo–address
MRS = 12 ;
READ = 0 ;
WRITE = 1 ;
blk_wr = 9 ;
VRAM_AV = A31 & !A30 & A29 & !A28 ;
TVP_AV = A31 & !A30 & A29 & !A28 ;
SDRAM_cyc =(!STAT5 & !STAT4 & !STAT3 & !STAT2 & STAT1 & STAT0)
#(!STAT5 & !STAT4 & STAT3 & STAT2 & !STAT1 & !STAT0);
equations
AS2 = 0 ;
”#(SYSTEM_SPECIFIC_REQUIRING_AS2=1)
AS1 = (VRAM_AV) & !(SDRAM_cyc) ;
”#(SYSTEM_SPECIFIC_REQUIRING_AS1=1)
AS0 = 0 ;
”#(SYSTEM_SPECIFIC_REQUIRING_AS0=1)
BS1 = (VRAM_AV) & !(SDRAM_cyc) ;
”#(SYSTEM_SPECIFIC_REQUIRING_BS1=1)
BS0 = (VRAM_AV) & !(SDRAM_cyc # blk_wrt);
”#(SYSTEM_SPECIFIC_REQUIRING_BS0=1)
!_UTIME = (TVP_AV) & !(SDRAM_cyc)
#(!_RESET);
”#(SYSTEM_SPECIFIC_REQUIRING_UTIME=0)
blk_wrt =(!STAT5 & !STAT4 & STAT3 & !STAT2 & !STAT1 & STAT0);
test_vectors”AS2
([ ADDR , STAT ] –> [AS2])
[ 0 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 1 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ; ” TVP3020 addressed
[ 8 , MRS ] –> [ 0 ] ; ” TVP3020 addressed– MRS
ABEL Files
SPRA156C-10
[ 9 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 10 , .X. ] –> [ 0 ] ; ” VRAM addressed
[ 10 , MRS ] –> [ 0 ] ; ” VRAM addressed – MRS
[ 11 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ; ” VRAM not addressed
test_vectors”AS1
([ ADDR , STAT ] –> [AS1])
[ 0 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 1 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ; ” TVP3020 addressed
[ 8 , MRS ] –> [ 0 ] ; ” TVP3020 addressed– MRS
[ 9 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 10 , .X. ] –> [ 1 ] ; ” VRAM addressed
[ 10 , MRS ] –> [ 0 ] ; ” VRAM addressed – MRS
[ 11 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ; ” VRAM not addressed
test_vectors”AS0
([ ADDR , STAT ] –> [AS0])
[ 0 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 1 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ; ” VRAM not addressed
ABEL Files
C-11 TMS320C80 Frame Buffer
[ 6 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ; ” TVP3020 addressed
[ 8 , MRS ] –> [ 0 ] ; ” TVP3020 addressed– MRS
[ 9 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 10 , .X. ] –> [ 0 ] ; ” VRAM addressed
[ 10 , MRS ] –> [ 0 ] ; ” VRAM addressed – MRS
[ 11 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ; ” VRAM not addressed
test_vectors”BS1
([ ADDR , STAT ] –> [BS1])
[ 0 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 1 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ; ” TVP3020 addressed
[ 9 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 10 ,WRITE ] –> [ 1 ] ; ” VRAM addressed (writes)
[ 10 ,READ ] –> [ 1 ] ; ” VRAM addressed (reads)
[ 10 ,blk_wr] –> [ 1 ] ; ” VRAM addressed (block write)
[ 11 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ .X. , MRS ] –> [ 0 ] ; ” MRS (change as req’d)
test_vectors”BS0
([ ADDR , STAT ] –> [BS0])
[ 0 , .X. ] –> [ 0 ] ; ” VRAM not addressed
ABEL Files
SPRA156C-12
[ 1 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 2 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 3 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 4 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 5 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 6 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 7 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 8 , .X. ] –> [ 0 ] ; ” TVP3020 addressed
[ 9 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 10 ,WRITE ] –> [ 1 ] ; ” VRAM addressed (writes)
[ 10 ,READ ] –> [ 1 ] ; ” VRAM addressed (reads)
[ 10 ,blk_wr] –> [ 0 ] ; ” VRAM addressed (block write)
[ 11 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 12 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 13 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 14 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ 15 , .X. ] –> [ 0 ] ; ” VRAM not addressed
[ .X. , MRS ] –> [ 0 ] ; ” MRS (change as req’d)
end C80codes2
ABEL Files
C-13 TMS320C80 Frame Buffer
module vramctl
title’
DWG NAME LOGIC.SCH
PAL # U37
COMPANY TEXAS INSTRUMENTS INCORPORATED
ENGINEER C80 APPLICATIONS
DATE 02_28_96’
xx_001 device ’P22V10C’; ” PAL22LV10–7 PLCC
CLKOUT Pin 2; ”C80 CLKOUT
LSTAT5 Pin 3; ”C80 STATUS[5] ––EXTERNALLY LATCHED BY _RL
LSTAT4 Pin 4; ”C80 STATUS[4] ––EXTERNALLY LATCHED BY _RL
LSTAT3 Pin 5; ”C80 STATUS[3] ––EXTERNALLY LATCHED BY _RL
LSTAT2 Pin 6; ”C80 STATUS[2] ––EXTERNALLY LATCHED BY _RL
LSTAT1 Pin 7; ”C80 STATUS[1] ––EXTERNALLY LATCHED BY _RL
LSTAT0 Pin 9; ”C80 STATUS[0] ––EXTERNALLY LATCHED BY _RL
LA31 Pin 10; ”C80 address line 31 ––EXTERNALLY LATCHED BY _RL
LA30 Pin 11; ”C80 address line 30 ––EXTERNALLY LATCHED BY _RL
LA29 Pin 12; ”C80 address line 29 ––EXTERNALLY LATCHED BY _RL
LA28 Pin 13; ”C80 address line 28 ––EXTERNALLY LATCHED BY _RL
LA21 Pin 16; ”C80 address line 21 ––EXTERNALLY LATCHED BY _RL
vss Pin 14; ”Ground
vcc Pin 28; ”Power
_RAS Pin 27; ”C80 _RAS
VSTATE Pin 26;
_VRAS1 Pin 25; ”VRAM bank 1 _RAS
_VRAS0 Pin 24; ”VRAM bank 0 _RAS
_VSE1 Pin 23; ”VRAM Bank1 serial output enable
_VSE0 Pin 21; ”VRAM Bank0 serial output enable
”NC Pin 20;
”NC Pin 19;
LA17 Pin 18; ”C80 address line 17 ––EXTERNALLY LATCHED BY _RL
LA16 Pin 17; ”C80 address line 16 ––EXTERNALLY LATCHED BY _RL
”constants and alias names
ADDR = [LA31..LA28] ;
REFADD = [LA17..LA16] ;
STAT = [LSTAT5..LSTAT0] ;
MRS = 12 ;
ABEL Files
SPRA156C-14
DCAB = 3 ;
READ = 0 ;
WRITE = 1 ;
RFR = 2 ;
SDRAM_cyc =(!LSTAT5 & !LSTAT4 & !LSTAT3 & !LSTAT2 & LSTAT1 & LSTAT0)
#(!LSTAT5 & !LSTAT4 & LSTAT3 & LSTAT2 & !LSTAT1 & !LSTAT0);
REFH = (!LSTAT5 & !LSTAT4 & !LSTAT3 & !LSTAT2 & LSTAT1 & !LSTAT0);
SRT = (!LSTAT5 & LSTAT4 & !LSTAT3 & LSTAT2 & !LSTAT0);
VRAM_AV = LA31 & !LA30 & LA29 & !LA28 ;
equations
!_VRAS1 = (!_RAS & VRAM_AV & LA21) & !(SDRAM_cyc # REFH)
#(REFH & !_RAS & !LA17 & LA16);
!_VRAS0 = (!_RAS & VRAM_AV & !LA21) & !(SDRAM_cyc # REFH)
#(REFH & !_RAS & !LA17 & !LA16);
!_VSE1 = (SRT & LA21 & !_RAS)
#(!_VSE1 & !SRT)
#(!_VSE1 & _RAS);
!_VSE0 = !_VSE1 ;
ABEL Files
C-15 TMS320C80 Frame Buffer
test_vectors”_VRAS1, _VRAS0
([ ADDR , STAT, _RAS, REFADD, LA21 ] –> [_VRAS1, _VRAS0])
[ .X. , RFR , 1 , .X. , .X. ] –> [ 1 , 1 ];”Refresh– RAS high
[ .X. , RFR , 0 , 0 , .X. ] –> [ 1 , 0 ];”Refresh– bank 0
[ .X. , RFR , 0 , 1 , .X. ] –> [ 0 , 1 ];”Refresh– bank 1
[ .X. , RFR , 0 , 2 , .X. ] –> [ 1 , 1 ];”Refresh– not VRAM
[ .X. , RFR , 0 , 3 , .X. ] –> [ 1 , 1 ];”Refresh– not VRAM
[ .X. , RFR , 0 , 3 , .X. ] –> [ 1 , 1 ];”Refresh– not VRAM
[ 0 ,READ , 0 , .X. , .X. ] –> [ 1 , 1 ];”access– not VRAM
[ 8 ,READ , 0 , .X. , .X. ] –> [ 1 , 1 ];”access– not VRAM
[ 9 ,READ , 0 , .X. , .X. ] –> [ 1 , 1 ];”access– not VRAM
[ 10 ,READ , 0 , .X. , 0 ] –> [ 1 , 0 ];”access– bank 0
[ 10 ,WRITE, 0 , .X. , 0 ] –> [ 1 , 0 ];”access– bank 0
[ 10 ,READ , 0 , .X. , 1 ] –> [ 0 , 1 ];”access– bank 1
[ 10 ,WRITE, 0 , .X. , 1 ] –> [ 0 , 1 ];”access– bank 1
[ 10 , MRS , 0 , .X. , .X. ] –> [ 1 , 1 ];”MRS cycle
[ 10 , DCAB, 0 , .X. , .X. ] –> [ 1 , 1 ];”DCAB cycle
end vramctl
ABEL Files
SPRA156C-16
module dacctl
title’
DWG NAME LOGIC.SCH
PAL # U43
COMPANY TEXAS INSTRUMENTS INCORPORATED
ENGINEER C80 APPLICATIONS
DATE 02_28_96’
xx_001 device ’P22V10C’; ” PAL22LV10–7 PLCC
CLKOUT Pin 2; ”C80 CLKOUT
LSTAT5 Pin 3; ”C80 STATUS[5] ––EXTERNALLY LATCHED BY _RL
LSTAT4 Pin 4; ”C80 STATUS[4] ––EXTERNALLY LATCHED BY _RL
LSTAT3 Pin 5; ”C80 STATUS[3] ––EXTERNALLY LATCHED BY _RL
LSTAT2 Pin 6; ”C80 STATUS[2] ––EXTERNALLY LATCHED BY _RL
LSTAT1 Pin 7; ”C80 STATUS[1] ––EXTERNALLY LATCHED BY _RL
LSTAT0 Pin 9; ”C80 STATUS[0] ––EXTERNALLY LATCHED BY _RL
LA31 Pin 10; ”C80 address line 31 ––EXTERNALLY LATCHED BY _RL
LA30 Pin 11; ”C80 address line 30 ––EXTERNALLY LATCHED BY _RL
LA29 Pin 12; ”C80 address line 29 ––EXTERNALLY LATCHED BY _RL
LA28 Pin 13; ”C80 address line 28 ––EXTERNALLY LATCHED BY _RL
_CAS7 Pin 16; ”C80 _CAS line
vss Pin 14; ”Ground
vcc Pin 28; ”Power
_DRAS Pin 27; ”C80 _RAS delayed 1/2 clk cycle
_DDRAS Pin 26; ”_DRAS with ext delay– compensates for nonoverlap on /W
_RAS Pin 25; ”C80 _RAS
”NC Pin 24;
_DACWR Pin 23; ”TVP /WR pulse
_DACRD Pin 21; ”TVP /RD pulse
”NC Pin 20;
_DRAS3 Pin 19; ”C80 _RAS delay 2 1/2 cycles
_DRAS2 Pin 18; ”C80 _RAS delay 1 1/2 cycles
_DDRAS2 Pin 17; ”_DDRAS2 with ext– compensates for nonoverlap on /W
”constants and alias names
ADDR = [LA31..LA28] ;
STAT = [LSTAT5..LSTAT0] ;
MRS = 12 ;
ABEL Files
C-17 TMS320C80 Frame Buffer
DCAB = 3 ;
READ = 0 ;
WRT = 1 ;
RFR = 2 ;
SDRAM_cyc =(!LSTAT5 & !LSTAT4 & !LSTAT3 & !LSTAT2 & LSTAT1 & LSTAT0)
#(!LSTAT5 & !LSTAT4 & LSTAT3 & LSTAT2 & !LSTAT1 & !LSTAT0);
REFH = (!LSTAT5 & !LSTAT4 & !LSTAT3 & !LSTAT2 & LSTAT1 & !LSTAT0);
TVP_AV = LA31 & !LA30 & !LA29 & !LA28 ;
equations
!_DACRD = (TVP_AV)
& (!LSTAT5 & !LSTAT4 & !LSTAT3 & !LSTAT2 & !LSTAT1 & !LSTAT0)& !_CAS7 ;
!_DACWR = (TVP_AV)
& (!LSTAT5 & !LSTAT4 & !LSTAT3 & !LSTAT2 & !LSTAT1 & LSTAT0)& (!_RAS # !_DDRAS # !_DDRAS2 # !_DRAS3);
!_DRAS := (!_RAS) & (TVP_AV)
& (!LSTAT5 & !LSTAT4 & !LSTAT3 & !LSTAT2 & !LSTAT1);
_DRAS2 := _DRAS ;
_DRAS3 := _DDRAS2 ;
ABEL Files
SPRA156C-18
test_vectors”_DACWR,_DACRD([CLKOUT,ADDR,STAT,_RAS,_DDRAS,_DRAS2,_DDRAS2,_DRAS3,_CAS7] –>[_DACRD,_DACWR])”READY
[ 0 , 0 , 0, 0 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 0 , 0, 0 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 0 , 0, 0 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 0 , 0, 0 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 , WRT, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 8 , WRT, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 , WRT, 0 , 1 , 1 , 1 , 1 , 0 ] –> [ 1 , 0 ];” 1
[ 1 , 8 , WRT, 0 , 0 , 1 , 1 , 1 , 0 ] –> [ 1 , 0 ];” 1
[ 0 , 8 , WRT, 1 , 0 , 1 , 1 , 1 , 0 ] –> [ 1 , 0 ];” 1
[ 1 , 8 , WRT, 1 , 1 , 0 , 0 , 1 , 0 ] –> [ 1 , 0 ];” 0
[ 0 , 8 , WRT, 1 , 1 , 0 , 0 , 1 , 0 ] –> [ 1 , 0 ];” 0
[ 1 , 8 , WRT, 1 , 1 , 1 , 1 , 0 , 0 ] –> [ 1 , 0 ];” 1
[ 0 , 8 , WRT, 1 , 1 , 1 , 1 , 0 , 0 ] –> [ 1 , 0 ];” 1
[ 1 , 8 , WRT, 1 , 1 , 1 , 1 , 1 , 0 ] –> [ 1 , 1 ];” 1
[ 0 , 8 , WRT, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 8 , WRT, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 , .X., 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 8 , .X., 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 , .X., 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 8 , .X., 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 ,READ, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 8 ,READ, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 ,READ, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 8 ,READ, 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 ,READ, 0 , 1 , 1 , 1 , 1 , 0 ] –> [ 0 , 1 ];” 1
[ 1 , 8 ,READ, 0 , 0 , 1 , 1 , 1 , 0 ] –> [ 0 , 1 ];” 1
[ 0 , 8 ,READ, 1 , 0 , 1 , 1 , 1 , 0 ] –> [ 0 , 1 ];” 1
[ 1 , 8 ,READ, 1 , 1 , 0 , 0 , 1 , 0 ] –> [ 0 , 1 ];” 0
[ 0 , 8 ,READ, 1 , 1 , 0 , 0 , 1 , 0 ] –> [ 0 , 1 ];” 0
[ 1 , 8 ,READ, 1 , 1 , 1 , 1 , 0 , 0 ] –> [ 0 , 1 ];” 1
[ 0 , 8 ,READ, 1 , 1 , 1 , 1 , 0 , 0 ] –> [ 0 , 1 ];” 1
[ 1 , 8 ,READ, 1 , 1 , 1 , 1 , 1 , 0 ] –> [ 0 , 1 ];” 1
[ 0 , 8 , .X. , 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 8 , .X. , 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 0 , 8 , .X. , 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 9 , .X. , 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
ABEL Files
C-19 TMS320C80 Frame Buffer
[ 0 , 3 , .X. , 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
[ 1 , 6 , .X. , 1 , 1 , 1 , 1 , 1 , 1 ] –> [ 1 , 1 ];” 1
end dacctl
SPRA156C-20