today’s class

42
Informationsteknologi Friday, October 19, 2 007 Computer Architecture I - Class 6 1 Today’s class Floating point numbers Computer systems organization

Upload: wilbur

Post on 04-Jan-2016

26 views

Category:

Documents


1 download

DESCRIPTION

Today’s class. Floating point numbers Computer systems organization. Principles of Floating Point. Must separate range from precision Use scientific notation n = f × 10 e f is the fraction or mantissa e is the exponent (a positive or negative integer) - PowerPoint PPT Presentation

TRANSCRIPT

Page 1: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 1

Today’s class

Floating point numbers Computer systems organization

Page 2: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 2

Principles of Floating Point Must separate range from precision Use scientific notation n = f × 10e

f is the fraction or mantissa e is the exponent (a positive or negative integer)

Examples3.14 = 0.314 × 101 = 3.14 × 100

0.000001 = 0.1 × 10−5 = 1.0 × 10−6

1941 = 0.1941 × 104 = 1.941 × 103

Page 3: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 3

Seven Regions of Real Number Line Large negative numbers less than −0.999 × 1099

Negative numbers between −0.999 × 1099 and −0.100 × 10−99

Small negative numbers, magnitudes less than 0.100 × 10−99

Zero Small positive numbers, magnitudes less than 0.100 ×

10−99

Positive numbers between 0.100 × 10−99 and 0.999 × 1099

Large positive numbers greater than 0.999 × 1099

Page 4: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 4

Seven Regions of Real Number Line

Page 5: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 5

Approximate Bounds of Expressible Floating-Point Numbers (Unnormalized)

Page 6: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 6

Normalized numbers

Examples of normalized floating-point numbers.

Page 7: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 7

IEEE Floating-Point Standard 754

IEEE floating-point formats. (a) Single precision. (b) Double precision.

Page 8: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 8

IEEE Floating-point Standard 754

Characteristics of IEEE floating-point numbers.

Page 9: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 9

IEEE Numerical Types

Page 10: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 10

In-Class Exercise Convert the following numbers to IEEE single-

precision format. Give the results as 8 hexadecimal digits. 9.0 -6.125

Convert the following IEEE single-precision floating-point numbers from hex to decimal: 42E48000 3F880000

Page 11: Today’s class

Computer Systems Organization

Page 12: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 12

Organization of a simple computer

Page 13: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 13

CPU Organization

Page 14: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 14

Instructions Register-memory

Allow memory words to be fetched into registers Allow registers to be stored to memory words

Register-register Fetches two operands from the registers Brings them to the ALU input registers Performs some operation on them Stores the result back in one of the registers

Page 15: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 15

Instruction Execution Steps Fetch next instruction from memory into instruction

register Change program counter to point to next instruction Determine type of instruction just fetched If instruction uses a word in memory, determine where it

is Fetch word, if needed, into CPU register Execute the instruction Go to step 1 to begin executing the following instruction

Page 16: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 16

Design Principles for Modern Computers

All instructions are directly executed by hardware

Maximize the rate at which instructions are issued

Instructions should be easy to decode Only loads and stores should reference

memory Provide plenty of registers

Page 17: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 17

Instruction-Level Parallelism

Page 18: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 18

Pipelining effect Suppose the cycle time of the machine is 2 ns For the 5-stage pipeline shown in the previous

slide, it takes 10 ns for an instruction to completely execute

It appears this machine can run at 100 MIPS However, it’s much better than this At every clock cycle, starting with the 5th, one

instruction completes execution This gives an actual processing rate of 500

MIPS

Page 19: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 19

Dual Pipelines

If one pipeline is good, two must be better!

Page 20: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 20

Superscalar Architecture

Page 21: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 21

Processor-Level Parallelism

Page 22: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 22

Multiprocessors

A single-bus multiprocessor

A multicomputer with local memories

Page 23: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 23

Memory

Most basic unit of memory is the bit, a 0 or 1 (binary digit)

Smallest addressable unit of memory in a computer is the byte (containing 8 bits)

Words are groups of bytes, typically 4 bytes (32 bits) to a word

Page 24: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 24

Big- and Little-Endian

Bytes can be numbered left-to-right or right-to left

Page 25: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 25

Byte Ordering

Page 26: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 26

Parity Memories can have occasional errors Errors will be bit inversions Can detect one-bit errors by adding an

extra bit called a parity bit This bit is set or cleared so that the total

number of 1’s in the word is either even or odd, depending on which type of parity is being used

Page 27: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 27

Codewords Let one memory word consist of m data bits Let’s add r redundant (or check or parity) bits Total length is n bits, where n = m + r The n-bit unit is called a codeword Given two codewords you can determine how

many bits differ by computing the exclusive or (XOR) of the two codewords and counting how many 1s are in the result

This sum is called the Hamming distance

Page 28: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 28

How Many Check Bits?

There are 2m valid memory words Each valid memory word has n illegal

codewords 1 bit away from it Thus, each of the 2m valid words needs

n+1 bit patterns dedicated to it Total number of bit patterns is 2n

So, (n+1)2m ≤ 2n, or (m+r+1) ≤ 2r

Page 29: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 29

Number of check bits for a code that can correct a single error

Page 30: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 30

Error Correcting Codes

(a) Encoding of 1100

(b) Even parity added

(c) Error in AC

Page 31: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 31

Hamming Codes 16-bit word needs 5 parity bits The parity bits are the bits whose positions are powers

of 2 Bit b is checked by the parity bits whose positions sum

to b For example, bit 6 is checked by bits 2 and 4

Page 32: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 32

Cache Memory

Page 33: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 33

Memory Hierarchy

Page 34: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 34

Magnetic Disk Format

Page 35: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 35

Disk Platters

Page 36: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 36

Disk Performance First, arm must be moved to the correct track; this is

called a seek Average seek times between random tracks are in the

range 5-10 ms Then we have the rotational delay to find the correct

sector Average rotational delay is 3-6 ms Transfer time depends on the linear density and rotation

speed Typical transfer times for one sector are 13-26 μs Clearly seek time and rotational delay dominate the

transfer time

Page 37: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 37

Zones Outer tracks of a disk have

larger circumferences than inner tracks

Thus linear density is lower the further out you go

To increase capacity the disk is divided into zones (there are 5 zones to the right)

The number of sectors per track is increased as you move from zone to zone going outward

Page 38: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 38

CD-ROM

Page 39: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 39

CD-ROM Logical Data Layout

Page 40: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 40

DVD

Smaller pits than CD (0.4 microns vs. 0.8 microns for CD)

Tighter spiral (0.74 microns vs. 1.6 microns for CD)

Capacity is 4.7 GB

Page 41: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 41

Input/Output

Page 42: Today’s class

Info

rmat

ions

tekn

olog

i

Friday, October 19, 2007 Computer Architecture I - Class 6 42

Buses