topics: 1. trees - properties 2. the master theorem 3. decoders מבנה המחשב - אביב 2004...

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Topics: 1. Trees - properties 2. The master theorem 3. Decoders בבבב- בבבב בבבבב2004 בבבבב4#

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Topics:1. Trees - properties 2. The master theorem3. Decoders

2004מבנה המחשב - אביב

4#תרגול

Tree: Basic properties•An undirected graph is a tree if it is:

•Connected, i.e., there is a path between every two vertices.

•Contains no cycles.

•One of these properties can be replaced with the following:

•|E| = |V|-1

Directed Tree: Basic properties•An directed graph is a directed tree if it is:

•In-degree = 1 for all v, besides the root.

•In degree of the root is 0.

•There is a directed path from the root to every node.

•Tree directed tree:

•Pick one of its vertices to be a root

•Direct all the edges out from the root

•Repeat it with the vertices as the roots.

Directed Tree (cont.)•A leaf is a node with out-degree zero.

•We define on the vertices of a directed tree:

•The parent of a node v. Note there is only one such vertices.

•A child of a node v (there may be many).

•Ancestor and Descendent of v.

The root (source): Ancestor for all x, but has no parent.

Internal node: has a parent, may have children.

A leaf (sink): has no children.

A claim on Trees•In a directed tree, any non-leaf is called an internal node.

•For a tree: a leaf is a node whose degree is 1.

•Claim: If the degree of any vertex in the tree 3, then the number of internal nodes the number of the leaves –2.

•Note: the underlying graph of a directed binary tree is such a tree, but since the root does not count as a leaf, we have in directed trees:

#internal nodes #internal leaves -1

A claim on Trees (cont.)•Proof (Induction on the number of nodes):

•Basis: trivial for n=1,2 , check for all trees with 3 nodes (there is only one such tree).

•Assumption: correct for all trees of size n.

•Step: prove for any tree of size n+1. Given such a tree, it must contain an internal node v.

• Pick such a v that is connected to a leaf.

•Define |T|=n = m+k, (m is #leaf, k is # internal.

A claim on Trees (cont.)•If v is connected to one leaf u:

• remove (u,v), to obtain a tree T’ of size n-1

m (# leafs) is the same for T and T’

k (# internal) increased by 1

k m-2 (induction hypothesis).

A claim on Trees (cont.)•If v is connected to two leaves u,w:

• remove both edges, to obtain a tree T’ of size n-2

m’ = m – 2 + 1 (u,w were removed, but v became a leaf in T’)

k’ = k – 1 (v is an internal node in T)

Applying the induction hypothesis, we obtain: k = k’+1 m’-2+1 = m-2 m-2

The master theorem• a,b are two constants 1. is a constant > 0.

• f(n) is a function.

• T(n) = aT(n/b) + f(n)

1. If f(n) = O(n(logb

a - )) then T(n) = (n(logb

a))

2. If f(n) = O(nlogb

a) then T(n)= (n(logb

a)logn)

3. If f(n) = O(n(logb

a + )) and af(n/b) cf(n) for some c < 1, then T(n) = (f(n))

The master theorem - Examples• T(n) = 9T(n/3) +n. Set =1and we are in the

first case. Hence T(n) = (n(log3

9)) = (n2).

• T(n) = T(2n/3) + 1. a=1, b=3/2 note that log(1) = 0 so f(n) = (n0) and we are in case 2. Hence T(n) = (n0logn) = (logn).

The master theorem – Techniques for the proof

• Two main techniques used in the proof.

• First we may focus on exact powers of b. This simplifies the arguments.

• Next we examine the recurrence tree.

• Finally we extend it to any n. This step is purely technical.

• In algorithmic cases, we usually may assume that instead of running on an input of size n, we run on a larger input n’ which is a power of b. This would not change the asymptotic.

The master theorem - Examples

• T(n) = 9T(n/3) +n. Set =1and we are in the first case. Hence T(n) = (n(log

3 9)) = (n2).

• T(n) = T(2n/3) + 1. a=1, b=3/2 note that log(1) = 0 so f(n) = (n0) and we are in case 2. Hence T(n) = (n0logn) = (logn).

• Input: A string {0,1}n .

• Output: A string {0,1}2n .

• Functionality: For every string s, returns 1 in the bit which is the binary representation of s.

• Implementation:

• Construct a device with n inputs and 1 output, that returns 1 when its input is the number k.

• The device is implemented using up to n NOT gates, and one AND gate of fan-in n.

Brute force decoder(n)

• Implementation (cont.):

• For every output bit k, connect the device that implements k.

• Correctness: Trivial, it is the implementation of the required boolean function.

• Size: O(n2n).

• Delay: O(1), if we use and gates with non-restricted fan-in. If we need to implement with and gates with fan-in = 2, requires O(log n).

Brute force decoder(n) (cont.)

Decoder’(n)

Decoder(n) design shown and proven in class:

for k = n-1:

Decoder(1)

Decoder’(n)

Decoder’(n) is a private case of Decoder(n) design. (k = n-1 or k = 1)

Decoder’(n) is a correct implementation of a decoder.

otherwise22)1(

1n if1 INVcANDcnc

INVcnc n

Cost analysis:

Solving the recurrence:

INVcANDcncnc n 21

INVcnANDcc nn 12221 21

ANDcINVcnn

1212

21

2

ANDcINVcn n 42 1

n2

:1n

asymptotics

otherwise1,max

1n if)(

ANDdndINVd

INVdnd

ANDdndINVdnd 1,max

ANDdnd 1

ANDdnd 11

ANDdnINVd 1

n Linear Delay!!!

Delay analysis:

Solving the recurrence:

:1n

otherwise0

0:10:112,mod 222

nn xIiA

n

otherwise0

:1:11

2

22

2

nn nxnIiB n

Decoder(n) for k = n/2

Consider the top two recursion steps:

each AND-gate in the “AND-gates array” of the second recursion step, i.e. Decoder(n/2), feeds 2n/2 AND-gates in the “AND-gates array” of the primary recursion step, i.e. Decoder(n).

22 net a offanout Maximumn

otherwise22

1n if

2 ANDcc

INVcnc nn

n2

otherwise

1n if)(

2 ANDdd

INVdnd

n nlog

Design

n

Decoder(n)

k=n/2

Decoder’(n)

111

233

457

8715

16931

Design

n

Decoder(n)

k=n/2

Decoder’(n)

111

21010

45260

86161024

16132304262152

Cost

Delay

The next slides are for the curious students (home reading)

• Input: A string {0,1}2n.

• Output: A string {0,1}n .

• Functionality: For every string s with weight 1, returns the the binary representation of s.

• Implementation:

• Connect all the bits with an OR gate of size 2n, this gate sets bit 0 of the output.

• Connect bits 1,3,…2n–1 with an OR gate of size 2n-1, this gate sets bit 1 of the output.

• And so on for each power of 2.

Brute force encoder(n)

• Correctness: Trivial, bit j of the output is 1 if and only if any of the inputs in the set Sj is 1. The set Sj is the set of all input bits whose index is such that 2j is 1 in its binary representation.

• Size: O(n2n).

• Delay: O(1), if we use OR gates with non-restricted fan-in. If we need to implement with and gates with fan-in = 2, requires O(n).

Brute force encoder(n) (cont.)

11 bufferc

11 bufferd

2fanout

A balanced tree structure minimizes the delay and cost.

The tree is a binary tree due to fan-out limitations.

buffer1

bufferdnnd 11log2

buffercnnc 12

Notice: * The leaves of the tree feed the gate outputs.

* The root of the tree is fed by the gate input.

* The first branching is free → no need for a “root” gate.

Buffers

bufctreebufc

INVcANDcncncn

n

1212

211

bufc

INVcANDcncn

n

132

21

Cost analysis:

1-buf-trees

INVcc 1

:1n

:1n

Fanout limitation effect on design2fanout

ANDd

nd

treebufdbufd

treebufdINVd

nd n

n

1

211

21

max 1

1

Delay analysis:

INVdd 11-buf-trees

ANDd

nd

bufdn

bufdnINVd

1

1

11

max

:1n

:1n

ANDdtreebufddndn

n 2212

22 2122

22 2

nn

treebufc

ANDccnc nn

Cost analysis:

Delay analysis:

bufc

ANDccnn

nn

1222

22

221

2

INVcc 1

INVdd 1

ANDdbufdd nn 1122

:1n

:1n

:1n

:1n

1-buf-trees

Cost Decoder(n):n=1: 1n=2: 10n=4: 52n=8: 616n=16: 132304n=32: 8.5902e+009n=64: 3.68935e+019n=128: 6.80565e+038

Cost Decoder‘(n):n=1: 1n=2: 10n=4: 60n=8: 1024n=16: 262152n=32: 1.71799e+010n=64: 7.3787e+019n=128: 1.36113e+039

Cost Decoder‘(n), Fanout<=2:n=1: 1n=2: 11n=4: 79n=8: 1511n=16: 393175n=32: 2.57698e+010n=64: 1.1068e+020n=128: 2.04169e+039

Cost Decoder(n), Fanout<=2:n=1: 1n=2: 10n=4: 68n=8: 1096n=16: 263312n=32: 1.71801e+010n=64: 7.3787e+019n=128: 1.36113e+039

Delay Decoder(n):n=1: 1n=2: 3n=4: 5n=8: 7n=16: 9n=32: 11n=64: 13n=128: 15

Delay Decoder‘(n):n=1: 1n=2: 3n=4: 7n=8: 15n=16: 31n=32: 63n=64: 127n=128: 255

Delay Decoder‘(n), Fanout<=2:n=1: 1n=2: 4n=4: 8n=8: 16n=16: 32n=32: 64n=64: 128n=128: 256

Delay Decoder(n), Fanout<=2:n=1: 1n=2: 3n=4: 6n=8: 11n=16: 20n=32: 37n=64: 70n=128: 135