towards the design of heterogeneous real-time multicore system m5151117 yumiko kimezawa february 1,...

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Towards the Design of Heterogeneous Real-Time Multicore System m5151117 Yumiko Kimezawa February 1, 2013 1 MT2012

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Towards the Design ofHeterogeneous

Real-Time Multicore System

m5151117 Yumiko Kimezawa

February 1, 2013 1MT2012

Background (1/5)

• Electrocardiography (ECG) is a well known method for heart diagnosis- Used as one of major diagnosis for conventional health

monitoring

• Main challenges of processing ECG arise from: - High computational demand for processing huge amount of

data under: Strict time constraints Relatively high sampling frequency Life critical conditions

February 1, 2013 MT2012 2

February 1, 2013 MT2012 3

• Most ECG systems use Pan-Tompkins approach based on QRS complexo Usage of R-peak as a reference pointo Accurate detection of R-peak is a must

R-peak detection might be inaccurate

• Traditional techniques may fail in detecting serious heart problems

Background (2/5)

February 1, 2013 MT2012 4

• Most ECG systems use Pan-Tompkins approach based on QRS complexo Usage of R-peak as a reference pointo Accurate detection of R-peak is a must

R-peak detection might be inaccurate

• Traditional techniques may fail in detecting serious heart problems

Background (2/5)

February 1, 2013 MT2012 5

• Most ECG systems use Pan-Tompkins approach based on QRS complexo Usage of R-peak as a reference pointo Accurate detection of R-peak is a must

R-peak detection might be inaccurate

• Traditional techniques may fail in detecting serious heart problems

Background (2/5)

Background(3/5):BANSMOM System

February 1, 2013 MT2012 6System Architecture of BANSMOM System

Stratix III

Real-timemonitoring interface

Verification

LnynyLN

nyR

0

Ry: Autocorrelation function

y[n]: The filtered ECG signal

L: Lags of the calculations to get the period

PPD algorithm- Autocorrelation

Background (4/5)

February 1, 2013 MT2012 7

Graphic LCD Controller

Master CPUMemory

MasterCPUTimer

GraphicLCDLED JTAG

UART

PPD Module Master Module

LEDController

Avalon Bus

FIR FilterTimer

Slave CPU Memory

Slave CPU

ExternalMemory

SharedMemory

ECG Data Rom

: Data flow : Control signal

• Master module- Controlling the whole systems such as reading date from shared memory, etc

• PPD module- Detection of following information using PPD algorithm

Intervals and their position Position and voltage of each peak (P, Q, R, S, T and U)

Figure: Block diagram of 3-lead system

8

Period detection

Peaks detection

Reading data

Derivation

Autocorrelation

Find interval

Extraction of max point

Store results

Discrimination

• Based on autocorrelation approach

Background (5/5) : PPD Algorithm

February 1, 2013 MT2012

Problems• Requiring a large amount of hardware

resources- Logic utilization shows a linear increase for each additional

PPD modules

• PPD Algorithm runs on single processor may miss Real-Time deadlines

• The need for connecting to database server in order to monitor data efficiently in real-time

February 1, 2013 MT2012 9

Research Goals

1. Software Optimization Parallelize PPD algorithm to boost performance and meet

real-time deadlines

2. Hardware Optimization Optimize system hardware (Sharing, DMA and Ethernet

cores)

3. System Integration▪ Integrate and evaluate the new optimized system

with a Real-Time Monitoring Interface (being Developed by Achraf)

February 1, 2013 MT2012 10

Graphic LCD

Controller

Master CPUMemory

MasterCPUTimer

GraphicLCDLED

JTAGUART

PPD Module Master Module

LEDController

Avalon Bus

FIR FilterTimer

Slave CPU

MemorySlaveCPU

Filtered Data

Memory

SharedMemory

ECG Data Rom

: Data flow : Control signal

DMAController

EthernetModule

EthernetPHY

TSE MAC

TXSGDMA

DescriptorMemory

The Block Diagram of improved system

February 1, 2013 11MT2012

The Broad layout of N-lead System

February 1, 2013 MT2012 12

PPD module

PPD module

PPD module

PPD module

1-lead

2-lead

3-lead

N-lead

EthernetPHY

Master m

odule,Ethernet m

odule

Graphic LCD

Input Output

Evaluation methodology

• Language: Verilog HDL• Tools: Quartus II, SOPC Builder, and NIOS II IDE• Target device: Stratix III DSP Board (EP3SL150F1152C2)• Target data: 10 sample data

- From MIT-BIH Normal Sinus Rhythm Database

• Evaluation approach- Hardware complexity- Execution time

February 1, 2013 13MT2012

Hardware Complexity

February 1, 2013 MT2012 14

System model

Logic utilizationBlock memory

bitsFmax(MHz)

Power(mW)

Combinational ALUTs

MemoryALUTs

DedicatedLogic

registersTotal

1-lead 12,388 194 15,336 18% 1,368,920(24%) 90.99 696.35

2-lead 20,246 218 25,231 31% 1,971,992(35%) 94.33 730.23

3-lead 28,270 238 35,153 43% 2,575,064(46%) 88.39 766.37

4-lead 36,240 258 45,024 55% 3,178,584(56%) 94.10 792.70

5-lead 44,161 0 54,278 67% 3,783,066(67%) 86.01 814.52

6-lead 52,060 0 64,066 79% 4,386,330(78%) 86.07 826.88

7-lead 66,496 0 82,356 104% 4,972,866(88%) N/A N/A

Execution Time

February 1, 2013 MT2012 15

•The following table shows the average execution time

•10 kinds of sample data is used to calculate that time

•Comparing the execution time of improved system including the feature of DMA transfer to execution time of previous system

Architecture Improved System Previous System

1-lead2-lead3-lead4-lead

Conclusion

• Optimizing hardware part by adding DMA feature to previous system

• Optimizing software to boost performance and meet real-time deadlines (not yet)

• Processing time is decreased by (not yet)- XXX % in improved system

February 1, 2013 MT2012 16

Future Work

• Integrating and evaluating the new improved system with a Real-Time Monitoring Interface

February 1, 2013 MT2012 17

Thank you for listening

February 1, 2013 MT2012 18

19

Period detection

Peaks detection

Reading data

Derivation

Autocorrelation

Find interval

Extraction of max point

Store results

Discrimination

• Based on autocorrelation approach

Background (3/5) : PPD Algorithm

February 1, 2013 MT2012

Research Schedule

February 1, 2013 MT2012 20

Task Date Status

Investigating DMA transfer ○

Investigating how to transfer data using Ethernet ○

Minor modification of software November, 2012 ○

Adding DMA controller ~ December, 2012 ×

Adding Ethernet module ~December, 2012 ×

Modification of software ~ January, 2012 ×

Performance evaluation ~ January, 2012 ×

Writing thesis ~ January, 2013 ×