tps6281x-q1 2.75-v to 6-v adjustable-frequency step-down converter … · 2021. 5. 20. ·...

TPS6281x-Q1 2.75-V to 6-V Adjustable-Frequency Step-Down Converter

1 Features• AEC-Q100 qualified for automotive applications

– Device temperature grade 1:–40°C to +125°C TA

• Functional Safety-Capable– Documentation available to aid functional safety

system design• Input voltage range: 2.75 V to 6 V• Family of 1 A, 2 A, 3 A and 4 A• Quiescent current 15-µA typical• Output voltage from 0.6 V to 5.5 V• Output voltage accuracy ±1% (PWM operation)• Adjustable soft start• Forced PWM or PWM and PFM operation• Adjustable switching frequency of

1.8 MHz to 4 MHz• Precise ENABLE input allows

– User-defined undervoltage lockout– Exact sequencing

• 100% duty cycle mode• Active output discharge• Spread spectrum clocking - optional• Power good output with window comparator• Package with wettable flanks

2 Applications• Infotainment head unit• Hybrid and reconfigurable cluster• Telematics control unit• Surround view ECU, ADAS sensor fusion• External amplifier

3 DescriptionThe TPS6281x-Q1 is family of pin-to-pin 1-A, 2-A, 3-A, and 4-A synchronous step-down DC/DCconverters. All devices offer high efficiency and easeof use. The TPS6281x-Q1 family is based on apeak current mode control topology. The TPS6281x-Q1 is designed for automotive applications such asinfotainment and advanced driver assistance systems.Low resistive switches allow up to 4-A continuousoutput current at high ambient temperature. Theswitching frequency is externally adjustable from 1.8MHz to 4 MHz and can also be synchronized toan external clock in the same frequency range. InPWM/PFM mode, the TPS6281x-Q1 automaticallyenter Power Save Mode at light loads to maintainhigh efficiency across the whole load range. TheTPS6281x-Q1 provide 1% output voltage accuracyin PWM mode which helps design a power supplywith high output voltage accuracy. The SS/TR pinallows setting the start-up time or forming trackingof the output voltage to an external source. Thisallows external sequencing of different supply railsand limiting the inrush current during start-up.

The TPS6281x-Q1 is available in a 3-mm × 2-mmVQFN package with wettable flanks.

Device InformationPART NUMBER PACKAGE(1) BODY SIZE (NOM)TPS62810-Q1

VQFN 3 mm × 2 mmTPS62811-Q1

TPS62812-Q1

TPS62813-Q1

(1) For all available packages, see the orderable addendum atthe end of the data sheet.

L

0.47 Hm

MODE/SYNC

SW

FB

VIN

VIN

2.75 V - V6

CIN

22 mF

COUT

2 x 22 Fm

+ 10 Fm

TPS62810-Q1

EN

R1

VOUT

R2

GND

PG

SS/TR

COMP/FSET

RC

F CSS

R3

CFF

Simplified SchematicOutput Current (A)

Eff

icie

ncy

(%

)

50

55

60

65

70

75

80

85

90

95

100

100P 1m 10m 100m 1 4

D002

VIN = 4.0 VVIN = 5.0 VVIN = 6.0 V

Efficiency vs Output Current; VOUT = 3.3 V; PWM/PFM; fS = 2.25 MHz

www.ti.comTPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1

SLVSDU1H – AUGUST 2018 – REVISED APRIL 2021

Copyright © 2021 Texas Instruments Incorporated Submit Document Feedback 1

Product Folder Links: TPS62810-Q1 TPS62811-Q1 TPS62812-Q1 TPS62813-Q1

TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1SLVSDU1H – AUGUST 2018 – REVISED APRIL 2021

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,intellectual property matters and other important disclaimers. PRODUCTION DATA.

https://www.ti.com/technologies/functional-safety/overview.html

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http://www.ti.com/applications/automotive/infotainment-cluster/overview.html

http://www.ti.com/solution/automotive-telematics-control-unit

http://www.ti.com/solution/surround-view-system-ecu

http://www.ti.com/applications/automotive/adas/overview.html

http://www.ti.com/solution/automotive-external-amplifier

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Table of Contents1 Features............................................................................12 Applications..................................................................... 13 Description.......................................................................14 Revision History.............................................................. 25 Device Comparison Table...............................................46 Pin Configuration and Functions...................................57 Specifications.................................................................. 6

7.1 Absolute Maximum Ratings ....................................... 67.2 ESD Ratings .............................................................. 67.3 Recommended Operating Conditions ........................67.4 Thermal Information ...................................................67.5 Electrical Characteristics ............................................77.6 Typical Characteristics................................................ 9

8 Parameter Measurement Information.......................... 108.1 Schematic................................................................. 10

9 Detailed Description......................................................129.1 Overview................................................................... 129.2 Functional Block Diagram......................................... 129.3 Feature Description...................................................13

9.4 Device Functional Modes..........................................1510 Application and Implementation................................ 18

10.1 Application Information........................................... 1810.2 Typical Application.................................................. 2010.3 System Examples................................................... 31

11 Power Supply Recommendations..............................3412 Layout...........................................................................35

12.1 Layout Guidelines................................................... 3512.2 Layout Example...................................................... 35

13 Device and Documentation Support..........................3613.1 Device Support....................................................... 3613.2 Documentation Support.......................................... 3613.3 Receiving Notification of Documentation Updates..3613.4 Support Resources................................................. 3613.5 Trademarks.............................................................3613.6 Electrostatic Discharge Caution..............................3613.7 Glossary..................................................................36

14 Mechanical, Packaging, and OrderableInformation.................................................................... 36

4 Revision HistoryNOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision G (March 2021) to Revision H (April 2021) Page• Added device version to Device Comparison Table .......................................................................................... 4

Changes from Revision F (November 2020) to Revision G (March 2021) Page• Added new voltage spins to Device Comparison Table .....................................................................................4• Added feedback voltage for fixed voltage version TPS6281326........................................................................ 7• Added feedback voltage for fixed voltage version TPS628100M....................................................................... 7

Changes from Revision E (April 2020) to Revision F (November 2020) Page• Updated the numbering format for tables, figures and cross-references throughout the document. .................1• Added functional safety bullet ............................................................................................................................1• Added new voltage spins to Device Comparison Table .....................................................................................4• Added feedback voltage for fixed voltage version TPS6281126........................................................................ 7• Added feedback voltage for fixed voltage version TPS6281228........................................................................ 7• Added feedback voltage for fixed voltage version TPS6281109........................................................................ 7• Added feedback voltage for fixed voltage version TPS628132D........................................................................7• Added feedback voltage for fixed voltage version TPS628132M....................................................................... 7• Added feedback voltage for fixed voltage version TPS628113H........................................................................7

Changes from Revision D (December 2019) to Revision E (April 2020) Page• Added TPS628122GQWRWYRQ1 into Device Comparison Table ...................................................................4• Added feedback voltage for fixed voltage version TPS628122G....................................................................... 7

Changes from Revision C (August 2019) to Revision D (December 2019) Page• Added Functional safety capable information and link ...................................................................................... 1• Added new voltage spins to Device Comparison Table .....................................................................................4• Changed duty cycle for external synchronization to allow a wider range........................................................... 7• Added feedback voltage for fixed voltage versions TPS6281206, TPS628110A, TPS628112A, TPS6281008,

TPS628112M, TPS628120M ............................................................................................................................. 7

TPS62810-Q1, TPS62811-Q1, TPS62812-Q1, TPS62813-Q1SLVSDU1H – AUGUST 2018 – REVISED APRIL 2021 www.ti.com

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• Changed description for Power Save Mode Operation.................................................................................... 15

Changes from Revision B (June 2019) to Revision C (December 2019) Page• Changed marketing status from Advance Information to initial release for the TPS62811-Q1 and TPS62812-

Q1....................................................................................................................................................................... 1• Changed Test Condition for Tracking Gain.........................................................................................................7• Changed Test Condition for Tracking Offset....................................................................................................... 7• Added feedback voltage for fixed voltage version TPS6281208........................................................................ 7• Added FB input current for fixed voltage versions.............................................................................................. 7• Added feedback voltage accuracy for fixed voltage versions............................................................................. 7• Deleted Preview label for Systems Example ................................................................................................... 31

Changes from Revision A (March 2019) to Revision B (June 2019) Page• Changed marketing status from Advance Information to initial release for the TPS62810-Q1 and TPS62813-

Q1....................................................................................................................................................................... 1• Changed parameter name from RFSET to RCF ..................................................................................................6• Changed minimum value for UVLO threshold for falling input voltage ............................................................. 7• Deleted high-side MOSFET leakage current at TJ = 85°C................................................................................. 7• Deleted low-side MOSFET leakage current at TJ = 85°C...................................................................................7• Changed max value for high-side MOSFET current limit of TPS62810 and TPS62813.................................... 7• Changed min / max value for high-side MOSFET current limit of TPS62812 and TPS62811...........................7• Changed min / max value for switching frequency tolerance for fS = 1.8 MHz to 4 MHz...................................7• Changed min / max value for feedback voltage accuracy with voltage tracking................................................7• Deleted start-up delay time for VIn ≥ 3.1 V........................................................................................................7

Changes from Revision * (August 2018) to Revision A (March 2019) Page• Added planned device spins to Device Comparison Table ................................................................................4• Changed max inductance in Recommended Operating Conditions for the frequency range up to 3.5 MHz .... 6• Changed max inductance in Recommended Operating Conditions for the frequency range above 3.5 MHz....6• Deleted min/max value for Thermal Shutdown Temperature .............................................................................7• Changed max value for high-side MOSFET leakage current at TJ = 85°C .......................................................7• Changed max value for high-side MOSFET leakage current............................................................................. 7• Changed ax value for Low-Side MOSFET leakage current at TJ = 85°C........................................................... 7• Changed max value for low-side MOSFET leakage current...............................................................................7• Added Added spec for SW leakage...................................................................................................................7• Changed min / max value for PWM switching frequency tolerance for fS = 3 MHz to 4 MHz.............................7• Changed Changed load regulation from 0.025%/V to 0.05%/V.........................................................................7• Changed equation for compensation setting 2 ................................................................................................ 13• Changed RCF range for comp setting 2 in Table 9-1 ........................................................................................13• Changed RCF range for comp setting 2 in Table 9-2 ........................................................................................13• Changed CFF from 22 pF to 10 pF in Table 10-2 and all schematics ...............................................................20





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5 Device Comparison TableDEVICE NUMBER OUTPUT

CURRENTVout

DISCHARGEFOLDBACK

CURRENT LIMITSPREAD SPECTRUM

CLOCKING (SSC)OUTPUT VOLTAGE

TPS62811QWRWYRQ1 1 A ON OFF OFF adjustable

TPS6281120QWRWYRQ1 1 A ON OFF ON adjustable

TPS6281126QWRWYRQ1 1 A ON OFF ON fixed 1.0 V

TPS6281109QWRWYRQ1 1 A ON OFF OFF fixed 1.15 V

TPS628110AQWRWYRQ1 1 A ON OFF OFF fixed 1.2 V

TPS628112AQWRWYRQ1 1 A ON OFF ON fixed 1.2 V

TPS628112MQWRWYRQ1 1 A ON OFF ON fixed 1.8 V

TPS628113HQWRWYRQ1 1 A ON OFF ON fixed 3.3 V






TPS628122GQWRWYRQ1 2 A ON OFF ON fixed 1.5 V

TPS628120MQWRWYRQ1 2 A ON OFF OFF fixed 1.8 V




TPS628132DQWRWYRQ1 3 A ON OFF ON fixed 1.35 V

TPS628132MQWRWYRQ1 3 A ON OFF ON fixed 1.8 V




TPS628100MQWRWYRQ1 4 A ON OFF OFF fixed 1.8 V

(1) PREVIEW








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6 Pin Configuration and Functions

PG SS/TRVIN SW GND

54

6

78

9

1 2 3

PG

EN

VINSWGND

5 4

6

7 8

9

123

bottom viewtop view

FB

COMP/FSET

EN

Figure 6-1. RWY Package 9 Pin (VQFN) Top View

Table 6-1. Pin FunctionsPIN

I/O DESCRIPTIONNAME NO.

EN 8 I This is the enable pin of the device. Connect to logic low to disable the device. Pull high toenable the device. Do not leave this pin unconnected.

FB 5 I Voltage feedback input, connect the resistive output voltage divider to this pin. For the fixedvoltage versions, connect the FB pin directly to the output voltage.

GND 4 Ground pin

MODE/SYNC 1 I

The device runs in PFM/PWM mode when this pin is pulled low. If the pin is pulled high, thedevice runs in forced PWM mode. Do not leave this pin unconnected. The mode pin canalso be used to synchronize the device to an external frequency. See the Section 7 for thedetailed specification of the digital signal applied to this pin for external synchronization.

COMP/FSET 7 I

Device compensation and frequency set input. A resistor from this pin to GND definesthe compensation of the control loop as well as the switching frequency if not externallysynchronized. If the pin is tied to GND or VIN, the switching frequency is set to 2.25 MHz.Do not leave this pin unconnected.

PG 9 O Open drain power good output. Low impedance when not "power good", high impedancewhen "power good". This pin can be left open or be tied to GND when not used.

SS/TR 6 ISoft-Start / Tracking pin. A capacitor connected from this pin to GND defines the rise timefor the internal reference voltage. The pin can also be used as an input for tracking andsequencing - see the Section 9.4.7 section.

SW 3 This is the switch pin of the converter and is connected to the internal Power MOSFETs.

VIN 2 Power supply input. Connect the input capacitor as close as possible between pin VIN andGND.





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7 Specifications7.1 Absolute Maximum Ratingsover operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

Pin voltage range(1)

VIN -0.3 6.5 V

SW -0.3 VIN+0.3 V

SW (transient for less than 10 ns)(2) -3 10 V

FB -0.3 4 V

PG, SS/TR, COMP/FSET -0.3 VIN+0.3 V

Pin voltage range(1) EN, MODE/SYNC -0.3 6.5 V

Storage temperature, Tstg -65 150 °C

(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stressratings only, which do not imply functional operation of the device at these or any other conditions beyond those indicated underRecommended Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect devicereliability.

(2) While switching

7.2 ESD RatingsVALUE UNIT

V(ESD) Electrostatic dischargeHuman-body model (HBM), per AEC Q100-002(1) ±2000

VCharged-device model (CDM), per AEC Q100-011 ±750

(1) AEC Q100-002 indicates that HBM stressing shall be in accordance with the ANSI/ESDA/JEDEC JS-001 specification.

7.3 Recommended Operating ConditionsMIN NOM MAX UNIT

VIN Supply voltage range 2.75 6 V

VOUT Output voltage range 0.6 5.5 V

L Effective inductance for a switching frequency of 1.8 MHz to 3.5 MHz 0.32 0.47 0.9 µH

L Effective inductance for a switching frequency of 3.5 MHz to 4 MHz 0.25 0.33 0.9 µH

COUT Effective output capacitance for 1A and 2A version(1) 15 22 470 µF

COUT Effective output capacitance for 3A and 4A version (1) 27 47 470 µF

CIN Effective input capacitance(1) 5 10 µF

RCF 4.5 100 kΩ

TJ Operating junction temperature -40 +150 °C

(1) The values given for the capacitors in the table are effective capacitance, which includes the DC bias effect. Due to the DC biaseffect of ceramic capacitors, the effective capacitance is lower than the nominal value when a voltage is applied. Please check themanufacturer´s DC bias curves for the effective capacitance vs DC voltage applied. Further restrictions may apply. Please see thefeature description for COMP/FSET about the output capacitance vs compensation setting and output voltage.

7.4 Thermal Information

THERMAL METRIC(1)

TPS6281x-Q1

UNITRWY

9 PINS

RθJA Junction-to-ambient thermal resistance 71.1 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 37.2 °C/W

RθJB Junction-to-board thermal resistance 16.4 °C/W

ψJT Junction-to-top characterization parameter 0.9 °C/W

ψJB Junction-to-board characterization parameter 16.1 °C/W








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THERMAL METRIC(1)

TPS6281x-Q1

UNITRWY

9 PINS

RθJC(bot) Junction-to-case (bottom) thermal resistance n/a °C/W

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics applicationreport.

7.5 Electrical Characteristicsover operating junction temperature (TJ = -40 °C to +150 °C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

SUPPLY

IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching,TJ= 125 °C 21 µA

IQ Operating Quiescent Current EN = high, IOUT= 0 mA, Device not switching 15 30 µA

ISD Shutdown Current EN = 0 V, at TJ= 125 °C 18 µA

ISD Shutdown Current EN = 0 V, Nominal value at TJ= 25 °C,Max value at TJ= 150 °C 1.5 26 µA

VUVLOUndervoltage LockoutThreshold

Rising Input Voltage 2.5 2.6 2.75 V

Falling Input Voltage 2.25 2.5 2.6 V

TSD

Thermal ShutdownTemperature Rising Junction Temperature 170

°CThermal Shutdown Hysteresis 15

CONTROL (EN, SS/TR, PG, MODE/SYNC)

VIHHigh Level Input Voltage forMODE/SYNC Pin 1.1 V

VILLow Level Input Voltage forMODE/SYNC Pin 0.3 V

fSYNCFrequency Range on MODE/SYNC Pin for Synchronization

requires a resistor from COMP/FSET to GND, see applicationsection 1.8 4 MHz

Duty Cycle of SynchronizationSignal at MODE/SYNC Pin 20% 50% 80%

Time to Lock to ExternalFrequency 50 µs

VIHInput Threshold Voltage forEN pin; Rising Edge 1.06 1.1 1.15 V

VILInput Threshold Voltage forEN pin; Falling Edge 0.96 1.0 1.05 V

ILKGInput Leakage Current for EN,MODE/SYNC VIH = VIN or VIL= GND 150 nA

Resistance from COMP/FSETto GND for Logic Low internal frequency setting with f = 2.25 MHz 0 2.5 kΩ

voltage on COMP/FSET forlogic high internal frequency setting with f = 2.25 MHz VIN V

VTH_PG

UVP Power Good ThresholdVoltage; dc Level Rising (%VFB) 92% 95% 98%

UVP Power Good ThresholdVoltage; dc Level Falling (%VFB) 87% 90% 93%

OVP Power Good Threshold;dc Level Rising (%VFB) 107% 110% 113%

OVP Power Good Threshold;dc Level Falling (%VFB) 104% 107% 111%

Power Good De-glitch Time for a high level to low level transition on power good 40 µs

VOL_PGPower Good Output LowVoltage IPG = 2 mA 0.07 0.3 V

ILKG_PG Input Leakage Current (PG) VPG = 5 V 100 nA

ISS/TR SS/TR Pin Source Current 2.1 2.5 2.8 µA





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over operating junction temperature (TJ = -40 °C to +150 °C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)


Tracking Gain VFB / VSS/TR for nominal VFB = 0.6 V 1

Tracking Offset feedback voltage with VSS/TR = 0 V for nominal VFB = 0.6 V 17 mV

POWER SWITCH

RDS(ON)High-Side MOSFET ON-Resistance VIN ≥ 5 V 37 60 mΩ

RDS(ON)Low-Side MOSFET ON-Resistance VIN ≥ 5 V 15 35 mΩ

High-Side MOSFET leakagecurrent VIN = 6 V; V(SW) = 0 V 30 µA

Low-Side MOSFET leakagecurrent V(SW) = 6 V 55 µA

SW leakage V(SW) = 0.6 V; current into SW pin -0.025 30 µA

ILIMHHigh-Side MOSFET CurrentLimit dc value, for TPS62810; VIN = 3 V to 6 V 4.8 5.6 6.55 A

ILIMHHigh-Side MOSFET CurrentLimit dc value, for TPS62813; VIN = 3V to 6 V 3.9 4.5 5.25 A



ILIMNEG Negative Valley Current Limit dc value -1.8 A

fSPWM Switching FrequencyRange 1.8 2.25 4 MHz

fSPWM Switching Frequency with COMP/FSET tied to VIN or GND 2.025 2.25 2.475 MHz

PWM Switching FrequencyTolerance

using a resistor from COMP/FSET to GND, fs = 1.8 MHz to 4MHz -19% 18%

ton,min Minimum on-time of HS FET TJ = -40 °C to 125 °C, VIN = 3.3 V 50 75 ns

ton,min Minimum on-time of LS FET VIN = 3.3 V 30 ns

OUTPUT

VFB Feedback Voltage adjustable output voltage versions 0.6 V

VFB Feedback Voltagefixed output voltageTPS6281206, TPS6281126,TPS6281326

1.0 V

VFB Feedback Voltagefixed output voltageTPS6281208, TPS6281008,TPS6281228

1.1 V

VFB Feedback Voltage fixed output voltageTPS6281109 1.15 V

VFB Feedback Voltage fixed output voltageTPS628110A, TPS628112A 1.2 V

VFB Feedback Voltage fixed output voltageTPS628132D 1.35 V

VFB Feedback Voltage fixed output voltageTPS628122G 1.5 V

VFB Feedback Voltage

fixed output voltageTPS628112M, TPS628120M,TPS628132D, TPS628100M,TPS628132M

1.8 V

VFB Feedback VoltageVoltage fixed output voltageTPS628113H 3.3 V

ILKG_FBFB Input Leakage Current forAdjustable Voltage Versions VFB = 0.6 V 1 70 nA

ILKG_FBFB Input Current for FixedVoltage Versions

VFB voltage at target outputvoltage 1 µA

VFB

Feedback Voltage Accuracyfor Adjustable VoltageVersions

VIN ≥ VOUT + 1 V PWM mode -1% 1%








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over operating junction temperature (TJ = -40 °C to +150 °C) and VIN = 2.75 V to 6 V. Typical values at VIN = 5 V and TJ = 25°C. (unless otherwise noted)


VFBFeedback Voltage Accuracyfor Fixed Voltage Versions VIN ≥ VOUT + 1 V PWM mode, Tj = -40°C to

125°C -1% 1%

VFBFeedback Voltage Accuracyfor Fixed Voltage Versions VIN ≥ VOUT + 1 V PWM mode -1% 1.3%

VFB Feedback Voltage Accuracy VIN ≥ VOUT + 1 V;VOUT ≥ 1.5 V

PFM mode;Co,eff ≥ 22 µF,L = 0.47 µH

-1% 2%

VFB Feedback Voltage Accuracy 1 V ≤ VOUT < 1.5 VPFM mode;Co,eff ≥ 47 µF,L = 0.47 µH

-1% 2.5%

VFBFeedback Voltage Accuracywith Voltage Tracking

VIN ≥ VOUT + 1 V;VSS/TR = 0.3 V PWM mode -1% 7%

Load Regulation PWM mode operation 0.05 %/A

Line Regulation PWM mode operation, IOUT= 1 A, VIN ≥ VOUT + 1 V 0.02 %/V

Output Discharge Resistance 50 Ω

tdelay Start-up Delay Time IOUT = 0 mA, Time from EN=high to start switching; VINapplied already 135 250 470 µs

tramp Ramp time; SS/TR Pin Open IOUT = 0 mA, Time from first switching pulse until 95% ofnominal output voltage; device not in current limit 100 150 200 µs

7.6 Typical Characteristics

Junction Temperature (°C)

Rds(

on)

(m:

)

20

24

28

32

36

40

44

48

52

56

60

64

68

72

76

80

-40 125 15025 85

D002

VIN = 2.7VVIN = 3.3VVIN = 4.0VVIN = 5.0VVIN = 6.0V

Figure 7-1. Rds(on) of High-side SwitchJunction Temperature (°C)

Rds(

on)

(m:

)

10

14

18

22

26

30

34

38

42

46

50

-40 125 15025 85

D002

VIN = 2.7VVIN = 3.3VVIN = 4.0VVIN = 5.0VVIN = 6.0V

Figure 7-2. Rds(on) of Low-side Switch





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8 Parameter Measurement Information8.1 Schematic

L

0.47 Hm

MODE/SYNC

SW

FB

VIN

VIN

2.75 V - V6

CIN

22 mF

COUT

2 x 22 Fm

+ 10 Fm

TPS62810-Q1

EN

R1

VOUT

R2

GND

PG

SS/TR

COMP/FSET

RC

F CSS

R3

CFF

Figure 8-1. Measurement Setup for TPS62810-Q1 and TPS62813-Q1

Table 8-1. List of ComponentsREFERENCE DESCRIPTION MANUFACTURER (1)

IC TPS62810-Q1 or TPS62813-Q1 Texas Instruments

L 0.47 µH inductor; XEL4030-471MEB Coilcraft

CIN 22 µF / 10 V; GCM31CR71A226KE02L Murata

COUT2 x 22 µF / 10 V; GCM31CR71A226KE02L+ 1 x 10 µF 6.3 V; GCM188D70J106ME36 Murata

CSS 4.7 nF (equal to 1-ms start-up ramp) Any

RCF 8.06 kΩ Any

CFF 10 pF Any

R1 Depending on VOUT Any


R3 100 kΩ Any

(1) See the Third-party Products Disclaimer.

L

0.47 Hm

MODE/SYNC

SW

FB

VIN

VIN

2.75 V - V6

CIN

22 mF

COUT

1 x 22 Fm

+ 10 Fm

TPS62812-Q1

EN

R1

VOUT

R2

GND

PG

SS/TR

COMP/FSET

RC

F CSS

R3

CFF

Figure 8-2. Measurement Setup for TPS62812-Q1 and TPS62811-Q1








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Table 8-2. List of ComponentsREFERENCE DESCRIPTION MANUFACTURER (1)

IC TPS62812-Q1 or TPS62811-Q1 Texas Instruments

L 0.56-µH inductor; XEL4020-561MEB Coilcraft

CIN 22 µF / 10 V; GCM31CR71A226KE02L Murata

COUT1 x 22 µF / 10 V; GCM31CR71A226KE02L+ 1 x 10 µF 6.3 V; GCM188D70J106ME36 Murata

CSS 4.7 nF (equal to 1-ms start-up ramp) Any

RCF 8.06 kΩ Any

CFF 10 pF Any



R3 100 kΩ Any





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9 Detailed Description9.1 OverviewThe TPS6281x-Q1 synchronous switch mode DC/DC converters are based on a peak current mode controltopology. The control loop is internally compensated. To optimize the bandwidth of the control loop to thewide range of output capacitance that can be used with TPS6281x-Q1, one of three internal compensationsettings can be selected. See Section 9.3.2. The compensation setting is selected either by a resistor fromCOMP/FSET to GND, or by the logic state of this pin. The regulation network achieves fast and stable operationwith small external components and low ESR ceramic output capacitors. The device can be operated withouta feedforward capacitor on the output voltage divider, however, using a typically 10-pF feedforward capacitorimproves transient response.

The devices support forced fixed frequency PWM operation with the MODE pin tied to a logic high level. Thefrequency is defined as either 2.25 MHz internally fixed when COMP/FSET is tied to GND or VIN, or in arange of 1.8 MHz to 4 MHz defined by a resistor from COMP/FSET to GND. Alternatively, the devices canbe synchronized to an external clock signal in a range from 1.8 MHz to 4 MHz, applied to the MODE pinwith no need for additional passive components. External synchronization is only possible if a resistor fromCOMP/FSET to GND is used. If COMP/FSET is directly tied to GND or VIN, the TPS6281x-Q1 cannot besynchronized externally. An internal PLL allows to change from internal clock to external clock during operation.The synchronization to the external clock is done on a falling edge of the clock applied at MODE to therising edge on the SW pin. This allows a roughly 180° phase shift when the SW pin is used to generatethe synchronization signal for a second converter. When the MODE pin is set to a logic low level, the deviceoperates in power save mode (PFM) at low output current and automatically transfers to fixed frequency PWMmode at higher output current. In PFM mode, the switching frequency decreases linearly based on the load tosustain high efficiency down to very low output current.

9.2 Functional Block Diagram

_+

+-

GND

FB

SWVIN

EN

Oscillator

Gate Drive and Control

DeviceControl

PG

ThermalShutdown

BiasRegulator

_+

gm

_+Ipeak Izero

Bandgap

SS/TR

COMP/FSET

MODE








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9.3 Feature Description9.3.1 Precise Enable

The voltage applied at the Enable pin of the TPS6281x-Q1 is compared to a fixed threshold of 1.1 V for a risingvoltage. This allows to drive the pin by a slowly changing voltage and enables the use of an external RC networkto achieve a power-up delay.

The Precise Enable input provides a user-programmable undervoltage lockout by adding a resistor divider to theinput of the Enable pin.

The enable input threshold for a falling edge is typically 100 mV lower than the rising edge threshold. TheTPS6281x-Q1 starts operation when the rising threshold is exceeded. For proper operation, the EN pin must beterminated and must not be left floating. Pulling the EN pin low forces the device into shutdown, with a shutdowncurrent of typically 1 μA. In this mode, the internal high-side and low-side MOSFETs are turned off and the entireinternal control circuitry is switched off.

9.3.2 COMP/FSET

This pin allows to set two different parameters independently:

• Internal compensation settings for the control loop• The switching frequency in PWM mode from 1.8 MHz to 4 MHz

A resistor from COMP/FSET to GND changes the compensation as well as the switching frequency. The changein compensation allows you to adapt the device to different values of output capacitance. The resistor must beplaced close to the pin to keep the parasitic capacitance on the pin to a minimum. The compensation settingis sampled at start-up of the converter, so a change in the resistor during operation only has an effect on theswitching frequency but not on the compensation.

To save external components, the pin can also be directly tied to VIN or GND to set a pre-defined switchingfrequency / compensation. Do not leave the pin floating.

The switching frequency has to be selected based on the input voltage and the output voltage to meet thespecifications for the minimum on-time and minimum off-time.

For example: VIN = 5 V, VOUT = 1 V --> duty cycle (DC) = 1 V / 5 V = 0.2• with ton = DC × T --> ton,min = 1 / fs,max × DC• --> fs,max = 1 / ton,min × DC = 1 / 0.075 µs · 0.2 = 2.67 MHz

The compensation range has to be chosen based on the minimum capacitance used. The capacitance can beincreased from the minimum value as given in Table 9-1 and Table 9-2, up to the maximum of 470 µF in all ofthe three compensation ranges. If the capacitance of an output changes during operation, for example, whenload switches are used to connect or disconnect parts of the circuitry, the compensation has to be chosen for theminimum capacitance on the output. With large output capacitance, the compensation must be done based onthat large capacitance to get the best load transient response. Compensating for large output capacitance butplacing less capacitance on the output can lead to instability.

The switching frequency for the different compensation setting is determined by the following equations.

For compensation (comp) setting 1:

Space

18( )

( )CF

S

MHz kR k

f MHz

× WW =

(1)


Space





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60( )

( )CF

S

MHz kR k

f MHz

× WW =

(2)

Space


Space

180( )

( )CF

S

MHz kR k

f MHz

× WW =

(3)

Table 9-1. Switching Frequency and Compensation for TPS62810-Q1 (4 A) and TPS62813-Q1 (3 A)

COMPENSATION RCF SWITCHING FREQUENCYMINIMUM OUTPUT

CAPACITANCEFOR VOUT < 1 V

MINIMUM OUTPUTCAPACITANCE

FOR 1 V ≤ VOUT < 3.3 V


FOR VOUT ≥ 3.3 V

for smallest outputcapacitance

(comp setting 1)10 kΩ ... 4.5 kΩ 1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)

according to Equation 1 53 µF 32 µF 27 µF

for medium outputcapacitance

(comp setting 2)33 kΩ ... 15 kΩ 1.8 MHz (33 kΩ) ... 4 MHz (15 kΩ)


for large outputcapacitance




(comp setting 1)tied to GND internally fixed 2.25 MHz 53 µF 32 µF 27 µF


(comp setting 3)tied to VIN internally fixed 2.25 MHz 200 µF 120 µF 100 µF

Table 9-2. Switching Frequency and Compensation for TPS62812-Q1 (2 A) and TPS62811-Q1 (1 A)

COMPENSATION RCF SWITCHING FREQUENCYMINIMUM OUTPUT

CAPACITANCEFOR VOUT < 1 V


FOR 1 V ≤ VOUT < 3.3 V


FOR VOUT ≥ 3.3 V


(comp setting 1)10 kΩ ... 4.5 kΩ 1.8 MHz (10 kΩ) ... 4 MHz (4.5 kΩ)


for medium outputcapacitance




(comp setting 3)100 kΩ ... 45 kΩ 1.8MHz (100 kΩ) ...4 MHz (45 kΩ)



(comp setting 1)tied to GND internally fixed 2.25 MHz 30 µF 18 µF 15 µF


(comp setting 3)tied to VIN internally fixed 2.25 MHz 130 µF 80 µF 68 µF

Refer to Section 10.1.3.2 for further details on the output capacitance required depending on the output voltage.

A too high resistor value for RCF is decoded as "tied to VIN", a value below the lowest range is decoded as "tiedto GND". The minimum output capacitance in Table 9-1 and Table 9-2 is for capacitors close to the output of thedevice. If the capacitance is distributed, a lower compensation setting can be required. All values are effectivecapacitance, including all tolerances, aging, dc bias effect, and so forth.

9.3.3 MODE / SYNC

When MODE/SYNC is set low, the device operates in PWM or PFM mode, depending on the output current.The MODE/SYNC pin allows to force PWM mode when set high. The pin also allows you to apply an external








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clock in a frequency range from 1.8 MHz to 4 MHz for external synchronization. Similar to COMP/FSET, thespecifications for the minimum on-time and minimum off-time have to be taken into account when settingthe external frequency. For use with external synchronization on the MODE/SYNC pin, the internal switchingfrequency must be set by RCF to a similar value than the externally applied clock. This ensures a fast settlingto the external clock and, if the external clock fails, the switching frequency stays in the same range and thecompensation settings are still valid. When there is no resistor from COMP/FSET to GND but the pin is pulledhigh or low, external synchronization is not possible.

9.3.4 Spread Spectrum Clocking (SSC)

For device versions with SSC enabled, the switching frequency is randomly changed in PWM mode when theinternal clock is used. The frequency variation is typically between the nominal switching frequency and up to288 kHz above the nominal switching frequency. When the device is externally synchronized by applying a clocksignal to the MODE/SYNC pin, the TPS6281x-Q1 follows the external clock and the internal spread spectrumblock is turned off. SSC is also disabled during soft start.

9.3.5 Undervoltage Lockout (UVLO)

If the input voltage drops, the undervoltage lockout prevents mis-operation of the device by switching off boththe power FETs. The device is fully operational for voltages above the rising UVLO threshold and turns off if theinput voltage trips below the threshold for a falling supply voltage.

9.3.6 Power Good Output (PG)

Power good is an open-drain output driven by a window comparator. PG is held low when the device is disabled,in undervoltage lockout, and in thermal shutdown. When the output voltage is in regulation hence, within thewindow defined in the electrical characteristics, the output is high impedance.

Table 9-3. PG StatusEN DEVICE STATUS PG STATEX VIN < 2 V undefined

low VIN ≥ 2 V low

high 2 V ≤ VIN ≤ UVLO OR in thermal shutdown OR VOUT not in regulation low

high VOUT in regulation high impedance

9.3.7 Thermal Shutdown

The junction temperature (TJ) of the device is monitored by an internal temperature sensor. If TJ exceeds 170°C(typ), the device goes into thermal shutdown. Both the high-side and low-side power FETs are turned off andPG goes low. When TJ decreases by the hysteresis amount of typically 15°C, the converter resumes normaloperation, beginning with soft start. During a PFM pause, the thermal shutdown is not active. After a PFM pause,the device needs up to 9 µs to detect a too high junction temperature. If the PFM burst is shorter than this delay,the device does not detect a too high junction temperature.

9.4 Device Functional Modes9.4.1 Pulse Width Modulation (PWM) Operation

TPS6281x-Q1 has two operating modes: Forced PWM mode (discussed in this section) and PWM/PFM(discussed in Section 9.4.2).

With the MODE/SYNC pin set to high, the TPS6281x-Q1 operates with pulse width modulation in continuousconduction mode (CCM). The switching frequency is either defined by a resistor from the COMP pin to GND orby an external clock signal applied to the MODE/SYNC pin. With an external clock is applied to MODE/SYNC,the TPS6281x-Q1 follows the frequency applied to the pin. To maintain regulation, the frequency needs to be ina range the TPS6281x-Q1 can operate at, taking the minimum on-time into account.

9.4.2 Power Save Mode Operation (PWM/PFM)

When the MODE/SYNC pin is low, power save mode is allowed. The device operates in PWM mode as longas the peak inductor current is above the PFM threshold of about 1.2 A. When the peak inductor current





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drops below the PFM threshold, the device starts to skip switching pulses. In power save mode, the switchingfrequency decreases with the load current maintaining high efficiency.

9.4.3 100% Duty-Cycle Operation

The duty cycle of a buck converter operated in PWM mode is given as D = VOUT / VIN. The duty cycleincreases as the input voltage comes close to the output voltage and the off-time gets smaller. When theminimum off-time of typically 30 ns is reached, the TPS6281x-Q1 skips switching cycles while it approaches100% mode. In 100% mode, it keeps the high-side switch on continuously. The high-side switch stays turnedon as long as the output voltage is below the target. In 100% mode, the low-side switch is turned off. Themaximum dropout voltage in 100% mode is the product of the on-resistance of the high-side switch plus theseries resistance of the inductor and the load current.

9.4.4 Current Limit and Short Circuit Protection

The TPS6281x-Q1 is protected against overload and short circuit events. If the inductor current exceeds thecurrent limit ILIMH, the high-side switch is turned off and the low-side switch is turned on to ramp down theinductor current. The high-side switch turns on again only if the current in the low-side switch has decreasedbelow the low-side current limit. Due to internal propagation delay, the actual current can exceed the staticcurrent limit. The dynamic current limit is given as:

( )L

peak typ LIMH PDV

I I tL

= + ×

(4)

where

• ILIMH is the static current limit as specified in the electrical characteristics• L is the effective inductance at the peak current• VL is the voltage across the inductor (VIN - VOUT)• tPD is the internal propagation delay of typically 50 ns

The current limit can exceed static values, especially if the input voltage is high and very small inductances areused. The dynamic high-side switch peak current can be calculated as follows:

( ) 50IN OUT

peak typ LIMHV V

I I nsL

-= + ×

(5)

9.4.5 Foldback Current Limit and Short Circuit Protection

This is valid for devices where foldback current limit is enabled.

When the device detects current limit for more than 1024 subsequent switching cycles, it reduces the currentlimit from its nominal value to typically 1.8 A. Foldback current limit is left when the current limit indication goesaway. For the case that device operation continues in current limit, it would, after 3072 switching cycles, try againfull current limit for again 1024 switching cycles.

9.4.6 Output Discharge

The purpose of the discharge function is to ensure a defined down-ramp of the output voltage when the deviceis being disabled but also to keep the output voltage close to 0 V when the device is off. The output dischargefeature is only active once TPS6281x-Q1 has been enabled at least once since the supply voltage was applied.The discharge function is enabled as soon as the device is disabled, in thermal shutdown, or in undervoltagelockout. The minimum supply voltage required for the discharge function to remain active typically is 2 V. Outputdischarge is not activated during a current limit or foldback current limit event.

9.4.7 Soft Start / Tracking (SS/TR)

The internal soft-start circuitry controls the output voltage slope during start-up. This avoids excessive inrushcurrent and ensures a controlled output voltage rise time. It also prevents unwanted voltage drops from highimpedance power sources or batteries. When EN is set high to start operation, the device starts switching after








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a delay of about 200 μs then the internal reference and hence VOUT rises with a slope controlled by an externalcapacitor connected to the SS/TR pin.

Leaving the SS/TR pin un-connected provides the fastest startup ramp with 150 µs typically. A capacitorconnected from SS/TR to GND is charged with 2.5 µA by an internal current source during soft start until itreaches the reference voltage of 0.6 V. The capacitance required to set a certain ramp-time (tramp) therefore is:

(6)

If the device is set to shutdown (EN = GND), undervoltage lockout, or thermal shutdown, an internal resistorpulls the SS/TR pin to GND to ensure a proper low level. Returning from those states causes a new start-upsequence.

A voltage applied at SS/TR can be used to track a master voltage. The output voltage follows this voltage in bothdirections up and down in forced PWM mode. In PFM mode, the output voltage decreases based on the loadcurrent. The SS/TR pin must not be connected to the SS/TR pin of other devices. An external voltage applied onSS/TR is internally clamped to the feedback voltage (0.6 V). It is recommended to set the target for the externalvoltage on SS/TR slightly above the feedback voltage. Given the tolerances of the resistor divider R5 and R6 onSS/TR, this ensures the device "switches" to the internal reference voltage when the power-up sequencing isfinished. See Figure 10-58.





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10 Application and ImplementationNote

Information in the following applications sections is not part of the TI component specification, andTI does not warrant its accuracy or completeness. TI’s customers are responsible for determiningsuitability of components for their purposes. Customers should validate and test their designimplementation to confirm system functionality.

10.1 Application Information10.1.1 Programming the Output Voltage

The output voltage of the TPS6281x-Q1 is adjustable. It can be programmed for output voltages from 0.6 V to5.5 V using a resistor divider from VOUT to GND. The voltage at the FB pin is regulated to 600 mV. The valueof the output voltage is set by the selection of the resistor divider from Equation 7. It is recommended to chooseresistor values which allow a current of at least 2 µA, meaning the value of R2 must not exceed 400 kΩ. Lowerresistor values are recommended for highest accuracy and most robust design.

1 2 1OUT

FB

VR R

V×æ ö

= -ç ÷è ø (7)

10.1.2 External Component Selection10.1.2.1 Inductor Selection

The TPS6281x-Q1 is designed for a nominal 0.47-µH inductor with a switching frequency of typically 2.25 MHz.Larger values can be used to achieve a lower inductor current ripple but they can have a negative impact onefficiency and transient response. Smaller values than 0.47 µH cause a larger inductor current ripple whichcauses larger negative inductor current in forced PWM mode at low or no output current. For a higher or lowernominal switching frequency, the inductance must be changed accordingly. See Section 7.3 for details.

The inductor selection is affected by several effects like inductor ripple current, output ripple voltage, PWM-to-PFM transition point, and efficiency. In addition, the inductor selected has to be rated for appropriate saturationcurrent and DC resistance (DCR). Equation 8 calculates the maximum inductor current.

2

(max)

(max)(max)

L

OUTL

III

D+=

(8)

(max)

11

min

OUTOUT

INL

SW

VV

VI

L f

×æ ö

-ç ÷è øD = ×

(9)

where

• IL(max) is the maximum inductor current• ΔIL(max) is the peak-to-peak inductor ripple current• Lmin is the minimum inductance at the operating point

Table 10-1. Typical Inductors

TYPE INDUCTANCE[µH]

CURRENT [A](1) FOR DEVICE

NOMINALSWITCHINGFREQUENCY

DIMENSIONS[LxBxH] mm MANUFACTURER(2)

XFL4015-471ME 0.47 µH, ±20% 3.5 TPS62813-Q1 / 12-Q1 2.25 MHz 4 x 4 x 1.6 Coilcraft

XEL4020-561ME 0.56 µH, ±20% 9.9 TPS62810-Q1 / 13-Q1 /12-Q1 2.25 MHz 4 x 4 x 2.1 Coilcraft

XEL4030-471ME 0.47 µH, ±20% 12.3 TPS62810-Q1 / 13-Q1 /12-Q1 2.25 MHz 4 x 4 x 3.1 Coilcraft








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Table 10-1. Typical Inductors (continued)

TYPE INDUCTANCE[µH]

CURRENT [A](1) FOR DEVICE

NOMINALSWITCHINGFREQUENCY

DIMENSIONS[LxBxH] mm MANUFACTURER(2)

XEL3515-561ME 0.56 µH, ±20% 4.5 TPS62813-Q1 / 12-Q1 2.25 MHz 3.5 x 3.2 x 1.5 Coilcraft

XFL3012-331MEB 0.33 µH, ±20% 2.6 TPS62811-Q1 / 12-Q1 ≥ 3.5 MHz 3 x 3 x 1.3 Coilcraft

XPL2010-681ML 0.68 µH, ±20% 1.5 TPS62811-Q1 2.25 MHz 2 x 1.9 x 1 Coilcraft

DFE252012PD-R47M 0.47 µH, ±20% see data sheet TPS62813-Q1 / 12-Q1 /11-Q1 2.25 MHz 2.5 x 2 x 1.2 Murata

(1) Lower of IRMS at 20°C rise or ISAT at 20% drop.(2) See the Third-party Products Disclaimer.

Calculating the maximum inductor current using the actual operating conditions gives the minimum saturationcurrent of the inductor needed. A margin of about 20% is recommended to add. A larger inductor value is alsouseful to get lower ripple current, but increases the transient response time and size as well.

10.1.3 Capacitor Selection10.1.3.1 Input Capacitor

For most applications, 22 µF nominal is sufficient and is recommended. The input capacitor buffers the inputvoltage for transient events and also decouples the converter from the supply. A low-ESR multilayer ceramiccapacitor (MLCC) is recommended for best filtering and must be placed between VIN and GND as close aspossible to those pins.

10.1.3.2 Output Capacitor

The architecture of the TPS6281x-Q1 allows the use of tiny ceramic output capacitors with low equivalent seriesresistance (ESR). These capacitors provide low output voltage ripple and are recommended. To keep its lowresistance up to high frequencies and to get narrow capacitance variation with temperature, it is recommendedto use dielectric X7R, X7T, or an equivalent. Using a higher value has advantages like smaller voltage ripple anda tighter DC output accuracy in power save mode. By changing the device compensation with a resistor fromCOMP/FSET to GND, the device can be compensated in three steps based on the minimum capacitance usedon the output. The maximum capacitance is 470 µF in any of the compensation settings.

The minimum capacitance required on the output depends on the compensation setting as well as on the currentrating of the device. TPS62810-Q1 and TPS62813-Q1 require a minimum output capacitance of 27 µF whilethe lower current versions TPS62812-Q1 and TPS62811-Q1 require 15 µF at minimum. The required outputcapacitance also changes with the output voltage.

For output voltages below 1 V, the minimum increases linearly from 32 µF at 1 V to 53 µF at 0.6 V forthe TPS62810-Q1, the TPS62813-Q1 with the compensation setting for smallest output capacitance. Othercompensation ranges, ranges for TPS62811-Q1 and TPS62812-Q1, or both are equivalent. See Table 9-1 andTable 9-2 for details.





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10.2 Typical ApplicationL

0.47 Hm

MODE/SYNC

SW

FB

VIN

VIN

2.75 V - V6

CIN

22 mF

COUT

2 x 22 Fm

+ 10 Fm

TPS62810-Q1

EN

R1

VOUT

R2

GND

PG

SS/TR

COMP/FSETR

CF C

SS

R3

CFF

Figure 10-1. Typical Application

10.2.1 Design Requirements

The design guidelines provide a component selection to operate the device within the recommended operatingconditions.

10.2.2 Detailed Design Procedure

1 2 1OUT

FB

VR R

V×æ ö

= -ç ÷è ø (10)

With VFB = 0.6 V:

Table 10-2. Setting the Output VoltageNOMINAL OUTPUT VOLTAGE

VOUTR1 R2 CFF EXACT OUTPUT VOLTAGE

0.8 V 16.9 kΩ 51 kΩ 10 pF 0.7988 V

1.0 V 20 kΩ 30 kΩ 10 pF 1.0 V

1.1 V 39.2 kΩ 47 kΩ 10 pF 1.101 V

1.2 V 68 kΩ 68 kΩ 10 pF 1.2 V

1.5 V 76.8 kΩ 51 kΩ 10 pF 1.5 V

1.8 V 80.6 kΩ 40.2 kΩ 10 pF 1.803 V

2.5 V 47.5 kΩ 15 kΩ 10 pF 2.5 V

3.3 V 88.7 kΩ 19.6 kΩ 10 pF 3.315 V








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10.2.3 Application Curves

All plots have been taken with a nominal switching frequency of 2.25 MHz when set to PWM mode, unlessotherwise noted. The BOM is according to Table 8-1.

Output Current (A)

Eff

icie

ncy

(%

)

50

55

60

65

70

75

80

85

90

95

100

100P 1m 10m 100m 1 4

D002

VIN = 4.0 VVIN = 5.0 VVIN = 6.0 V

VOUT = 3.3 V PFM TA = 25°C

Figure 10-2. Efficiency versus Output Current

Output Current (A)

Effic

iency

(%

)

70

75

80

85

90

95

100

1 40 2 3

D002

VIN = 4.0 VVIN = 5.0 VVIN = 6.0 V

VOUT = 3.3 V PWM TA = 25°C


Output Current (A)

Effic

iency

(%

)

50

55

60

65

70

75

80

85

90

95

100

100P 1m 10m 100m 1 4

D002

VIN = 2.7 VVIN = 3.3 VVIN = 4.0 VVIN = 5.0 VVIN = 6.0 V



Output Current (A)

Effic

iency

(%

)

60

65

70

75

80

85

90

95

100

1 40 2 3

D002




Output Current (A)

Eff

icie

ncy

(%

)

50

55

60

65

70

75

80

85

90

95

100

100P 1m 10m 100m 1 4

D002




Output Current (A)

Effic

iency

(%

)

70

75

80

85

90

95

100

1 40 2 3

D002








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Output Current (A)

Eff

icie

ncy

(%

)

50

55

60

65

70

75

80

85

90

95

100

100P 1m 10m 100m 1 4

D002




Output Current (A)

Eff

icie

ncy

(%

)

60

65

70

75

80

85

90

95

100

1 40 2 3

D002




Output Current (A)

Effic

iency

(%

)

50

55

60

65

70

75

80

85

90

100P 1m 10m 100m 1 4

D002

VIN = 2.7 VVIN = 3.3 VVIN = 4.0 V



Output Current (A)

Effic

iency

(%

)

50

55

60

65

70

75

80

85

90

1 40 2 3

D002

VIN = 2.7 VVIN = 3.3 VVIN = 4.0 V



Output Current (A)

Outp

ut V

olta

ge (

V)

3,27

3,275

3,28

3,285

3,29

3,295

3,3

3,305

3,31

3,315

3,32

100P 1m 10m 100m 1 4

D002

VIN = 4.0 VVIN = 5.0 VVIN = 6.0 V


Figure 10-12. Output Voltage versus OutputCurrent

Output Current (A)

Outp

ut V

olta

ge (

V)

3,276

3,28

3,284

3,288

3,292

3,296

3,3

3,304

3,308

3,312

3,316

3,32

100P 1m 10m 100m 1 4

D002

VIN = 4.0 VVIN = 5.0 VVIN = 6.0 V










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Output Current (A)

Outp

ut V

olta

ge (

V)

1,78

1,784

1,788

1,792

1,796

1,8

1,804

1,808

1,812

1,816

1,82

100P 1m 10m 100m 1 4

D002




Output Current (A)

Outp

ut V

olta

ge (

V)

1,78

1,784

1,788

1,792

1,796

1,8

1,804

1,808

1,812

1,816

1,82

100P 1m 10m 100m 1 4

D002




Output Current (A)

Outp

ut

Volta

ge (

V)

1,1875

1,19

1,1925

1,195

1,1975

1,2

1,2025

1,205

1,2075

1,21

1,2125

100P 1m 10m 100m 1 4

D002




Output Current (A)

Outp

ut

Volta

ge (

V)

1,1875

1,19

1,1925

1,195

1,1975

1,2

1,2025

1,205

1,2075

1,21

1,2125

100P 1m 10m 100m 1 4

D002




Output Current (A)

Outp

ut V

olta

ge (

V)

0,99

0,992

0,994

0,996

0,998

1

1,002

1,004

1,006

1,008

1,01

100P 1m 10m 100m 1 4

D002




Output Current (A)

Outp

ut V

olta

ge (

V)

0,99

0,992

0,994

0,996

0,998

1

1,002

1,004

1,006

1,008

1,01

100P 1m 10m 100m 1 4

D002








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Output Current (A)

Outp

ut V

olta

ge (

V)

0,594

0,596

0,598

0,6

0,602

0,604

0,606

0,608

0,61

0,612

100P 1m 10m 100m 1 4

D002

VIN = 2.7 VVIN = 3.3 VVIN = 4.0 V



Output Current (A)

Outp

ut

Volta

ge (

V)

0,594

0,5955

0,597

0,5985

0,6

0,6015

0,603

0,6045

0,606

100P 1m 10m 100m 1 4

D002

VIN = 2.7 VVIN = 3.3 VVIN = 4.0 VVIN = 5.0 V




VIN = 5.0 V IOUT = 0.4 A to 3.6 A to 0.4 A

Figure 10-22. Load Transient Response

















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IOUT = 0.5 A VIN = 4.5 V to 5.5 V to 4.5 V

Figure 10-32. Line Transient Response


IOUT = 4 A VIN = 4.5 V to 5.5 V to 4.5 V





















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IOUT = 0.5 A VIN = 5.0 V BW = 20 MHz

Figure 10-42. Output Voltage Ripple


IOUT = 4 A VIN = 5.0 V BW = 20 MHz






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IOUT = 0.5 A VIN = 5.0 V BW = 20 MHz






IOUT = 0.5 A VIN = 5.0 V BW = 20 MHz






IOUT = 0.5 A VIN = 5.0 V BW = 20 MHz












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IOUT = 0.5 A VIN = 3.3 V BW = 20 MHz






IOUT = 4 A VIN = 5 V CSS = 4.7 nF

Figure 10-52. Start-Up Timing














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IOUT = 4 A VIN = 3.3 V CSS = 4.7 nF

Figure 10-56. Start-up Timing








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10.3 System Examples10.3.1 Fixed Output Voltage Versions

Versions with an internally fixed output voltage allow you to remove the external feedback voltage divider. Thisnot only allows you to reduce the total solution size but also provides higher accuracy as there is no additionalerror caused by the external resistor divider. The FB pin needs to be tied to the output voltage directly as shownin Figure 10-57. Independent of that, the application shown runs with an internally defined switching frequency of2.25 MHz by connecting COMP/FSET to GND.

L

0.56 Hm

MODE/SYNC

SW

FB

VIN

VIN

2.75 V - V6

CIN

22 mF

COUT

1 x 22 Fm

+ 10 Fm

TPS62812x-Q1

EN

VOUT

GND

PG

SS/TR

COMP/FSET

CSS

R3

Figure 10-57. Schematic for Fixed Output Voltage Versions

10.3.2 Voltage Tracking

The TPS6281x-Q1 follows the voltage applied to the SS/TR pin. A voltage ramp on SS/TR to 0.6 V ramps theoutput voltage according to the 0.6 V feedback voltage.

Tracking the 3.3 V of device 1, such that both rails reach their target voltage at the same time, requires a resistordivider on SS/TR of device 2 equal to the output voltage divider of device 1. The output current of 2.5 µA onthe SS/TR pin causes an offset voltage on the resistor divider formed by R5 and R6. The equivalent resistanceof R5 // R6, so it must be kept below 15 kΩ. The current from SS/TR causes a slightly higher voltage across R6than 0.6 V, which is desired because device 2 switches to its internal reference as soon as the voltage at SS/TRis higher than 0.6 V.

In case both devices need to run in forced PWM mode, it is recommended to tie the MODE pin of device 2 tothe output voltage or the power good signal of device 1, the master device. The TPS6281x-Q1 has a duty cyclelimitation defined by the minimum on-time. For tracking down to low output voltages, device 2 cannot follow oncethe minimum duty cycle is reached. Enabling PFM mode while tracking is in progress allows you to ramp downthe output voltage close to 0 V.





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L

0.47 Hm

MODE/SYNC

SW

FB

VIN

VIN

2.75 V - V6

CIN

22 mF

COUT

47 Fm

TPS62810-Q1

EN

3.3 V

GND

PG

SS/TR

COMP/FSET

8.0

6 k

W4.7 nF

10 pF

L

0.47 Hm

MODE/SYNC

SW

FB

VIN

CIN

22 mF

COUT

47 Fm

TPS62810-Q1

ENR5

1.8 V

R6

GND

PG

SS/TR

COMP/FSET

10 pF

8.0

6 k

W

4.2

2 k

W19.6

kW

Device 1 (master)

Device 2 (slave)

57.6

kW

12.7

kW

80.6

kW

40.2

kW

EN

Figure 10-58. Schematic for Output Voltage Tracking

Figure 10-59. Scope Plot for Output Voltage Tracking

10.3.3 Synchronizing to an External Clock

The TPS6281x-Q1 can be externally synchronized by applying an external clock on the MODE/SYNC pin.There is no need for any additional circuitry as long as the input signal meets the requirements given in theelectrical specifications. The clock can be applied / removed during operation, allowing you to switch from anexternally-defined fixed frequency to power-save mode or to internal fixed frequency operation. The value of theRCF resistor must be chosen so that the internally defined frequency and the externally applied frequency areclose to each other. This ensures a smooth transition from internal to external frequency and vice versa.








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L

0.47 Hm

MODE/SYNC

SW

FB

VIN

VIN

2.75 V - V6

CIN

22 mF

COUT

47 Fm

TPS62810-Q1

EN

R1

VOUT

R2

GND

PG

SS/TR

COMP/FSETR

CF C

SS

R3

CFF

fEXT

Figure 10-60. Schematic Using External Synchronization

VIN = 5 V RCF = 8.06 kΩ IOUT = 0.1 A

VOUT = 1.8 V fEXT = 2.5 MHz

Figure 10-61. Switching from ExternalSynchronization to Power-Save Mode (PFM)

VIN = 5 V RCF = 8.06 kΩ IOUT = 1 A

VOUT = 1.8 V fEXT = 2.5 MHz

Figure 10-62. Switching from ExternalSynchronization to Internal Fixed Frequency





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11 Power Supply RecommendationsThe TPS6281x-Q1 device family has no special requirements for its input power supply. The output current ofthe input power supply needs to be rated according to the supply voltage, output voltage, and output current ofthe TPS6281x-Q1.








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12 Layout12.1 Layout GuidelinesA proper layout is critical for the operation of a switched mode power supply, even more at high switchingfrequencies. Therefore, the PCB layout of the TPS6281x-Q1 demands careful attention to ensure operation andto get the performance specified. A poor layout can lead to issues like poor regulation (both line and load),stability and accuracy weaknesses increased EMI radiation and noise sensitivity.

See Section 12.2 for the recommended layout of the TPS6281x-Q1, which is designed for common externalground connections. The input capacitor must be placed as close as possible between the VIN and GND pin.

Provide low inductive and resistive paths for loops with high di/dt. Therefore, paths conducting the switched loadcurrent must be as short and wide as possible. Provide low capacitive paths (with respect to all other nodes) forwires with high dv/dt. Therefore, the input and output capacitance must be placed as close as possible to the ICpins and parallel wiring over long distances as well as narrow traces must be avoided. Loops that conduct analternating current must outline an area as small as possible, as this area is proportional to the energy radiated.

Sensitive nodes like FB need to be connected with short wires and not nearby high dv/dt signals (for exampleSW). Since they carry information about the output voltage, they must be connected as close as possible to theactual output voltage (at the output capacitor). The capacitor on the SS/TR pin as well as the FB resistors, R1and R2, must be kept close to the IC and connect directly to those pins and the system ground plane.

The package uses the pins for power dissipation. Thermal vias on the VIN and GND pins help spread the heatinto the pcb.

The recommended layout is implemented on the EVM and shown in the TPS62810EVM-015 Evaluation ModuleUser's Guide.

12.2 Layout Example

GND

VIN

GND

VOUT

Figure 12-1. Example Layout





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13 Device and Documentation Support13.1 Device Support13.1.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOTCONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICESOR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHERALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

13.2 Documentation Support13.2.1 Related Documentation

For related documentation see the following:

Texas Instruments, TPS62810EVM-015 Evaluation Module, SLVUBG0

13.3 Receiving Notification of Documentation UpdatesTo receive notification of documentation updates, navigate to the device product folder on ti.com. Click onSubscribe to updates to register and receive a weekly digest of any product information that has changed. Forchange details, review the revision history included in any revised document.

13.4 Support ResourcesTI E2E™ support forums are an engineer's go-to source for fast, verified answers and design help — straightfrom the experts. Search existing answers or ask your own question to get the quick design help you need.

Linked content is provided "AS IS" by the respective contributors. They do not constitute TI specifications and donot necessarily reflect TI's views; see TI's Terms of Use.

13.5 TrademarksTI E2E™ is a trademark of Texas Instruments.All trademarks are the property of their respective owners.13.6 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handledwith appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits maybe more susceptible to damage because very small parametric changes could cause the device not to meet its publishedspecifications.

13.7 GlossaryTI Glossary This glossary lists and explains terms, acronyms, and definitions.

14 Mechanical, Packaging, and Orderable InformationThe following pages include mechanical, packaging, and orderable information. This information is the mostcurrent data available for the designated devices. This data is subject to change without notice and revision ofthis document. For browser-based versions of this data sheet, refer to the left-hand navigation.





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https://www.ti.com/lit/pdf/SLYZ022





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A A

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PACKAGE OUTLINE

C1 MAX

0.1 MIN

2

0.5 TYP

1.1

0.55

0.1 C A B

0.05 C

9X0.30.2

0.1 C A B

0.05 C

4X0.40.30.675

0.575

0.2 0.05

0.550.45

0.6750.575

0.050.00

B2.11.9

A

3.12.9

(0.2) TYP

(0.05)

(0.9)

VQFN-HR - 1 mm max heightRWY0009APLASTIC QUAD FLATPACK - NO LEAD

4224015/B 01/2018

PIN 1 INDEX AREA

SEATING PLANE

0.08 C

1

9

7

SYMM

SYMM

5

6

8

NOTES:

1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancingper ASME Y14.5M.

2. This drawing is subject to change without notice.

2

3

4

SCALE 5.000

SCALE 30.000SECTION A-A

SECTION A-ATYPICAL





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EXAMPLE BOARD LAYOUT

0.05 MAXALL AROUND

(0.65)

0.25

(0.5)

(0.55)

(0.25)

(0.35)

(0.5)

3X (0.25)

3X (2.3)

(2.65)

(R0.05) TYP

(0.775)

(0.775)


4224015/B 01/2018

NOTES: (continued)

3. This package is designed to be soldered to thermal pads on the board. For more information, see Texas Instruments literaturenumber SLUA271 (www.ti.com/lit/slua271).

4. Vias are optional depending on application, refer to device data sheet. It is recommended that vias under paste be filled, plugged or tented.

1

2

7

9

4

5

6

8

3

EXPOSED METAL SHOWNLAND PATTERN EXAMPLE

SCALE: 25X

SYMM

SYMM

SEE SOLDER MASK DETAIL

EXPOSED METAL

METAL EDGE

SOLDER MASKOPENING

NON SOLDER MASKDEFINED

SOLDER MASK DETAIL








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EXAMPLE STENCIL DESIGN

(0.25)

(0.775)

(0.21)

(0.775)

(0.31)

(2.65)

(1.25)

(0.65)

6X (0.25)

6X (1.05)

(R0.05) TYP

(0.5)


4224015/B 01/2018

NOTES: (continued)

5. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternatedesign recommendations.

SYMM

1

75

9

6

4

3

8

2

SYMM

SOLDER PASTE EXAMPLEBASED ON 0.1 mm THICK STENCIL

PADS 1, 5, 7 & 8:90% PRINTED SOLDER COVERAGE BY AREA UNDER PACKAGE

SCALE: 25X

EXPOSED METALTYP





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PACKAGE OPTION ADDENDUM

www.ti.com 19-May-2021

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples

TPS6281008QWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 81008Q

TPS628100MQWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 8100MQ




TPS628110AQWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 8110AQ



TPS628112AQWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 8112AQ


TPS628113HQWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 8113HQ







TPS628122GQWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 8122GQ



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Addendum-Page 2

Orderable Device Status(1)

Package Type PackageDrawing

Pins PackageQty

Eco Plan(2)

Lead finish/Ball material

(6)

MSL Peak Temp(3)

Op Temp (°C) Device Marking(4/5)

Samples


TPS628132DQWRWYRQ1 ACTIVE VQFN-HR RWY 9 3000 RoHS & Green SN Level-2-260C-1 YEAR -40 to 125 8132DQ



(1) The marketing status values are defined as follows:ACTIVE: Product device recommended for new designs.LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.PREVIEW: Device has been announced but is not in production. Samples may or may not be available.OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substancedo not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI mayreference these types of products as "Pb-Free".RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide basedflame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuationof the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to twolines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on informationprovided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken andcontinues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.







Addendum-Page 3

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

TPS6281008QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628100MQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281020QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS62810QWRWYRQ1 VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281109QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628110AQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281120QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281126QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628112AQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628112MQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628113HQWRWYRQ VQFN- RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

PACKAGE MATERIALS INFORMATION


Pack Materials-Page 1

Device PackageType

PackageDrawing

Pins SPQ ReelDiameter

(mm)

ReelWidth

W1 (mm)

A0(mm)

B0(mm)

K0(mm)

P1(mm)

W(mm)

Pin1Quadrant

1 HR


RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281206QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281208QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628120MQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281220QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281228QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628122GQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1


RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281320QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS6281326QWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628132DQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1

TPS628132MQWRWYRQ1

VQFN-HR

RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1


RWY 9 3000 180.0 12.4 2.25 3.25 1.15 4.0 12.0 Q1




*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

TPS6281008QWRWYRQ1 VQFN-HR RWY 9 3000 213.0 191.0 35.0

TPS628100MQWRWYRQ1 VQFN-HR RWY 9 3000 213.0 191.0 35.0




TPS628110AQWRWYRQ1 VQFN-HR RWY 9 3000 213.0 191.0 35.0



TPS628112AQWRWYRQ1 VQFN-HR RWY 9 3000 213.0 191.0 35.0


TPS628113HQWRWYRQ1 VQFN-HR RWY 9 3000 213.0 191.0 35.0







TPS628122GQWRWYRQ1 VQFN-HR RWY 9 3000 213.0 191.0 35.0






Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)


TPS628132DQWRWYRQ1 VQFN-HR RWY 9 3000 213.0 191.0 35.0






IMPORTANT NOTICE AND DISCLAIMERTI PROVIDES TECHNICAL AND RELIABILITY DATA (INCLUDING DATASHEETS), DESIGN RESOURCES (INCLUDING REFERENCEDESIGNS), APPLICATION OR OTHER DESIGN ADVICE, WEB TOOLS, SAFETY INFORMATION, AND OTHER RESOURCES “AS IS”AND WITH ALL FAULTS, AND DISCLAIMS ALL WARRANTIES, EXPRESS AND IMPLIED, INCLUDING WITHOUT LIMITATION ANYIMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE OR NON-INFRINGEMENT OF THIRDPARTY INTELLECTUAL PROPERTY RIGHTS.These resources are intended for skilled developers designing with TI products. You are solely responsible for (1) selecting the appropriateTI products for your application, (2) designing, validating and testing your application, and (3) ensuring your application meets applicablestandards, and any other safety, security, or other requirements. These resources are subject to change without notice. TI grants youpermission to use these resources only for development of an application that uses the TI products described in the resource. Otherreproduction and display of these resources is prohibited. No license is granted to any other TI intellectual property right or to any third partyintellectual property right. TI disclaims responsibility for, and you will fully indemnify TI and its representatives against, any claims, damages,costs, losses, and liabilities arising out of your use of these resources.TI’s products are provided subject to TI’s Terms of Sale (https:www.ti.com/legal/termsofsale.html) or other applicable terms available eitheron ti.com or provided in conjunction with such TI products. TI’s provision of these resources does not expand or otherwise alter TI’sapplicable warranties or warranty disclaimers for TI products.IMPORTANT NOTICE

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265Copyright © 2021, Texas Instruments Incorporated

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tps6281x-q1 2.75-v to 6-v adjustable-frequency step-down converter … · 2021. 5. 20. ·...

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