TPU: time functions

• Input event detection

• Output event generation

• Pulse-rate sensing

• Pulse-rate modulation

• Pulse-width modulation

Time Processor Unit (TPU)

RCPU

U-busSystem

InterfaceUnit

(USIU)SRAM

L-bus

SRAM

U-bus

TPU TPUSerialComm

ADC ADC

IMB

TPU

Controls 16 channels (available as pins).

Can observe events on these channels (input).

Can generate events on these channels (output).

Events: transitions to indicate some state.

TPU

IMB3

Memory-mappedinterface

SystemConfig.

Channelcontrol

ParameterRAM

Micro-Engine

channels

Chan 0Chan 1

Chan 15

TCR1

TCR2

16-bitcounters

TPU TimersTwo timers: TCR1 & TCR2 -- 16 bits each

TCR1 programmed in TPUMCR.

TCR2 can be driven by an external clock.

All channel events are created or capturedw.r.t. a timer.

TPU RegistersTPU Module Configuration Register: TPUMCR0x30 4000

0

TCR1P

00: div by 101: div by 210: div by 411: div by 8

1:2

supv

8

psck

9

Clock prescalar0: 321: 4

TPU Control RegistersTPU Interrupt Configuration Register (TICR)0x30 4008

0:4

CIRL

5:7

Channel interruptrequest level: 0-7.

ILBS8:9

TPU Control Registers

Channel Interrupt Enable Register (CIER)0x30 400a

Ch15

Ch14

Ch13

Ch1

Ch0

0 1 2 14 15

0: interrupt disabled1: interrupt enabled

TPU Control Registers

Channel Interrupt Status Register (CISR)0x30 4020

Ch15

Ch14

Ch13

Ch1

Ch0

0 1 2 14 15

Channel interrupt status:0: interrupt not asserted1: interrupt asserted

Channel Programming

16 predefined functions.

Input Capture: capture one or multiple transitions on an input pin.

Channel 0

Capture the time of the transition

Channel ProgrammingProgram as an output channel.

Output Compare: generate an event on the output: a single output transition, a single pulse, or a continuous 50% duty cycle pulse train.

REF_TIME1

offset

Ref_Time = REF_TIME1 + offset

Channel InitializationChoose channel function: Code for IC: 0xAChannel function code for OC: 0x4

Ch 15 Ch 14 Ch 13 Ch 12

0x30 400c: Channel Function Select Register 0 (CFSR0)

Ch 11 Ch 10 Ch 9 Ch 8

0x30 400e: Channel Function Select Register 1 (CFSR1)

Ch 7 Ch 6 Ch 5 Ch 4

0x30 4010: Channel Function Select Register 2 (CFSR2)

Ch 3 Ch 2 Ch 1 Ch 0

0x30 4012: Channel Function Select Register 3 (CFSR3)

Input Capture Parameters

Channel Control (9 bits)

MAX_COUNT

TRANS_COUNT

FINAL_TRANS_TIME

LAST_TRANS_TIME

Channel W

0x3041W0

0x3041W2

0x3041W4

0x3041W6

0x3041W8

0x3041Wa

Input Capture/Transition CounterInput Parameters:MAX_COUNT:The TPU raises an interrupt after counting as many events as MAX_COUNT.

Output Parameters:TRANS_COUNT: current count of captured transitions.

FINAL_TRANS_TIME: Timer time when the final transition (MAX_COUNTth) is captured.

LAST_TRANS_TIME: Timer time when the lasttransition (TRANS_COUNTth) is captured.

Memory Map of ParametersChannel 0:MAX_COUNT: 0x30 4104TRANS_COUNT: 0x30 4106FINAL_TRANS_TIME: 0x30 4108LAST_TRANS_TIME: 0x30 410A

General Channel Y:MAX_COUNT: 0x30 41Y4TRANS_COUNT: 0x30 41Y6FINAL_TRANS_TIME: 0x30 41Y8LAST_TRANS_TIME: 0x30 41YA

General Parameter Memory Map

P1 P2 P3 P4 P5 P6 P7 P8

P1 P2 P3 P4 P5 P6 P7 P8

P1 P2 P3 P4 P5 P6 P7 P8

P1 P2 P3 P4 P5 P6 P7 P8

Ch 0

Ch 1

Ch 2

Ch 15

0x304100 02 04 06 08 0a 0c 0e

10 12 14 16 08 1a 1c 1e

20 22 24 26 28 2a 2c 2e

f0 f2 f4 f6 f8 fa fc fe

Channel Control OptionsPart of channel initialization

0:6

TBS

7:10

Time Base Selection00xx: input channel000x: capture TCR1001x: capture TCR2

PAC

11:13

Pin Action Control000:do not detect trans.001:detect rising edge010:detect falling edge011:detect either edge1xx:do not change PAC

PSC

14:15

Pin State Control11:do not force any state input pin01: force high10: force low

Channel Priority

Choose channel priority: 0:disable; 1:low; 2: medium; 3: high

0x30 401c: Channel Priority Register 0 (CPR0)

Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8

0x30 401e: Channel Priority Register 1 (CPR1)

Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0

Channel Function Activation

After initializing channel, the channel function is activated by host service request, which can be further specialized through host sequence.

0x30 4018: Host Service Request Register 0 (HSRR0)

Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8

0x30 401a: Host Service Request Register 1 (HSRR1)

Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0

Host Sequence

0x30 4014: Host Sequence Register 0 (HSQR0)

Ch 15 Ch 14 Ch 13 Ch 12 Ch 11 Ch 10 Ch 9 Ch 8

0x30 4016: Host Sequence Register 1 (HSQR1)

Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0

Transition sequencing:

x0: single shotx1: continual

Typical Initialization Sequence• Disable the channel before programming it

– CPR[ch] 00 (channel priority – disabled)

• Assign the channel function

– CFSR[ch] 0xA (for input capture/ITC)

• Program the function parameters

– MAX_COUNT=1 for input capture

– Channel control: TBS: 000x (input channel; capture TCR1); PAC: 001 (detect rising edge); PSC: 11 (do not force)

– Host sequence single shot. Write 00 into HSQRR[ch].

– etc.

• Initialize host service (activate the channel):

– HSRR[ch] 01 (initialize TCR mode)

• Enable the channel:

– CPR[ch] 01, 10, 11

Shared Register Modification0x30 401a: Host Service Request Register 1 (HSRR1)

Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0

00: Host service complete by TPU channel01: Initialize TCR mode by CPU Program

Modification of HSRR involves read-modify-write:

lhz r6, 0x401a(r5) //read andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0]) ori r6, r6, 0x1 sh r6, 0x401a(r5) // write

Does it work?

How many independent potential writers into HSRR1?

Shared Register Modification Contd.

00 00 10 00 00 11 01 00lhz r6, 0x401a(r5) //read

andi r6, r6, 0xfffc // modify (write %01 to HSRR[ch0])ori r6, r6, 0x1

sth r6, 0x401a(r5) // write

00 00 10 00 00 11 01 01

00 00 10 00 00 11 00 00

We don’t really know what happens to ch 1-7 fields while we modify ch 0 field.

Shared Register Modification Contd.Solution: into ch 1-7 fields, write something we are definitely not supposed to write.

00 is written by only the TPU, no CPU program should legitimately write that value.

li r6, 0x1 //00 00 00 00 00 00 01 sth r6, 0x401a(r5)

00 00 10 00 00 11 00 00

Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1 Ch 0

Write guard logic only allows 01, 10, 11 to go through!

01

Output Compare (OC)REF_TIME1

offset

Ref_Time = REF_TIME1 + offset

The pin state is not forced into an immediate output.

REF_TIME1

offset

Ref_Time = REF_TIME1+ offset

Pin state forced to high (immediate output selected).

Output Compare (OC)

OC parameters specified by the CPU program: REF_TIME1 as a pointer into the parameter space of any of the 16 channels. Parameter address space: 0x3041 00 – 0x3041 fe

Need to specify only 8-bits of address for REF_ADDR1.

OFFSET: a 16-bit quantity: 0x0 – 0x8000.

OC Programming(REF_ADDR1)

OFFSET

REF_TIME = (REF_ADDR1) + OFFSET

Point REF_ADDR1 to 0x3041 ec (TCR1 value captured at this parameter address).

OFFSET = 0x1000 with TCR1 resolution at 1 micro-s: 4.096 milli-s.

Channel function code for OC: 0x4 CFSR[ch] 0x4

Output CompareOC initialization (host service request of 01 -- host initiated pulse mode) writes the current value: TCR1 0x3041 ec; TCR2 0x3041ee

(REF_ADDR1)

OFFSET

REF_TIME = (REF_ADDR1) + OFFSET

Program channel 0 for this pulse.

OC Channel Control Options

TBS

Time Base Selection01xx: output channel0100: capture TCR1, match TCR10101: capture TCR1, match TCR20110: capture TCR2, match TCR10111: capture TCR2, match TCR21xxx: do not change TBS

0:6 7:10 11:13

PAC

Pin Action Control000: do not change pin state on match001: high on match010: low on match011: toggle on match1xx: do not change PAC

PSC

14:15

Pin State Control11: do not force any state01: force high10: force low

OC Channel Control

(REF_ADDR1)

OFFSET

REF_TIME = (REF_ADDR1) + OFFSET

110110100

Do not force initial state

Toggle on match

Capture TCR1, match TCR1

OC Channel Control

010100100

Force high

Low on match

Capture TCR1, match TCR1

(REF_ADDR1)

OFFSET

REF_TIME = (REF_ADDR1) + OFFSET

Other OC Parameters

Channel Control (9 bits)

OFFSET

REF_ADDR2

REF_TIME

ACTUAL_MATCH_TIME

Channel W

0x3041W0

0x3041W2

0x3041W4

0x3041W6

0x3041W8

0x3041Wa

RATIO REF_ADDR1 0

0 REF_ADDR3 0

We will write 0’s into RATIO, REF_ADDR2, and REF_ADDR3.

OC Output ParametersWhen a channel is initialized for OC through a service request of 01, REF_TIME is computed as (REF_ADDR1) + OFFSET and placed in parameter REF_TIME.

REF_TIME is the next time instant when an event would occur (and an interrupt is raised).

This is the match event: compare TCR1/2 with REF_TIME for a match.ACTUAL_MATCH_TIME is updated with the TCR1/2

time when the match is serviced (by raising an interrupt, and changing the level of the output channel).