trading flash translation layer for performance and lifetime 王 江 涛王 江 涛
TRANSCRIPT
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Trading Flash Translation Layer For Performance and Lifetime
王 江 涛
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Introduction
Outline
1
Flash Translation Layer2
Address Mapping3
Wear Leveling4
5 Conclusion
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Introduction of Flash Memory
• Pros Small size and Lighter weight Low power consumption and Non-Volatility Shock resistance and Lesser noise Faster access performance
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flash memory chip
OOBECC(Hamming Code)Logical page numberState:
erased/valid/invalid
DATA
OOB
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Introduction of Flash Memory
Cons Write granularity (page) Erase before write (block) Sequential write within a block Limited erase/write
Out-of-place update when a page is to be overwritten, we allocate a new free
or erased page we used a software layer called FTL indicate the
physical location change of the page
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Introduction
Outline
1
Flash Translation Layer2
Address Mapping3
Wear Leveling4
5 Conclusion
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Flash Translation Layer
Function Address mapping Garbage collection(block reclamation) Wear-leveling
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Introduction
Outline
1
Flash Translation Layer2
Address Mapping3
Wear Leveling4
5 Conclusion
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Address Mapping
• Block-level FTL Scheme The same page offset within logical and physical block Mapping table reside in RAM (size is small) Erase operation frequent and space utilization is low
• Mapping granularity Page-level scheme Block-level scheme Hybrid scheme
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Address Mapping
• Hybrid FTL Scheme DBA: store user data (block-level mapping) LBA: store overwriting data (page-level mapping)
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Address Mapping
• Page-level FTL Scheme A logical page number can be mapped into any page Mapping table stored in SRAM[1995] Mapping table is stored in Flash and cached in
SRAM[2009]
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Page-level FTL Scheme
• Related work DFTL:A Flash Translation Layer Employing Demand-based
Selective Caching of Page-level Address Mapping. (ASPLOS 2009)
A Workload-Aware Adaptive Hybrid Flash Translation Layer with an Efficient Caching Strategy (CFTL)
(MASCOTS 2011)
LazyFTL: A Page-level Flash Translation Layer Optimized for NAND Flash Memory
(SIGMOD 2011)
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DFTL
• Divided flash memory into MBA and DBA MBA--Store the full mapping table on flash DBA—Store user data
• Use page-level mapping• Dynamically swap page-level mapping entries
in/out SRAM
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DFTL
SRAM
CMT: Caching Mapping TableGMD: Global Mapping DirectoryLPN : logical page numberPPN: physical page number
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DFTL
Pros Realize sequential program within a block Avoid full merge
Cons Frequently update the mapping pages during
garbage collection A poor reliability of mapping information The cost of read is large
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Workload-Aware Adaptive FTL(CFTL)
• Divided flash memory into MBA and DBA MBA--Store the full mapping on flash DBA—Store user data
• Use page-level mapping and block-level mapping• Dynamically swap page-level mapping entries in/out
SRAM
• Convert to each other based on data access patterns Read intensive: Block-level mapping Write intensive: Page-level mapping
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Workload-Aware Adaptive FTL(CFTL)
Pros Realize sequential program within a block Avoid full merge Exploit temporal and spatial locality and workloads Improve the performance of read
Cons Frequently update the mapping pages during garbage
collection A poor reliability of mapping information Expensive read/write cost to build block mapping table
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LazyFTL
DBA: store user dataMBA: store mapping pages(page-level scheme)CBA: store valid user data when implement garbage
collectionUBA: Implement write requests
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LazyFTL
Write Complete a write request in the UBA Store new mapping formation in RAM ( UMT: update mapping table )
Garbage CollectionReclaim a victim block in the DBA or the MBAMove valid data pages to CBA and store new mapping formation in RAM (UMT)
ConvertImplement a batch updatesConvert CBA/UBA to DBA
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LazyFTL
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Convert Algorithm
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Performance Evaluation
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LazyFTL
• Pros Adopt an update buffer to decrease frequently update
the mapping pages Achieve consistency and reliability Improve write performance by reduce erase operation
• Cons Increase the cost of read operation Decrease speedup of garbage collectionNot considering hot-cold data for wear leveling
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Introduction
Outline
1
Flash Translation Layer2
Address Mapping3
Wear Leveling4
5 Conclusion
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Wear Leveling
• Introduction Any one part of flash memory can only withstand a
limited number of erase-write cycles Localities of data access inevitably degrade wear
evenness in flash
• Some definitions Hot data block and cold data block (access frequency) Old block and young block (erase counts)
• Basic principle Prevent old blocks from being erased(cool down) Start erasing young blocks actively(heat up)
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Wear Leveling
Cold data migration move cold data from young blocks to old blocks Select young blocks when execute garbage collection
• Related work(Hybrid FTL Scheme) A Low-Cost Wear-Leveling Algorithm for Block-Mapping Solid-
State Disks (lazy scheme) (LCTES2011)
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Lazy Scheme
• Recency Update recency ( a logical block ) the time length since the latest update to a logical block Erase recency ( a physical block )the time length since the latest erase operation on a
physical block
• Frequency Elder block larger than the average erase count Junior block smaller than the average erase count
• OverviewCold data migration Consider recency (recent wear history ) and
frequency
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Lazy Scheme
The goal of wear-leveling is that a block should keep its erase count close to the average.For junior block, we are interested in Block e and f.For elder block, we are interested in block a and b.We need to move valid data in block e and f to block a and bRe-map e and f to a and b and select Block e and f as victim blocks
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Algorithm
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Lazy Scheme
• Prosdoes not store wear information in RAM, but leaves all of
this information in flash instead.utilizes the address-mapping information available and
do not need to add extra data structures for wear leveling
Cons It is important to uniformly visit every logical block
when selecting a logical block for re-mapping.
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Introduction
Outline
1
Flash Translation Layer2
Address Mapping3
Wear Leveling4
5 Conclusion
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Conclusion
• Conclusion Page mapping scheme shows the best performance in
that it can decrease erase operations It is necessary to design an efficient wear leveling
scheme for Page-Mapping Solid-State disks Some operations in FTL can be executed without
interrupting current flash accesses by exploiting internal parallelism of flash memory
As write caching to reduce erase operation SSD for primary storage, auxiliary PCM
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Thank you