trams project terascale reliable adaptive memory systems fp7 248789 y1 ec review meeting april 12 th...

TRAMS PROJECT

TERASCALE RELIABLE ADAPTIVE MEMORY SYSTEMS

FP7 248789

Y1 EC Review Meeting April 12th 2011

FIRST YEAR PROJECT REVIEW MEETINGLeuven, April 12th 2011


AGENDA

1. Introduction 10.30

2. Project management & organization (WP6) 11.30

Lunch 12.00

3. Detailed review of technical Work Packages (WP1-WP4)

13.30

4. Dissemination and exploitation of results (WP5)

15.50

5. Q&A 16.20

6. Breakdown 16.45

7. Conclusions 17.30

Closing 18.00

Power point presentations


IN

• public/me.com/rubio2010• Intranet of the project “Reviewers area”


AGENDA

1. Introduction 10.30

2. Project management & organization (WP6) 11.30

Lunch 12.00

3. Detailed review of technical Work Packages (WP1-WP4)

13.30

4. Dissemination and exploitation of results (WP5)

15.50

5. Q&A 16.20

6. Breakdown 16.45

7. Conclusions 17.30

Closing 18.00


1. Introduction (45’+15’)

1.1 Welcome and agenda presentation

1.2 General Project Objectives and Milestones

1.3 Modifications during Y1 respect original DoW

1.4 Milestones and deliverables 1st year

1.5 Use of resources Y1

1.6 Work plan summary for the 2nd year

1.7 Modifications respect original DoW for 2nd and 3rd years


1. Introduction








Motivation: Research on Memory technologies for terascale multicore microprocessors


MOTIVATION

Memories are a key technology driver in semiconductor industry, having an extremely important role in terascale

multicore microprocessorsIn such systems cores and memory may exhibit high failure

rates due to process variations and devices degradation mechanisms.


Pictures from Intel Corporation

MOTIVATION

Motivation


1.2 General project and objectives


Objectives of the TRAMS project

To investigate the impact of statistical variability and reliability of near and beyond the end of the ITRS devices on Terabit memory design.

(Sub-16nm bulk (18,13nm) CMOS,Sub 10nm Finfet, 15nm III-V/Ge and CNT)(WP1-WP2)

To design,implement, deploy and assess compensating techniques and countermeasures at circuit and microarchitectural level for memories used in

multicore processors(WP3-WP4)

To develop a methodology for specifying and implementing performance-, power- and reliability –aware reconfiguration policies for multicore processor.

(WP4)



THE CONSORTIUM



4 TECHNICAL WPs, 15 TASKS



WORK PACKAGE 1 (WP1)

Title PDK for end of roadmap transistors in the presence of statistical variability and reliability

81 PMs

Leader UOG (71) Other participants: UPC (6), Imec (4)

Objectives • To design the bulk, FinFET, III/V and CNT devices• To extract nominal compact models for them• To consider the initial variability and the aging• To extract statistical compact models of fresh and degraded

devicesTasks T1.1. Design of the devices. Nominal compact models.

T1.2 Extraction of statistical compact models for fresh devices.T1.3 Extraction of statistical reliability compact models for degraded devicesT1.4 Extraction of reliability injectors

Deliverables: D1.1 (bulk), D1.2 (CNT), D1.3 (FinFET), D1.4 (III-V/Ge)




Title Modelling and analysis of faulty components at circuit level.

45 PMs

Leader Imec (30.5) Other participants: UPC (11.5), UOG (3)

Objectives • To develop a method for a prototype tool flow for Variability and Reliability –aware modelling of SRAM blocks for the different technologies.

Tasks T2.1 Variability and Reliability modelling toolflow for bulk.T2.2 Variability modelling toolflow for FinFET SRAM blocks.T2.3 Towards III-V/Ge, CNT and other Emerging Research Devices

Deliverables: D2.1 (bulk), D2.2 (FinFETs), D2.3 (III/V and CNT)




Title Hardware countermeasures at the circuit level 105 PMs

Leader UPC (86) Other participants: Imec (13), Intel (6)

Objectives • Research on the effect of environmental and process variability on the performances of the memory systems

• Mitigating mechanisms and strategies.• Compensating and redundant structures• Method and prototype tool flow for run-time monitoring.

Tasks T3.1 Mitigation of the impact of variability. Redundant circuits.T3.2 Countermeasure techniques based on environmental variables, on compensation and reconfiguration mechanismsT3.3 Prototype toolflow for run-time switchable buffer insertion and Reconfiguration.

Deliverables: D3.1, D3.2, D3.3, D3.4, D3.5, D3.6




Title Hybrid countermeasures at the micro-architectural and system level

130 PMs

Leader Intel (65) Other participants: UPC (53), Imec (12)

Objectives • To develop mixed run-time methodologies to predict memory faulty behaviour.

• To develop run-time methodologies to identify program memory requirements in terms of correctness, performance and power.

• To develop run-time decision mechanisms for best memory configuration.

Tasks T4.1 Dynamic characterization of memory and applications.T4.2 Memory reconfiguration.T4.3 Hybrid system scenario countermeasures.T4.4 Global Micro-controller

Deliverables: D4.1, D4.2, D4.3, D4.4

1.2 Summary of staff effort


21%

11%

27%

33%

5%

3%

43%16%20%20%

1.2 Milestones (as in the DoW)


M0 M12 M24 M36

MS0web

MS1v&r for bulk CMOS

MS3v&r FinFET

MS4reconfiguration

MS5v&r III/V

MS6v&r CNT

MS7Countermeasures

circuit level

MS8CountermeasuresMicro-arch. level

MS9Final dissemination

report

Conceptual flow of the project (from DoW work planning)


WP1

WP2

WP3

WP4

WP5

Y1

Y2 Y3

PDK x V&R sub 16nm bulk MOSFET

idem x FinFET

idem x CNT

idem x III-V/Ge

V&R modelling x bulk CMOS SRAM

V&R modelling x FinFET SRAM

Towards V&R evaluation x III-V/Ge, CNT and ERD

Effect of PTV on different memory cells

performance

Countermeasure techniques against V&R: Mitigation, Redundancy, Compensation, Reconfiguration, Monitor insertion

Dynamic characterization Memory reconfiguration, countermeasures

Global MIcrocontroller

WEB

Dissemination

Milestone 2

Milestone 3 Milestone 6 Milestone 5

Milestone 4

Milestone 7

Milestone 8

Milestone 1

Milestone 9

Device

Modelling and analysis methods

Cell and circuit level

Microarchitecture and system level


1. Introduction










3 modifications

no change of objectives

no change of milestones

Modification of title in deliverable D2.1

Modification work period in T2.2

Exchange of two deliverables in WP3



Description modification 1 (Title of D2.1)

D2.1: Report on method for a tool flow for Variability and Reliability modeling for bulk CMOS SRAM blocks. (IMEC) T0+12M

Justification

• Task description refers to a method yet the title method for tool flow may be understood as the expected outcome is a tool while this is not the case.

• Change ensures correct interpretation



Description modification 2 (T2.2 period)

Justification

• FinFET research in WP1 is concentrated on Y2.

Task 2.2: Variability modelling toolflow for FinFET SRAM blocks. [Task Leader: IMEC (10 pms), Duration: [M313-M1824]

Conceptual flux of the project (from DoW work planning)


WP1

WP2

WP3

WP4

WP5

Y1

Y2 Y3


= x FinFET

= x CNT

= x III-V/Ge


V&R modeling x FinFET SRAM



performance




WEB

Dissemination

Milestone 2


Milestone 4

Milestone 7

Milestone 8

Milestone 1

Milestone 9

Device

Modeling and analysis methods





Description modification 3 (WP3 deliverable order)

Justification

• D3.6 corresponds to the analysis of environmental and process variations. It is necessary to have this analysis before to consider mitigation and countermeasures research. This decision fits with the description of milestone 2 (M12) (v&r analysis for bulk CMOS), and D3.6 pertains to T3.1 that finished M24!

• D3.6 initially scheduled for M36 M12• D3.1 initially scheduled for M12 M24

Conceptual flux of the project (from DoW work planning)


WP1

WP2

WP3

WP4

WP5

Y1

Y2 Y3


= x FinFET

= x CNT

= x III-V/Ge





performance




WEB

Dissemination

Milestone 2


Milestone 4

Milestone 7

Milestone 8

Milestone 1

Milestone 9

Device




Conceptual flux of the project


WP1

WP2

WP3

WP4

WP5

Y1

Y2 Y3


= x FinFET

= x CNT

= x III-V/Ge





performance




WEB

Dissemination

Milestone 2

Milestone 1

Device




D3.1D3.6

D3.6D3.1


1. Introduction








1.4 Milestones (as the DoW)


M0 M12 M24 M36

MS0web


MS3v&r FinFET

MS4reconfiguration

MS5v&r III/V

MS6v&r CNT

MS7Countermeasures

circuit level



report

✔

✔

1.4 Milestones


M0 M12

MS0web

MS1v&r analysis for bulk CMOS

✔

✔

D5.1 (M6)

D1.1 (M12)

D2.1 (M12)

D3.6 (M12)*

D4.1 (M12)

D5.2 (M12)

D6.1 (M12)

1.4 Deliverables for Y1 period


MS WP Description

MS0 WP5 D5.1 TRAMS project website description

MS1 WP1 D1.1 PDK for sub 16nm technology bulk MOSFETs including statistical variability and reliability

MS1 WP2 D2.1 Report on method for variability and reliability modelling for bulk CMOS SRAM blocks

MS1 WP3 D3.6 Report on the effect of environmental and process variations on the variability of memory cells and systems

MS1 WP4 D4.1 Report on the different phase identifier mechanisms

MS1 WP5 D5.2 Dissemination, use plan and joint collaborative actions

MS1 WP6 D6.1 Progress report and cost statement Y1


1. Introduction










16.5%

26.6%

40%

16.2%

22.7%

34.6%

24.7%

34.3%

22.9%

18.9%

11.5%


1. Introduction








1.4 Milestones


M0 M12 M24 M36

MS0web


MS3v&r FinFET

MS4reconfiguration

MS5v&r III/V

MS6v&r CNT

MS7Countermeasures

circuit level



report

✔

✔

★

★

★

★

★

1.5 Work plan summary for the second year


Y2 plan of work

All task actives

WP Description

WP1 PDK x CNT tech. (D1.2), PDK x FinFETs (D1.3)

WP2 Method for V & R modelling in FinFET SRAM blocks (D2.2)

WP3 Mitigation mechanisms (D3.1)Improving reliability through redundancy D(3.2)Mechanisms to detect latency of SRAM D(3.3)Compensation/Reconfiguration mechanisms D(3.4)

WP4 Identifier mechanisms (D4.1_2)Reconfiguration mechanisms (D4.2)

WP5 Dissemination, use plan and joint collaborative actions (D5.3)

WP6 Progress report and cost statement of year 2 (D6.2)

WP


1. Introduction








Proposed amendments for DoW


Proposed amendments (including modifications Y1)

No change of objectives

No modification of milestones and schedule of the project

No modification of work plan

Inclusion of a new deliverable with demonstration in WP4



Amendments in WP1 (2)



Description modification WP1 1 (D1.3 due date)

Justification

This is required as the results of D1.3 (PDK for sub 16 nm technology FinFET transistors including statistical variability and statistical reliability) are a necessary input to Task T2.2.

Move due date D1.3 (FinFET) from M27 to M18



Description modification WP1 2 (D1.2 due date)

Justification

Balanced distribution of work in WP1, and D1.2 will include the analysis of v&r for 6T and 3T1D cells.

Move due date D1.2 (CNT) from M18 to M24



Description modification WP2 1 (title of D2.1 and D2.2 )

Justification

• Task description refers to a method yet the title method for tool flow may be understood as the expected outcome is a tool while this is not the case.

• Change ensures correct interpretation

• D2.1: Report on method for a tool flow for Variability and Reliability modeling for bulk CMOS SRAM blocks.

• D2.2: Report on method for a prototype tool flow for Variability modeling forFinFET SRAM blocks.

amendment from Y1



Description modification WP2 2 (Move T2.2 and D2.2)

Justification

• D2.2 ends on M18 and should end on M24 because• T2.2 ends on M24• it consumes output from D1.3 that ends on M18

• Task 2.2: Variability modelling toolflow for FinFET SRAM blocks. [Task Leader: IMEC (10 pms), Duration: [M313-M1824]

• D2.2: Report on method for Variability modeling forFinFET SRAM blocks. T0+ 1824M

amendment from Y1



Description modification WP2 3 (Moving 4PMs from T2.3 to T4.4)

Justification

• Imec moves 4PM from T2.3 to T4.4 to reinforce a demo (new deliverable D4.5)

• Imec will focus on assessment of III-V technologies and benchmarking against Si under nominal process conditions

• UPC keeps with CNT and ERD

Task 2.3: Towards III-V/Ge, Carbon NanoTubes (CNT) and other Emerging Research Devices. [Task Leader: UPC (11.5 pms), Contribution: IMEC (8.54.5pm) Duration: M18-M36]



Description modification WP2 4 (Moving 3PMs from T2.1 to T2.2)

Justification

UoG has previously done statistical SRAM analysis based on full statistical bulk MOSFET simulations and feel it would provide more value and novelty to this project to investigate the use of FinFETs, using the SRAM netlist generated by IMEC in T2.2.

UoG would like to move the 3PM allocated to T2.1 (Variability and Reliability modelling toolflow for bulk CMOS SRAM blocks) to T2.2 (Variability modelling toolflow for FinFET SRAM blocks).



Description modification WP3 1(WP3 deliverable order) Y1

Justification

• D3.6 corresponds to the analysis of environmental and process variations. It is necessary to have this analysis before to consider mitigation and countermeasures research. This decision fits with the description of milestone 2 (M12) (v&r analysis for bulk CMOS)

• D3.6 initially scheduled for M36 M12• D3.1 initially scheduled for M12 M24

amendment from Y1



Description modification WP3 2 (Transfer 18PMs from T3.3 to T3.2)

Justification

• T3.3 as described in DoW describes two different areas:• research on a timing monitor insertion technique (Imec 13PMs)• research on reconfiguration mechanisms (circuit level) (UPC 18 PMs)

• Reconfiguration is a mechanism to compensate aging so it is more reasonable in T3.2, so it is a countermeasure

• No modification of deliverables content, title, schedule

Movement of 18PMs from UPC in T3.3 to T3.2



Description modification WP3 3 (Change timing in T3.3 and advance due date D3.5)

• Task 3.3: Prototype Toolflow for run-time switchable buffer insertion and reconfiguration in SRAMs Design Flow for timing monitor insertion for runtime monitoring of an ASIC during synthesis. [Task Leader: IMEC (13 pms), Contribution: UPC (18 pms). Duration: M1213-M3624].

• With changes in the description to make explicit the focus on monitor insertion

• D3.5: Report on the method toolflow that instantiates the SKM monitor insertion in SRAMs ASICs descriptions. (IMEC) T0+(M36)24

• Timing: for deliverable and task are advanced

• UPC moves work on reconfiguration to T3.2• Imec remains with 13PM• Imec will focus on monitors (complementary), already communicated in Brussels

meeting with EC• Similar to WP2 with an effort of approx 1PY/Y/deliverable imec prefers to focus

task T3.3 and its associated deliverable D3.5 in Y2

Justification



Description modification WP4 1 (New deliverable)

Justification

Reinforce evaluation, impact and dissemination of results will be much better

• Request: add a new deliverable (D4.5)We will prepare a demo showing the most promising results from WP4 in real hardware based on Intel SCC

• Change: IMEC requests extra 4PMs to be allocated to T4.4 for that purpose



Description modification WP6 1 (PTC introduction)

Justification

• The concept was introduced at the creation of the Consortium Agreement. The PTC is responsible of the technical decisions, with meetings each four months. Formed by 2 members from each institution.

• No role conflicts with PMB functions described in the Management section.

Introduction of the Project Technical Committee in the Project Management Structure

Conclusions


• The objectives of the TRAMS project have a continued relevance with respect to the scientific state of the art and industrial requirements.

• The utilized resources agree with the planned and the achieved progress

• A set of minor modifications (task and deliverable title and date changes) has been proposed for the 3 years, the result is a smoother project flux.

• TRAMS objectives are key in the development of aggressively scaled systems beyond 2020.

• The proposed v&r solutions will enable integrated circuit progress to continue.

trams project terascale reliable adaptive memory systems fp7 248789 y1 ec review meeting april 12 th...

Documents

general project objectives

y1 ec review meeting

y1 respect original

work plan summary

agenda presentation1

use of resources y11

memory technologies

nm cmos