tridas lhcc report cms level 1 trigger - university of …wsmith/cms/lhcc_jan99.pdf · wesley...

Wesley Smith, U. Wisconsin January, 1999

TriDAS LHCC ReportTriDAS LHCC ReportCMS Level 1 TriggerCMS Level 1 Trigger

Wesley Smith, U. Wisconsin, 19.1.99

Overview & Recent Progress:• Calorimeter Trigger• Muon Trigger• Global Trigger

Organization, Cost, Schedule

The pdf file of this talk is available at:http://cmsdoc.cern.ch/~wsmith/LHCC_Jan99.pdfSee also CMS Level 1 Trigger Home page at

http://cmsdoc.cern.ch/ftp/afscms/TRIDAS/html/level1.html


Detector Frontend

Computing Services

Readout

FilterFarms

Event Flow

Control Readout Network

Level 1Trigger

Controls

40 MHz

105 Hz

102 Hz

100 Tbyte/s

100 Gbyte/s

100 Mbyte/s

Collision rate 40 MHzLevel-1 Maximum trigger rate 100 kHzAverage event size ≈ 1 MbyteNo. of In-Out units (200-5000 byte/event) 1000Readout network (512-512 switch) bandwidth ≈ 500 Gbit/s Event filter computing power ≈ 5 106 MIPSData production ≈ Tbyte/dayNo. of readout crates ≈ 250No. of electronics boards ≈ 10000

CMS Trigger & DAQCMS Trigger & DAQ

Basic Structure


•

High trigger levels. Network and CPU farms- Clean particle signature- Finer granularity precise measurement- Kinematics. effective mass cuts and event topology- Track reconstruction and detector matching- Event reconstruction and analysis

Level-1. Specialized processors- Particle identification: high pT electron,

muon, jets, missing ET

- Local pattern recognition and energy evaluation on prompt macro-granular information from calorimeter and muon detectors

40 MHz

Up to 100 kHz

≈ 100 Hz

Detector Frontend

Computing Services

Event Manager Switch

Level 1Trigger

Detector Frontend

Computing Services

Event Manager Switch

Level 1Trigger

CMS Trigger LevelsCMS Trigger Levels

•

• •• ••

•


Synchronous 40 MHz digital system

- 160 MHz internal pipeline

- Readout and processing latency < 1µs

- Signal distribution latency ≈ 2 µs

Global Trigger 1

Accept/Reject LV-1

Trigger Primitive Generator

Front-End Digitizer

Local level-1Primitive e, γ, jets, µ

Pipeline delay ( ≈ 3 µs)

≈ 3 µs latency

loop

Level-1 trigger systemLevel-1 trigger system

Communication Loop:


Level 1 LatencyLevel 1 Latency

RPC DT CSC CALO

detector

CALOtrigger

global trigger

clk/control

local clk/control

RPCPACT

M. Kudla

J. Ero

J. Hauser W. Smith

link to detector~ 18 bx

W. Smith

linklin

k

R. Martinelli

logicalunitsinterconnections between logical units

links between detector and control room (18 bx)

66 bx

=>28 bx

126 bx

A. Taurok

5 bx5bx

frontend frontend frontend frontend

DTTPG

CSCTPG

CALOTPG

TRACKFINDERS

DT

global muon trigger79 bx

74 bx

80 bx

link

link

92 bx

A. Taurok

98 bx

77 bx

CSC

D. Acosta


CMS/LHC Trigger PhysicsCMS/LHC Trigger Physics

Standard model Higgs (high luminosity)

• H (80 GeV) → γ γ • H (120 GeV) → Z Z* (4 leptons)

• H (>500 GeV) → leptons ( + ν's)

• H (< 2MW Associated t or W or Z) → b b (lepton + X) SUSY Higgs (low luminosity)

• (standard model Higgs like channels)

• h, H, A → τ τ (lepton + X) or → µµ• A → Z h ; h → bb (lepton + X)

• p p → t t X; t → H+ b; H+ → τ ν; t → lepton + X; τ → X SUSY sparticle searches (low luminosity)

• MSSM sparticle → LSP (Missing Et) + n jets

• MSSM sparticle → Same sign dileptons + X Other new particles

• Z' → dileptons

• Leptoquarks: dileptons Top physics (low luminosity)

• t → lepton + X

• t → multijets Bottom physics (low luminosity)

• b → lepton + X

• b → ψks (leptons + X) QCD

• Low luminosity 100 GeV jets

• High luminosity 200 GeV jets ⇒ Trigger candidate requirements:

• High luminosity: lepton/γ (30 GeV), dileptons/γγ (15 GeV) missing Et (100 GeV), jets (200 GeV)

• Low luminosity: lepton/γ (15 GeV), dileptons/γγ (10 GeV) missing Et (50 GeV), jets (100 GeV)


Cal. Trigger requirementsCal. Trigger requirements Input

• ECAL trigger towers, 0.087φ x 0.087η• Matching HCAL towers

• Data every 25ns - including any corrections for time development of calorimeter signal

• 8 bit transverse energy

• 1 bit finegrain charecterization of energy deposit

• Data presynchronized across all channels, ECAL and HCAL

Output

• Top 4 nonisolated electrons/photons (Et and location)

• Top 4 isolated electrons/photons (Et and location)

• Top 6 jets (Et and location) & no. above threshold

• Total and missing transverse energy (Et, Ex, Ey)

• Minimimum ionization ID and isolation bits for use with muon trigger

Outut rate

• 75/2=37.5 kHz maximum for calorimeter trigger

• Simulations should indicate significant safety margin - i.e., ~15 kHz rate from calorimeter trigger simulation

Efficiency

• Trigger should contribute no more than a few percent inefficiency for any physics channel compared to other offline analysis cuts.

• Trigger efficiencies should be measurable

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Receiver Card PrototypeReceiver Card Prototype

160 MHz Prototype Card Under Test:• VME Interface working• Adder ASIC's functioning• Detailed timing under study


Vitesse 0.6µ H-GaAs Process: ECL I/O• 13 bits per operand x 8 operands• Single thirteen bit output• Latency: 25 ns @ 160 MHz• Full Boundary Scan support

Technical analysis by Vitesse• ~11,000 cells• 4 Watts• 308 MHz

Status:• 5 tested

devices delivered

• select nets exceed simulation speed by 10%

Receiver Card:

- J. Lackey

8 x 13-bit 160 MHz Adder ASIC8 x 13-bit 160 MHz Adder ASIC


160 MHz Backplane 160 MHz Backplane

std.2

conn. VMEarea

std.2

conn. VMEarea

triggerprocessing

area

triggerprocessing

area

singleVME

connector

singleVME

connector

- J. Lackey

Display 3 of 6 signal layers:

Receiver Cards

Electron Isolation Cards

Data Flow

Rear

3.56 cm center to centerPower Plane Dielectric

VME Section

Trigger DataSection

Not to scale: Traces

Top View:

Input clock to clock card:

0V

-1V0V

-1V

Last position on backplane*:

500 mV/div, 2 ns/div

Signal performance:rise < 1 ns:


Backplane Test SetupBackplane Test Setup

Front view of crate & backplane with clock board installed

Top rear view of crate & backplane with power supplies

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η=0

4T

2T

MS1 MS2 MS3 MS4RPC pattern recognition- pattern catalog- fast logic

Muon trigger systemMuon trigger system

track segment

muon station 4muon station 3

muon station 2muon station 1

2 x extrapolation

threshold

3 track segment pairs arecombined to one track string f2 - f 1

DT and CSC track finding:- combines vectors- forms a track- assigns p

t value

The CMS muon trigger is based on:1) Dedicated trigger detector (Resistive Plate Chamber)2) Muon chambers (Drift Tubes, Cathode Strip Chambers)

pt = 6 GeV

pt = 3.5 GeV

0

100

200

300

400

500

600

700

800

020

040

060

080

010

0012

00Z

(cm

)

R (cm)R

PC

CS

CD

rift T

ubes


Muon Trigger Summary - IMuon Trigger Summary - I

RPCs (barrel & endcap)• |η| < 2.1, strips of ∆η x ∆φ = 0.1 x 5/16°• 4 RPC stations compared to templates for

different pT ranges by Pattern Comparator ASICs• 144 φ segments/ring; 38 ring processors

Drift Tubes (barrel)• 2 φ, 1 z superlayers/stations (no z in station 4)• 6 rings (∆η = 0.35) of 12 φ segments• Bunch & Track Identifier forms superlayer r-φ

vectors by solving linear equations• Track Correlator combines two φ superlayers to

form a vector for each station• Trigger Server sorts vectors by quality & pT and

outputs 2 highest pT segments to Track Finder CSCs (endcaps)

• 6-layer CSC/station for 3 (upgrade to 4?) stations• Fast-shaped radial-strip pulses fed to Local

Charged Track processor to find coincidence in ≥ 4 out of 6 layers inside predefined roads

• Coincidence made with perpendicular anode wires to identify crossing

• Vector from each station sent to Track Finder


Muon Trigger Summary - IIMuon Trigger Summary - II

Drift Tube Track Finder• Accepts DT segments from Trigger Server• Accepts Segments from CSC Trigger in low

|η| barrel/endcap overlap region• Combines track segments into full tracks• Assigns pT and quality to each track

CSC Track Finder• Accepts CSC vectors from each station• Accepts Segments from DT Trigger in high |η|

barrel/endcap overlap region• Combines track segments into full tracks• Assigns pT and quality to each track

Global Muon Trigger• Separate Sort of 4 highest pT CSC, DT and 8

highest RPC PACT candidates forms Input• Examines "quiet bits" from calorimeter to

find isolated muons• Removes Ghosts• Outputs 4 highest pT muons to Global Trigger• Muons identified with ∆η x ∆φ ~ 0.1 x 2.5°• pT coded as 5 bits nonlinear; sign; quality

Muon Trigger structureRPChits

DThits

CSChits

PAtternComparator

Trigger

≤8 muontracks

(pt, η, φ, qual.)

local trigger

tracksegments

(φ, δφ, η, δη)

local trigger

tracksegments

(φ, δφ, η, δη)

regional triggerEndcap

Track Finder

≤4 muon tracks(pt, η, φ, qual.)

Global Muon Trigger

≤4 muons(pt, η, φ, quality)

regional triggerBarrel

Track Finder

≤4 muon tracks(pt, η, φ, qual.)

Track Finder

DT/CSC sorter

RPC

PACTprocessors

RPC ring sorter

RPC s/ring sorter

DT

BTI, TraCoTrig. Server

CSC

strip cardswire cards

motherboards

Global Trigger

Global Muon TriggerCALO quiet regions

CALO trigger

Port Cards

Bari

Warsaw

USADUBNA

BariWarsaw

Vienna

KoreaHelsinki

Padova, Bologna

Vienna

USABologna

RPC Pattern Comparator Trigger

Principle: pattern of hit strips is compared to predefined patterns corresponding to various p t.

MS 4

MS 3

MS 2

MS 1

LATCHES

LATCHES

pt

coding

4T

2T

MS4 MS3 MS2 MS1

RPC configuration in CMS

Interaction point

High Pt Muonpattern: (0,0,0)defined on 4 layerscode: (1,1,F)

Medium Pt Positive Muon pattern: (-4,4,4)defined on 3 layerscode: (0,0,A)

Segment i Segment i+1

code bit (5) - quality bit set to 1 if Muon defind on hits from 4 chamber;code bit (4) - Muon sign bit;code bits (3..0) - Muon Pt code

RPC Muon Station 4

Medium Pt Negative Muonpattern: (2,-1,-1)defined on 4 layerscode: (1,1,A)

RPC Muon Station 3

RPC Muon Station 1

RPC Muon Station 2 (reference)

Pattern Comparator (PAC) - idea

RPC Muon Trigger System

CMS Tridas Review, CERN November 9-13, 1998 Ignacy Maciek Kudla, Warsaw University

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PAC

PAC

PAC

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PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

PAC

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40 dies (10 packed, 30 unpacked) delivered March 98

All building blocks of every packed PAC tested.The results are following:

- PAC programming (via JTAG - 10 MHz clock): - 8 PAC's - OK; - 1 PAC - 1 pattern bank not accesible; - 1 PAC - intermittent error.

- cascade, mask circuit: - 10 PAC's - OK;- encoding circuit: - 10 PAC's - OK;- code selection circuit (demuxes): - 10 PAC's - OK;- pattern selection circuit (muxes): - fast test - logically OK but timing problem found at level of input buffer and dynamic logic: - 3/4 tracks are working from 30 ns clock, - 4/4 track code are extended to 2 bx's.

PAC test results :

SORTER &MERGER

MERGERMERGER

SORTER &MERGER

SORTER &MERGER

MERGER

SORTER &MERGER

VME CARD 2

VME CARD 1

VME CARD 3

VME CARD 4

SORTER &MERGER

MERGERMERGER

SORTER &MERGER

SORTER &MERGER

MERGER

SORTER &MERGER

VME CARD 6

VME CARD 5

VME CARD 8

VME CARD 9

SORTER &MERGER

SORTER &MERGER

MERGER

SORTER &MERGER

VME CARD 11

VME CARD 10

VME CARD 12

VME CARD 13

SORTER &MERGER MERGER

MERGER

MERGER

VME CARD 7

MERGER

MERGER

Sorting tree in Ring Trigger Crate

6*(7+1)

4*(7+4)

4*(7+5)

4*(7+6)

4*(7+7)

4*(7+8)

In Ring Trigger Crate:- 12 Sorter&Mergers,- 12 Mergers.Total all 33 Ring Trigger Crates:- 792 Sorter or Mergers

TRIGGER CRATE




Muon Chamber TriggersMuon Chamber Triggers

strips

wires

Q2Q1

Q3

+-

+ -- +- +

threshold

CSC

Comparators give 1/2-strip resol.

Hit strips of 6 layers form a vector.

m

43

21

12

34

Drift Tubes

Meantimers recognize tracksand form vector / quartet.

Correlator combines theminto one vector / station.

(DT)Drift Tubes (DT) Cathode Strip Chambers (CSC)

Out 0 Out 1 Out 2 Out 3 Out 4 Out 5 Out 6 Out 7 Out 8 Out 9 Out 10 Out 11

In 0 In 1 In 2 In3

OuterLayer

InnerLayer

µ

Xcal

Kcal

D = 23.7 cm

Track Correlator

Correlates BTIs in the inner and outer SuperlayersRefines the track measurement Applies noise filtering using θ-view information

Track Correlator

µ

1

4

3

2 9

9

6

7

8

5

Bunch and Track Identifier

Bunch crossing is detected using a generalized mean-timer methodAt the same time the track inclination and position are measured

HTRG Alignment of four hitsLTRG Alignment of three hits

Triggers

LTRG triggers close to a HTRG are suppressed (LTS mechanism)

Bunch and Track Identifier

0

100

200

300

400

500

600

-5 -4 -3 -2 -1 0 1 2 3 4 5

0

10

20

30

40

50

60

-15 -10 -5 0 5 10 15

Position Difference [mm]

All Triggers

Position Difference [mm]

Low Quality

Position parameter quality

σ ~ 0.7 mm

σ ~ 1.15 mm

BTI # 6in the right time slot

Time slot

Time slot

HTRG

LTRG

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ViennaPrototypeTrack-FinderTest Setup

Drift Tube Regional TriggerDrift Tube Regional Trigger

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Jay Hauser, UCLA TRIDAS Week, November 1998 11

Type Board SlotsCLCT 9 9ALCT 9 18MBT 5 5MBD 5 5MPC 1 1Total 29 38Fits two 9U crates

Trigger Crates

Each iron disk handles 12 sectors30o sectors on YE1 for ME1,60o sectors on YE2 for ME2 and ME3

Per sector:

Positions of 24 crates around the iron disks is under discussion.


‘98 Prototypes:48-ch LCT Card

Channel linkTo TMB

Input Gate Array Altera 10K50

Data selection

RAM tables128K x 8 bit

P0 Mezzanine Card

Comparators, A/D conversion

Output Gate ArrayAltera 10K20Priority encoders,

Sequencer

Buffers

Test points, LEDs

JTAG ports,Analog inputs,Ext Clk, Trig,

LEDs

CAMACGate Array

Altera 10K20

Software configurable as anode or cathode LCT


Comparator Study #2

Fit track in Layers 1,2,4,5,6, look at comparator bits in Layer 3.

•

Simple tracking results are good•No corrections for gain, xtalk, etc.→Energy-weighted means →Corrected means by sin(x) gives ~300um resolution

→


Anode BX Efficiency Summary

Run 183 at H2old gas, HV=3.9kV, θ=25o, φ=0o, µ+(225), 4x4cm triganode thresholds 15~58fC

Coincidence Level

Relative Timing

BX Efficiency

1 0ns 98.0 ±1.0%

2 +3ns 99.2 ±0.3%

3 +8ns 99.2 ±0.3%

4 +12ns 99.1 ±0.5%

5 +14ns 98.5 ±0.6%

6 +19ns 98.0 ±0.8%


CSC Trigger LayoutCSC Trigger LayoutTrigger Mother Boards in Iron Disk Peripheral Crates: US & Dubna EMU

Peripheral Crates:Rice

Backplane

Optical Links:Rice

Counting RoomCrates: UCLA

Counting RoomCrates: UCLA

Counting RoomCrates: Florida

6 Sector ProcessorCrates

10° 10° 10° 10° 10° 10°

20° 20° 20°

10° 10° 10° 10° 10° 10°

20° 20° 20°

10° 10° 10° 10° 10° 10°

10° 10° 10° 10° 10° 10°

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MuonPortCard

MuonPortCard

MuonPortCard

MuonPortCard

20°Sector

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SectorReceiver

SectorReceiver

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OVRSector

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cien

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pT [GeV/c]

Effi

cien

cy

0.85

0.9

0.95

1

0 10 20 30 40 50 60 70 80 90 100

Trigger efficiency [%] for 1 µ events

|η|<0.8 0 µ 1 µ >1 µ

RPC 4.49 ±0.10 95.49 ±0.61 0.02 ±0.01

DT 6.08 ±0.11 93.70 ±0.60 0.22 ±0.02

GMT 1.04 ±0.05 98.78 ±0.70 0.18 ±0.02

Trigger efficiency [%] for 2 µ events

|η|<0.8 0 µ 1 µ 2 µ >2 µ

RPC 0.24 ±0.03 8.98 ±0.22 90.72 ±0.93 0.05 ±0.02

DT 0.39 ±0.04 12.75 ±0.27 86.40 ±0.90 0.46 ±0.05

GMT 0.00 ±0.01 2.70 ±0.12 96.87 ±0.98 0.42 ±0.05

Global Muon Trigger

LV2 input 100 kHz / safety factor 3 = LV1 output 15+15 kHz

LV2 input 75 kHz / safety factor 3 = LV1 output 12+12 kHz

threshold 2-4 GeV means the minimal possible muon p t cut~4 GeV in the barrel, ~2 GeV in the endcap

L = 1033cm-2s-1 L = 1034cm -2s-1

trigger threshold rate [kHz] threshold rate [kHz]type [GeV] indiv. cumul. [GeV] indiv. cumul.ΣEt 150 1.0 1.0 400 0.5 0.5

Etmiss 40 2.1 2.8 80 1.3 1.7

e 12 10.3 12.3 25 6.8 8.3e e 7 1.5 13.1 12 1.5 9.5

j 50 2.0 13.5 100 2.1 10.7j j 30 1.6 13.9 60 2.2 11.6j j j 20 1.0 14.1 30 3.2 13.3j j j j 15 0.7 14.2 20 3.0 14.3e j 9, 15 6.0 15.2 12, 50 1.4 14.9µ 7 7.0 7.0 20 7.8 7.8

µ µ 2-4 0.5 7.3 4 1.6 9.2µ e/γ 2-4, 7 2.4 9.2 4, 8 5.5 14.4µ eb 2-4, 4 5.2 12.8µ j 2-4, 10 4.2 14.4 4, 40 0.3 14.3

µ Etmiss 2-4, 40 0.2 14.4 4, 60 1.0 15.3

µ ΣEt 2-4, 100 0.7 14.4 4, 250 0.2 15.3

µ 7 7.0 7.0µ µ 2-4 0.5 7.3

µ e/γ 2-4, 7 2.4 9.2µ eb 2-4, 4.5 3.3 11.1µ j 2-4, 15 2.0 11.9

µ Etmiss 2-4, 40 0.2 11.9

µ ΣEt 2-4, 100 0.7 11.9

Muon and Calorimeter Trigger Rates

LV1 output rate is reduced to the required limit by adjusting the trigger thresholds


Global Trigger SystemGlobal Trigger System

Final level-1 decision logic• 32 inputs with energy, coordinate, quality bits

• 4 muons, 4 isolated e/γ, 4 non-isolated e/γ• 6 jets & total number of jets above threshold• Total ET, Missing ET

• 128 Output Triggers• example:

1 µ > 20 GeV & 1 isolated e/γ > 10 GeV

Cards:• Pipeline Synchronizer & Buffer

• Aligns data from different subsystems• Global Trigger Logic

• Threshold & Comparator stages• Cuts on ET, pT, quality, η

• Global Trigger Final• Combinatorial logic array• Prescales

GLOBAL TRIGGERCRATE

10.11.98 A.T. HEPHY VIENNA

144 ISOLATION BITS=9 Channels with 16 bits

MUONS:4 RPC4 DT

4 CSC

GLOBALMUONTRIGGER

4EG4IEG4HAD

6JETETT

ETM

TECHNICALTRIGGERS12 CHAN=

12.24=288bits

AMP-Z-PACK 2mm BACKPLANECONNECTORS 488 pins

GLOBAL TRIGGER

CHANNEL LINK for 28 bits5LVDS pairs =10lines

CUSTOM BACKPLANE: VME + fast links

TTC

CAPACITY of Backplane: 40 ChannelLinks+88 CTRL lines

12 FREECHAN.

PSB12PSB12

9CHISO-bits

GTMU GTMU PSB12 PSB12 PSB12 GTL GTL GTF GTL PSB12

3 free

TIM

36 (40)CH24 CH<40 xx bits

GTFE

CLK+CTRL

GTFE LINKto GTFE

8GTFE LINKS

1-2DAQLINKS

DAQ TTC

Send 4MUONS viabackplane or frontpanel

4MUONS

**

**

PSB12=12Ch.PipelineSynchronisingBufferGTL =GlobTrigg Logic moduleGTF =GlobTrigg Final moduleGTFE=GlobTrigg FrontEnd moduleTIM = Timing ModuleGTMU=Global Trigger for MUONS

optional 80MHzparallelSYP

orXIN

28bits->5 diffPar->Ser

DPmem

VME

CLK, BCResStart

JTAG

1 of 12 CHANNELsoptionalparallel

28 bits LVDS

PSB OVERVIEW

5diff->28 bitsSer->Par

X_DPMBC_nrEvent_nr


CHANNELLINK

MIN. LATENCY: 3 bx PIPELINE DELAY5 bx FIFO DELAY

GTFELink

Readout processor

PIPELINE or FIFO DELAYSYNCHRONISATION by TTCrx40 MHz CLKBCRes....every LHC-cycleBC-counters

GTFEFrontEnd

Card

1 or 3 BX 1 BX1 BX

TIM

TIM

VME

TTC

GTL Logic module


PSB

FPGA

GTL-ovw.cdd

OR- LOGIC

CLK40CLK80

BCntRes

4 CHANNLINKS

PSB 4 CHANNLINKS

SETUPREGS

ALGO chip64 algorithms

PSB 4 CHANNLINKS

36 (40) CHANNELS=9(10) groups

128ALGORITHMS

128 CABLEDRIVERS

LATENCY 4 BX

OR CHIP:(3840+128)=3968 IO pins3968/12= 331 IO-pins

-->12 OR chips

24x4=96 signals

768x10=7680 bits--> 3840 nets

128 algo bits

96x10=960 input bits

80MHz transfer between ALGO and OR chips: bits/2=nr.of nets

ALGO CHIP: logic for 64 algorithms6 bits x 64 algor.=384bits384/2= 192 OUT-pins (80MHz)96 IN-pins(40MHz) ---> 288 IO-pins

-->20 ALGO chips

40MHz

80MHz

40MHz



1BX 1BX1BX 0.5BX 0.5BX

GTF

VME

ALGO chip forCalorimeter

Particles2.11.98

HEPHY VIENNA

PSB

FPGA

GTL-Algo_Calo.cdd

4 PARTICLES

SETUPREGS

LATENCY 3 BX

24x4=96 INPUTS at 40 MHz

80MHz transfer between ALGO and OR chips: bits/2=nr.of nets

COMP.MATRIX

1BX 1BX1BX

OR-chip

16 WindowComparatorsin ETA, PHI

TH(J)

ET(I) of4

Particles

ET(I,J)

FIND A-particlesFIND B-particles...........FIND F-particles

VME

LOGIC to FIND A-particles

Calculate 6 different numbersof calorimeter particles

6 bits

LOGIC for 1 CALO-ALGORITHM

64 CALO-ALGORITHMS

6bits x 64 algo. = 384 bits384/2=192 OUTPUTS at 80 MHz

N.(N+1)/2=10 COMP

GTF Final Logic module4.11.98 A.T HEPHY VIENNA

GTF-ovw.cdd

128ALGORITHM

BITS

GTLTTC

CLK40CLK80

BCntRes

JTAG

READOUT X_DPM

BC-numberEventnr

GTFEFrontEnd Card

128Pre-

scalers

FinalOR

logic

DPMTIM

DPM

DPM=Dual Port Memory

L1_ACCEPT

VMEReadout processor

GTFELink

setup by VME

Local Monitoring + Tests

CableDrivers

Events + Global Monitoring

Rec

eive

r +

reg

iste

r

MonitoringCOUNTERS

A.Taurok 2.11-98

Timing ModuleTIM

TIM-Ovw.cdd

TTCrx

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20 MHz

BCnrBCnr

GT-Backplane

Eventnr

Local 40MHz ClockClockChip

40 MHz Clock

80+20 MHz Clock

40 MHz

Eventnr*

Bus to allPSB+GTFmodules

Point2pointto all

modulesBCntRes

40 MHz Clock

LocalBC_Cntr

LocalEvent_Cntr

NewRun

L1Acc

SimL1Acc

X_DPM extracts data from DPM on GTF + all PSB boards.L1Acc extracts EVENT data.SimL1Acc simulates L1Acc.Read_Mon_Bx reads DPM data for Global Monitoring.

X_DPM

BCntRes

3to1MUX

X_DPM

*)Eventnr. with Mon/Event flag

L1Acc

2to1MUX

Mon BCnrLocal BCnr

VME

Global MonitoringRead_Mon_Bx

green=VME

SimL1Acc

TTC_ON

ClockFanout

BCntResFanout

TTC_onFanout

'

&

$

%

| CMS Synchronization Workshop, Nov 1998 |

Distribution of CLK and L1 to Front{End

TTCvi

DAQ

APVs

Underground counting room

FED FEC

FEM CCUM

TTCrx TTCrx

PLLPLL

Experimental hall

7)

5)

6)

4)

3)2)

1)

CLK + L1

L1LHC CLK

L1BX #

EV #CLK

B0

L1 delay along the critical path TTCvi ! FEM:

1) TTCvi (input) ! TTCrx (output): ' 135ns + 5ns/m (10 BX with

20m �bre)

2) TTCrx on FEC: programmable delay, foreseen to be set to zero

3) FEC, opto!electrical conversion: < 50ns ( < 2 BX)

4) FEC ! CCUMs: 90 to 120 m optical �bre ! 450 to 600 ns (18 to

24 BX)

5) Ring of CCUMs: ' 2m of electrical cables ! ' 20ns (< 1 BX)

6) CCUM: opto!electrical conversion + distribution via electrical cables

to the PLLs in the FE + (CLK+L1) decoding ! ' 75ns (3 BX) (?)

7) PLL on the FEM: programmable (�ne and coarse) delay

Impact on the latency

3

Initi

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atL=

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ates

at

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gle

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—21

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om p

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pt m

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(c-

and

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0 H

z fr

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ng a

t the

tim

e) f

or P

b-P

b—

mas

s st

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ty: ~

100

MB

/s—

equa

l rat

es fo

r m

uon

and

calo

rimet

er tr

igge

rs—

max

. eve

nt s

ize

(cen

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col

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ns):

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ger

stra

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Hz

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ttle

or n

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duct

ion

need

ed a

t hig

her

leve

ls

Det

ecto

rO

ccup

ancy

k B

ytes

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el b

arre

l<

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%30

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yers

+ 4

dis

ks~

10 %

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AL

full

(1 ti

me

slic

e)10

0 %

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AL

full

100

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Muo

n D

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SC

+RP

C<

0.1

%54

TOTA

L~1

.5 M

B

Str

ateg

y fo

r dim

uon

trig

ger


CMS Trigger OrganizationCMS Trigger Organization

TriDASS. Cittolin

Trigger:W. Smith

DAQ:S. Cittolin

Calorimeter: W. Smith

Muon: G. Wrochna

Global: C. Wulz

Primitives:P. Busson

Regional: W. Smith

Global: G. Heath

Rd.& Ctrl: S. Silva

RPC: Krolikowski

CSC: J. Hauser

DT: P. Zotto

Trk Find:F. Szoncso

Global:A. Taurok

Processor

Monitoring

The Compact Muon Solenoid. SC 1998

Trigger cost book 9

103

CMS Cost Estimate - Version 9 Release Date: March 31, 1998

No. Item Unit Type # Units Unit Cost Total Cost

6.1.1 CALORIMETER TRIGGER 5225 0

6.1.1.1 Regional trigger System 1 4050.020 4050

6.1.1.2 Global Cal. Trigger System 1 400.000 400

6.1.1.3 Readout & Control System 1 255.000 255

6.1.1.4 Data Communication System 1 520.000 520

6.1.2 CSC TRIGGER 1100 0

6.1.2.1 Muon Port Card Board 63 7.475 471

6.1.2.2 Sector Receivers Board 65 4.217 274

6.1.2.3 Sector Processors Board 15 7.020 102

6.1.2.4 Overlap Processors Board 15 7.020 105

6.1.2.5 Clock and Control Card Board 12 5.233 63

6.1.2.6 Crate Monitor Card Board 10 1.300 13

6.1.2.7 Trigger Crate Crate 10 7.107 71

6.1.2.7 Institute Manpower Manyears 0 0.000 0

6.1.3 DT TRIGGER 780 0


6.1.3.2 Sector Processor Card Board 60 8.000 480

6.1.3.3 Muon Sorter Card Board 5 8.000 40

6.1.3.4 Clock and Control Card Board 4 4.000 16

6.1.3.5 Crate Monitor Card Board 4 2.000 8

6.1.3.6 Cables Cables 1 50.000 50

6.1.3.7 Readout and Control System 1 32.000 32

6.1.3.8 Monitoring and Test System 1 70.000 70

6.1.3.9 Prototypes and spares System 1 60.000 60

6.1.3.10 Institute Manpower Manyears 0 0.000 0 0

6.1.4 RPC TRIGGER 3695 0

6.1.4.1 Link Board Board 936 0.475 445

6.1.4.2 Data Communication System 1 755.160 755

6.1.4.3 Trigger Board (Barrel) Board 156 3.830 597

6.1.4.4 Trigger Board (EndCap) Board 240 3.350 804

6.1.4.5 Final Sorter Board Board 33 1.600 53

6.1.4.6 Readout board Board 396 0.700 277

6.1.4.7 Readout Concentrator Board Board 33 1.000 33

6.1.4.8 Clock Control Board Board 33 4.000 132



6.1.4.11 ASICs Development Service 1 200.000 200

6.1.4.12 Prototypes and spares System 1 100.000 100


6.1.5 GLOBAL TRIGGER 1340 0

6.1.5.1 Global Trigger Crate Crate 1 27.046 27

6.1.5.2 PipelineSyncBuffer Board 5 8.290 41

6.1.5.3 Global Trigger Logic Board 5 12.168 61

6.1.5.4 Global Trigger Final Board 1 5.199 5

6.1.5.5 Cables Cables 1 4.070 4

6.1.5.6 Global Muon Trigger System 1 158.272 158


6.1.5.8 Prototypes System 1 32.700 33

6.1.5.9 Monitoring & Test System 1 80.000 80

6.1.5.10 Trigger Throttle System System 6000 0.150 900



M&S for Crates, Boards & Cables:

WBS Item Unit Cost Number Total 3.1.2.4 Power Supplies 3,600 22 79,200 3.1.2.5 Crates 600 22 13,200 3.1.2.6 Backplane 5,910 22 130,020 3.1.2.7 Clock & Control Card 2,960 22 65,120 3.1.2.8 Receiver Card 8,870 176 1,561,120 3.1.2.9 Electron ID Card 3,690 176 649,440 3.1.2.10 Jet Summary Card 4,670 22 102,740 3.1.2.11 Cables $1/ft 7,300 7,300

Cost Detail Ex: Regional Cal. Trig $Cost Detail Ex: Regional Cal. Trig $

Detail for Boards:

Card Size Board Assmbl. Parts TotalBackplane crate 1,000 300 4,610 5,910Clock & Control 9Ux280mm 600 400 1,960 2,960Receiver 9Ux400mm 800 650 7,420 8,870Electron ID 9Ux280mm 400 300 2,990 3,960 Jet Summary 9Ux280mm 600 500 3,570 4,670

Detail for ASICS (WBS 3.1.2.2):

ASIC NRE Cst/Prt #/RC #/EIC #/JSC Tot.#Adder (GaAs) 50,000 179 3 0 2 520 Phase (GaAs) 50,000 360 8 0 0 1,280 Sort (GaAs) 80,000 300 0 1 2 200 Electron ID(GaAs) 80,000 300 0 2 0 320 Bndry. Scan(GaAs) 50,000 150 1 1 1 340

(costs per part are included in board parts costs above)

Tas

k N

ame

Tri

gg

er S

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m

Initi

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n

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plet

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itial

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TD

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ricat

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Trig

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s

Inte

grat

ion

& T

est w

/DA

Q &

FE

Inte

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test

Trig

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Fin

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trig

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com

pone

nts

Fin

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trig

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prod

uctio

n

Fin

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trig

ger

deliv

ery

Fin

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trig

ger

com

mis

sion

/3/9

711

/4/9

8

11/4

/98

11/4

/98

11/3

/99

11/3

/99

11/4

/99

11/2

/00

11/4

/99

11/2

/00

11/2

/00

8/24

/00

12/7

/00

12/7

/00

11/2

/00

4/9/

01

4/10

/01

10/1

/01

7/1/

01

7/3/

017/

1/03

1/1/

021/

2/04

7/1/

02

7/2/

026/

30/0

4

3/3/

039/

2/04

8/27

/03

8/28

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2/25

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4/5/

05

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04

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1/05

Jul

Jan

Jul

Jan

Jul

Jan

Jul

Jan

Jul

Jan

Jul

Jan

Jul

Jan

Jul

Jan

Jul

997

1998

1999

2000

2001

2002

2003

2004

2005

W. S

mith

, U. W

isco

nsin

CM

S T

RIG

GE

R S

CH

ED

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1/18

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Pag

e 1

Janu

ary,

199

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3

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30

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Inst

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Apr

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ests

Apr

30

Fin

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Trig

ger

Sys

tem

Tes

tsS

ep 9

Oct

Apr

Oct

Apr

Oct

Apr

Oct

Apr

Oct

Apr

Oct

Apr

Oct

Apr

Oct

Apr

Oct

Apr

Oct

Apr

1996

1997

1998

1999

2000

2001

2002

2003

2004

2005


Trigger Milestone ListTrigger Milestone List Level 1 (1998-2000)

• Nov. 1998 Complete Initial Trigger Design:• Algorithms finalized

• Functional blocks determined

• Numbers of ASICs, boards, cards and crates specified

• Interfaces specified

• Trigger geometry determined

• Nov. 1999 Complete Phase 1 Prototype Design:• Designs of boards, cards

• ASICs for prototype tests done

• Nov. 2000 Phase 1 Prototype Tests Finished:• All tests necessary to begin design of production electronics

are complete

• Nov. 2000 Technical Design Report

Level 2 (1998-2000)• Nov. 1998:

• Complete Initial Muon Trigger Design

• Complete Initial Calorimeter Trigger Design

• Complete Initial Global Trigger Design

• Nov. 1999:• Complete Prototype Muon Trigger Design

• Complete Prototype Calorimeter Trigger Design

• Complete Prototype Global Trigger Design

• Nov. 2000:• Prototype Muon Trigger Tests Finished

• Prototype Calorimeter Trigger Tests Finished

• Prototype Global Trigger Tests Finished


Trigger Milestone ProgressTrigger Milestone Progress 1998 L1 Milestone:

• Nov. 1998 Complete Initial Trigger Design:• Algorithms finalized• Functional blocks determined • Numbers of ASICs, boards, cards and

crates specified• Interfaces specified• Trigger geometry determined

• Status: Complete

1998 L2 Milestones:• Nov. 1998:

• Complete Initial Muon Trigger Design• http://cmsdoc.cern.ch/ftp/afscms/TRIDAS/mutrig/html/

• Complete Initial Calorimeter Trigger Design• http://cmsdoc.cern.ch/ftp/afscms/TRIDAS/caltrig/html/

CalTrig.html

• Complete Initial Global Trigger Design• http://sungraz.cern.ch/CMS/trigger/globalTrigger/

Welcome.html

• Status: Complete

Janu

ary,

199

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