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Nuclear Instruments and Methods in Physics Research A 518 (2004) 525–528

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doi:10.1016

Trigger electronics for the Alice PHOS detector

Hans M .ullera,*, Rui Pimentaa, Luciano Musaa, Zhongbao Yinb, Dieter R .ohrichb,Bernhard Skaalic, Iouri Sibiriakd, Dmitry Budnikove

aCERN, Division EP, Geneva, SwitzerlandbDepartment of Physics, University of Bergen, NorwaycDepartment of Physics, University of Oslo, Norway

dKurchatov Institute, Moscow, RussiaeRFNC VNIEF, Sarov, Russia

Abstract

The Photon Spectrometer of ALICE consists of 5 identical modules of 56� 64 PWO crystals with a total of 100�

azimuthal coverage of the barrel. The electronics required for implementing both the L0 trigger for high luminosity p–p

physics and the L1 trigger for high pT Pb+Pb physics has been studied. A full integration of the trigger logic into the

detector’s enclosure is based on analog transmission of fast trigger sums between stacks of front-end boards and trigger-

router units. The latter contain 112 digitizer channels of 10 bit, which are mapped into a single FPGA per trigger unit,

covering areas of 24� 16 crystals. The running modes allow for Level-0 trigger at 800 ns and Level-1 at 6200 ns trigger

latencies. The design and status of the PHOS trigger electronics are outlined.

r 2003 Elsevier B.V. All rights reserved.

PACS: 07.05.Hd

Keywords: Trigger electronics; Photon spectrometer; Altro-16 digitizer; Programmable logic

1. ALICE electromagnetic calorimeter PHOS

The PHOS (PHOton Spectrometer) covers 100�

of azimuthal angle of the barrel below the ALICETime Projection Chamber (TPC). It is situated atradius of ca. 4.6m from the interaction center [1].

A cradle structure within the all-surroundingmagnet supports 5 piecewise linear PHOS modulesover a length of 8.2m. The detector presents atotal surface of ca. 8m2 with 17920 lead tungstate(PWO) scintillator crystals embedded in five

onding author. Tel.: +41-22-767-3533; fax: +41-

.

ddress: hans.muller@cern.ch (H. M .uller).

- see front matter r 2003 Elsevier B.V. All rights reserve

/j.nima.2003.11.076

distinct modules. Each module maps exactly oneof the five 20� sectors of the TPC, providing singleregions-of interest per TPC sector.

Within a module’s cold zone, PWO crystalassemblies are operated at �25�C in order toincrease the light-yield by a factor of B3compared to room temperature. The readout andtrigger electronics is embedded in the warm zonesbelow the crystals.

1.1. Crystal strips

Each PHOS module consists of 56� 64 crystalsof 2.2� 2.2� 18 cm3. Avalanche Photo Diodes

d.

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Fig. 1. One of 224 strip units within a PHOS module: 16

crystals are grouped by one T-connector.

H. M .uller et al. / Nuclear Instruments and Methods in Physics Research A 518 (2004) 525–528526

(APD) with a sensitive surface of 5� 5mm2 [2]are glued to the end of each crystal. As depictedin Fig. 1, a strip unit consists of two rowsof 8 crystals, which are mounted on metalsupport beams. It’s APDs and associated pream-plifiers provide 2� 8 analog signals to a T-shapedconnector that passes them from the cold to thewarm zone where they are picked up by shaper/digitizer/trigger electronics.

2. PHOS level-0 and level-1 triggers

Simulations [3] show that optimal triggerefficiency requires charge summing within crystalareas of 4� 4. With a fixed analog sum input of2� 2 to the FPGA-based trigger units, a triggerefficiency of 95% is achievable by applying a 4� 4sliding window method over the whole triggerregion.

2.1. Level-0 trigger

The PHOS level-0 trigger is conceived as aminimum bias trigger for p–p interactions at alatency of 800 ns. The FPGA logic is sensitive toenergy deposits in at least one 2� 2 kernel matrix.At thresholds of 5MeV and 200 kHz interactionrate, the geometrical acceptance is 35 kHz, hencewith an occupancy of 0.1% the channel rate is35Hz.

After subtraction of signal delays, the bareelectronics trigger processing time in hard-ware is 200 ns. The following algorithm isexecuted:

(1)

2D domain: sample-wise charge summing ofall 4� 4 windows in parallel.

(2)

Time domain: pipelined summing of all 2Dsums in consecutive samples.

(3)

Threshold comparison per window sum. (4) Peak finder lookup for LHC clock phase. (5) OR’ed output L0 YES.

A NRZ signal, synchronous with the 40MHzclock of the LHC machine outputs an L0 decisionfrom the FPGA at ca. 600 ns after collision. Thisallows the NRZ signal to arrive in time (800 nsmax.) over 40m cable at the central triggerprocessor.

2.2. Level-1 trigger

The level-1 trigger is sensitive to high pT

photons in Pb+Pb interactions at a maximumlatency of 6.2 ms. At pT > 9GeV/c and an interac-tion rate of 8 kHz the occupancy is 40%. With anL1 acceptance rate per channel of ca. 3 kHz, signalpileup is negligible.

Within the pure electronic L1 processingtime of 5.6 ms, more ADC samples than for L0can be processed and three different thres-holds (low, middle high pT) can be applied, eachproviding one trigger output. A precisepeak finding relative to the LHC clock phase ispossible using a scalar product method forsignal peak finding [4], for which coefficients aredetermined offline according to a known pulse-shape.

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3. Embedded electronics

The PHOS digitization and trigger electronics isembedded in the warm zone below the crystals.Each group of 4� 8 crystals generates 32 analogchannels. T-shaped adapters pass these signals intothe warm zone where 32-channel Front EndElectronics (FEE) cards perform the shaping,digitization, bufferization and 2� 2 analog signalsumming. Two stacks of 7 FEE cards areinterconnected left and right to one Trigger RouterUnit (TRU) of size 340� 215mm. Fig. 2 shows theconnectivity per TRU unit, each covering adetector area of 32� 14 crystals.

With 14 FEE cards, each outputting 8 analogsums, the TRU card contains 112 ADCs on 56multiplexed receivers with programmable gain/attenuation. The digitized data channels of the 14FEEs are read out via the GTL bus of the TRU.

The latter combines the readout of both energyand trigger channels via an address-mapped read-

Fig. 2. Connectivity of one-eighth PHOS module (448 crystals

out protocol like in the Alice TPC where anexternal Readout Control Unit (RCU) [5] mastersthe data transfer to the DAQ system and providestiming and control information to the embeddedPHOS electronics.

3.1. Front end electronics (FEE) card

In order to cover a pT range up to 100GeV/c, 32energy channels are digitized with a resolution of12 bits per crystal using two 10-bit ADCs and adual gain shaper of 1.6 ms shaping time. Inaddition, 8 trigger channels are obtained by analogsumming of rectangular 2� 2 crystal groups with afast shaping time of 100 ns.

3.1.1. Analog sums

A FEE-card resident bias voltage regulation perAPD provides that the error in the 2� 2 analogsums is at the 1% level. The PWO light output is95% within 50 ns, therefore the L0 algorithm

): 14 FEE digitizer cards and 1 TRU trigger-router unit.

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can be processed taking only two 50 ns ADCsamples.

3.2. Trigger router unit (TRU) card

The TRU receives analog signals from the FEEon 56 multiplexed, differential inputs correspond-ing to 112 ADCs. The common digitizer technol-ogy for both the energy and trigger channels is theALTRO-16 chip [6]. Eight of its ADCs are readout in ‘‘fast mode’’ at a 20MS/s sampling rate inphase with the LHC clock. From the available10 bits only 8 bits are required to digitize quadsums. A programmable amplifier/attenuatoradapts the dynamic ranges for the low and highthreshold modes. One TRU card handles 448crystals within a single Altera Stratix [7] FPGA of25K logic elements. The algorithms for the L0 andL1 modes of operation have been described inSection 2. The FPGA trigger outputs NRZ-encoded trigger decisions at 40MHz. For readoutand configuration, the FPGA is memory-mappedto the GTL bus of the RCU.

4. Trigger logic

The FPGA on the TRU cards receives digitizedADC samples from 14 FEEs every 50 ns andoutputs NRZ-encoded, 40MHz Yes/No decisionsat a fixed latency relative to the moment ofinteraction.

4.1. Level-0 logic

Within only 200 ns decision time, ‘‘4� 4 slidingwindow’’ scans are implemented as 91 parallelFPGA processes and comparisons with L0 thresh-olds. The peak finding relative to the 40MHz LHC

clock phase is implemented via a lookup table. Thehistory of L0 Yes trigger samples can be read outvia the RCU.

4.2. Level-1 logic

With 5.6 ms decision time, L1 is a more refinedprocess, similar to L0, however based on moreADC samples and a more precise peak finding.Three L1 outputs correspond to low, middle andhigh pT thresholds. L1 also provides a hit-map ofFEE cards allowing skipping empty FEEs duringthe readout.

Acknowledgements

The PHOS electronics has been inspired by thefront-end electronics of the ALICE TPC.

References

[1] Photon Spectrometer PHOS, Alice Technical Design

Report, CERN /LHCC 99-4, 5 March 1999.

[2] S8664-55 Avalanche Photo Diode, Hamamatsu http://

www.hpk.co.jp/Eng/main.htm.

[3] D. Rohrich, L0/L1 triggering with PHOS, Presentation of

Simulation results in ALICE week, April 2003.

[4] V. Buzuloiu, et al., Opt. Eng. 35 (6) (1996) 1576ff.

[5] R. Esteve-Bosch, et al., Readout control unit of the front

end electronics for the ALICE time projection chamber,

Proceedings of the Eighth Workshop on Electronics for

LHC Experiments, September 2002, Colmar, France.

[6] R. Esteve Bosch, et al. The ALTRO Chip: A 16-channel

A/D converter and digital processor for gas detectors,

Proceedings of the IEEE NSS/MIC, November 2002,

Norfolk Virginia.

[7] EP1S25 Altera Stratix programmable logic, http://www.

altera.com.