An On-Chip Trimming Technique for CMOS Voltage References

Kevin Parker

A thesis submitted to the Department of Electrical and Computer

Engineering in conformity with the requirements for

the degree of Mister of Science (Engineering)

Queen's University

Kingston, Ontario, Canada

June, 1991

Copyright 0 Kevin Parker, 1997

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June, 1997 KcvinPazker

Abstract

A bandgap voltage reference can be implemented in a standard CMOS process using parasitic

vertical bipolar transistors to extract the bandgap voltage. The implementation of a predictable

design requires three well matched resistors to create the feedback nekork and a very low offset

op amp to drive i t To overcome the problem of poor device matching it is necessary to be able to

trim the process mismatches out of the h a 1 design. Most conventional metbods of trimming are

expensive and require extra processing procedms. For low cost mixed-signal applications it is

necessary to use an on-chip trimming technique to reduce the effect of process variations.

By using mode connected MOSFETs as the resistive devices in the fetdback network, a num-

ber of advantages are realized. Most importantly, they allow two methods of on-chip trimming.

MOSFETs can be trimmed by adjusting either their gate voltage or their threshold voltage (FIT).

Although, VT is generally considered a fixed process dependent property, adjusting the buIk

potential of the MOSFET causes a change in VT through the body effect When triode MOSFETs

are fabricated in their own device wells they can have their bulk potentials controlled indepen-

dently allowing VT adjustment. A simple R-2R ladder DAC can be used to control the substrate

potential of these input devices to ailow a permanent trimming of the op amp. Trimming through

the substrate is more accurate than trimming through the gate at the cost of some trimming range.

Any offset in the op amp can be removed by applying a similar technique to individually

adjust the threshold voltages of the transistors in the op amp's input stage.

W1th these trimming techniques it is possible to create a voltage reference that will have an

output voltage of - 1.369V that is accurate to lmw This accuracy is limited mostly by the temper-

ature response of the circuit and not the matching capabilities of the trimming network.

Acknowledgments

Fist and foremost, I would like to thank my supervisor Dr. David 6. Naim. He was a source

of guidance and provided a great deal of insight to the praject. I would also like to thaak the

National Sciences and Engineering Research Council, Queen's University and Micronet for their

generous financial support. The Canadian Mcrotlectronics Corporation (CMC), Mite1 and

Nortel were instrumental in providing fabrication services for prototype chips. The Department

of Physics at Queen's University deserves thanks for supplying test equipment to the project. As

well Dr. Al P. Freundorfer should be thanked for providing the software used for modelling the

BJTs as well as the expertise required for its use. Thaaks should as well be given to Aapool

Biman who provided many interesting discussions during the come of the work. I would also

like to thank my fiancee Jodi Gmdmont for putting up with me over the last couple of years.

Finally, I would like to thank my parents for all of the support they have given me over the years.

June. 1997 KcvioPdccr

Table of Contents

.. .. Acknowledgments . ...o.o.o.o..oooo.w,.oo~.o..o..o...ooo...~....... u

List of Figures .w.....a............. .oooooooo.~owo.... ............................... vi

1.0 Introduction to Voltage References ............ ..,.,,.....,1

1 . I Types of References ..................................................................................... 2 ..................................................................... 1.1.1 MOSOnIyReferences 3 ................................................................. 1.1.2 Buried Zener References .5

......................................................................... 1.1.3 Bandgap References 6 .......................................................................... 1.1.4 Mixed References I1

1.2 Curvature Compensation ..................................................................... 1 3

1.3 Trends in Voltage References ..................................................................... 14

............................................. 1.4 The Push for an Accurate CMOS Reference 17

References .................................................................................................. 19

. . ........................................................................................ 2.1 Cmwt Overview 21

2.2 Bipolar Transistors In CMOS .................................................................... 23 2.2.1 Implementation of Bipolar Transistors in CMOS .......................... 24 2.2.2 Modelling Bipolar Transistors in CMOS ...................................... -26

2.3 Resistors in a Digital CMOS Process ....................................................... -27 2.3.1 Resistor Trimming ......................................................................... 30

2.4 The Op Amp .............................................................................................. 32 ................................................................................................. 2.5 Summary 34

References .................................................................................................. 36

3.0 Modelling Vertical Bipolar Junction ~ F S . , ~ . , ..oo.o~.oow.owoow.o.ow.. ~owowoooow~7 ......................................................................... 3.1 The Gummel-Pam Model 37

............................................................. 3.2 SauctureoftheBipolarTraasistor 40

......................................................... 3.3 Modelling From Process Parameters 46 ............................................. 3.4 Modelling From a Measured Test Structure -49

3.5 Summary .................................................................................................... 53 References .................................................................................................. 54

.. Design of ltimmoble Resistors and The Op Amp ~~~..~.....~~e...~.~~m 55 4.1 Resistor Implementation ........................................................................... 56 4.2 Resistor Trimming .....................................................................................

4.2.1 R-2RDACImplementation ........................................................... 63 4.2.2 Counterhplementation ................................................................ 68

4.3 Charge Pump Design ................................................................................. 70

4.4 Op Amp Design ........................................................................................ -75

4.5 Control Circuitry ........................................................................................ 83

4.6 Summary .................................................................................................... 86

References .................................................................................................. 88

Experimental R Q S U l t s ~ o o m o m o e e o o - * o o o o o o o o e o e o o o o o o o o o o o ~ o o o o o o o o ~ w o ~ ~ e m o ~ w ~ ~ o e o m o ~ ~ o o e o o e m o 8 9 5.1 The Charge Pump ...................................................................................... 89

............................................................................... 5.2 The Voltage Reference 95 5.2.1 Op Amp Operation and Trimming ................................................. 97 5.2.2 TotalReferenceCircuitTrimming .......................................... 101

5.3 Summary .................................................................................................. 104

C O I ~ C I ~ O ~ O O ~ O ~ ~ O o ~ O O O ~ O o O O O O O O ~ O ~ ~ H O ~ O O O O ~ O O * O ~ O H O ~ W W O o ~ ~ O ~ O H O ~ O o O o O O O ~ ~ O e O e ~ e e O ~ O O O ~ O ~ O ~ ~ O O O ~ O O O O ~ O O ~ O ~ 1 0 6

........ . Appendix A Theoretical BJT Model Qmtio I~s.,,.... ...~ee~~~..~.m.~~m~109 Appendix B . Reference Test Circuit Description m ~ ~ ~ ~ ~ o o m o ~ o o ~ m ~ e o e ~ ~ m o o ~ ~ o o 111

Vita .................................................................................................................... 114

List of Tables TABLE 1.1 . TABLE 2 . 1 . TABLE 4.1 . TABLE 4.2 . TABLE 4.3 . TABLE 4.4 . TABLE 4.5 . T B L E 5.1 . TABLE 5.2 . TABLE 5.3 . TABLE 5.4 . TABLE 5.5 . TABLE B.1-

Trends in Reference Voltages ................................................................. 16 Typical Sheet Resistance Values for Various CMOS Structures .............. 2 8 Final Resistor Parameters ...................................................~...................... 59 T Flip-Hop Truth Table ............................................................................. 69 Charge Pump Component Parameters ....................................................... 75 Device Sizes in the Final Op Amp ............................................................. 80 Op Amp Specifications .............................................................................. 80

........... Major Design Parameters for the Different Charge Pump Designs 92 ...... ................... Summary of Charge Pump Test Chip ~easurements .. 93

............ Comparison Between Measured and Simulated Op Amp Results 98 Measured Trimming Results .................................................................... 100 Resistor Trimming Specifications .......................................................... 103

....................................................................................... Pin Descriptions 112

List of Figwes Figure Number Figure Title

Page Number

............................................................................................. MOS Voltage Reference 4 Zener Voltage Reference ............................................................................................. 5

.............................................. Temperature Dependence of the Base-Emitter Voitage 7 .................................................................................... Bandgap Reference (Original) 9

........................................................................................ Bandgap Reference (New) 10 ..................................................................................... CMOS Bandgap Reference 1 3

.................................................................... Trimmable CMOS Bandgap Reference 21 Lateral NPN ....................*..............................................................................*.......... 24 Vertical NPN ............................................................................................................. 26

.................................................................... I-V Characteristic of a Silicon Resistor 29 .................................................................... Typical CMOS Process Cross Section 3 1

Op Amp Schematic ................................................................................................... 32 ....................................... Amplifier With Bulk Connections On The Input Devices -33

............. Equivalent Circuit Model for The GummeI Poon Model used by HSPICE 38 ................... Typical 1- Relationship for an NPN Bipolar Junction Transistor .40

Parasitic Bipolar Layout ........................................................................................... 42 ................................................................... Comparison of Device Doping Profiles 44

.............................................. Comparison of Measured Data and Modelled Curves 52 .................... .......... High Level Circuit Schematic ............................................... 56

................................................................... NSPICE Plot of Temperature Response 60 Effect of R2's Trim Voltage On The Temperature Response of the Reference ........ 61

....................................................................... Resistor Trimming Circuit Overview 62 R-2R DAC Structure ................................................................................................. 63 Current to Voltage Converter .....................................*.............................................. 65

.............................................................................. R-2R Implementation in CMOS -66 ............................................................................. Current Output of the R-2R DAC 67

Voltage Output of the R-2R DAC ............................................................................. 68 ........................................................................................ Ripple Counter Schematic 69

'I' Flip-Flop Schematic .................................................~............................................ 70 Charge Pump Schematic ..............................................*............................................ 71 Plot of Runping Action ............................................................................................ 72

.............................................................................................. Plot of Start-up Ramp 74 Op Amp Schematic ........................*.......................................................................... 76

.......................................................................... Find Op Amp Design Schernatic Op Amp Trimming Circuit ............................................................................... 8 1 Comparator Schematic .............................................................................................. 83

Figure Number Figure Title

Page Number

Control Logic Trming Diagram ..................................................~............................. 85 Control Logic Schematic ...........................................................~............................ ..86 Charge Pump Schematics ..........................................~.............................................. 90 Chip Photo of Charge Pump Test Chip ..................................................................... 92 Reference Chip Schematic .......................~................................................................ 96 Chip Photo of Voltage Reference Test Chip ............................................................. 97

................... Effects of Varying Resistor Substrate Voltages on Reference Output A02 ...................................................................................... Reference Chip Schematic 111

vii

List of Symbols

Symbol Definition Temperature Coefficient for the threshoId voItage Threshold voltage process parameter

Permittivity of fke space - 8.85~10-'~ F/m Coefficient of barrier lowering Bulk potential in a MOSFET, accounts for substrate doping.

Carrier mobility, H, for electrons c(p for holes

Distance fkom the emitter surface to the start of the emitter-base depletion region Distance from the emitter surface to the end of the ernitter-base depletion region

Gain fkom the gate inputs to the output

Gain h m the bulk inputs to the output

Top view area of the emitter

Distance from the emitter surface to the start of the base-collector depletion region

Distance from the emitter surface to the end of the base-collector depletion region

Maximum forward current gain for a BJT, HSPICE model parameter DAC input bit number 'x' where, bit 0 is the least signifmnt bit

MOSFET gate oxide capacitance per unit area

Diffusion constant of minority carriers in the emitter, base and collector respectively. Unity gain frequency

Base to collector current in the HSPICE model of a BJT Base to emitter current in the HSPICE model of a BJT Collector to emitter current in the HSPICE model of a BJT Full scde DAC current DAC output current

Base current for a BJT

Collector current of a BJT

Collector current in a BJT biased at Vh0 and To

Drain source current of a MOSFET

High current roll off factor for a BJT. HSPICE model parameter

June. 1997 KNiDFxkec

Symbol Definition IS, IS T~il11sport saturation cunent in BJT, HSPICE model parameter

Current density in the base of a BJT

Boltzmann's Constant - 1.38~10'~ J/K MOSFET conductivity parameter MOSFET gate length BJT process parameter - usualIy ranges between 1 and 2 for silicon BJTs

hainsic electron concentration of silicon - 15x10 ~ r n - ~ at room tempera- ture

Doping densities of the emitter, base and collector respectively

Charge on an electron - 1.6x10-~~ C Resistance value Resistor values in the reference circuit. Output resistance of a transistor

Temperature Maximum temperature at which the reference output is considered valid

Minimum temperature at which the reference output is considered valid

Temperature coefficient of the reference Initial temperature of a BJT

Bias voltage for a device

Bandgap voltage of silicon at absolute zero - 1.1 N

Negative input voltage to an op amp or comparator

Positive input voltage to an op amp or comparator

Differential input voltage applied to the bulk contacts of a differential pair

DifTerential input voltage applied to the gates of a differential pair

Maximum reference output voltage between the temperatures T,, and Tmin

Minimum reference output voltage between the temperatures T,, and T-

Output of the voltage reference

Difference between the supply rails

Thermal voltage for a p-n junction - - 25.9 mV at room temperature

Forward early voltage for a BJT, HSPICE model parameter Difference between the base emitter voltages of two separate BSTs

Base to emitter voltage in a BJT

Symbol Definition

VBEO Baseemitter voltage of a BJT biased at To and Ic0

v~~ Base-collector voltage for the BJT

v c ~ v c ~ Collectoremiaer voltage of a BJT

Vmc Zero bias junction potential for the base collector junction

High power supply voltage

Drain source voltage of a MOSFET

Gate to source voltage of a MOSFET

Avo Change in the reference output voltage.

Input referred offset voltage for a comparator or op amp

Voltage across resistor labelled R2

W s Change in the supply voltage

v s ~ Source to substrate (bulk) voltage

v~~ Low power supply voltage

v ~ . v~ MOSFET threshold voltage

v~~ MOSFET threshold voltage at absolute zero

VTO HSPICE model parameter corresponding to Vm

w MOSFET gate width

June, 1997 Kcvin PYjFtt

1.0 Introduction to Voltage References

The increasingly high density of digital CMOS processes coupled with new advances in Digi-

tal Signal Processing @SP) is sparking a desire to be able to implem&t mixed signal systems on

a single chip. To realize a single chip implementation an accurate voltage reference is required to

perform conversions between the analog and digital domains.

DSP has advanced to the point that signal processing is generally easier in the digital domain

than in the analog domain. The high density that can be achieved with today's digital processes

allows very compact implementations of DSP chips. Since these chips can be condensed into

such a small area it makes sense to try and include the leading analog to digital converter (ADC)

and the trailing digital to analog converter (DAC) on the same chip. A system that can be imple-

mented on a single chip gains many speed and power advantages over a multi-chip design.

Since CMOS processes are ideally suited for digital design it is makes sense to try to imple-

ment good data converters in these processes. This presents some problems that do not occur in

bipolar only processes or mixed BiCMOS processes. Since digital circuits are very tolerant of

inaccuracies in the devices from which they are composed, typical digital CMOS processes do not

have extremely accurate device specifications. Therefore. matching between devices is typically

quite poor.

Since the push for single chip implementation has been on for some time now there have been

many advances in the accuracy of ADCs and DACs. In many cases the accuracy of these devices

is limited by the accuracy of the voltage reference that is necessary for the conversion. When

high accuracy is required an external device is often needed to supply the reference voltage. This

is especially true in the case of CMOS components. Current external references can have accura-

cies in excess of 14 bits (0.006%) [I] while cumnt CMOS references can have accuracies as

poor as 6 bits (1.695) [2]. Since single chip CMOS designs are desired, it is necessary to create a

voltage reference with a much higher degree of accu~itcy.

There are a number of characteristics that are desirable in a high quality voltage reference. It

is important that the reference can deliver a very cons& voItage over many varying conditions.

Changes in the supply voltage should not cause significant changes in the output voltage of the

reference. The effects of temperature on the output of the device should also be minimal. Finally,

two identical references should have the same output characteristics.

There has been a great deal of effort directed towards reducing the effects of temperature on

the output of these devices. References are now being constructed that have very flat temperature

responses and very Little dependence on the power supply voltage. However, the output of two

identical references can have differences of above 1.646 [2]. These references can easily have

temperature dependences lower than 0.196 [3] over a range. In many cases it is the accu-

racy of the actual output voltages of identical devices that limits the performance of the system.

The question of how to make the devices more accurate and st i l l maintain a constant output

voltage is an interesting one. A valid design should be implemented in a standard CMOS process

and have an accurate continuous DC output that doesn't require any extra processing to achieve.

1.1 Qpes of References

There are various different methods of designing a voltage reference. Of these there are about

four major categories that the different designs can fall into. These categories generally describe

either the technology in which the reference is constructed or the method of deriving the constant

output voltage. In MOS techno10gies the most obvious way of deriving a refemnce voItage is

through the use of the threshold voltage (b). Very accurate refmnces often use buried Zener

diodes. In strictly bipolar processes the emitter base junction of a BJT can be used to derive the

bandgap voltage of silicon for use as a refmnce voltage. Finally, it is possible to create bipolar

transistors, in a MOS process, that are adequate to extract the bandgap voltage of silicon. These

can be used with other MOS circuitry to produce a reference voltage.

1.1.1 MOS OnIy References

Since there is a big push to be able to implement mixed signal applications on a single CMOS

chip there have been numerous different attempts to design a good voltage reference using only

CMOS components. The most obvious method of producing a CMOS reference uses the differ-

ence between OKO different threshold voltages to extract the constant reference voltage.

The threshold voltage can be described as

Vr = VTo-aT (1.1)

where, VTo is the threshold voltage at absolute zero and a is the temperatwe coefficient of the

threshold voltage. If a process exists in which there are two different threshold~voltages for the

same type of device (either NMOS or PMOS) then these two voltages can be subtracted to pro-

duce the desired temperature independent voltage at the output. If the devices are of the same

type it is assumed that they will have a similar temperature dependence but have different Vm.

The gate voltage Vm is given by

If I,, and K are the same for the two different types of transistors then the difference between

their gate voltages will give an output that is strictly the di&rence between their threshold volt-

ages. A circuit that extracts this difference is shown in Figure 1.1 [4].

In this figure the transistor that is circled is the device that has the lower threshold voltage.

The feedback in the circuit will strive to make the two inputs of the op amp equal. If the two

resistors are matched they will have identical currents when the op amp inputs become equal.

This implies that the currents though the MOSFETs will be equal. The op amp must set VGs2 to

achieve this equal cturent condition. We now have the equal current condition required for

equation 1.2. The output voltage will be the difference between VGsl and VGSZ which is strictly

the difference between their threshold voltages.

A difference in threshold voltages can be achieved in a number of ways. The difference

between enhancement and depletion devices can be used or a lower threshold device can be cre-

ated by leaving out the threshold adjust implant that is added in many processes. Extra processing

steps are sti l l required if depletion mode devices are desired but a lower threshold device does not

add processing.

The lower thnshold method looks promising since no extra processing is required However,

the implant under the gate region is poorly controlled and this step has a direct impact on the

actual threshold voltage. So whik it may be possible to build a temperature stable device it is dif-

ficult to obtain a device that will yield an accurate output voltage h m die to die.

1.1 -2 Buried Zener References

The most basic type of reference that can be constructed uses the reverse breakdown voltage

of a zener diode. An example of a simple zener reference circuit is shown in Figure 1.2. This

type of reference can usually be made very accurateIy. The reference has very little dependence

on the supply but it does have a fairly strong temperature dependence. Another major problem

with this reference type is the large amount of noise generated by a diode in its Zener breakdown

region. Some of this noise can be eliminated if the zener diode is buried in the substrate away

from the surface giving rise to buried Zener references [I].

These references can be made well in a special process that is optimized for creating low noise

buried Zener diodes. A Zener reference is typically used in applications where extremely high

precision is necessary. The tailor made processes that are required are generally significantly

more expensive than a standard digitaI CMOS process which makes a buried zener reference a

poor choice for inexpensive mixed signal ICs. However, bipolar processes offer an alternative for

the construction of a voltage reference.

1.13 Bandgap References

The next major step in reference sources is the bandgap reference. This type of reference

uses the base emitter junction of two or more bipolar transistors to extract the OK bandgap voltage

of silicon. By using two transistors the hear temperature dependence of the bandgap voltage can

be canceled out.

The voltage across the base emitter junction of a transistor, for a collector current Ic0 and a

temperature To, is given by

where Vg, is the bandgap voltage of silicon extrapoIated to 0 K and V' is the base emitter volt-

age of the transistor at Ic0 and To 151. The third term containing the natural log of T is small and

can be ignored in a first order approximation. Figure 1.3 shows a plot of equation 1.3 for different

values of Ic [6]. From this it can be seen that the baseemitter voltage has an almost linear rela-

tionship with temperature. The logarithmic term plays very little role in the response of the

device to changes in temperature. If the terms that are proportional to Tare cancelled out, a con-

stant bandgap voltage, of approximately 1.2V, remains. This is only approximate because V' is

June 1997 KevinRrk

an extrapolated quantity that depends on the values of To and I& The actual bandgap voltage of

silicon at OK is 1.17V [n.

A circuit capable of creating a voltage proportional to absolute temperature can be used to

cancel the temperature dependence of the base-emitter voltage. This will create a reference volt-

age that is essentially independent of temperature variations.

The difference between the base emitter voltages of two transistors with different current den-

sities provides a voltage with the proper temperature dependence. For two transistors biased with

June, 1997 Kevin P a k r

different collector currents ( I , al l of the terms in equation I 3 are the same except the final term,

q') q rco . Therefore if we take the difference between two base emitter voltages we get,

If the transistors are identical the values of Icol and Icoz will be the same. However, if they have

different base areas they may have different values of Im with dl the other parameters being

constant. From equation 1.4 we can see that with either a difference in collector current or a dif-

ference in base area a temperature dependent voltage can be created. It is therefore the cunent

density that is the important factor. Equation 1.4 can be simplified as,

where JI and Jt are the current densities through the two transistors.

The

cient of

perature

major temperature component in equation 1.3 gives VBE a negative temperature coeffi-

around 2 m V E at a temperature of 20°C. For a current density ratio 3 of 10 the tern- 4

coefficient of AVBE is 0.2mVPC. If the current density ratio is increased to 1000 the

temperature coefficient only increases to 0.6mVPC. It is apparent that an unreasonably high cur-

rent ratio would be required to make AVm large enough to cancel the temperature coefficient of

VBE. In order to cancel the temperature dependence of the base emitter voltage it is necessary to

amplify AV' Typically a current ratio of 10 and a gain of 10 are used to cancel the temperature

effect of the bandgap voltage. These are quite easily realized using standard circuit techniques.

The original circuit used to cancel the tempera- dependence is shown in Figure 1.4. It was

developed by RJ. Wdar in 197 1 [5].

The ratio of R1 to R2 sets up a collector current ratio. This ratio controls the difference

between the baseemitter voltages of Q1 and 42. AV' appears across R3. Since the collector

current is approximately equal to the emitter cumnt, the voltage across R2 is,

The voltage at the collector of 42 is set by the base voltage of 43. The voltage at the output is

therefore,

June. 1997 Kevin P a r k

Using equation 1.6 we can more fully express this as,

A newer version of the circuit is shown in Figure 1.5. This circuit uses the properties of an op

amp to perform the addition of the two voltages. In an ideal op amp the voltage difference

between the two input terminals is zero. Since Vm appears at the positive terminal it must also

appear at the negative terminal. This means that AV' appears across R3. The current 12 flows

through both RZ and R3. As in the previous circuit the voltage across R2 is given by

equation 1 -6. The output voltage has the same form as before,

June. 1997 Kevin P a r k

The circuit in Figure 1.5 initially looks more complicated than its predecessor in Figure 1.4.

However, the newer circuit has a few advantages over the original. Instead of using a third tran-

sistor to obtain the baseemitter voltage it takes the base-emitter voltage from one of the transis-

tors that is utilized in calculating AVBE- Therefore, it only needs two bipolar transistors to derive

the reference voltage. Both of these BJTs are also connected to one of the supply rails in the

newer design. In the original design it is necessary to have a bipolar transistor (42) that can have

all of its terminals floating between the supply rails.

At a 6 n t glance, these two small differences don't seem to warrant the extra circuit complex-

ity of an op amp since an op amp is typically constructed from many bipolar transistors. How-

ever, if we use a CMOS op amp we now have a circuit that requires only two fairly simple bipolar

transistors to be able to create a good bandgap voltage reference.

1.1.4 Mixed References

It has been seen that MOS only references cannot provide the accuracy required for the needs

of today's signal processing. It is also apparent that in standard integrated circuit technologies the

best type of voltage reference is a band gap reference. If it is possible to combine a CMOS pro-

cess with bipolar devices, references could easily be developed that would be compatible with

digital designs. Commercially available BiCMOS processes can integrate both bipolar and MOS

devices on a single chip. Unfortunately, these processes are much more expensive than a standard

digital CMOS process and are therefore not a valid alternative. However, it is possible to create

two types of bipolar transistors in a digital CMOS process without adding any process steps.

These transistors may not be high gain or high speed devices but they function consistently from

chip to chip. Therefore, they can be used to extract the bandgap voltage for a reference.

June. 1997 Kevin EWccr

The most versatile type of bipolar transistor that can be created in a CMOS process is a lateral

device. The lateral bipolar transistor uses the standard MOSFET structure to create a transistor

whose base current flows laterally below a gate structwe- Standard operation suffers h m surface

effects under the gate so a large reverse bias is necessary to push the carriers deeper into the sili-

con. This transistor, while it is versatile requires extra biasing to make it operational.

A more simple transistor can be constructed if the substrate is allowed as a terminal. This

type of device will have a vertical current flow from the emitter which is composed of a source

conract to the collector which is made h m the substrate, with the base being constructed from a

device well. The major drawback is obviously that all of the collectors are counected to the same

potential through the substrate and due to other factors related to the operation of the standard

CMOS devices on the chip, this node must be comected to one of the power supplies. This

restriction seems prohibitive but with some slight modifications to the circuit in Figure 1.5 these

simple devices can be used to create a bandgap reference. The required modifications are shown

in Figure 1.6.

The only changes between this new circuit and the one in Figure 1.5 is the type of transistor

used to extract the bandgap voltage. The transistor is still connected in a diode configuration but

the op amp can now be constructed soIeIy tkom MOS devices. This circuit is very suitable for

implementation in a standard digital CMOS process. It gives a well controlled output voltage

and does not require any special processing.

June. 1997 Kwin Parker

1.2 Curvature Compensation

All of the circuits discussed to this point are designed to cancel the hear temperature depen-

dence of the base-emitter junction. The baseemitter voltage from equation 1.3 has a small term

that is not Linear with temperature. This term can be ignored unless you want to achieve accura-

cies greater than ImV over a 100°C temperature range. The temperature dependences, of the ref-

erences discussed above, have a slightly parabolic shape that is the result of the non-hear tern,

- ln (5) in equation 1.3. If this &rm can be elimiOafed then the circuit will theoretically 4

have a completely flat temperature response. The final term in equation 1.3, 4

be used cancel this logarithmic temperature dependence. If Ic is given a linear temperature

June, 1997 Kevin Parker

dependence these two terms can cancel each other out. The process of eliminating the parabolic

curve in the output voltage of the reference is termed curvatwe compensation.

1.3 Trends in Voltage References

Most of the research that has been directed at voltage references deals with eliminating the

temperature dependence. The result has been some circuits that do an excellent job of curvature

compensation. References with very low temperature coefficients have been created. Table 1.1

shows how the research has progressed over the years. It lists many of the major papers dealing

with voltage references. The emphasis of the table is references that have applications in CMOS

technologies. Some of the more important specifications are listed to give an idea of what has

been done to try to improve voltage references.

The first column in Table 1.1 lists the reference number that corresponds to the number of the

paper in the reference section at the end of the chapter. The second column contains the year in

which the paper was published This gives an idea of how current the information is as well as

showing the direction that research has taken over time.

The third column gives the nominal reference voltage that was achieved by each design.

Notice that most of the references have an output voltage that is close to 1.17V which is the band-

gap of silicon.

The fourth column gives a measurement of the temperature dependence of the different refer-

ences. This temperature dependence is measured by taking the maximum and minimum voltages

and dividing by the temperature range over which the device is intended to operate.

Junc 1997 Kevin Pyktr

This method of measurement can be slightly misleading. When the temperature dependence has

a parabolic shape it can be made to look better by making the allowable temperature range smaller

and centering it right at the minimum of the parabola. Since there are many different standard

ranges for allowable operating temperature, it is hard to accurately compare these values unless

the range over which the reference is measured is known. Even so, the numbers st i l l suggest that

references have come a long way in the past 25 years.

The next column states the accuracy of the reference. This number gives an idea of how close

the actual reference voltage will be to what has been designed. It gives an indication of how the

process variations effect the output of individual references.

The power supply rejection ratio is an indication of how much power supply fluctuations

will affect the output It is measuredas

PSRR = 20 - log [y -

where, AVs is the change in power supply voltage and AVO is the change in the output voltage.

All references have a range of valid supply voltages that can be used to power the reference. This

range is shown in the Supply Voltage columns.

The table also shows whether the reference was implemented in a standard Bipolar or W S

process or if it was implemented with a Special process. The method of deriving the voltage is

also given. As stated above most references are derived from either a band gap voltage (BG), a

threshold voltage (VT) or the breakdown potential of a zener diode (2).

Many of the papers only publish the specifications that directly affect what they are trying to

improve. As a result, since most of the papers are trying to improve the temperature response, a

significant number do not state what kind of accuracy their designs can achieve.

Ref

#

5

10

11

12

4

13

6

14

1

15

9

16

17

18

19

20

3

2

21

Y m

1971

1973

1974

1976

1978

1978

1979

1980

1980

1980

1983

I984

I985

1989

1991

1993

1995

1995

1996

V=f

Volts

5

9-880

2.5

2.5

4.2

-

1-25

5.000

12

1.158

1.192

130

1.2281

0.200

2.48

6 2

-

1.236

0.200

TC

ppmPC

200

4

5

4.2

5

85

22

0.3

300

0.5

13

43

30

6

20

15

9

85

20

Tech

BlMlS

Acc.

%

Area

m2

Type

BGRNT

- - 2

- 10

-

4

0.004

5

- 0.083

2

0.028

-

0.1

0.4

- 1 -6

PSRR

dB

Power

pW

70

- - -

76

- -

113

- -

60

64

77

-

67

90

-

95

-

- -

1.5

-

0.045

- 0.43

- -

4

22.5

0-4

0.18

- -

0.43

0.063

0.07

-

r

-

30000

- -

3000

- -

650000

0.2

1400

12000

-

34

95

do00

4800

1500

loo0

5

Supply

Min

B

B

B

B

M

M

M

S

M

B

M

M

M

M

M

B

M

M

B

Voltage

Max

6 5

13

4

- 12

- -

11.4

2

5.5

10

5

1.7

1 -0

- 10

-

BG

BG

BG

BG

VT

VT

BG

Z

VT

BG

BG

BG

BG

BG

BG

BG

BG

BG

BG

35

30

- 25

-

40

10

15

- - -

2.0

- - -

2.7

- 5.5

-

June. 1997 Kevin EW&r - - - -

1.4 The Push for an Accurate CMOS Reference

As stated above the drive for single chip implementations of mixed signal systems has made it

very desirable to be able to design analog circuits in processes that are optimized for digital

CMOS circuitry. There have been many advances in the accuracy of DACs and ADCs in the

recent past. However, many of these systems still require a very accurate off chip voltage refer-

ence to function properly. Complete on-chip mixed signal systems will be realizable if an accu-

rate on chip implementation of the voltage reference can be created

Through an overview of the previous research it has become apparent that a bandgap type of

reference is probably the best choice for implementation on a CMOS chip. The bandgap voltage

carries with it an inherent temperature dependence. There has been a lot of research directed at

eliminating this temperature dependence to the point where voltage references can be designed

that have temperature dependences of less than 10 p p d C .

The output of these references is very flat across the allowable operating temperatures but the

actual output voltage is not reproducible &om chip to chip. Poor device matching in digital

CMOS processes is at the root of this problem. As a result it is difficult to obtain a reference that

has an output accuracy that varies by less than 1% from chip to chip.

Does it make sense to design a chip with an extremely flat temperature response if the output

voltage is not going to be accurate? Less research has been devoted to making a very accurate

design than has been devoted to eliminating the temperature dependence. Since the temperature

coefficient of many references is now significantly lower than the accuracy that can be achieved,

it would be beneficial to design a reference that can create a more accurate output voltage.

June. 1997 Kevin Parker

1.5 Overview

A CMOS bandgap reference has been designed that can tdm itselfele~tronically~ This refer-

ence uses the substrate comection of various MOSFETs to crim out mismatches that result from

process variations. The trimming requires no extra processing steps so it will not add any cost to

the fabrication of the chips in a standard CMOS process.

Chapter 2 is an overview of the design. It deals with the major components and what type of

operating specifications are required of them.

The vertical bipolar transistors are discussed in Chapter 3. Transistor models and methods of

deriving them for the devices in question are examined. The theoretical and empirical models

that were used in the design are presented-

The design and trimming of the op amp and resistors is considered in Chapter 4. Design con-

siderations and final circuit diagrams of the op amp and resistors are looked at Other trimming

and support circuitry is also covered in this section. The design is done in the absence of noise

because the output, noise of the voltage reference will be dominated by noise that is external to the

actual reference circuit-

Chapter 5 examines the results of fabricating some test circuits that investigate different

aspects of the design. Measured operating specifications are compared to simulated data.

The final chapter offers a brief conclusion and some insight into problems that may be

encountered when attempting a design such as this. Mmcations that can be made to the exist-

ing design to enhance its performance are also discussed.

June, 1997 K& Parker

References

D. P. Laude and I. D. Beasom, "5 V Temperature Regulated Voltage Reference," IEEE Jour- nal of Solid State Circuits, VOI. SC-15, pp. 1070-1075, Dec. 1980.

R. J. Reay, E. H. Klassen and G. T. A. Kovacs, "A Micmmachinsd Low-Power Tempera- ture-Regulated Bandgap Voltage Reference," IEEE Journal of Solid State Circuits, vol. 30, pp. 1374-138 1, Dcc. 1995.

IS-M. Tham and K Nagataj, "A Low Supply Voltage High PSRR Voltage Reference in a CMOS Process," IEEE Journal of Solid State Circuis, vo1- 30, pp. 586-590, May 1995.

R. A. Blauschild, P. A. Tucci, R S. MuLler and R G. Meyer "A New NMOS Temperature- Stable Voltage Reference," IEEE Journal of Solid State Circuits, vol. SC- 13, pp. 767.773, Dec. 1978.

R. J. Wddar, "New Developments in IC Voltage Regulators," IEEE Journal of Solid State Circuits, vol. SC-6, pp. 2-7, Feb. 1971.

E. A. Vittoz and 0. Neyrwd, "A Low-Voltage CMOS Bandgap Reference," IEEE Journal of Solid State Circuits, vol. SC-14, pp. 573-577, June 1979.

C. Kinei, Introduction to Solid State Physics, 6th Edition, New York: Wdey, 1986, pg. 185.

E. A. Vi noz, "MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMGS Technology," IEEE Jouml of Solid State Circuits, vol. SC-18, pp. 273-279, June 1983,

B-P. Song and P. R. Gray, "A Precision Curvature Compensated CMOS Bandgap Refer- ence," IEEE Journal of Solid Stute Circuits, vol. SC-18, pp. 634-643, Dec. 1983.

K. E. Kuijk, "A Recision Reference Voltage Source," IEEE JoumI of Solid State Circuits, vol. SC-8, pp. 222-226, June 1973.

A. P. Brokaw, "A Simple Three-Terminal IC Bandgap Reference," IEEE Journal of Solid State Circuits, vol. SC-9, pp. 388-393, Dec. 1974.

G. C. M. Meijer and J. B. Verhaff, "An Integrated Bandgap Reference," IEEE Journal of Solid State Circuits, voi. SC-11, pp. 403-406, June 1976.

Y. P. Tsividis and R. W. Ulmer, "A CMOS Voltage Reference," IEEE Journal of Solid Stare Circuits, vol. SC- 1 3, pp. 774-778, Dec. 1978.

H. J. Oguey and B. Gerber, "MOS Voltage Reference Based on Polysilicon Gate Work Function Difference," IEEE J o u d of Solid State Circuits, vol. SC-15, pp. 264-269, June 1980-

G. C. M. Meijer, P. C. Schmde and K Van Zalinge, ' A New Cwature-Corrected Bandgap Reference," IEEE Joumul of Solid State Circuits, vol. SC-15, pp. 1139-1 143, Dec. 1980.

June. 1997 Kevin Parker

J. Michejda and Suk. K Kim, "A Recision CMOS Bandgap Reference," IEEE Journal of Solid State Circuits, vol. SC-18, pp. 1014-1021, Dec. 1984.

M. G. R. Degrauwe, 0. N. Leuthold, E A Vittoz, H. J. Ogwy and A. Descombes, C'CMOS Voltage References Using Lateral Bipolar Transistors," IEEE Jounral of Solid State Cir- cuits, vol. SC-20, pp. 115 1-1 157, Dec. 1985.

M. Ferro, F. Salerno and R Castello, "A Floating CMOS Bandgap Voltage Reference for Differential Applications," IEEE Joumul of Solid State Cimuits, voi. 24, pp. 690-697, June 1989.

G. Nicollini and D. Senderowicz, "A CMOS Bandgap Reference for Differential Signal Processing," IEEE Journal of Solid State Circuits, vol. 26, pp. 4 1 -50, Jan. 199 I.

M. Gunawan, G . C M Meijer, J. Fonderie and J. H. Huijsing, " A Curvature-Corrected Low- Voltage Bandgap Reference," IEEE Journal ofSolid Stare Circuits, vol. 28, pp. 667-669, June 1993.

A. van Staveren, C. J. M. Verhwven and A. H. M. van Roexmund, 'The Design of Low- Noise Bandgap References," IEEE Transaction on Circuits and System - I: Fundamental Zbeory and Applications, vol. 43, no. 4, pp. 290-300, Apr. 1996.

2.0 The Voltage Reference Cirmit

The need for a more accurate voltage reference has been examined, From Chapter 1 it is

apparent that there is a need to be able to trim voltage reference circuits in order to overcome the

effects of process variations and thus, provide a higher accuracy output There has been a great

deal of research focused on creating very temperature insensitive references in various technolo-

gies. Given that methods exist for greatly reducing the temperature dependence of voltage refer-

ences the design emphasis has been placed on increasing the accuracy of the reference circuit's

output voltage.

2.1 Circuit Overview

The basic design, shown below, is similar to the mixed reference discussed in the introduc-

tion. Accuracy of the reference is controlled by the matching of the resistors, the offset of the op

amp and the ability to fabricate a reproducible bipolar device in CMOS. To deal with the problem

of mismatched resistors and the op amp offset we can create structures that allow these effects to

be uimmed out of the circuit. However, the question of creating a reproducible bipolar device in

CMOS seems to be the k t major problem to overcome in designing a voltage reference.

f unc, 1997 Kevin Parker

The size of the transistors and therefore the &sired current density through them is important

in determining the appropriate resistor sizes for the reference. Larger devices will require larger

bias currents which implies smaller resistors in the feedback network. The current flowing

through the two bipolar transistors is one of the major factors atkcting the minimum possible

power consumption of the circuit. However, it should be noted that if the circuit is designed to be

able to drive a large load the power consumption will be significantly more than this minimum.

Since low power consumption is desired, it is beneficial to use the smallest transistors available.

Once the transistor bias points have been determined the resistor values that are required to

achieve these bias points can be considered. In order to keep the power in the reference as low as

possible, large resistor values are necessary in the feedback netwok The size of these resistors

will be limited by physical size constraints imposed by the implementation of the resistors.

As in any circuit, the requirements for the op amp are defined by the needs of the rest of the

circuit. The voltage reference circuit operates at DC therefore the bandwidth of the op amp is not

a critical factor. However, the DC offset of the op amp will have a significant effect on the output

voltage of the reference [I]. A high gain is required in the op amp to force its inputs to remain

approximately equal because the assumption that the two inputs to the op amp are held at the

same potential was vital in determining the output voltage of the reference. As the gain of the op

amp increases this assumption becomes more valid. Finally, the op amp must have a low enough

output resistance to be able to supply the cumnt needed in the feedback network. If the resistors

are large, as is expected from the previous discussion, this output resistance can have a fairly high

value. While meeting these design specifications it is also desirable to keep the quiescent power

consumption of the op amp to a minimum.

June, 1997 Kcrin Pyktr

2.2 Bipolar TMlnsistors In CMOS

There are two major problems that face designers attempting to use BJTs in a CMOS process.

Since a CMOS process engineer doesn't intend for people to use bipolar devices, there are no

standard architectures for the transistors. The lack of standard bipolar architectures means that,

even if a bipolar device can be created, models for these devices will not exist. As in any design

the lack of good models reduces the effectiveness of the simulation tools available to the designer.

With some restrictions it is possible to create two types of bipolar devices from the standard

structures available in a digital CMOS process. One of these structures is similar to a lateral bipo-

lar device that might be seen in a typical bipolar process. The other is similar to that of a standard

vertical device that can be found in most bipolar processes.

An ideal BJT has certain characteristics that should be taken into account. The doping of the

device should follow a specific pattern. The emitter should have the highest doping level, fol-

lowed by the base, with the collector having the lowest doping level. In an ideal device the base is

typically very narrow to improve the speed of the device. Having a nanow base helps reduce the

amount of charge that can be stored on the base and in turn improves the device's switching

speed. Finally, the collector should have an area much larger than the emitter to aid in collecting

as many charge carriers as possible. This wiU improve the current gain of the device.

When implementing a bipolar transistor in a CMOS process it is not possible to control these

parameters since only the standard CMOS structures can be used. The designer cannot change

any of these process parameters.

Typically either NPN devices or PNP devices are available in any given CMOS process. Both

types of devices are not available due to constraints imposed by the process. In both of the smc-

June. 1997 Kevin M e r

tures that will be examined the base of the transistor is constructed from a device well. Most

CMOS processes only offer one type of device well since one type of MOSFET can sit in the

actual substrate of the chip. The type of device well availabIe in the process will define which

type of bipolar device can be constructed. Therefore, in a pwell process only NPN devices can

be fabricated.

2.2.1 Implementation of Bipolar 'Ikansistors in CMOS

The first type of transistor is a lateral transistor that has a cross-section similar to that in

Figure 2.2 [2]. These lateral transistors arrange the standard MOSFET structure into a topology

that will function as a bipolar transistor. Unfortunately they do not have ideal transistor character-

istics.

. - - - -

Bias Bias

From Figure 2.2 it is apparent that the collector and emitter have the same doping and not the

large doping difference that is required by an ideal BJT. The base region in these lateral transis-

ton is also considerably wider than is generally desired. Since the current flow between the col-

lector and emitter is lateral and near the gate junction, these devices suffer from many problems

associated with surface effects. To eliminate these effects a substantial reverse bias on the gate

structure is required to push alI of the charge carriers away from the surface. With a sufficient

bias the laterai device will act as a true bipolar transistor.

In addition, the substrate in the lateral device stnrcture acts as a pamsitic collector terminal

drawing current away from the intended collector and reducing the current gain of the transistor.

This parasitic terminal reduces the performance of the lateral device, although the device st i l l

operates as a typical BJT.

The parasitic device seen in the lateral transistor can be implemented by itself to create a ver-

tical BJT [3]. This type of transistor is shown in Figure 2.3. The vertical device is much more

straightforward than the lateral device but it has one major draw back. In order to create the col-

lector it is necessary to use the substrate as an active terminal in the transistor. This means that

the collector voltage of a l l vertical devices on a single chip must be connected to the same poten-

tial. Depending on the type of process this wiU be either the highest or lowest potential in the cir-

cuit. A p-type subsrrate is always the Iowest potential in a circuit and an n-type substrate is

always the highest. At first this seems like an very prohibitive constraint but after examining the

circuit in Figure 2.1 it is apparent that these vertical devices can be configured to extract the

bandgap voltage [4].

While the lateral bipolar device is more versatile, the added complexity that it introduces

makes it an unattractive option. This complexity stems from both the construction of the device

as well as its modelling. Since the gate bias has a large impact on the operation of the device, it

is difficult to create an accurate model for design purposes. It may even be necessary to create

different models for different bias conditions.

June. 1997 Kevin PYkcr

Collector Emitter Base

Although the vertical bipolar device is very restricted in its operation, it can be utilized in the

bandgap circuit that is under consideration. Since it is the simplest to implement and it pedorms

the desired function the vertical device is the best choice for extraction of the bandgap voltage in

this situation. A vertical BJT also brings with it the advantage of having a very standard model.

2.2.2 Modelling Bipolar Ttansistors in CMOS

In many situations the lack of a model that is tailored to the particular design being considered

is the major factor that separates simulations fiom the real world. In this instance however, the

problem is a complete lack of models for the bipolar transistors. Any technology that is comrner-

cially available to designers will have device models that can be utilized by a designer in simulat-

ing potential designs. The manufacturers of standard CMOS processes don't intend for the

designer to use bipolar devices in their processes so they do not create models for these types of

structures. It is therefore up to the designer to decide what parameters are the most critical and

create his own transistor model.

In the reference circuit the baudgap voltage is derived fkom the emitter-base diode characteris-

tic of two transistors. From Figure 2.1 it is apparent that the circuit only utilizes diode c o ~ e c t e d

transistors. Therefore, the important models parameters are those that define the diode character-

June. 1997 KcviaParker

istics of these bipolar devices. Also, since the reference operates at DC with no AC components,

the capacitance values and other dynamic modei parameters are less important.

The model for the bipolar transistor can be created in two ways. The best way to create a

model involves fabricating test structures that can be tested and analyzed to develop an empirical

transistor model. A designer can also use certain process parameters to arrive at a theoretical

model of the devices in question [a. The empirical models are inherently better since they

model the actual operation of the device. However, the turn around time on a design that uses

empirical models is extended Therefore, theoretical models can be used while the test structures

are being fabricated and tested to arrive at an initial estimate for required resistor values. Once

empirical models are available small optimizations can be made to the original resistors to

improve the overall performance of the reference.

2.3 Resistors in a Digital CMOS Process

In a bandgap reference circuit the majority of the circuit properties are defined by the resistor

values that are used. Since these values must be fine tuned in order to achieve a design that is

insensitive to temperature variations, their matching is extremely important.

In most digital CMOS processes there are no standard structures for the sole purpose of imple-

menting resistors. This makes it diflicult to create a resistor that will perform well. Through the

use of various structures in CMOS processes a number of adequate resistors can be created.

Some typical sheet resistance values for a CMOS process are shown in Table 2.1.

TABLE 21 - Ippicol Sbcct RcsiotoMw V d m for Various CMOS Sbrrctater

MOS resistors suffer from various problems. For most resistor structures available in MOS

processes the I-V characteristic is not a straight line (See Fi,oure 2.4). Since the majority of these

resistors must sit in the substrate, there is the possibility that a forward biased p-n junction can be

formed. This situation must be avoided by the designer. The resistance value of these types of

structures is strongly dependent on their doping. These doping levels are poorly controlled in a

standard digital CMOS process.

s m l c ~ t l ~

N+ Diffusion P+ Diffusion Poly Silicon Gate P-field in P-Well Metal hterco~ect

P-type M O S W

Since minimum power dissipation is desirable, it is necessary to use large resistor values in

the feedback network of the voltage reference. From Table 2.1, the two best choices for imple-

menting large resistors are MOSFET resistors and P-field resistors. Both of these devices suffer

from non-linearity probIerns. The P-field resistors also suffer from the threat of a forward biased

Resistance R/Square

50 100

20

3000

0.05

1 lo00

p-n junction. AU of these effects can be accounted for in the design of the voltage reference.

However, the uncertainty of the doping of the devices makes the final value of the resistance

uncertain.

1 a For a square triode connected device with a maU VDs and IVGSI=5V

June. 1997 Kevin Parker

N+ D i e i o n Resistor 25 pm long 20 pm wide

Voltage (V)

GURE 2.4 - I-V C- of a S- . . . .

Since a very predictable output from the circuit is desired, a method of adjusting the resistance

values must be available to fix the problems that will occur due to process variations. Electroni-

cally adjusting the resistance vaIue of a MOSFET resistor after fabrication is straight forward

The P-field resistors can probably be trimmed by varying the potential of the well in which they

sit but this is a very poorly defined relationship and is therefore not suitable for the design at hand.

The best method of implementing the required resistors in CMOS uses a MOSFET connected

in the triode mode of operation. The current in a MOSFET in the triode region is given by,

June. 1997 Kevin Parker

For small values of V' the second order term can be ignored and the MOSFET acts as a resistor

with a value of,

I Cul In a typical 1 . 5 p process' an NMOS device has -pCox = 40-. This makes equation 2.2, 2 d

From this equation it is apparent that larger resistance values can be created easily with a triode

l device. By simply making the - ratio large we can arrive at a large resistance value. A low VGS

W

value can also create a larger resistance at the cost of increased non-linearity.

23.1 Resistor Trimming

The mode transistor method of implementing resistors wiU not sufficiently reduce the process

variations to a level that will allow the desired output accuracy- A solution to the matching prob-

lem exists if the MOSFETS are built in their own device wells. PMOS and NMOS devices

require different substrates. In any CMOS process, one of these devices must be built in a sepa-

rate device well that has the opposite doping of the substrate (See Figure 2.5). Since these

devices sit in their own device wells the potential of their bulk connections can be varied indepen-

dently. The result of this variation is w e d the body effect. Varying the bulk potential allows

the effective adjustment of VT through the relationship,

- -

1. Provided by Mite1

June, 1997 Kcvin PYlra

where VTO is the zero bias threshold voltage, y is a process parameter, ab is termed the bulk

potential which accounts for the doping of the substrate and q is the coefficient of barrier lower-

ing by VDs.

n-gate P e t e n-bulk n-source 1 n-drain p-drain I p-source pbulk I

FIGIJRE 2 5 - 'RQW

From equation 2.3 it is apparent that adjusting VT will allow the resistance value to be

trimmed. The resistor value is much less sensitive to changes in Vm than it is to changes in VGS-

Therefore, adjusting VT through use of the bulk connection of the triode transistors allows a

higher trimming resolution. This improved resolution comes at the expense of a lower trimming

range. For example in a typical CMOS process, with VSB varying around LSV, variations in the

bulk potential cause a 40% change in the value of VF (i.e. A V' change of O.1V causes a VT

change of 0.04V.)

Trio& connected MOSFET devices offer the advantages of being more accurate than other

resistive structures in a digital CMOS process as well as the ability to have their resistance value

trimmed through the bulk connection. To complete the reference circuit the bipolar transistors

and resistors must be placed in the feedback network of an op amp.

l u n c 1997 Ktvin Parker

2.4 The Op Amp

A fairly high gain op amp with low offset can be designed in the configuration shown in

Figure 2.6. It has been shown that the systematic offset in this type of structure can be minimized

through the use of certain optimal transistor ratios [q. If M1 and M7 have the same gate bias, as

they do here, the ratio of the sizes of MI to M4 and M5 should be the same ratio as the ratio

between the sizes of M7 to M6. By using these size ratios the op amp can be designed to have a

very low systematic offset voltage. Therefore, the ideal design can have the offset completely

removed. In practice, problems arise due to device matching as a result of process variations

similar to those mentioned above with resistors. A method similar to that of trimming the resis-

tors, described above, can be used to remove this process variation induced offset voltage.

lunc. 1997 Kevin Psrkct

The input devices (M2 and M3) control the output of the op amp by switching current

between the two sides of the input stage. The current through the MOSFETs is controIled by

either equation 2.1 or

depending on whether the device is in the triode or saturation mode of operation respectively. In

either case the current is largely controlled by (VGS - VT) . AS shown in equation 2.4 the thresh-

old voltage can be effectively adjusted through the body effect By varying the bulk potential of

one of the input devices it is possible to adjust the offset voltage of the amplifier 171. This allows

an additional two input terminals to be added to the amplifier, if the bulk of both of the input tran-

sistors are utilized. The output of the amplifier will be the suprposition of both sets of inputs

with their appropriate gains. (See Figure 2.7.) For an amplifier with an input referred offset Vos

the output will be given by,

June. L997 Kevin Parka

From equation 2.6 it is apparent that if the appropriate input voltage is applied between the

b u k of the w o input transistors the effect of the offset voltage can be cancelled out. For this

cancellation to occur

This method is limited by how accurately the input voltage to the bulk can be specified. If the

r a gate - ratio is large then V& can be trimmed to a value much lower than the accuracy of YdUk. A b d k

Thus, allowing the offset voltage to be reduced without requiring stringent controls on the bulk

potential.

There are other ways of trimming the offset voltage of an op amp but in general they either

use dynamic methods to cancel the offset voltage or special processing to trim out the effects of

process variations. The circuit at hand deals with a DC output voltage so dynamic trimming

methods are undesirable because they will create a sampled output. Allowing the voltage refer-

ence to be implemented in a standard CMOS process, without any special procedures, is one of

the design's major gods, therefore, any trimming method that requires added processing steps is

undesirable.

2.5 Summary

The bandgap reference circuit shown in Figure 2.1 can be used to create an accurate reference

voltage. Methods of implementing the various devices that comprise this circuit have been dis-

cussed.

June, 1997 Kevin Parkc

Parasitic vertical bipolar devices have been chosen for the two BJTs that are needed for the

bandgap extraction. These devices offer a sirnpIe implementation but have the operating restric-

tion that the collector must be connected to the supply. They can be modelled using standard

transistor models and techniques. The imponant model parameters in this application are those

that define the emitter-base junction characteristics. Minimum size devices should be used to

keep the necessary bias currents low and therefore reduce overall power consumption.

There are many ways to implement resistive structures in CMOS. Most of the methods dis-

cussed have problems with poor matching, non-linearities or low sheet resistance values. A triode

connected MOSFET can be used to overcome some of these problems. The MOSFET offers a

sheet resistance that is controlled by VGs and VT. Vm can be used to control VT through the body

effect which allows finer trimming results than those attainable through VGS. making V T ~ g

the preferred choice for trimming the resistors-

The required op amp must have a gain that is sufficiently large to produce very small differ-

ences between the two inputs. The op amp also requires a very small offset voltage. This low

offset can be obtained by allowing the op amp to be trimmed through the substrate voltages of the

input devices.

The most important devices in the reference are the bipolar transistors since they are responsi-

ble for extracting the bandgap voltage of silicon. Their implementation and modeuiag must be

done in an accurate manner to ensure that the final circuit will perform as desired.

J u n c I997 Kevin Rrkcr

References

B-P. Song and P. R. Gray, "A Precision Cwature compensated CMOS Baudgap Refer- ence," IEEE Joumnl of Solid State Cimits, vol. SC-18, pp. 634-643, Dec. 1983.

E. A. Wttoz, "MOS Transistors Operated in the Lateral Bipolar Mode and Their Application in CMOS Technology,~' IEEE Journal of Solid State Circuits, vol. SC-18, pp. 273-279, June 1983.

R. W. Sandage and LA ComeIIy, ''Producing Phototransistors in a Standard Digital CMOS Technology," Proceedings IEEE Interntiom1 Symposium on Circuis and Systems, vol. 1 pp. 369-372, 1996.

J. Michejda and Suk K. Kim, "A Recision CMOS Bandgap Reference," IEEE Journal 4 Solid State Circuits, v01. SC-18, pp. 1014-1021, Dec. 1984.

R. Benumof, J. Zouteadyk, "Theoretical Values of Various Parameters in the Gummel-Poon Model of a Bipolar Junction Transistor," Journal of Applied Physics, vol. 59, pp. 636-644, Jan. 1986.

P. R. Gray and R. G. Meyer, "MOS Operational Amplifier Design - A Tutorial Overview," IEEE Journal of Solid State Circuits, vol. SC-17, no. 6, pp. 969-982, Dec. 1982.

A. Biman and D. G. Naim, cTrimming of Current Mode DACs by Adjusting V," Proceed- ings IEEE Intenatiomi Symposilrm on Cincuits and System, vol. 1, pp. 33-36, 1996.

Jut, 1997 Ktvin Packer

3.0 Modelling Vertical Bipolar Junction Transistors

Bipolar devices are responsible for extracting the bandgap voltage of silicon on which the ref-

erence is based. In order to design an accurate reference the operation of these devices must be

well modelled. The feedback network must be fine tuned to produce a minimum temperature

coefficient. If the bipolar transistors do not closely track their modeIs the time and effort that is

taken in this fine tuning will be wasted.

This chapter is by no means a comprehensive study of how to model bipolar junction transis-

tors. It is intended to outline the information required by a designer to perform the necessary

steps in modelling bipolar transistors for the purpose of designing a bandgap reference in a

CMOS process. The models used are based on the theories and subsequent models developed by

Gummel and Poon [I]. These models do not have to be complete but must provide very close

matching between the modelled and measured DC characteris tics.

3.1 The Gummel-Poon Model

The most common bipolar transistor model used with the HSPICE~ circuit simulator is the

Gummel-Poon charge conservation model [2]. This model has many parameters to define the

bipolar transistor in all modes of operation. In the reference circuit under consideration the DC

diode characteristics are the most important factors. The junction capacitance parameters and

other high frequency effects are less important Since we are trying to remove any temperature

dependence from the circuit, the parameters that define this temperahm! dependence are also

important.

The equivalent circuit diagram used by HSPICE to model the BJT is shown in Figure 3.1 [3].

This model uses the two diodes formed by the base-emitter and the base-collector junctions to

June, 1997 Kcvin Parka

control the current flowing between the collector and the emitter. Through various mode1 param-

eters 'ic' is controlled by 'ibc' and 'iW. The capacitors in the model are, in general, variable

which allows them to model various junction effects; in particular the bias sensitive effects of

junction capacitance and charge storage in the p n junctions of the transistor. However, the prob-

lem at hand deals only with the DC characteristics of the device so these model parameters are not

important. Finally the three separate terminal resistances must be modelled. The collector and

emitter resistances are typically a fimction of the sheet resistance of the materials that are use to

connect to the transistor. The base resistance is more complicated since in the structwe of a BJT

the base runs between the collector and emitter and is contacted from the side. It does not have a

specfic contact point but has a range over which the effects of current flowing out of the base are

experienced. This range is affected by parameters such as the amount of current flowing out of

the base and the voltages across the base-collector and baseemitter junctions.

Base

0 Emitter

CBEP

Typical transistors have an b V C E relationship as shown in Figure 3.2. Since the reference

operates at DC the important parameters in the model are those that directly affect the shape of

these curves. In particular, since the transistors are C O M ~ C ~ ~ in a diode configuration, the most

important model parameters are those that defme the b V B E characteristics of the bipolar transis-

tor in their linear region of operation. These are IS, BF, VAF and IKF. The simplified form of the

relationship between these parameters, in the linear region of operation, is shown below [4].

VAF

IS is the transport saturation current It has the effect of scaling the k-VE curves in the vertical

direction. BF is the maximum forward curtent gain of the transisto' This quantity defines the

maximum ratio between the collector and base currents. The slopes of the lines in the linear

region of operation of the transistor are affected by the forward early voltage, VAF. If the linear

region of the curves are extrapolated back through the x-axis of the plot in Figure 3.2 they theoret-

ically intersect at a point which is termed the early voltage for the device. The final parameter,

IKF, is a higher order term and therefore doesn't appear in the above equations. It defmes the

current at which the current gain starts to drop due to the effects of high current densities. These

high currents are relative to the size and structure of the device in question. In some instances the

roll off can start to occur at fairly low cumnts. Therefore, the effects of roll off should be consid-

ered but may not be an important factor in the final model.

The other major factors in the DC operation of the bipolar device are the terminal resistances.

These resistances are important because they affect the actual voltages at the internal transistor

June. 1997 KWin Padw

terminals. Since the bipolar transistor is an exponential device a small voltage drop across one of

these resistors can have a large effect on the f ind cumnt flowing in the device. These effects are

particularly important in the emitter and base terminals since they directly affect the actual VE of

the internal transistor which controls the cunent flowing in the base and, in turn, defines the

observed collector current,

With the important modelling parameters in hand, a closer look at the structure of the bipolar

device is needed to help define these parameters.

3.2 Structure of the Bipolar Transistor

The structure of the parasitic bipolar transistor used in the design of the voltage reference is

shown in Figure 3.3. The model of this device is strongly dependent on the doping concentration

and depth of the different structures that make up the bipolar transistor. Three main areas must be

June. 1997 KcvinPyka

constructed to form the NPN transistor. These are the emitter (N), the base (P) and the collector

(N). The various structures in the transistor are laid out as shown to try and make the best use of

the layers available to the designer in a standard digital CMOS process.

The first thing to note about the structure shown in Figure 3.3 is that it is centered around the

emitter. A source contact is used for this emitter struchue since this is the most highly doped N

type structure available in the CMOS process. The high doping is required to make the injection

of electrons into the base more efficient The amount of current that flows in the device is propor-

tional to the size of the emitter-base junction. To keep the power consumption as low as possible

a minimum size emitter must be used for the tramistor.

To both the left and right of the emitter are the base contacts. The reason for using two base

contacts stems from the need to keep the base resistance to a minimum. If the base is contacted

from both sides it is cbar that there will be two base resistors acting in paraUeI. This reduces the

base resistance by a factor of two. The double base contact will also aid in reducing some of the

high current effects. Base current flows down from the surface of the wafer into the base of the

device and back up into the emitter. When current flows around any corner the current density

increases near the corner more rapidly than it does away from the comer. This raises the base

resistance at higher currents producing a non-linearity. The crowding effect may also push some

of the current in through the side of the emitter which wiU have the effect of lowering the current

gain of the transistor. The electrons that flow out the side of the emitter have an extremely low

chance of finding their way to the collector thus, adding to the base cumnt while reducing the

collector current. If two base contacts are used this crowding effect will not occur until a higher

current is experienced.

FTG-33-P- .. . a) Top View From Cadence Analog Artist

b) Cross Section Along A-A

The final structure to consider is the collector. It has been designed to completely surround

the rest of the device. Tbis was done to achieve two positive effects. Having the collector contact

completely surround the rest of the transistor will reduce the collector resistance of the device in a

manner similar to that of adding a double base contact. The collector collects the electrons that

diffuse to the edge of the collector-base junction. W~th a large collector area the electrons have a

J u n ~ 1997 Kevin Parker

higher probability of aLTiving at the junction to be collected and become part of the collector cur-

rent.

The surrounding collector not only aids the efficient collection of electrons, it also helps to

protect the circuitry in the vicinity of the bipolar transistor on-chip. Carriers that make it into the

substrate and are not collected will flow through the substrate to another area of the chip.

Depending on where they eventually end up, they can cause problems. In the best case scenario

they will simply add to a current that is already present onchip. In the worst case they may

induce a latch-up condition in another MOSFET structure [S]. This latch-up condition not only

completely alters the performance of the devices, it can destroy the devices with the high currents

that will created. Because of the detrimental effects of these stray carriers, it is important to com-

pletely surround the device with a collector contact to mbimke the number of stray caniers

escaping fiom the bipolar transistor structure m.

Although the layout of the transistor can be done in a manner to optimize the structures avail-

able in the process, the transistor's operation is iargely determined by factors which the designer

cannot control. The operation is predominantly defined by the vertical doping profile taken

through the emitter of the transistor This vertical structure is used for the simplest form of theo-

retical modelling.

The modelling problem can be simplified down to a one dimensional situation so that analyti-

cal methods may be used to arrive at a modei. Otherwise numerical methods are required to

determine the current densities flowing through a two dimensional structure. Two dimensional

analyses are typically performed by process simulation software to give the process designer

insight into the workings of devices in the design phase of a new process. This type of analysis is

Junc. 1997 Kevin Parker

beyond what is required to obtain a working model which allows design work to start before an

empirical model becomes available.

The doping profiles of the parasitic device under question and a more traditional bipolar tran-

sistor are compared in Figure 3.4. From the diagram it is apparent that the parasitic device is far

from ideal. The differences in the structure will have a definite impact on the operation of the

transistor.

-3 n++ ldOon ,., h n+ P - P -.

3 P

0 Y

O, n- Buried ' .

0 i - ,/ ' ~011ector ,. L(jlm-l i \

ow 3w - Depth

h

UI n+ E L

P -1. P 8 n Y

k w-. ' /*

01 / , A

0 - I , i

ldLon" t OIua

D 3m

Depth

A) Typical Vertical BJT Rofile [n B) Estimate of Parasitic BJT Profile

June 1997 KcvinParkcf

There are three major differences between the two devices shown in Figure 3.4. They are the

width of the base, the doping of the emitter and the doping of the collector- Each of these will

affect different aspects of the bipolar transistor's operation.

Current flows between the emitter and collector through diffusion of minority carriers across

the base junction- Some of these carriers recombine as they travel across the base. If the base is

narrower the probability of this recombination occurring is reduced. Since, the amount of recom-

bination is a major factor in determining the current gain of the device, it is desirable to have a

narrow base. In other applications the width of the base can effect the switching speed of the nan-

sistor. These same carriers that are diffusing through the base must be removed in order to turn a

transistor off. To be removed they must diffuse to one of the three available terminals of the tran-

sistor. A narrower base will decrease the transit time required, allowing the transistor to be

switched faster.

The emitter doping in the parasitic device is probably Iower than that of the more conven-

tional transistor. A high emitter doping reduces the emitter resistance and improves the number

of electrons that are available for injection into the base.

The collector doping and doping profile of the parasitic device are vastly different than those

of a typical device. The typical device has a very low doping directly in contact with the base and

a higher doped area much lower in the substrate.

The low doping in the collector causes most of the depletion in the basecollector junction to

occur in the collector. As the reverse bias on this junction increases the depletion area gets wider.

With the low collector doping the width of the depletion expands considerably more into the col-

lector than the base. The expansion into the base effectively makes it narrower. As discussed

June. 1997 K& Parker

above the current flowing through the device is a function of the diffusion across the base. As the

effective width of the base goes down the cumnt goes up. This effect causes the slope in the

Vn curves of Figure 3.2. Since the parasitic device under consideration has almost equal collec-

tor and base doping the slope of this line is going to be quite steep n%dting in a very low Early

Voltage (VAF).

The highly doped area, that is buried in the substrate, gives the collector a low resistance path

to the terminal that will be at the top of the substrate. This connection is generally made through

a very tall highly doped region that penetrates to the buried collector terminal.

3.3 Modelling From Process Panuneten

Creating a model fiom process parameters is necessary to reduce the time required to com-

plete the design. It is not a necessary step in the design process s h e this theoretical model will

eventually be replaced with an empirical model when one becomes available.

The operation of a bipolar device is quite complex and is highly dependent on its structure. In

particular, the exact doping profile controls most of the model parameters. An accurate model

should take the actual doping profle into consideration through various numerical techniques.

However, knowing that the model will eventually be replaced by an empirical model allows some

approximations to be made that will allow creation of a model, quickly, at the expense of some

decrease in accuracy.

The model can be derived using a very limited set of parameters taken from the doping profile

as seen in Figure 3.4. The required parameters are the average doping of each of the three termi-

nals, the area of the emitter, the depth of the emitter and the width of the base. The mobility of

Junc, 1997 Kevin Pasker p p p p p

minority carriers in the emitter and base are also required. Mth this limited selection of structural

parameters all of the major model parameters can be detexmined.

The equations that define the major parameters in the HSPICE model are given below 181.

For a more complete view of the relationship between the structural parameters and the rest of the

model variables see Appendix A.

- - ( b - a*) - NAB

In these equations there are various different types of components. The geometrical parame-

ters are AE, a and (b-a*). These define the top view area of the emitter, the depth of the emitter

and the width of the base. as shown in Figure 3.4, respectively. The parameters NDE. NAB and

NcE give the doping densities of the emitter, base and collector respectively.

DB is the diffusion constant of the minority electrons in the base and is given by,

J u n s 1997 Kevin PYkcr

where p, is the mobility of the electrons in the base. A similar equation exists for DE in the emit-

ter with pp substituted for pn.

The voltage VDBC defines the junction voltage set up across the depletion region by diffusion

with no applied bias and is defined by,

Vsc is the actual voltage applied across the base-collector junction.

The remainder of the components are constants; E is the permittivity of free space, k is Bolt-

zmann's constant, q is the electron charge, Ri is the intrinsic carrier concentration of silicon and T

is the temperature.

In the situation at hand the necessary parameters were considered proprietary by the manufac-

turer and were not available so a theoretical model could not be created. To allow the design pro-

cess to proceed, without having to wait for the test structures to be fabricated and measured, the

model for an npn bipolar transistor from a BiCMOS process with similar dimensions was used.

The model in its HSPICE form is shown below.

June. I997 Kevin Parker

AMm~gh this model defines the B i O S device very we& it is a very crude approximation

to the transistors that are used in this situation. The parasitic devices used will have a very differ-

ent doping prolle and therefore have different operadng characteristics. However, this model

provides a starting point for the initial design in the absence of a valid empirical model.

3.4 Modelling From a Measured Test Structure

It is apparent that there is a need for a more accurate model than can be obtained from the

available data. The key in any type of modeUing is to have the model match reality as close as

possible. Clearly the best model will be one that is fit to the actual measwed data taken from the

devices under consideration. Such work is best done with a device modelling package.

I . For a definition of dl of the model parameters see HSPICE User's Manual, Vol. 2, Elements and Mod- els, Meta-Software, pg. 4-6, 1992

June 1997 Kcvin Pyka

The software that was used to mate the empirical model was called H A R P E ~ . This soft-

ware takes measured data and allows user defined model parameters to be adjusted to produce a

best fit model to the data. In its basic form the software solves a multivariable minimization

problem. The user defines which model parameters wiU be allowed to be changed and the soft-

ware adjusts these parameters though an iterative process to get the best fit between the measured

data and the model. HARPE also ailows the parameters to be adjusted manually. Once the opti-

mization has been completed a plot comparing the measured results to the fitted curves can be

viewed.

When taking measurements of the device's operation, for empirical modeIling, it is important

to consider the software that wiU be used to optimize the model. Different software packages are

set up to work with different sets of parameters. When using HARPE, the best measurements to

consider are the classic k V C E curves taken at different VBE settings. With BJTs the measure-

ments are typically done for different IB settings but the optimization software requires the input

data at different VBEs.

The iterative optimization process depends on a few external parameters. The first parameter

being the origiaal guess at the model. In this case the theoretical model shown above was used as

the initial guess. Optimization works much better if only a few parameters are allowed to be

adjusted at a time. To this end, experience has shown that to arrive at the best model one should

allow the parameters to be adjusted in the order of importance. In this case the first fit was done

by allowing only IS to be adjusted. This gets the curves into the proper ball park After this fit the

other three major parameters, (BE IKR, VAF) discussed above, are added to the adjustment. The

terminal resistors are then allowed to be adjusted independently. After these steps have been

June 1997 Kevin P;uktr

taken, other parameters can be adjusted individually or in related groups to fine tune the matching

between the measured data and the model behavior- It is beneficial to cycle through the parame-

ters a few times since a change in one parameter may lead to a better optimization o f another

parameter.

In the end how well the model fits the measured data is a judgement that must be made by the

user. This judgement will be based on the plots of the measured vs. modelled curves. The optimi-

zation process also returns a number that gives some indication of how accurately the curves fit

the data. This error number is made up of a combination of how closely the terminal currents fit

the data and the weighting these currents are given in the optimization. While it doesn't 3 - ve an

absolute measure of the accuracy of the model, it does give an indication of how much the model

has improved with the last optimization. Still it is up to the designer to decide when the model's

fit is close enough to the data points to be considered adequate.

In determining the adequacy of the model special care should be taken to ensure the model fits

very well in the region where the devices will be operating. For the voltage reference this is the

region where VBE and Va are equal.

The plot in Figure 3.5 shows the matching between the optimized model response and the

actual transistor operation. The area on the curves where VCE equals VBE is in very close agree-

ment as is required. The empirical model that mated the curves below is given following the plot

in its HSPICE form. This model is very dependent on the major parameters that are highlighted

in bold print The minor parameters (italics) were also optimized to fine tune the fit of the model.

Parameters that would change the frequency response of the model were not adjusted.

June. I997 Kevin Pylw

MODEL EMPIRICAL NPN + IS= 1.7739E-17 BF= 221,761 + VAF=10,211 3 , 76639e-4

+ NE= 1,71101 + BR=. 0,341192 BR= 0.970454 + IKR= le6 ISC= O.OOOE+OO + RB= 91,5562 IRB= 1.000E46 + RE= 37,9729 RC= 119,453 + CJE= 1.509E-14 VJE= 8.719E-01 + TF= 1.248E-11 XTF= 9.162E+O2 + ITF= 8.672E-02 PTF= 2.OOOE+O1 + CJC= I.751E-14 VJC= 6.99OE-01 + XCJC=2.800E-01 TR= 4.000E-09 i- C J S = 4.0293-14 VJS= 6-39OE-01 + XTB= 1,38OE+OO EG= 1.110E+OO + RF= 2,8743-09 AF= 1.997E+00

LeQend Major Paramatar Minor Parameter Unchanged

Junc I997 Kcvia Rrkcr

This model is quite different from the one used in the original design. There are some major

differences to note. The saturation cumnt, IS, is significantly less than what is seen in the

BiCMOS model. This implies that the doping difference between the base and the emitter is not

as high in the parasitic device The early vohge, V* in the empirical model is less than in the

original, implying that the doping in the base and collector regions in the parasitic device are

comparable. These two differences are expected. One surprising difference comes h r n the

increased BF that is observed in the parasitic model. This wouid imply that the base is narrower

in the parasitic device than in the BiCMOS device which is completely unexpected. The reduc-

tion in BF could be the result of an increased resistance effect in the BiCMOS device. Overall the

model matches the measured results very well and can be used confidently in simulating the para-

sitic bipolar junction transistor in the reference design.

3.5 Summary

The design of the voltage reference requires an accurate model of the parasitic vertical bipolar

transistors that are used to extract the bandgap voltage. Since these are non-standard structures, a

model for them does not exist. Therefore, it is necessary for the designer to create this model. It

is clear that an empirical model will more accurately match the actual operation of the devices

than a theoretical model. Once an empirical model has beea obtained the design of the rest of the

reference circuit can proceed.

June. 1997 Kevin Parkcr

References

LE. Getxeu, Modeling the Bipolar Transisror, New Yo* Elsvier, 1976.

I. I. Liou, Advanced Semicondufror Device Physics rmd Modeing, Norwood: Artech House, pp. 273-280, 1994.

HSPICE User's Manual, Vol. 2, Elements and Models, Meta-Software, pg. 4-6, 1992

M. S hur, Physics of Smicoductor Devices, New Jersey: Prentice Hall, pp. 270-28 1, 1990.

P. Pavan, G. Spiazzi, E. Zanoni, M. MuschitieIIo and M. Cecchetti, "Latch-Up DC Trigger- ing and Holding Characteristics of N-Well. Twin-Tub and Epitaxial CMOS Technologies," IEE Proceedings-G, vol. 138, no. 5, pp. 604612, Oct. 1991.

R.R Trouman and HE Zappe. ""Layout and Bias Considerations for Preventing Transiently Triggered Latch-Up in CMOS," IEEE Trmuactions on Electron Devices, vol. ED-3 1, no. 3, pp. 315-321, MaK 1984.

M. Kurata, Numerical Analysis for Semiconductor Devices, Toronto: Lexington Books, pg. 77, 1982.

R. Benumof and J. Zoutendyk, "Theoretical Vdues of Various Parameters in the Gummel- Poon Model of a Bipolar Junction Transistor," Journal of Applied Physics, vol59, no. 2, pp. 636-644, Jan 1986.

4.0 Design of flrimmable Resistors and The Op Amp

The voltage reference schematic is shown again in Figure 4.1. Once design and modeiling of

the bipolar transistors has been considered the designer's next task falls to selecting and imple-

menting the resistors and op amp for the feedback network. The output of the reference in the

presence of an ideal op amp is completely defined by the feedback network. The reference volt-

age will be given by,

VBEo will be defined by the empirical transistor model that was found in Chapter 3. It will

depend on this model as well as the bias current in 42. The final term in the equation produces

the required temperature compensation which is completely defined by the three resistor values.

In order for the actual circuit to reproduce the temperature compensation for which it was

designed, the resistors must match very well. Typically the matching required to obtain the

desired reference accuracy cannot be obtained through simple layout considerations therefore, it

is necessary to make the resistors mimmable. For the op amp the design restrictions are much

more lenient. Nevertheless any offset voltage in the op amp will cause a shift in the desired out-

put voltage. Consequently, to achieve an accuracy of better than ImV at the output, both the

resistors and the op amp must be trimmed.

lune, 1997 Kevin Parlrcr

4.1 Resistor Implementation

As shown in Figure 4.1 the reference voltage is negative and the circuit runs off of a negative

supply voltage. This is due to restrictions imposed by the pwell process. In a p-well process,

only NPN bipolar transistors can be fabricated, with the restriction that their collectors must be

connected to the subsmte, which in this case, is the highest potential. Therefore, the circuit must

be designed to have a negative output. In a similar manner, an n-well process would be restricted

to a positive reference voltage.

To create resistors in a CMOS process, MOSFETs comected in the triode configuration can

be used. The MOSFET acts as a resistor when its gate voltage is higher than both the drain and

source voltages by at least one threshold voltage. (i-e. Va>VT and V&-pV7) These conditions

create a resistive channel in the device. The resulting resistor is defmed by,

In this equation there is a non-linear term in Vm However, if the changes in V' are small com-

pared to VmVT then the operation can be considered linear. Thus, a higher VGS Will provide a

more linear resistor-

Using the triode MOSFET implementation for the resistors allows two electronic trimming

methods to be implemented. Looking at Equation 4.2 both VGs and VT control the resistance

value of the triode connected MOSFm. Traditionally VT is considered a constant value but, as

shown in Equation 4.3 below, adjusting the substrate voltage of the MOSFET induces a change

in VT through the body effect

A closer examination of this equation shows that VsB does not have a Linear relationship to VF As

the bias level increases the effect VsB has on V+iecreases. When trimming, it is desirable to have

changes in the trim voltage have a small effect on the value that is being trimmed. This allows

more accuracy in the final trim. However, the trade off comes in the overall trim range that can

be achieved. A more accurate trim comes at the cost of a reduced overall trim range since the

range of the applied aim voltage is limited due to other circuit constraints. In the configuration

used in the final design, a 100 mV change in VSB Will change a given MOSFET resistor's value by

0.95%. A similar change in Vm results in a resistance value change of 3.8%. Trimming through

the substrate offers an adequate trim range and results in an improved trim resolution so it is the

method of choice for the resistors implemented here.

June. 1997 Kevin hka

To accomplish trimming via VT adjustment the MOSFETS that are to be trimmed must be

implemented in individual device wells. This allows the substrate voltages of the transistors to be

adjusted independently. In the process under consideration. this requires the MOSFETs to be n-

channel devices. These devices require a highly positive VGs to create a linear resistance. As can

be seen in Figure 4.1 the maximum VGS for R3 will be approximately 0.m if the maximum

allowed voltage is ground. Given that VT is approximately 0.8V, this is insufficient to turn on the

MOSFET. To overcome this problem it is necessary to mate an on-chip voltage that is higher

than ground. Based on the charge pump discussed in Section 4.3, a voltage of +2.6V can be cre-

ated on-chip.

The resistor sizes can be h e tuned using HSPICE to simulate the reference circuit. To

improve matching, resistors are created from combinations of 10pm x 10p square triode con-

nected devices in series. These are much larger than the minimum process dimension of 1 . 5 ~ in

order to improve the inherent matching of the devices [I]. To create larger resistance values mul-

tiple devices were connected in series. For design purposes it was assumed that the charge pump

would create a positive 3.3V supply for biasing the gates of the triode transistors although subse-

quent work has shown that only 2.6V can be achieved This results in an approximate Va of

4.OV for R3 and a bias level of 4.W for R1 and R2.

Since these MOSFET resistors all sit in their own device wells. their individual substrate volt-

ages must be defined. The circuit is designed to have a -3.3V supply. Therefore, two of the

devices, RI and R2, can have their substrate fixed at -3.3V. R2 will be trimmed and therefore

must have its substrate held at some trim voltage. In the design the ideal substrate voltage will be

held at -2.0 V. This fd s between the trim limits of -3.W and -1.7V

June. 1997 Kevin P a c k

The initial theoretical estimates for resistor ratios are R2:Rl= 10: 1 and R2: R3=LO: 1 (see

Chapter 2). With these ratios in mind the untuned circuit started with R1 and R3 being composed

of two transistors in series while R2 had 20 transistors in series. These resistors sizes were

adjusted until the temperature response of the circuit exhibited the second order shape shown in

Figure 4.2. This parabolic response is the best that can be achieved without some form of curva-

ture compensation. It should be noted that the final output is slightly lower than the -12V that

was expected born analysis using equation 4.1. This might be due to the non-ideal characteristics

of the op amp that was used. Taking the value at room temperature (20°C), a reference voltage of

- 1.369V with a temperature coefficient of 26 ppd'C is obtained. The simulated output imped-

ance is 2.64R. The final values used for the resistors are shown in Table 4.1. Naturally, these val-

ues are subject to the variations that will occur in processing.

TABLE 4.1 - E " i Resistor Parameters

June. 1997 Kevin Parker

4.2 Resistor T k h d n g

In a practical circuit, process variations lead to mismatches between the resistors hence one or

more of the resistors must have its value trimmed to be able to accomplish the desired ImV accu-

racy of the reference circuit. As discussed above adjusting VsB individually will trim the values

of each of the resistors. The important thing to bear in mind is that the goal is trimming the output

voltage of the circuit so that it has the proper value and the appropriate temperature compensa-

tion. To this end, it is the ratios R2R3 and R2R1 that are important. The ratio R1:R3 is not

important by itself. Adjusting R2 will affect both of these ratios. A look at Equation 4.1 shows

that adjusting R2 done can achieve the proper trimming of these ratios. The h a 1 value of the

June. 1997 Kcvia Parkn

temperature coefficient of the third term is the important factor and W will effectively control this

The plot in Figure 4.3 shows the effects of varying the trim voltage on R2. This data was

obtained through simulations using HSPLCE. The six curves represect the temperature respouse

of the reference for each of the substrate bias points shown. Notice how changing the resistor

value not only changes the output voltage of the reference but also changes the shape of its tem-

perature response. The limits of the trim range are determined by the lower supply rail and the

requirement that the substrate-source junction is always reverse biased. To ensure the reverse bias

condition, the substrate is limited to a maximum value of - 1 .7V

Trim Voltage

-1 -31

-1.32

-1.33 5 w

0 p -1.34 L.

9 Y

1 -1 -35 Cz Y

6 -1.36

-1.37

-1.38

-1.39 * 0

. 8 I 1 I 1 1 1

-

-

-

- -

- -

d -

- - I I I I I J I

10 20 30 40 50 60 70 80 Temperature (OC)

June, I997 KtvinPdur

In order for the uim method to be useN it must be automated and be able to hold the trimmed

value at the desired level. To achieve this, a system similar to that in Figure 4.4 was designed.

Trigger Pulse Count Enable

Control I 8 Bit Counter Logic

I Comparator Input

The automated aimming circuit requires two external inputs- These are a trigger pulse to start

the trimming exercise and an external reference to ensure that the voltage is trimmed to the proper

value. When the trigger input is recognized the control circuit will allow the counter to start

counting. With each count of the counter the output of the DAC wilI be adjusted. The DAC is

connected to the substrate of R 2 to trim its value thus changing the output of the overall circuit.

u

Andog

The output of the circuit is compared to the external reference. When the two are equal, or the

output crosses the reference voltage, the comparator output wili change causing the counting to

stop. With the counting stopped the circuit will hold the value on the substrate voltage. This

trimming method will hold the trimmed output indefinitely in the absence of any drift phenome-

non.

8-Bit DAC

t

The major draw back encountered here is the necessity to supply an external reference voltage

when the trimming is performed. To complicate this matter the trim value is lost when the power

Trirn Voltage

.

June. 1997 Kevin Pykcr

is removed from the chip. The reference wilI therefore have to be trimmed every time the chip is

powered up. To solve this problem it is conceivable to implement an extra step in the trim pro-

cess. An EEPROM could be added to the circuit allowing the reference to be trimmed at the end

of the production line. The required trim count could then be stored in the EEPROM ehhating

the need to trim the chip with each power up.

The major components in the trimming circuit are the DAC and a counter to drive it. These

devices have been implemented as an R-2R ladder DAC and a simple ripple counter.

4.2.1 R-2R DAC Implementation

The R-2R DAC is a very elegant resistor structure that successively splits currents equally to

give a number of binary weighted currents [2]. Switches can be added to the structure to allow

the current to be summed according to a binary input giving a current output weighted by the

binary scale factor. A simple three bit R-2R DAC is shown in figure 4.5.

For the structure to operate properly it is important that the voltage from ground to the ourput

terminals remains constant This implies that the current must be measured at I,, and f,, with a

constant bias voltage. The operation of the structure is based on the fact that the resistance seen

below and to the left of any node in the circuit is 2R. Below node 3 the resistance is composed of

2R in parallel with 2R giving an equivalent resistance of R- This is in series with the resistor R

between nodes 2 and 3 giving an equivalent resistance of 2R. Which is in parallel with the other

2R at node 2 giving an equivalent resistance of R. This can be continued for as many current splits

as the designer wishes. The limit to the number of legs that can be used in this way is generally

determined by the accuracy of the resistors. Regardless of the number of legs in the structure the

equivalent resistance of the entire network will be R. This means that the current I will always be

defined by,

where Vbi, is the constant voltage at Io, and I,,,

Since each node sees two identical resistances the current splits equalIy at each successive

branch giving binary weighted currents. In the example of Figure 4.5 the currents that are created

are 1/2,1/4 and 118. By controlling the three switches, these currents can be summed to produce an

I,,, having 8 equal steps between 0 current and I ( 1- :,). The circuit fwctions as a 3-bit current

mode DAC. The f,,, current has an extra current added from the last 2R resistor in the chain mak-

I ing I,, count from to I. This extra cumnt is required to achieve the proper c m n t division

2

ratios throughout the DAC.

Since the R-2R DAC operates in the current mode, it is necessary to convert the current into a

voltage. However, it is also important that the voltage across the R-2R structure remains constant

In order to accomplish this the gain of an op amp can be used, with feedback, to measure the cur-

rent while holding the input voltage constant. The simple circuit that accomplishes this is shown

in Figure 4.6.

If the op amp is considered ideal, both of its inputs can be considered to remain at the same

potential. This constant voltage can be set by supplying a bias potential to the positive input.

Current flowing into the negative input of the amplifier flows through the resistor creating a volt-

age which is proportional to this current. Thus, the output voltage of the converter is,

The accuracy of the converter depends on the actual gain of the op amp since it will control the

difference between the positive and negative input terminals. This difference can be considered

an error. Therefore, the higher the gain of the op amp the less error in the signal coming from the

DAC.

June, 1997 Kevin Padux

The R-2R DAC has a very simple implementation in CMOS. If triode connected MOSFETs

are used for the resistors, both the resistor and the switch can be constructed h m the same

device. The switching can be controlIed by switching the gate of the trioded device fiom the pos-

itive supply to the negative supply. A schematic of the CMOS implementation is shown in

Figure 4.7.

- - - --

The required structure, shown in Figure 4.7, can be followed by a current to voltage converter

to create the trimming voltage for the resistor. In this application the linearity of the DAC is not

important. However, the monotonicity of the DAC is critical.

An 8-bit trimming DAC was simulated with large square devices used for the resistors to help

achieve good matching and therefore good overall accuracy of the DAC. The transistors used

were 15pm x 1 5 p PMOS devices. A plot of the DAC's output current over al l 256 of the counts

is shown in Figure 4.8.

June, 1997 Kevin Parker

0 50 1 00 I S 0 200 250 Input Count

GURE 4.8 - Cumnt Output of R - W A C

The voltage after going through the current to voltage converter is shown in Figure 4.9. The

resistor used to create the output voltage was a 1 0 9 p x 1 5 . 0 ~ NMOS device. The bias level

for the converter was -1.6= Notice that the output, while not linear, is monotonic and therefore

meets the required specifications of the trimming circuit. The trim voltage can be controlled to an

accuracy of 1 step of the DAC which corresponds to 5mV at the mid-point of the trimming range.

100 Input count

4.2.2 Counter Implementation

W~th a DAC in place the control circuitry for the trimming must be considered. The most

important aspect of this is the counter. The trimming circuit is controlled by a h e running

counter that is turned on when the control circuitry receives a trigger pulse and w e d off when

the proper trim level is achieved The counter used was a simple rippIe counter with one control

pin [3]. This pin controls whether or not the counter counts. Note that there is no method of

resetting the counter to a zero count. The counter will cause the trim to pass through the desired

level twice. Once when the counter rolls over fkom a fidl count to zero aad once when the proper

trim has been achieved. Therefore, the extra circuitry required to reset the counter can be elimi-

June 1997 Kevin Parker

nated if the decision circuitry that determines when the proper trim level has been achieved is

edge-sensitive instead of level sensitive. A schematic of this counter is shown in Figure 4-10.

Count 1 Enable

The counter consists of a number of edge-triggered toggle (T) flip-flops cascaded together. If

T is high the flip-flops toggle and ifT is low they hold their data. (See Table 4.2) From this it can

be seen that if a flip-flop has its clock connected to the previous flip-flop's output it will toggle

when the previous flip-flop goes from 1 to 0, provided the T input is high. Therefore, with the

clock applied to the CLK input of the first flip flop in the chain and the T input high, a counter is

formed. When T goes low the data is held.

TABLE 4.2 - T Flip-Flop l h t h Table

A static master-slave T flip-flop was used to create the counter. A schematic using the logic

gates from a standard cell library is shown in Figure 4.11.'

June. I997 Kevin PYkcr

CLK

I FIGURE 4.11 - T I;lipIF10- I

The counter and the DAC perform the trimming function while being controlled by some con-

trol circuitry which will be discussed in Section 4.5.

4.3 Charge Pump Design

To complete the discussion of resistors the method of producing a voltage above ground, for

the purpose of biasing the gate of the triode c o ~ e c t e d MOSFETs, must be discussed. To create

this voltage a simple two stage charge pump can be used

A charge pump creates a voltage higher or lower than the maximum supplied voltages by stor-

ing charge on various capacitors and switching the nodes of these capacitors between the avail-

able supply rails [4]. A schematic of the charge pump used in th is application is shown in

Figure 4.12. It consists of inverters I1 and U, MOSFETs MI, M2 and M3, comected in the

diode configuration to control the connection of the different nodes and three capacitors CI, C2

and C3, to store the charge that is to be transferred The inverters switch one end of Cl and C2

1 . The Standard Cell Library was Supplied by CMC.

June 1997 Kevin PYLcr

between the negative supply and ground while the diode connected FETs switch the o&er node of

the transiston between ground and the floating high voltage that is created. Node 3 is the new

positive supply rail which is held roughly constant by C3 once the circuit has gone through its

pumping up sequence.

M1 M2 M3 I 1 I

I I I - - - vss

CLK - - -

To examine the pumping operation of the circuit first assume that ai l of the capacitors are dis-

charged and a square wave is supplied to the U K input to start the pumping action.

If the clock is initially high, the output of 11 will be low and the output of I2 will be high.

Since I1 is low, it pulls node 1 low and M1 turns on allowing charge to flow onto C1. (see

Figure 4.13) Node 1 will be lower than node 2 so M 2 is off. Nodes 2 and 3 are at the same

potential so M3 is also off. Assuming there is enough time C1 charges to IV,pplyl-VT.

When the clock switches low the pumping action begins. The output of I1 goes high connect-

ing the lower end of C1 to ground- At the same time the output of I2 is going low. Node 1 is now

June. I997 Ktvin P d e r

above ground so M1 tums off but node 2 is at the low supply so MZ turns on and the charge on CI

is shared between C1 and C2 increasing the voltage across C2.

The clock input will switch high again sending 11's output low and-causing C1 to recharge.

The output of I2 will be high which shifts the voltage on C2 above ground. Since the voltage at

node 2 is now higher than the voltage at node 3, M3 will turn on and the charge on C2 will be

shared between C2 and C3.

0 100 200 300 400 500 600

Time (PI FIGWE 4.13 - Plot of

As the cycle repeats itself the charge on C2 and C3 builds up creating an increased output

voltage. This output voltage is limited by the negative supply voltage and VT of the MOSFETs.

This means that C1 can only charge to IVWP&V7. The maximum voltage that can be placed on

June. 1997 - Kevin PYkcr

C2 is the maximum voltage on C1 plus the negative supply voltage less the VT drop across M2

which gives 2(IV'$-Vr). C2 supplies this voltage to C3 through the diode connected m i s t o r

M3 where it loses another VF Therefore the theoretical maximum output of the charge pump will

Taking IV-$ = 3.3V and VT= 1 .I, which is larger than the VTO that is specified in the models,

due to the body effect, results in a maximum charge pump voltage of 3.3w

The charge pump output will resemble that of a charging capacitor with steps superimposed

on it. Figure 4.14 shows an HSPICE simulation of the charge pump. The circuit had a 1MR

resistor attached as a load to model the oscilloscope input irnpedence that was used to take the

measurement on the test circuit. The plot clearly shows a steady state output voltage of 2.66V

which is significantly less than what was predicted. This difference can be explained through

either an increased VT or the effects of loading the circuit with the lMS2 resistor.

The actual components in the charge pump design must be chosen after a careful examination

of the requirements of the circuit. The two major factors that must be considered are the required

load and the amount of noise that can be tolerated in the design. For the voltage reference the

charge pump's load is composed of the gate capacitors of the triode co~ected MOSFET resistors.

This is close to a no load situation. The load is formed Born any leakage that occurs across the

gates or across the actual capacitors in the charge pump. Since we are dealing with a reference

circuit, the noise should be kept to a minimun

June. 1997 Kevin Packer

The size of the diode comected MOSFETs will determine the amount of cunent that can flow

to charge the capacitors. This charging current is also affected by the size of the transistors used

in the inverters. However, the inverter transistors have a much higher gate voltage when they are

turned on making their on resistance lower. Hence, the inverter transistors do not need to be as

large as the diode transistors. The amount of current that can be supplied determines the output

resistance of the charge pump. If more current can be supplied during the charging phase of C3

then more current can be drawn off during the hold phase. This means that the charge pump can

drive a larger load and therefore, has a lower output resistance.

The trade off with the size of the diode counected MOSFETs comes from their switching

speed. When node 2 goes low the diode M3 must turn off. If it doesn't turn off quickly enough

June. 1997 Ktviapylrtr

charge flows back off ofC3 creating a small square wave on top of the steady state output. This

problem can be partially eliminated by using larger capacitors which has the drawback of creating

a very large structure onchip.

Through experimentation with various devices using HSPICE an adequate design was

obtained. The final circuit bas component values as listed in Table 4.3. The average steady state

output value is 2.66 V.

TABLE 4 3 - Charge Pump Compownt Parameters

Device Size

CI I 2 PF

The triode connected MOSFETs and their supporting circuitry created resistors that can be

trimmed via the substrate voltage and can have that trim held indefinitely by the counter that

drives the trimming DAC. W~th these devices designed the task of designing a low offset op amp

that can drive the voltage reference &ses.

4.4 Op Amp Design

The design of the op amp does not have to meet a large number of stringent specifications

because the feedback will reduce any small variations drasticallyY However, there are a few very

important considerations that must be made. The op amp must have an open loop gain that is

l u n c 1997 Kevin Parker

greater than 1000. This wiil keep the inputs of the op amp within I mV of each other for a 1 V

output and thus keep the error in the output of the reference lower than lmv In this application

more gain will improve the accuracy of the device. The input referred offset must be kept below

100pV. W~th the closed loop gain of approximately 10 this will give an accuracy better than 1mV

A simple two stage op amp design can be used to achieve the desired gain. An op amp in the

configuration shown in Figure 4.15 can easily produce a gain well over 1000 [5]. However, the

question of the op amp's offset voltage is not as trivial.

If device sizes and other layout considerations are taken into account the op amp can be

designed to achieve an offset of approximately 5mV. To achieve this degree of matching the

devices used in the design must be made 10 times the minimum device dimensions. Increasing

June 1997 Kevin Packer

the sizes to greater than 10 times the minimum size will still give matching benefits but at sizes

greater than this the advantages fall off rapidly and become impractical. Therefore, to achieve an

offset voltage that is less than 1 w V some type of trimming scheme must be implemented This

trimming scheme must integrated of the op amp design.

There are many trimming methods that exist for removing the offset from an op amp. How-

ever, most of these have one of two draw backs. They either require expensive post processing of

the circuits or they affect the signal path. In this application an inexpensive solution that is capa-

ble of producing a constant output is desired These two requirements eliminate most conven-

tional trimming methods as valid choices.

The method used to trim the op amp is similar to the method used in trimming the resistors.

The input stage of the op amp (M2 and M3 in Figure 4.15) controls the output by switching cur-

rent between the two different legs of the amplifier. Typically this current is considered to be

controlled by the difference between the gate voltages of the input devices through the relation-

ship,

This equation shows that the current is also controlled by any differences in the threshold voltages

(VT) of the two input devices. Although these are typically considered to be equal, it has been

shown in Section 4.1 that the threshold can be adjusted through the body effect If the two input

transistors are fabricated in individual device wells their substrate voltages can be independently

adjusted to cause an effective change in VF

June. 1997 Kevin Packer

The addition of the two substrate inputs gives the amplifier two distinct differential inputs.

These inputs both control the output tbrough the relationship,

where ABare is the standard open loop gain of the op amp, Abulk is the gain from the bulk terminals,

Vbuk is the voltage difference between the bulk terminals, Yg,, is the standard input and Vos is

the offset voltage of the op amp. In the ideal situation,

To achieve this condition the proper voltage (Vbulk) must be applied across the bulk terminals to

cancel the offset voltage. This occurs when,

Agar'? Equation 4.10 shows that the ratio - defines the trim range and the accuracy with which Vbulk Abuik

must be specified to control V&. It is beneficial to create a situation where the bulk gain is con-

siderably lower than the amplifier gain. This implies that the offset can be trimmed to an accuracy

much better than the accuracy to which the trimming voltage can be controlled. The trade off for

a high ratio is a reduced trimming range.

The gain through the bulk is inherently lower than the gain through the gate of the input

devices. Typically, the difference in gain ranges from a factor of t .4 to 6, depending on the

amount of reverse bias on the substrate. Even though there is an inherent difference it is neces-

sary to increase the ratio to achieve the desired offset accuracy. If the trimming voltage can be

specified to an accuracy of 1mV a ratio of at least 10 is required to reduce the offset below 100pV

June. I997 Kcvin PiLdEtf

To achieve this ratio the input transistors have been made of composite devices. Nine MOSFETs

were connected in pardel with one MOSFET's bulk comection being made available for trim-

ming purposes. Nine transistors were chosen for the input device for two reasons. Fmt, the extra

gain ratio that will be achieved is 8: 1 which will easily push the total gain ratio past 10: 1. Sec-

ondly, nine transistors can be laid out in a tidy square array with the center transistor's bulk con-

nection tapped for trimming purposes. The symmetric structure helps to eliminate gradients that

can occur in processing and temperature across the face of the chip.

The final design of the op amp is shown in Figure 4.16. Notice the addition of the compensa-

tion capacitor C, to improve the stability of the design, and the bias network MB 1-3. Tabie 4.4

shows a list of the device sizes that were used in the final design of the op amp The major simu-

lated design parameters are shown in Table 4.5.

June. I997 Kevin PYku

'CGBLE 4.4 - Device S i i in tbe F d Op Amp

TABLE 4 5 - Op Amp Specifications

The op amp can have its offset trimmed to a level lower than is required for the accuracy of

the circuit being considered. To make the trimming effective there should be some method of

automation involved in the process.

The trimming can be automated once the conditions for a trimmed op amp are established. In

this situation the op amp was considered trimmed (i.e. V&O) when the output was at Vss/2 and

both of the inputs were at Vss/2. To achieve these conditions the inputs to the op amp must be set

equal to each other and to Vss/2. As the trhmhg voltage is adjusted the output of the op amp

must be observed to determine when it reaches the proper value.

June. 1997 Kevio Parka

To this end the circuit shown in the block diagram in Figure 4.17 can be used. The circuit

trims the op amp through a number of steps. Trimming must be done with the op amp in an open

loop configuration. Therefore, it must be disco~ected from the circuit to be trimmed. The two

inputs can then be shorted together with a switch and c o ~ e c t e d to Vss/2 which can be provided

through a simple voltage divider network When the op amp is switched out of the feedback loop

its output is connected to a comparator that will signal when the trim has reached the proper level.

The VSS12 level can be supplied by the same resistor network that is used to bias the op amp's

inputs.

Trigger Pulse

Control I Counter

Logic Trim I Enable

I DAC

Analog output

To Reference

v

GURE

As the counter counts up the output of the op amp will increase. When it passes the proper

trim level the comparator will switch to provide a signal to the control circuitry to stop trimming.

J u n e 1997 Ktvin Pykcr

The control circuitry can then switch the op amp back into the circuit and the reference will

resume its original function.

The counter and the DAC that are used are the same as those used to trim the resistors. How-

ever, two new components are now required to complete the trimming circuit. These are the com-

parator and low resistance switches.

It ori,@nally appears that a very accurate comparator is required to reduce the input offset of

the op amp but on closer examination it can be seen that this is not the case. In this situation a

fairly poor offset comparator can be utilized. Any offset in the comparator is divided by the gain

of the op amp which will be greater than 1000. Therefore, if the comparator offset is 1OmV the op

amp offset can be trimmed to better than IOpV.

The comparator design that is used is shown in Figure 4.18. This type of circuit offers the

advantage of a high output swing to drive the control logic [6]. The major design considerations

in the comparator were low power and good matching. Even though it has been shown that fairly

poor matching still allows for good trimming it is beneficial to try to achieve the best trimming

possible. For low power the circuit has been supplied with a low bias current through MI. To

help achieve good matching and therefore a low offset voltage, large input devices have been

used.

June. 1997 Kevin Parker

The switches used to switch the op amp in and out of the circuit are PMOS devices. These

transistors have a gate width of 100 pm and the minimum length of 1.5 pn. This very high width

to length ratio gives them a low on resistance of 500 R To turn the switches on the gate is con-

nected to VDD and to turn them off the gate is co~ected to VSS. These levels can be supplied by

the CMOS logic that was available in a standard cell library for the process.

4.5 Control Circuitry

With a l l of the components operating properly the circuit needs some type of control logic that

will allow the user to perform the trimming operation by supplying the chip with a single trim sig-

nal.

June 1997 KcvinPYker

The trimming circuitry is controlled by a simple logic block This block provides the signaIs

that are required to operate the counters and also controls the sequence in which the various

devices are trimmed.

There are three states required to control the trimming. The circuit will spend most of its time

in the hold state. In this state the counters are turned off and the trim values are held. The other

two states are passed through sequentially, once a mgger input has been received. The k t state

will operate the counter for trimming the op amp while the second state will perfom the trimming

of the resistor.

The control circuit is operated by thee inputs. The major input is the trigger input which will

override all of the other inputs. When a trigger signal is received the trimming process is started

from scratch regardless of what state the circuit was in previously. The other two inputs are feed-

back from the trimming operations. They are simply the outputs of the comparators that are used

to determine when the proper trim has been achieved

The trigger input is level sensitive. A trimming operation will commence whenever this input

goes low. The other two inputs are edge sensitive. This allows the elimination of a reset function

in the counter. When one of the counters counts up it will cause the comparator to switch twice.

One of these transitions occurs at the proper him level and the other occurs when the counter rolls

over from the highest count to the lowest count. If the comparator inputs are sensitive to rising

edges then it doesn't matter where the count starts because it will only be stopped when the com-

parator goes through the proper transition.

A timing diagram is shown in Figure 4.19. This figure shows the three inputs which are Trig-

ger, Cornp 1 and Comp2. The Compl and Comp2 inputs come from the op amp trim comparator

June. 1997 Kwin

and the resistor trim comparator respectively. To enable the counters their enable pins must be

supplied with a high input. Enable1 controk the op amp aim counter while Enable 2 controls the

resistor trim counter.

Trigger Y Enable I

Comp 1

It is advantageous to be able to run the circuit without a clock to avoid the addition of excess

circuitry. The desired function can be accomplished with two D tlip flops, one AND gate and one

exclusive OR gate as shown in Figure 4.20.

The flip flops have an asynchronous set function that sets them both when the trigger input

goes low. Both flip flops will remain set until the trigger input is returned to the high state. The

enable for the op amp trim circuit is the output of the k t D flip flop. So the counter will start

counting as soon as the trigger input goes low. However, the counting will not be allowed to stop

until the trigger is allowed to go back high, even if the comparator input senses the proper edge to

stop the trimming process. Once the trigger input returns high the comparator inputs will function

properly. When a positive edge is encountered the edge sensitive D flip flop will latch in the 0

that is present at its input thus stopping the trimmi~g of the op amp. At this point the inputs to the

exclusive OR gate will be a 0 and a 1 which turns on the enable for the second trimming opera-

tion. When the second comparator input experiences a rising edge the D flip flop wili latch in the

0 that is at its input stopping the trimming process and returning the control circuit to the hold

state.

Trigger I I

Enable I

4.6 Summary

The design of a trimmable voltage reference has been undertaken. An op amp that is capable

of having its offset trimmed was created. The feedback in the circuit has been implemented with

triode connected MOSFETs to form the resistive devices. Values and sizes of the major compo-

nents have been optimized and in the case of the op amp, simulated specifications have been

stated.

A charge pump was investigated as a mans of supplying a voltage greater than the positive

supply. This high voltage is necessary to bias the gates of the triode connected MOSFETs.

June 1997 Kcvin P k

All of the components required to perform the trimming of these circuits have also been dis-

cussed. In particular R-2R DACs were used to supply the two required trim voltages. These

DACs were driven by control circuitry that was capable of switching the op amp in and out of the

circuit as well as comparing various levels to their expected trim values. The trimming operation

can be performed automatidy with the input of a single trigger pulse.

From all of the circuitry discussed some test circuits were fabricated to determine how well

the simulated results will compare to reality. These circuits consist of a charge pump to investi-

gate the actual voltage available to the circuitry. As well, a voltage reference circuit was imple-

mented without the automated trim circuitry. However, the substrate connections of all of the

devices that can be trimmed were made available to investigate how well the reference can be

References

1. ICR. Lakshmikumar, RA. Hadaway and MA. Copeland, bCCharacterization and Modelling of Mismatch in MOS Transistors for Recision Analog Design," IEEE Jouml of Solid State Circuits, vol. SC-21, vol. 6, pp. 1057-1066, Dcc. 1986.

2. D.G. Nairn, "A 130pW DAC for Low-Power Video Systems," IEEE I994 Custom Inte- grated Circuits Conference, pp. 23 -5.1-23.5-4, May 14, 1994.

3. M.M. Mano, Digital Design, Second Editon, Toronto: Prentice-Hall Inc., pp. 208-214 and pp. 272- 274, 1991.

4. G. Di Cataldo and G. Palumbo, "Double and Triple Charge Pumps for Power IC: Dynamic Models Which Take Parasitic Effects into A c c o u ~ ~ " ~ IEEE Trrmsactions on Circuits ond Systems-1: Fundmnentul nteory and Applications, vol. 40, no. 2, pp. 92-10 1, Feb. 1993.

5. P.R. Gray and R.G. Meyer, "MOS Operational Amplifier Design - A Tutorid Oveniew," IEEE Journal of Solid State Circuits, vol. SC-17, no. 6, pp. 969-982, Dec. 1982.

6 . B. Hosticka, "Chapter 3 - CMOS Op Amps," Design of MOS VLSI Circuits for Telecommu- nications, Y. Tsividis and P. Antognetti editors, Toronto: Prentice-Hall, 1985.

June. 1997 Kevin PYlrcr

5.0 Experimental Results

To verify the feasibility of trimming out the process variations of a real voltage reference cir-

cuit using threshold voltage adjustment, two test chips were fabricated.' The first chip was fabri-

cated to look at the effects of varying parameters in the charge pump circuit The second chip

investigates the actual voltage reference and the feasibility trimming the circuit through the

various substrate contacts that are available.

5.1 The Charge Pump

The charge pump poses problems for simuiation. The many step changes in output of the

charge pump are seen as discontinuities by the simulator and cause convergence errors. To over-

come these problems six charge pumps were designed to investigate the effects of changing some

of the design parameters. First the number of stages was investigated, second the size of the

switching diodes was investigated and finally the ratio between the sizes of the different capaci-

tors was looked at.

These design parameters relate to the effective output resistance of the design which, in turn,

indirectly relates to the average output voltage of the charge pump. They will also affect the out-

put ripple caused by charge being removed fiom the final capacitor during its discharge phase.

The steady state output of the charge pump is reached when the amount of charge put onto the

final capacitor during the charging phase is equal to the amount of charge that comes off of the

capacitor during the discharge phase. The two major charge pump configurations that were used

are shown in Figure 5.1. This shows the difference between the one and two stage pumps. The

CLK input for all of the charge pump designs has been supplied by an on-chip ring oscillator.

1. Fabrication was done in a 1 . 5 ~ CMOS process by Mite1 through CMC.

June. 1997 Kevin Parker

A) Single Stage Pump B) Double Stage Pump

The number of stages in the charge pump directly affects its output voltage. If the threshold

voltage of the diode connected MOSFETs is ignored and a no load situation is considered then the

single stage charge pump will produce a positive voltage that is equal to the negative supply volt-

age and the double stage charge pump will have a positive output that is double the negative sup

ply voltage. Unfommately, the situation is not that simple and other parameters a e c t the final

output voltage of the circuit. When the body effect is considered the threshold voltage of the

diode connected MOSFETs is approximately 1.2V Since the supply voltage is only -3.3V the

threshold voltage of these MOSFETs has a major effect on the output voltage of the charge pump.

June. I997 Kevin PYkrr

Other than the number of stages, the first major parameter that was investigated was the size

of the diode connected MOSFETs. The shes of these devices have a drastic effect on the steady

state output voltage. Wider devices allow charge to flow between the capacitors faster. Since the

output of the charge pump is a steady state situation between the charging current and the dis-

charging current, if more current can be supplied during the charging phase then more cumeat can

be drawn from the holding capacitor dunhg the discharging phase. This results in a lower output

resistance and consequently a higher average output voltage. The drawback to increasing the size

of the charggg diodes is the effect they have on the ripple (noise) at the output. The problem

arises when the diode connected MOSFET goes fiom being forward biased to being reverse

biased. Initially, the MOSFET channel still exists. To eliminate this channel, charge must flow

backwards off of the capacitor that was being charged This reverse flow causes a ripple on the

output. Ln cases where there are large loads on the circuit this situation wil l not be as important

because the ripple will be dominated by the discharge of the final capacitor through the load.

The second design parameter that was adjusted was the ratio of the capacitors from the first

capacitor to the final capacitor. By charging a larger capacitor with a smaller capacitor the charge

pump will pump up faster initially. Since it is difficult to determine the final steady state output

from the simulations, this type of design was investigated to determine if a ratioed charge pump

would give an eventual higher steady state voltage due to the more rapid initial charging of the

capacitors.

A photomicrograph of the chip is shown below in Figure 5.2. The important design parame-

ten for each of the six charge pumps is given in Table 5.1. AU inverters on the chip are from a

standard cell library supplied by CMC. They have a PMOS device that is 22.5 HI wide and an

NMOS device that is 17.5 wide, both of these devices are the minimum length of 1.5 m.

TABLE 5.1 - Major Design Parameters for the Didlecent Charge Pump Wgns

The charge pumps were tested with a simple set up involving a digital oscilloscope and a sin-

gle power supply to power the chip. In the DC configuration the oscilloscope can measure the

average output voltage and in the AC configuration the scope can measure the size of the ripple

caused by the combination of the reverse flow though the diode connected MOSFETs and the dis-

Charge pump

Number .

1

2

Number of

Stages 1

I

Diode MOSFET

Wdth

1 3 ~ 25.0 pn

Diode MOSFET Wdth

1.5 Crrn 1.5 Crrn

C1

10 pF 10 pF

C2

10 pF

10 pF

C3

lunc, 1997 Kevin Parker

charge through the 1 U(Z load of the scope probe. The results of the testing are summarized in

Table 5.2.

I Av- Output Vdtage I A- Rippie Voltage I

The fast and slow models refer to best and worst case devices that can be expected in the pro-

cess. Since IC fabrication is a largely statistical process there is some variation expected in the

actual operation of the device between Merent chips. From Table 5.2 it is apparent that the out-

put of the charge pump can be expected to vary considerably from chip to chip. For charge pump

designs number 5 and 6, which have the largest output range, the variation between the results for

the different models is 1SV This makes a predictable reference design dificdt and trimming

becomes even more impoftant.

Charge Pump

Number

1

The measured outputs all fall within the range specified by the two extreme models. So it

appears that the devices operate properly. However, when output ripple is considered the simu-

lated results are substantially better than the measurements. This is due to a problem that wasn't

considered in the simulations. The ring oscillator induces noise on the supply line. This supply

line noise had a ripple value of 140mV which is larger than all of the observed charge pump rip-

ples. Although the charge pumps had a larger ripple than was expected, this ripple was consider-

Number of

Stages

1

Simulated WithFast

Modds 0.41 1 V

Measured Meam Vdue -5-pb

0.03 V

Simulated W i s l o w

Modds 0.010 V

Simulated WrthFast

Mad& 02 mV

Measured Mea~vdue OverSCbips

93 mV

Srmlrlrrtrd W~thSIow

Models 0-1 mV

June 1997 Kevin PYlrtr

ably less than the power supply noise which i m p k that the charge pumps filter power supply

One confusing measurement deals with the ripple measured for charge pumps 5 and 6. These

devices have the opposite relationships between their measured and simulated ripple. This sug-

gests that the ratioed charge pump does a better job of rejecting power supply noise while the non-

ratioed charge pump generates less ripple. In the measurement situation the output ripple is a

result of the supply noise, so the ratioed charge pump appears to have better performance.

In all cases on the test chip the CLK signal is supplied by means of a 25 inverter ting oscilla-

tor. To create the six CLK signals the ring oscillator has six taps roughly evenly spaced around

the ring. This reduces the loading effects that connecting ail of the CLK inputs to the same node

of the oscillator will have. By tapping the oscillator in th is fashion the charge pump inputs should

have very little effect on each other.

Simulated results give a ring oscillator fkquency of 68 MHz. Indirect measurement of the

oscillation fiequency of the fabricated chip gave an average of 54 MHz. This measurement was

obtained by examining the fkquency of the periodic ripple superimposed on the outputs. This

ripple frequency will correspond to the osciUation frequency of the on-chip ring oscillator. These

frequencies initially seem to be off by quite a bit. However, if the circuit is resimulated with the

slow comer models from Mite1 an oscillation frequency of 51.2 MHz is obtained. The observed

oscillation frequency falls well within these boundaries.

From the results it appears that the best charge pump design, for the pupuses of the reference,

is either number 5 or number 6- Both of these designs have a sufficient output voltage to bias the

gate terminals of the triode connected MOSFETs in the reference design. However, design num-

June. 1997 Kcvin PYlrtr

ber 6 seems to exhibit better noise rejection which will make it a better choice for the reference

circuit.

The expected uncertainty in the charge pump supply will make design of the voltage reference

very difficult. The reference must be capable of handling the large differences in the predicted

charge pump output. It must also be able to deal with the nppIe on the charge pump's output The

variation in the average output can be handled quite readily but the ripple will cause more of a

problem. Since the reference will be trimmable, the effects of variations in the gate bias of the

resistors can be removed through trimming. However, the effects of the ripple cannot be removed

in this manner. Therefore, it is desirabIe to create a design that is not heavily dependent on the

mate bias voltage. The design at hand deals with this faidy well for small variations. If the bias b

voltage changes it affects all of the resistors so the ratios remain relatively constant. It is these

ratios that are important, not the absolute value of the resistors.

5.2 The Voltage Reference

The test circuit that was fabricated to investigate the effectiveness of trimming the voltage ref-

erence is shown in Figure 5.3. It was designed to &ow probing of many different nodes of the

circuit. The op amp can be switched out of the reference circuit so it can be trimmed manually.

All of the op amp's inputs and outputs are present at external pins so thorough testing of its oper-

ation can be investigated. Trimming of the resistors has been taken to the extreme. Each of the

three resistors in the feedback network has both its gate and substrate brought out to an external

contact. This allows very extensive trimming of the resistor values. This was doae because the

validity of the bipolar transistor model was uncertain at the time when the test circuit was submit-

ted for fabrication. At this point the bipolar test structures were still being fabricated so an empir-

June. I997 Kevin Pyku

ical model was not available. However, in the h a 1 design only the substrate of R2 will need to be

trimmed.

Control- I @ vss

Some of the other circuit nodes that are brought to the outside world simply monitor onthip

voltages. There are also three pins that control the connection of the op amp with the rest of the

circuit. A full description of the function of each of the pins that emerge from the fabricated chip

is given in Appendix B.

A photomicrograph of the reference test chip is shown in Figure 5.4.

June. 1997 Kevin L'aduf

5.2.1 Op Amp Operation and W h m h g

The circuit shown in Figure 5.3 was connected so that the switches disconnected the op amp

from the feedback network completely. This made both of the inputs and the output available so

the op amp could be thoroughly tested In this configuration the inputs were not shorted together.

For this application the important op amp specifications are the open loop gain from the gate (A)

and the gain fiom the substrate connections (Abulk)- The unity gain bandwidth through the gate

of the op amp (f,) was also measured to make a comparison with the simulations. A comparison

of the results with the comer model simulations is given in Table 5.3.

From the table it is apparent that the gain ratio, which specifies the ratio between the gate gain

and the bulk gain, matches the simulated data quite well. The unity gain frequency almost

matches the simulated results and could be outside of the desired range because of measurement

uncertainty. However, the values for the absolute gains, both through the gate inputs and through

the substrate inputs, are two orders of magnitude below what was expected from simulations. The

discrepancy could very well be the result of poor modelling. The CMOS models supplied by

MITEL are intended to be used by digital designers where gain is not critical but factors such as

the switching speed of inverters are. This is very likely where the fast and slow designations

come from. The fast models are probably generated h m a fast switching inverter while the slow

models are generated fiom an inverter that switches more slowly. The people responsible for

modeliing are not overly concerned with the analog characteristics of the devices and therefore,

do not put a lot of effort into creating a good analog model.

From the results it appears that the major problem lies in modelling the output resistance (Ro)

of the transistor. This would explain the reduced gain with a relatively constant bandwidth. This

error is conceivable since very long devices were used in the input stage of the op amp to achieve

good matching. In digital circuitry a rnhimum length is always used to get the fastest possible

logic with the lowest power dissipation. Therefore, longer devices are modelled by adding scal-

June. 1997 Ktvin PYlrcr

ing factors to the minimum length models. However, for transistors that approach 10 times the

minimum length this linear scaling does not work well. Models targeted for analog applications

typically use multiple models to deal with various different lengths of devices. T h i s allows inter-

polation between the different size models instead of extrapolating al l of the information fiom one

minimum size model-

W~th models that are more suited for analog analysis, it is conceivable that the prediction of

the gain could be more accurate. However, the measured gain is high enough to d o w the circuit

to work properly and more importantly the gain ratio matches the simulated gain ratio quite

closely. This suggests that the trimming operation will work as predicted.

The effects of adjusting the substrate inputs of the op amp, on its offset voltage, were exam-

ined. These results are summarized in Table 5.4 below. The measurements were taken with the

positive uim terminal held at -3.OV, with the negative trim terminal allowed to vary fiom -2.7 V to

-3.3 V. The trim voltage must be kept between the supplies and below the gate voltage of the op

amp to avoid problems with a forward bias condition between the substrate and the gate. This is

the primary factor limiting the trim range. The trimmed offset voltage is limited to 40 pV simply

because the equipment used for measurement could not make readings that were more accurate.

This problem resulted from a combination of measurement device accuracy and noise present in

the system.

The fifth chip did not respond to any of the supplied inputs. A processing defect or bonding

error is probably at fault

V a - - It.im Vdtage b- 1 I 1.0mV 24 mV c40 pV

The first major thing to note concerns the untrimmed offset voltage of the op amp. It is inter-

esting to see that it is always positive. This suggests that the op amp has some systematic offset

designed into it. However, even though the offset is always positive it is still faitly low, having a

maximum value of 8.2 mV

As stated in Table 5.4, all of the functional circuits were capable of being trimmed. The max-

imum required trim voltage was 13 1 mv This is well within the range of +/- 300mV that is

allowed with this setup. The trim range can be expanded slightly if the voltage on the positive ter-

mind is raised to -2.8 V. This wiII allow a trim range of +/-XI0 my From the measurements it

appears that this modified setup would have a range capable of trimming offset voltages of up to

+/-3 1 mv.

If the DAC that is driving the substrate voltage has a step size of 5mV between bits this set up

will be able to trim the offset voltage to better than 0.42 mV. The trimming accuracy is con-

trolled by the gain ratio between the substrate inputs and the gate inputs. Either this ratio should

be increased or the DAC should be given a smaller step size so the op amp can be trimmed to an

accuracy less than 0.1 mV in the ha1 trimming circuit

June. 1997 Ktvia Packer

5.2.2 Total Reference Circuit 'ltimmiog

The chip was placed into the feedback mode to investigate the effects of changing the sub-

strate voltages of the resistors on the output ofthe reference. Originally an attempt was made to

determine the temperature behavior of the circuit by placing it in a furnace and varying the tem-

perature of the chip. The output was monitored to determine what the effects the elevated temper-

atures had on the reference's operation. Unfortunately, raising the temperature of the chips

caused premature aging and problems with the gate oxides of the MOSFET resistors. This could

be partly due to the lack of input protection on these nodes. Standard protection circuits could not

be used because the gate bias voltage was not between the supply voltages.

The temperature testing was stopped with one working chip remaining. This chip was used to

determine the results of adjusting the substrate voltages of each of the three resistors. AU of the

measurements were completed with the substrate voltages of all nodes being set to -3.3V' includ-

ing the trim voltages for the op amp. Each individual substrate was then varied between -3.3V

and - 1.7V.

The plot in Figure 5.5 shows a comparison of the measured and simulated trimming results.

Since the measurements were taken without removing the offset from the op amp an offset was

added to the simulated op amp to make the trimming curves line up.

June, 1997 Kevin Pykcr

Sulk Voltage (V)

In the plot the symbols represent the measured data and the lines represent the corresponding

simulated response. From the plot it can be seen that the measured and simulated data have the

same relationships to the output. Since the difference is simply a decrease in the slope of the mea-

sured response over the simulated response, it can easily be attributed to process variations. It can

be seen that R3 and R2 have the largest effect on the output of the reference circuit while R1 has a

reduced effect. This makes sense in terms of the output voltage relationship shown again in

Equation 5.1.

June. 1997 Kcvin PYlrtr

R2 and R3 control the feedback gain which is the major factor determining the temperature com-

pensation while R1 only controls the current ratio which has a very reduced effect on the output

volt age.

From the data in Table 5.5 trimming R2 offers the best trimming range. The trim range

parameter describes how much change in the output can be obtained with a variation of the input

between -3.3 V and -1-7V. In this w e , tdmming RZ also allows the output to be trimmed to the

proper level. The other two trim voltages send the output M e r away from the desired value of

- L -3 69V.

The trim gain column describes the change in the output of the reference for a 1 volt change in

the substrate voltage of the respective resistor. It is essentially the maximum trim range divided

by the range of the substrate input applied. Using the trim gain for R2, which is the resistor that

will be trimmed in the complete system, allows the reference to be trimmed within 0.19 mV of the

desired value. This trim is determined by assuming that the step size on the DAC output is 5 my

TABLE 5.5- Redstor Tkimmhg SpdiaPons

The circuit under consideration doesn't have an ideal set up. It should be designed to have the

substrate voltage of R2 sit half way between the trim limits of -1.7 V and -3.3V, at -25V' for an

ideal trim. This was the original design specification but the models of the BJTs used in this

design were invalid. Therefore, the ideal value ended up being very close to the upper limit of the

trim range. This can be seen in Figwe 5.5.

5.3 Summary

The charge pump operation matched reasonably well with the expectations from simulation.

However, the range of output from the fast and slow models is quite large. This creates a problem

for the designer because the output of the charge pump is not very well defined In this situation

the reference circuit has a trimming capability so the problem is reduced. The ripple at the output

will however, cause problems in the h a 1 design. Some of this ripple can feed through to the out-

put of the reference creating noise at the output which is undesirabie. If a Iarger reference voltage

can be tolerated, it may be possible to eliminate the charge pump from the design entirely- If Dar-

lington pairs are substituted for the single diode co~ected transistors in the reference, all of the

voltages double which allows enough voltage between ground and the negative op amp terminal

to turn on the triode resistor R3.

With the circuit as designed the reference can be tdmmed to an accuracy of 4.2 mV. This

accuracy is limited by the offset voltage of the op amp, which was only nimmable to 0.42 mV,

because the feedback gain of the circuit is 10. The accuracy could be increased by either increas-

ing the gain ratio between the substrate and gate inputs to the op amp or reducing the step size of

the DAC that drives the trim node. Both of these solutions will reduce the overall trim range of

the op amp. However, the DAC as it is designed provides a higher range than should be applied

to the substrate if the reverse bias of the gate-substrate junction is to be ensured. The op amp

itself also has more trim range than is necessarily needed.

June. 1997 Kevin Parker

The resistors can be trimmed accurarely enough to produce an output with a tolerance of

0.19mV which is well below the desired trim accuracy of lmv Resistor trimming through the

substrate is a very useN too1 in achieving higher accuracy reference circuits. It can be used to

help eliminate the random effects of process variations which will add an error to the output of the

reference circuit. Similar methods can be used to trim the process variation induced, offset volt-

age from an op amp to fbrther enhance the accuracy of the reference circuit.

June. 1997 KtvinParLtr "

6.0 Conclusions

The drive for single chip irnpIementati011~ of mixed signal systems has made it very desirable

to be able to design analog circuits in processes that are optimized for digital CMOS circuitry.

There have been many advances in the accuracy of the CMOS implementations of DACs and

ADCs in the recent past. However, many of these systems still require a very accurate off chip

voltage reference to function properIy. Complete on-chip mixed signal systems will be realizable

only if an accurate on-chip implementation of the voltage reference can be created

To create an accurate on-chip voltage, a bandgap reference circuit was chosen because it

offers good inherent accuracy. However, this circuit requires two bipolar transistors to be imple-

mented and modelled in the CMOS process used for the reference. Some sort of trimming is then

necessary to overcome the effects of process variations on the matching of the resistors. A

method of electronically trimming triode connected MOSFET resistors has been implemented

that provides a final trimming accuracy of better than ImV These resistors are trimmed by

adjusting their threshold voltages through the body effect. To complete the design requires; a

charge pump for bias purposes, some digitai control circuitry to drive the DACs that supply the

trimming voltages and a low offset op amp to drive the feedback loop of the reference circuit.

Physical and empirical parameters were found for models of parasitic vertical BJTs in Mitel's

1.5 pm CMOS process. These models were not available to the CMC design community but are

necessary for designing a bandgap reference. The resulting models were found to be suitable for

preliminary design estimates.

A new technique was developed for trimming resistors that involves individually adjusting the

substrate potentials of triode co~ected MOSFETs to cause an effective change in the threshold

June, I997 Kevin Ebrkcr

voltage. This change in the threshold voltage will cause the resistance of the triode connected

devices to change slightly. Trimming can also be accomplished by adjusting the gate voltage of

the triode connected MOSFETs. However, controlling the gate does not allow the same degree of

accuracy to be achieved as the VT trimming method The trimming accuracy is determined by the

bias of the substrate voltage. Due to the square root relationship between VSB and VT, a higher

substrate bias will result in a better accuracy. With theset up that was used a lOOmV change in

the substrate produced a 09546 change in the resistance values. Where as a 100 mV change in the

gate voltage would produce a 2.3% change in the same resistance value,

Due to process limitations a bias voltage above the supply was required to supply the gate bias

to the triode connected resistors. This requirement is a result of the low voltage difference

between the supply and the op amp inputs. To overcome this problem a two stage charge pump

was designed that suppiied +2.6V.

To control the trimming of the resistors some digital logic was designed to control an 8-bit

DAC. The output of the DAC had a 1.4 V range with a step of 5 mV between bit counts. This

step size is one of the limiting factors defining the accuracy of the h a 1 trimming circuit. Reduc-

ing the range will reduce the step size and offer more accuracy in the final trim but it will also

decrease the overall trim range to a point where it may not be possible to completely remove the

effects of the process variations.

An op amp was developed that could have its offset voltage trimmed to a very low level. The

aimming was accomplished through a method vev similar to the one used to trim the resistors.

The threshold voltages of the differential input devices were adjusted to cancel any offset that the

op amp might have. Trimming the op amp with the DAC resulted in an offset better than 0.42mv

June. 1997 KcvtoRzker

The trimmable reference that was designed shouId be capable of achieving a trimmed accu-

racy of better than 1 mV although the test circuits were only capable of achieving an accuracy of

4.2 mv This accuracy was limited by the trimmed op amp offset voltage. The resistor trimming

provided an accuracy better than 0.2 mV while the offset of the op amp was limited to 0.42 mV.

This offset translates into an accuracy of UrnV at the output of the reference due to the gain of 10

that is found in the feedback loop. Since there is excess trim range in the op amp trimming cir-

cuitry, the accuracy of the trim can be increased in one of two ways. The gain ratio between the

gate and substrate gain of the input transistors can be increased or the step size of the DAC can be

decreased. If one of these parameters is changed by a factor of4.2 the desired accuracy of ImV

will be obtainable while the trim range will decrease by a factor of 4.2.

One of the major external factors determining the accuracy of the reference circuit is the

uncertainty associated with the output of the charge pump that biases the gates of the triode resis-

tors. These uncertainties are the result of process variations and cannot be easily removed. A

reference that doesn't need a gate bias above the supply rail would eliminate this problem. If a

higher reference voltage can be tolerated, the high bias requirement can be removed. A new ref-

erence can be designed with a 2.4V output, by using Darlington pairs to replace the BJTs. This

will double all of the circuit's internal node voltages which leaves a minimum of 1.4 V available

to provide the gate bias for the MOSFET resistors and the problem of not being able to turn the

devices on is eliminated.

In summary, by trimming resistors using adjustment of VT a voltage reference circuit that was

designed to have an output voltage of -1.369V could be trimmed to an accuracy of 1 mV.

June. 1997 K w i n Packer

Appendix A - Theoretical B JT Model Equations

The following equations can be used, in conjunction with the major equations in Chapter 3, to

arrive at a more complete theoretical model of a BJT. This list is just an overview of the appropri-

ate equations. For a more complete description of the variables and their meaning see:

R. Benumof and J. Zoutendyk, "Theoretical Values of Various Parameters in the Gurnmel-Poon Model of a Bipolar Junction Transistor," J o u d of Applied Physics, vol59, no. 2, pp. 636-644, Jan 1986.

TF = ( Qso - Qs)

[IS(.? - I)]

[2DB - q - NAB - AE ( b - a*) 0] IKR = c)

CJE = A @%$VDE ( VDBE - VBE) (NAB + NDE)

(A. 10)

(A* 1 1)

June. 1997 Kevin Rfkr

VAR = ( L o * ) 2q ( VDBE - VBE) NAB (NAB + NDg)

%E

TF - IS CBEP = - vt

RC = (C - b*)

=CAE

(A. 13)

(A- 14)

(A. 16)

(A. 18)

June. I997 KtvinPark

Appendix B - Reference Test Circuit Description

This appendix describes the circuit that was fabricated to test the feasibiIity of trimming a

voltage reference through the process of adjusting VF Figure B.1 shows a schematic of the fabri-

cated circuit and Table B. 1 gives a description of the operation of each of the 16 pads that are

available for testing purposes.

Control- I VSS

TABLE B. l - Pm Descriptions

Allowed Voltage Range

ov

Pin Name Description

- - - - -

High Supply Rail for the en& circuit.

I VSS Low Supply Rail for the entire circuit.

Output/ Probe

This pin is directly connected to the ou~ut of the op amp. If the circuit is connected as a reference it will supply the reference's output. If the op amp is disconnected this out- put can will be used to characterize and trim the op amp.

In+

In-

Probe - -. -. - -

This pin directly probes the positive input tenninal of the op amp. None of the switches disconnect it from the op amp*

This pin directly probes the negative input terminal of the op amp. None of the switches disconnect it fkom the op amp-

Trim This pin allows positive trimming of the offset of the op amp. It is connected to the substrate of the negative input transistor.

Trim -

This pin allows negative trimming of the offset of the op amp. It is connected to the substrate of the positive input transistor.

Bias - - - - - -

These three pins an used to supply the bias voltage to the three feedback resistors. In the final circuit they will be C O M ~ C ~ ~ to a charge pump which wilI supply the required bias voltage. They are left external here to allow more adjustment range in case the operation of the actual bipolar transistors is drastically Werent from the models used in the original design.

Trim These are the substrate contacts of the three triode con- nected feedback resistors. Although it is hoped that all of the necessary trimming can be accomplished through B2, the other comections are brought out both to investigate their trimming properties and to allow extra trimming if the bipolar transistors operate vastly different than expected.

June, 1997 Kevin PYkcr

TABLE B.1- P h Descripti011~

Pin Name

Con+

Con-

Short

Type

Control Logic

Control Logic

Control Logic

Oor- 3.3v

Allowed Voltage Range

0 or - 3.3V

This input is used to disconnect the negative terminal and the output of the op amp as well connect a resistor to bias the bipolars so that the positive input sees approximately 0.N. This is used to allow independent trimming of the offset of the op amp. The disconnection occurs when a high input appears at the pin.

Description

This input controls the connection of the positive tenninal of the op amp to the rest of the circuit When the input is high the positive input to the op amp is disconnected fiom the rest of the circuit. For normal operation it should be ~ 0 ~ e ~ t e d OW.

Oor- 3.3v

This input is responsible for controlling the shorting together of the two op amp inputs. When a low is input the two input terminals of the op amp are shorted together for offset trimming purposes.