tsv interposer process flow with ime 300mm facilities fabrication flow_tsv_beol... · tsv formation...

Property of Institute of Microelectronics (IME)-Singapore © August 17, 2012

TSV Interposer Process Flow with

IME 300mm Facilities

2IME’s TSI Consortium on August 17, 2012© IME-Singapore

1. TSV interposer (TSI) cross sectional schematicTSI with BEOL, TSI with BEOL and IPD, TSI with RDL.

2. Process flows and examples for TSI wafer

fabrication and TBDB for thin wafer handling. TSV formation

BEOL

RDL

UBM and micro-bumping

Thin wafer handling and back side TSV revealing

Backside RDL and UBM

3. Summary

Outline


28-Aug-12

Si substrate

16μm>W>2μm

10um

(Cu)

~100μm

T[1]=1-2μm

T[2]= 1-2μmT[3]=1-2μm

T[4]=1-2μm

T[5]=1-2μm

T[6]=1-2μm

S>2μm

T[7]=1-2μm

T[8]=1-2μm

16μm>W>2μm

Cu/Ni/AuAl

BS RDLPolyimide

Front side (FS): TSV + upto 4 BEOL layers + UBM

Backside (BS): 1 layer RDL layer + C4 bump

TSV

ø10μm

BS UBM

TSI with BEOL


28-Aug-12

Si substrate

10um

(Cu)

~100μm

T[1]=1-2μm

T[2]= 1-2μm

T[3]=1-2μm

T[4]=1-2μm

T[5]=1-2μm

T[6]=1-2μm

T[7]=1-2μm

T[8]=1-2μm

16μm>W>2μm

Cu/Ni/AuAl

BS RDLPolyimide

MIM capacitors Resistors

TSV

ø10μm

Front side (FS): TSV + upto 4 BEOL layers + MIM capacitors + Resistors + UBM


BS UBM

TSI with BEOL and IPDs


Front side (FS): TSV + up to 3 layers RDL layers + UBM


Si-substrateSi-substrate

1st FS RDL

2nd FS RDL

3rd FS RDL

T=5-7μm

T=5-7μmT=3μm

BS UBM

FS UBM

TSV ø10µm

Liner oxide

Cu B/SH 100µm

polyimide

TSI with RDL


Si-substrate Si-substrate Si-substrate


1. Hard mask deposition 2. TSV patterning and etching 3. Liner oxide deposition

4. Barrier and seed layer deposition 5. Cu ECP and annealing 6. CMP

Key challenges:

1. TSV etching: small scallop, uniformity, straight profile

2. Liner oxide: high step coverage

3. Barrier and seed layer: high step coverage

4. Cu ECP: void free, seam free, small over burden

5. CMP: small oxide loss, uniformity

Process Flow for TSV Fabrication


Challenges Examples How to deal with?

TSV etching1. Uniformity control

2. Scallop control

3. Profile control

Botch etching recipe

optimization, gas flow,

pressure, cycling time,

RF power, etc.

Liner oxide CVD1. Step coverage

2. Scallop smoothing

SACVD O3 TEOS

Upto 50% step coverage

Smooth the scallop.

B/S layer PVDStep coverage

PVD process optimization.

Min 5% step coverage is

Required.

ECP1. Void-free

2. Low overburden

ECP recipe tuning.

TSV Formation Challenges

Seed layer

discontinuity

Void in TSV


Good Example: Through Si-Via Formation - Modules/Integration

TSV Etcher (Silvia); Unifire

• Straight profile (~90o)

• High cross wafer uniformity (<2%)

• Low scallop (<50nm)

PVD B/S (Endura, Charger)

•Step-Coverage

•Gap-Fill Co-optimization

Clean (Akrion) + CVD Liner (InVia)

•Pre-Clean Optiimization

•High step-coverage (Side>50%; Bottom

>20%)

Cu ECP (Raider)

• Void free

• Low overburden (~2.5mm)

• Low mounds (<3mm)

Cu CMP (Reflexion)

• Good post-CMP control

• Proper removal rate

• Accurate end point detection

• Post-CMP Topography (AFM) <50nm

D/H ~5μm/50μm

X-ray

Via Fill Evaluation

Furnace Cu Anneal

Well Optimized Temp. Profile

3D-AFM

Post-CMP Eval.




Si-substrate

Key challenges:

1. Diametric etching: uniformity, high SiO2 etching selectivity

to Si3N4

2. ECP: void free

3. CMP: small oxide loss, uniformity

2. M1 pattern, etch and clean1. M1 dialectical layers Si3N4/SiO2

deposition 3. M1 seed layer PVD, Cu ECP and CMP

4. M2 dielectric deposition

7. M3, M4, and Al pattern

5. Via 1 and M2 pattern, etching and

clean

6. Via 1 and M2 seed layer PVD, Cu ECP

and CMP

Process Flow for BEOL Fabrication


Si-substrateSi-substrate

PR

PR

Si-substrate

Polyimide

Si-substrate

1. Seed layer deposition and PR

patterning

3. PRS and Seed layer etching

4. Polyimide passivation and patterning 5. Seed layer deposition and PR

patenting6. Cu ECP to form 2nd RDL

Si-substrate

7. Repeated RDL process to form

RDL and passivation

Key challenges:

1. RDL PR patterning: fine line/space smaller than 5μm/5μm

2. RDL ECP: Micro loading effect

3. Passivation opening lithography process: tapered via

profile, via size uniformity

4. Seed layer etching: etching uniformity, small undercut

Si-substrate

PR

2. Cu plating

Process Flow for RDL Fabrication



RDL PR patterning

1. Need fine line/space

less than 5μm/5μm

2. Uniform and complete

de-scum process

PR material improvement.

Patterning optimization.

ECPMicro-loading effect

Plated thickness difference among different

pattern densities.

ECP recipe optimization

Passivation opening1. Need tapered via

profile, via.

2. Size uniformity.

3. De-scum

PVD process optimization.

Min 5% step coverage is

Required.

Seed layer etching

rate and uniformity

control

ECP recipe tuning.

Design CD bias.

Fine line PR patterning

Profile that is not

suitable for next RDL

seed layer deposition.

Seed layer

etching caused

undercut and line

width shrinkage

RDL Process Challenges


Line Width/Space

~ 5mm/5mm

PR Mold Patterned

On Ti/Cu Seed Layer (SL)

ECP Cu RDL

After SL Etch off

PVD for Seed Layer

Suss TrackSpin-Coat & Soft Bake

Ultratech StepperPR Patterning

Cu ECP (Semitool)Cu Electroplating

PRS (Suss Track)PR lift off

Seed Layer Patterning (GPTC Metal Spray Etcher)Wet-Etch Seed layer

Line Width/Space

~ 3.5mm/2.5mm

Example: RDL formation – Modules / Integration


1. Passivation opening 2. Seed layer deposition 3. PR patterning to define the

UBM area

4. UBM plating (Cu/Ni/Au) 5. PR strip and seed layer

etching

Key challenges:

1. Fine pitch thick PR patterning

2. Seed layer etching: etching

uniformity, small undercut

Si-substrate Si-substrate

PR

Si-substrate

PR


Process Flow for UBM / Landing Pads or Micro-bumping



Thick PR patterning

1. Straight profile

2. Size control

3. Uniform and complete

de-scum process

Litho process optimization

De-scum process control

ECP loading effect 1. Better design rule to control the density

uniformity.

2. ECP process tuning to improve plating

thickness uniformity.

UBM and Micro-bumping Process Challenges


Chip-to-Chip Bonding (TCB/FET300)

Bottom Wafer Landing Pad (Raider ECD)

Landing pads

• Stack: ~5µm-Cu / ~0.3µm-Au

• Pitch: X=50µm, Y=30µm

Top Wafer Micro-bump Formation: (Bottom Plate & Patterning;

Raider ECD Cu-Pillar / SnAg, Flux coater, Reflow Furnace, Clean)

Micro-bumps

• Stack: 10µm-Cu / 10µm-SnAg

• Pitch: X=50µm, Y=30µm

Au-Surface

Cu-Base

SnAg

Cu-PillarFlux Coat Reflow CleanCD~20mm

Top-Chip

Bottom-Chip

UBM, Micro-bumping and Micro-joining – Modules / Integration


1. Temporary bonding 2. Device wafer thinning 3. Passivation

4. CMP

Key challenges:

1. TTV control

2. Void free through-out the whole process

3. Chipping and cracking free during de-bonding

Si-carrier

Si-substrate

Si-carrier

Si-substrate

Si-carrier

Si-substrate

Si-carrier

Si-substrate

Thin Wafer Handling + Backside Revealing (BSR)


TBDB Approach

Challenges How to deal with? Result and remark

TTV control 1. Coating optimization

2. Back grinding and CMP process optimization

1. <8μm for 100μm adhesive



Edge cracking during

BG

1. Edge trimming on device wafer before bonding

2. Bonding process optimization

No edge cracking and

chipping

Void in

adhesive

1. Dehydration bake and pre-bake for both device and

carrier wafer

2. Bonding process optimization

No void or delamination

after bonding and

RDL process

De-bonding damage 1. EZR process optimization

2. De-bonding process optimization

De-bonded successfully

without edge cracking

or chipping

Carrier waferCarrier wafer

Adhesive

Cracks

Edge chipping

Thin Wafer Handling and Challenges


Backside RDL and UBM

18

1. Backside TSV revealing 2. Backside RDL formation 3. Polyimide passivation and

opening

4. Backside UBM formation 5. De-bonding

Si-carrier

Si-substrate

Si-carrier

Si-substrate

Si-carrier

Si-substrate

Si-carrier



• Reliable TSV integration process flow

i-line TSV patterning

TSV etching and cleaning

Liner oxide deposition

PVD barrier and seed layer deposition

ECP process for TSV void-free filling

CMP

• BEOL and RDL process

Thick Cu damascene process

Fine line PR patterning process for Cu plating

RDL passivation

• Thin wafer handling, backside RDL and micro-bumping

Device wafer preparation

Carrier wafer choice and preparation

Temporary bonding optimization

Wafer thinning down optimization to minimize device wafer TTV

Si recess etching with high selectivity to SiO2

CMP process to reveal TSV with minimized oxide loss

PVD process which is compatible with temporary bonded wafers

Curing

Target Deliverables


Thank You.

Q & A

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